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Cmos Vlsi Design 198

The document discusses logical effort analysis and its limitations in analyzing digital circuit paths and gates. It notes that logical effort increases with fan-in and suggests a practical limit of 4 inputs for gates and multiplexers. When paths fork, buffering the non-critical legs can reduce branching effort on the critical path. Logical effort does not account for interconnect delays and is best for regular layouts where routing delay is minor. Paths with non-uniform branching or reconvergence are difficult to analyze by hand using logical effort. Iterative solutions can be used to size gates to minimize delay by modeling each gate's logical effort, parasitic delay and drive in an optimization problem.

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Carlos Saavedra
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71 views1 page

Cmos Vlsi Design 198

The document discusses logical effort analysis and its limitations in analyzing digital circuit paths and gates. It notes that logical effort increases with fan-in and suggests a practical limit of 4 inputs for gates and multiplexers. When paths fork, buffering the non-critical legs can reduce branching effort on the critical path. Logical effort does not account for interconnect delays and is best for regular layouts where routing delay is minor. Paths with non-uniform branching or reconvergence are difficult to analyze by hand using logical effort. Iterative solutions can be used to size gates to minimize delay by modeling each gate's logical effort, parasitic delay and drive in an optimization problem.

Uploaded by

Carlos Saavedra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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4.

5 Logical Effort of Paths 171

 The logical effort of each input of a gate increases through no fault of its own as
the number of inputs grows. Considering both logical effort and parasitic delay, we
find a practical limit of about four series transistors in logic gates and about four
inputs to multiplexers. Beyond this fan-in, it is faster to split gates into multiple
stages of skinnier gates.
 Inverters or 2-input NAND gates with low logical efforts are best for driving
nodes with a large branching effort. Use small gates after the branches to minimize
load on the driving gate.
 When a path forks and one leg is more critical than the others, buffer the noncrit-
ical legs to reduce the branching effort on the critical path.

4.5.5 Limitations of Logical Effort


Logical Effort is based on the linear delay model and the simple premise that making the
effort delays of each stage equal minimizes path delay. This simplicity is the method’s
greatest strength, but also results in a number of limitations:
 Logical Effort does not account for interconnect. The effects of nonnegligible wire
capacitance and RC delay will be revisited in Chapter 6. Logical Effort is most
applicable to high-speed circuits with regular layouts where routing delay does not
dominate. Such structures include adders, multipliers, memories, and other data-
paths and arrays.
 Logical Effort explains how to design a critical path for maximum speed, but not
how to design an entire circuit for minimum area or power given a fixed speed con-
straint. This problem is addressed in Section 5.2.2.1.
 Paths with nonuniform branching or reconvergent fanout are difficult to analyze
by hand.
 The linear delay model fails to capture the effect of input slope. Fortunately, edge
rates tend to be about equal in well-designed circuits with equal effort delay per
stage.

4.5.6 Iterative Solutions for Sizing


To address the limitations in the previous section, we can write the delay equations for
each gate in the system and minimize the latest arrival time. No closed-form solutions
exist, but the equations are easy to solve iteratively on a computer and the formulation still
gives some insight for the designer. This section examines sizing for minimum delay, while
Section 5.2.2.1 examines sizing for minimum energy subject to a delay constraint.
The ith gate is characterized by its logical effort, gi , parasitic delay, pi , and drive,
xi .Formally, our goal is to find a nonnegative vector of drives x that minimizes the arrival
time of the latest output. This can be done using a commercial optimizer such as MOSEK
or, for smaller problems, Microsoft Excel’s solver. The arrival time equations are classified
as convex, which has the pleasant property of having a single optimum; there is no risk of
finding a wrong answer. Moreover, they are of a special class of functions called posynomi-
als, which allows an especially efficient technique called geometric programming to be
applied [Fishburn85].

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