Computer Organization

and Architecture

Chapter 3 (Part III)

The 8086 Microprocessor
Chere L. (M.Tech)
Lecturer, AASTU
Chapter 1 1
Outline
 Historical Overview

 Basic Characteristics and features

 Architecture of 8086 Processor

 Register Organization of 8086

 8086 Microprocessor
(Basic Characteristics and features )
 1) Historical Overview
 The first microprocessor is the Intel 4004, was a 4-bit microprocessor. It has 12-
bit address lines to access 4096 memory location. The 4004 microprocessor has
only 45 instructions.
 The Intel released the 4040 microprocessor, as updated version of 4004 with
enhancement in speed, and without any improvement in word length and
memory size.
 In 1971 announced the 8008 microprocessor, 8-bit and faster version of 4004
microprocessor. This version came up with expanded memory size up to 16
Kbytes and additional instructions to make total of 48 instructions.
 In 1977 Intel introduced updated version of 8080, which was 8085
microprocessor. The 8085 is an 8-bit microprocessor.
 In 1978, Intel came out with the 8086 processor which is our study in this
course.
 Today, the development of the microprocessors reached to the Pentium,
Core-2-duo,Core i.
2) Basic Characteristics and features
 A 16-bit microprocessor.
 The term “16-bit” means that its arithmetic logic unit, internal
registers and most of its instructions are designed to work with
16-bit binary words.

 It has
 A 16-bit data bus, so it can read data from or write data to
memory and ports either 16 bits or 8 bits at a time.
 A 20-bit address bus, so it can directly access 2^20 or 1,048,576
locations.
 generate 16-bit I/O address; hence it can access 2^16 = 65536
I/O ports.
 14 registers each one with 16-bit
 multiplexed address and data bus which reduced the number
of pins needed.
Cont. . . .

 Designed to operate in two modes (Min & Max mode)

 Minimum mode - only one 8086 CPU is to be used in a
microcomputer system

 Maximum mode - more than one processor in the system

(multiprocessor)

 It supports multiprogramming.
 In multiprogramming, the code for two or more processes is in
memory at the same time and is executed in a time-multiplexed
fashion.

 An interesting feature of the 8086 is that it fetches up to six

instruction bytes from memory and queue stores them in order to
speed up instruction execution.
 3) Architecture of 8086
 It is internally divided into two separate functional units.
 These are the Bus Interface Unit (BIU) and the Execution Unit
(EU).
 These two functional units can work simultaneously to increase
system and hence throughput.
 The throughput is a measure of number of instructions executed
per unit time (processing speed of the processor).

 The architecture of 8086 includes

 Arithmetic Logic Unit (ALU)
 Flags
 General registers
 Instruction byte queue
 Segment registers
Cont. . . . Architecture Diagram
Cont. . . .

The BIU has to interact with memory and input and output
devices in fetching the instructions and data required by the EU

EU is responsible for executing the instructions of the

programs and to carry out the required processing.
Bus Interface Unit (BIU)
 The BIU is the 8086’s interface to the outside world.
 It provides full 16-bits bi-directional data bus and 20-bits address
bus
 The BIU is responsible for performing all external bus operation, as
listed below.

 Functions of BIU  It sends address of the memory or I/O.

 It fetches instruction from memory.
 It reads data from port/memory.
 It writes data into port/memory.
 It supports instruction queuing.
 It provides the address relocation facility.
Cont. . . .
To provide these functions the BIU contains
A. Instruction Queue
 To speed up program execution, the BIU fetches six instruction bytes a
head of time from the memory.
 Feature of fetching the next instruction while the current (first)
instruction is executing is called Pipelining as shown in figure on the next
slide.
 From figure is seen that the required time for fetching and execution 3
instructions without pipelining is mare than with pipelining.
B. Address Summer
 A dedicated adder which is used to generate the 20 bit physical address
that is output on the address bus.
C. Bus Control Logic
 Control signal for operation such as read/write to memory
D. Segment Registers
E. Instruction Pointers
Cont. . . .
Execution Unit (EU)
 The EU of 8086 tells the BIU from where to fetch instructions or
data, decodes instructions and execute instructions.
 It contains:
1. Control Circuitry
 Control circuitry in the EU directs the internal operations.
2. Instruction Decoder
 A decoder in the EU translates the instructions fetched
from memory into a series of actions which the EU
performs
3. Arithmetic Logic Unit (ALU)
 It can add, subtract, AND, OR, XOR, increment, decrements,
complement and shift binary number.
4. Flag Register
5. General Purpose Registers
6. Pointers and Index Registers
4) Register Organization of 8086
 The 8086 has a powerful set of registers. It includes
 General purpose registers,
 Segment registers,
 Pointers, index registers,
 Flag register.
 The registers organization of 8086 is shown below.
 All registers are 16-bit registers.
Cont. . . . Registers of the 8086/80286
Cont. . . . General Purpose Register
 Has four 16-bit general purpose registers
 labeled as AX (Accumulator Register), BX (Base Register), CX
(Count Register), and DX (Data Register).
 The letter X is used to specify the 16-bit register.
 Each 16-bit general purpose register can be split into two 8-bit
registers.
 The letters L and H specify the lower and the higher bytes of a
particular register.
 For example, the BH means the higher byte (8-bits) of the BX
register and BL means the lower byte (8-bit) of the BX register.
 The general purpose register are either used for
 holding data, variables, intermediate result temporarily.
Cont. . . .

 The Accumulator register (AX) is used as 16-bit accumulator.

 It is used for all
 Input/output operations
 Some arithmetic operations
 String manipulation

 The Base register(BX) is also used as offset storage for generating

physical addresses in case of certain addressing modes.

 The Count register(CX) is also used as a default of counter in case

of string and loop instructions, string manipulation and
shift/rotate instructions.

 Data register(DX) can be used as a port number in I/O operations.

Cont. . . . Segment Registers

 The physical address of the 8086 is 20-bits wide to access 1M

byte memory locations.

 We know that the logical addresses (size of registers in 8086)

are just 16-bits wide.
 How the 20-bits Physical address obtained?
 And how 1Mbyte memory is addressed?
Cont. . . .

The four segment registers are:

 Code Segment (CS) Register
 Data Segment (DS) Register
 Stack Segment (SS) Register
 Extra Segment (ES) Register

 These are used to hold the 16-bits of the starting addresses of

the four memory segments.

 The starting address also called base address or segment

address.
Cont. . . .

Functions of Segment Registers

 The CS register holds the upper 16-bits of the starting address of

the segment from which the BIU is currently fetching the
instruction code byte.

 The SS register is used for the upper 16-bits of the starting

address for the program stack (all stack related instructions will
operate on stack).

 ES register and DS register are used to hold the upper 16-bits of

the starting address of the two memory segments which are used
for data.
Cont. . . .
Cont. . . .
Cont. . . . Pointers and Index Registers

 All segment registers are 16-bit wide.

 But it is necessary to generate 20-bit address (physical address) on the
address bus.
 To get 20-bit physical address one or more pointer or index registers
are associated with each segment register.
 The following pointer registers are associated with the adjacent
segment registers:
 IP (Instruction Pointer) associated with Code (CS) Register
 BP (Base Pointer) associated with Data (DS) Register
 SP (Stack Pointer) associated with Stack (SS) Register
 The Index registers are
 Source Index (SI)
 Destination Index (DI) registers.
• The index registers are used as a general purpose registers as well as for
offset storage in case of indexed, based indexed and relative based
indexed addressing mode.
Cont. . . . Flag Register (FR)

 A flag is a Flip-Flop (FF) which indicates some condition produced

by the execution of an instruction or controls certain operations of
the EU.
 Parity Flag (PF)
 Overflow Flag (OF)
 Carry flag (CF)
 Direction Flag (DF)
 Auxiliary Flag (AF)
 Interrupt enable Flag (IF)
 Zero Flag (ZF)
 Trap Flag (TF)
 Sign Flag (SF)

 The 8086 processor flag register contains (9) flags

 The content of the flag register of 8086 indicate some conditions
produced by the execution of an arithmetic or logic instruction.
 It also control some flag bits the certain operations of the execution unit.
Cont. . . .
Cont. . . .

 Carry flag (CF)

 In the case of addition this flag is set if there is a carry out of the MSB.
 The carry flag also serves as a borrow flag for subtraction. In case of
subtraction it is set when borrow is needed.

 Parity Flag (PF)

 It is set to 1 if result of byte operation or lower byte of the word operation
contains an even number of ones; otherwise it is zero.

 Auxiliary Flag (AF)

 This flag is set if there is an overflow out of bit i.e., carry from lower
nibble to higher nibble (D3 bit to D4 bit).
 This flag is used for BCD operations and it is not available for the
programmer.
Cont. . . .
 Zero Flag (ZF)
 The zero flag sets if the result of operation in ALU is zero and flag resets if
the result is non-zero.
 The zero flag also set if certain register content becomes zero following an
increment or decrement operation of that register.

 Sign Flag (SF)

 After the execution of arithmetic or logical operations, if the MSB of the
result is 1, the sign bit is set. Sign bit 1 indicates the result is negative;
otherwise it is positive.

 Overflow Flag (OF)

 It is set if the result is out of range.
 For addition this flag is set when there is a carry into the MSB and no carry
out of the MSB or vice-versa.
 For subtraction, it is set when the MSB needs a borrow and there is no
borrow from the MSB, or vice-versa.
Cont. . . .

 Trap Flag (TF) :

 Used for on-chip debugging.

 Interrupt enable Flag (IF)

 when this flag is set to 1 CPU reacts to interrupts from external devices.

 Direction Flag (DF)

 Used by some instructions to process data chains, when this flag is set to 0 -
the processing is done forward, when this flag is set to 1 the processing is
done backward.

 Overflow Flag (OF):

 set to 1 when there is a signed overflow
 Simulation
How a CPU Practically Works?
Homework
1. What is memory segmentation? Explain the relation between the
size of the register and the probability of addressing locations?
2. Explain the difference between Intel and AMD CPU and also
describe the historical overview of the respective processor
family.
3. On your computer, open the system information and discuss
what are the following attributes of CPU (processor)
 Logical processor
 Cores
 CPU Speed (GHz, Mhz)

Reading Assignment
 8086 processor pin configuration
31
 ?
THANKS!!

32
Questions
What is the relation between the size of the register and the probability
of addressing locations?

Answer:
• When we have 1 bit, to find the probability of addressing location
number we say that:
• No. of address =2^(no. of bits) = 2^1 =2
• This mean that we have two addresses for 1 bit, the addresses may
be 1 or 0.

 Now if we have two bits???

 We have the following addresses: 2^2=4 addresses

 Now for the 8086 MP, there are 20-bits address bits, so we have the following
locations in memory to be addressed:
2^20 =1,048,576 =1M locations
 The 1Mbyte memory is divided into segments, with maximum size of segments
with 16 Bits (i.e., 2^16) as shown in the calculation below:

 We have 16-bits logical address (because the registers are in 16-bits), so we

have maximum memory size locations which are addressed by 16-bits as below:
2^16 = 65,536

 But in memory system (in binary system) it is written as 64K.

 Achieving 20-bits physical addresses will be discussed later.
 Thus, any location within the segment can be accessed using 16-Bits.
 The 8086 allows only four active segments at a time, as shown in the figure.
 For the selection of four active segments the 16-bit segment registers are
provided by the bus interface unit (BIU) of the 8086.