Fpga Adv WKB 62
Fpga Adv WKB 62
Student Workbook
November 2003
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Table of Contents
TABLE OF CONTENTS
Module 1
FPGA Advantage Basics .....................................................................................1-1
TABLE OF CONTENTS
Module 2
Block Diagram Basics .........................................................................................2-1
Module 3
Finite State Machine Basics ................................................................................3-1
Module 4
Interactive Testing Basics ...................................................................................4-1
Module 5
Synthesis Basics ...................................................................................................5-1
Module 6
Preparing for Testing ..........................................................................................6-1
Module 7
Advanced Troubleshooting .................................................................................7-1
Module 8
Advanced Design Features .................................................................................8-1
Module 9
Synthesis Constraints ..........................................................................................9-1
Module 10
Top-Down Design ..............................................................................................10-1
Module 11
Synthesis Methodology .....................................................................................11-1
Setup_design ...................................................................................................11-18
Add_input_file ................................................................................................11-19
Compile ...........................................................................................................11-20
Synthesize .......................................................................................................11-21
Saving Netlists ................................................................................................11-22
Interactive Reporting Commands ...................................................................11-23
Block-Based Design Script .............................................................................11-24
Double-Click Help Reference .........................................................................11-25
Executing Script Files .....................................................................................11-26
Lab 11: Advanced Synthesis ..........................................................................11-27
Lab 11: Further Synthesis Opportunities ........................................................11-28
Module 12
Verification Methodology .................................................................................12-1
Appendix A
Additional Block Diagram Features .................................................................A-1
Appendix B
HDL Import / HDL2Graphics ..........................................................................B-1
Appendix C
Version Management Using HDL Designer .....................................................C-1
Appendix D
Packages ..............................................................................................................D-1
This document is the Designing with FPGA Advantage V6.2 training workbook, which instructs in the
concepts necessary for efficient use of the Mentor Graphics FPGA Advantage tool set (HDL Designer,
ModelSim, Leonardo Spectrum) when designing FPGAs.
Audience
The information in this course is intended for FPGA designers who will use the FPGA Advantage tools
to design and test FPGAs and who have the prerequisite knowledge specified below.
• An exhaustive examination of the individual applications. Instead, this course focuses on using
the FPGA Advantage tools in a design flow.
Prerequisite Knowledge
• Students should have the ability to read, write, and understand simple HDL code fragments
• Students should understand basic schematic capture, digital simulation, and FPGA design
concepts.
• Students should be able to create simple schematic designs from a text specification.
Software Compatibility
This training is designed to work with FPGA Advantage V6.2. While the basic concepts will work with
later releases, the various graphic user interfaces and some flow processes may change.
Documentation Compatibility
In every lab session, students may look at the online documentation to get additional information. The
online documents can be read using Acrobat Reader.
Lab Solutions
There are no explicit solutions provided since all Design Units of the Labs 1 to 10 are included in the
RTC design, which is provided in the training data. If solutions are needed, simply map the RTC
Library and copy the corresponding Design Units.
MyTestLib
Another FPGA Advantage library. This library has been mapped via the FPGAdv_Training.hdp file,
and does appear in the Regular Library window.
TEXT
Another FPGA Advantage library. This library has not been mapped via the HDS.ini file, and does
appear in the Regular Library window. It contains an example for TextIO usage in testbenches.
RTC
An FPGA Advantage library. This library is unmapped at the beginning of the first lab, and as such will
not appear in the Regular Library window. It holds the complete RTC design used in Labs 11-13.
Lab_Templates
An FPGA Advantage library. This library has been mapped via the FPGAdv_Training.hdp file, and
does appear in the Regular Library window. It holds templates and Design Units for Labs 6 and 8.
FPGAdv_Training.hdp
An initialization file for the HDL Designer tool. This file contains library mappings used by FPGA
Advantage. The file FPGAdv_Training.hdp-full holds all mappings needed for the training.
Timeline Table
When delivering the training class in four days it is very important to follow the timeline, especially
during the labs. 12 modules in four days means 3 modules per day. Ideally.
In reality at the end of day 1 three modules may not be covered until end of Lab 3 due to the extensive
module 1 and also the first lab, where students need to play around a little.
Table 1. 1
Lab Duration your Lab Begin Lab End
in minutes Duration
1 60
2 45
3 45
4 70
5 50
6 70
7 90
8 40
9 60
10 60
11 60
12 70
Objectives
This module will cover the following topics:
1-2 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
HDL Designer is key in the following design methodology.
The designer will create the design description with HDL Designer, creating block
diagrams, state machines, flow charts, truth tables, and HDL code to describe the
design. From HDL Designer the designer will generate HDL to feed the rest of the
design flow.
The HDL will be simulated with ModelSim first to verify the functionality of the
design.
Once the functionality is correct the designer will then synthesize the design with
Precision RTL to implement the design in the target technology.
Once the synthesis process has been completed the designer will take the netlist
from synthesis and use vendor place and route tools to implement the design for
the actual device.
After this process has completed the designer will take the netlist and SDF timing
file from the place and route process and designate in HDL Designer the gate level
netlist as new design view to the toplevel design unit.
Then ModelSim is used again with the same testbench as used for functional
verification to verify the real timing of the chip at the gate level.
1-3 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation
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The FPGA Advantage 6.1 software includes also the synthesis tool Leonardo
Spectrum 2003.a. Existing users of Leonardo Spectrum can still use Spectrum as
synthesis tool. The documentation in this training workbook is based on Precision
RTL as synthesis tool, which does not mean that it is not possible to use Leonardo
Spectrum for synthesis with FPGA Advantage.
1-4 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation
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HDL Designer is a graphical design capture tool that allows designers to create
ASIC and FPGA designs using graphical techniques. Designers need only little
HDL knowledge to create very good designs quickly and easily. HDL Designer
executes on the Windows, Linux and UNIX platform and generates VHDL or
Verilog HDL descriptions from the graphical design input. The design is captured
graphically using blocks, graphical state machines, flowcharts, and truth tables.
These graphical descriptions are automatically converted to fast efficient HDL
descriptions.
Notes:
1-6 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation
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The typical procedure for creating a design within HDL Designer will be as shown
by this flow diagram. A new design unit will be created within HDL Designer by
opening a block diagram. The designer will then create the behavior of the unit by
placing blocks on the block diagram and connecting the blocks with signals and
busses. Next the behavior of each block is created with another block diagram,
state machine, truth table, flow chart, or HDL code. The design is saved and HDL
code generated from the design. Once the HDL generation process completes
satisfactorily the design is compiled for downstream tools such as ModelSim,
Precision RTL, or Design Compiler.
Simulation Synthesis
1-7 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation
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What is ModelSim? It is a direct compiled VHDL/Verilog simulator. Direct
compiled means that it does not convert HDL to C/C++ and compile the C/C++
with a C compiler. Instead ModelSim generates the machine code directly from
the compiler. This provides the benefits of much faster compilation and some
speedup in runtime. ModelSim complies with VHDL and Verilog standards
including VITAL, Numeric Standard Math packages, VHDL93, SDF3.0, VITAL
2000 IEEE 1364, and PLI. ModelSim has a single kernel that executes both VHDL
and Verilog files or mixed VHDL/Verilog designs. This allows part of the design
to be in Verilog and part in VHDL. The single kernel allows VHDL to be called
from Verilog or Verilog to be called from VHDL. ModelSim also has a foreign
language interface to allow linking other C/C++ models into the simulation.
Simulation Synthesis
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Design
1
" VHDL
Verilog
Test
Bench
2 "
VHDL
Verilog
3
ModelSim
"
EDIF
2. Capture Test Bench
3. Simulate RTL Design
4 7 4. Synthesize and Optimize Design
"
5. Place and Route Design
6
FPGA Vendor HDL 6. Generate Back-annotated VHDL
Place and Route Vital + SDF
7. Simulate Design with timing
5
EDIF
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Status Bar
Shortcut Bar
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The design manager window is displayed when you invoke any HDL Designer
Series tool. The design manager window normally remains open throughout your
working session and cannot be closed. If the design manager is hidden below
other windows it can be popped to the top by choosing Design Manager from the
File menu in any graphic editor or DesignPad window.
• Tool Bar: The most commonly used commands are available from toolbars
in each window. Four toolbars are normally displayed in the design
• Shortcut Bar: The shortcut bar provides quick access shortcuts for
common setup operations, design explorer operations, tasks and
viewpoints.
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When a HDL Designer Series tool is invoked for the first time, the default library
mapping project files (examples.hdp and shared.hdp) are loaded and shown in the
non-scrolling area of the project manager in the source browser Project tab.
A regular library contains graphical or HDL text source design objects. HDL can
be generated from the graphical objects and all design objects can be compiled.
The library mappings for a regular library includes separate locations for the
graphical or HDL text objects, one or more mappings for downstream data and
may also include version management mappings.
defining standard HDL types. The library mappings for a protected library
includes locations for the graphical or HDL text objects but no mappings for
downstream data or version management.
Notes:
The "My project" examples.hdp file stores library mapping information for the
default HDS examples project which includes an empty scratch library, example
designs and libraries containing support packages.
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The shared.hdp file stores mapping for the ModuleWare component library and
standard VHDL packages. The libraries defined in this file are intended for shared
use and are usually maintained by a team or project administrator in multi-user
installations.
Concept of Library/Unit/View
Concept of Library/Unit/View
HDL Designer is built on a concept of Library/Unit/View.
♦ This is analogous to the structure of Library/Entity/Architecture in
VHDL.
♦ There can only be one interface per Design Unit. Therefore, there can
only be one Design Unit of a given name per Library.
♦ There may be multiple views per Unit. The same View name may be
used in different Units.
♦ To use the same Unit name with a different interface, the new Unit
must be stored in a different Library.
library $ x $
y
unit a b a a
Notes:
1. Save
HDL Designer
Design Data Directory
contains graphical data,
side data & meta data
2. Generate directory structure
(for graphical views)
3. Compile
Downstream Data Directories
any number of downstream
directories for tasks which
require working directories
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[ModelSim] Optional
Mappings
[Precision] - Downstream Data Directories
[Leonardo]
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Downstream
Mapping
(tool dependent)
HDL Designer
Design Data
Mapping
Library Type
Shared Mapping
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It is possible to edit the mappings of an existing library, but in order to do this the
library must not be ëactive'.
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The Design Units mode displays the design partitioned into design units
containing the source graphical or HDL text views.
The right pane of the Design Explorer can be used to show the hierarchy beneath
any of the design objects shown in the content pane.
♦ Represents graphical
Library and text components as
Design Units
! Shows logical content
down to leaf-level
! Hierarchy shown in
separate pane
Views
♦ Shortcuts:
! Drag ‘n drop
Design Units
! Expand/Collapse:
<space>
! Show/Hide Hierarchy:
< ctrl>+<space>
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The Design Units mode displays the design partitioned into design units
containing the source graphical or HDL text views. This is the default mode.
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The HDL Files mode displays all the HDL files in the design including source
HDL text views and the HDL text generated from graphical views. Source HDL
text views are prefixed by an icon S in HDL Files mode. All other views are
generated files which should not be directly edited and are normally opened read-
only.
All commands used in this mode operate directly on the HDL files which may
contain multiple design objects. For example, deleting a single file, deletes all
design objects defined within that file.
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The hierarchy below the top level design unit is shown in the right pane of the
design explorer by default. You can display hierarchy below any selected design
object by choosing Show Hierarchy from the Edit or popup menu, using the +
shortcut key or by dragging the object to the Design Hierarchy pane.
You can hide or show the hierarchy pane by setting Design Hierarchy in the
SubWindows cascade of the View menu or popup menu and hide it by choosing
Hide Design Hierarchy Window in the hierarchy pane popup menu.
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Icon Reference Page 1
For the complete reference browse to: "HDL Designer Series User Manual >
Design Explorer Notation"
♦ Unknown DU
♦ Unknown view
1-27 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation
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Icon Reference Page 2
For a complete reference browse to: "HDL Designer Series User Manual > Design
Explorer Notation"
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You can select objects in the source browser, side data browser or downstream
browser by clicking the left mouse button with the cursor over its icon or name.
You can move a design unit or a design unit view in the design explorer by
dragging with the left or right mouse button.
You can copy any design unit or a design unit view in the design explorer by
dragging with the right mouse button or the Ctrl + left mouse buttons.
When you use the right mouse button, a popup menu is displayed which includes
Copy Here option to make a copy at the position of the cursor and a Cancel
option to abort the operation.
♦ Design Data
! This part is used by HDS to store
some data that may be needed later
– edif file generated by CoreGen
– simulation result files
– sdf back-annotation file for gate
level simulation
– Tcl generated scripts
♦ User Data
! Reserved for the designer to store any kind of
design relative data
! Folders and sub-folders can be created by the user
! File can be copied or referenced
♦ The Side Data contents can be optionally versioned with the
source data
1-29 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation
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The side data browser displays the contents of the Design Data and User Data
directories which contain side data corresponding to the design unit view selected
in the design explorer (or corresponding to the default view when a design unit is
selected).
The side data browser can be displayed or hidden by setting Side Data in the
SubWindows cascade of the View or popup menu.
Downstream SubWindow
Downstream SubWindow
View → SubWindows → Downstream
♦ It is tool dependent.
Use tabs to switch between
downstream tool data
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The downstream browser displays the contents of the compiled library directories
corresponding to the design data libraries currently open in the design explorer.
Resource Settings
Resource Settings
The Resource setting allows the user:
1. To set his design environment (text editor, 3rd party tools,…)
2. To define his graphical environment
3. To control the code generation to stick to the in-house coding style
♦ Tool Settings
! Compiler, Simulator, Synthesizer, Custom tools...
♦ General Preferences
! Text Editor, Check, Save, ...
♦ Editors
! Block Diagram, State Machine, Flow Chart, Truth Table, Symbol
♦ Code generation
! VHDL, Verilog
♦ Two levels of Resources:
! User Resources
! Team Resources
1-31 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
The HDL Designer Series supports user resources which can be set by each
individual user and team resources which are shared by all members of a team
working on the same project.
1-32 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation
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The Main Settings dialog box is displayed when you choose Main from the
Options menu in any window.
1-33 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation
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The Text tab of the Main Settings dialog box provides preferences for choosing
the editor and viewer used for HDL text views. The default editor and viewer are
set to use the built-in DesignPad text editor. However, you can choose from a
dropdown list of alternative supported editors and use the Setup buttons to modify
the editor or viewer commands used to invoke these tools.
1-34 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation
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You can set user-defined internal variables by using the User Variables tab of the
Main Settings dialog box.
A number of default user variables are defined to specify the executable directory
pathname used by the default tasks to invoke downstream tools:
• task_NC-SimPath NC-Sim
• task_PrecisionRTLPath Precision Synthesis
• task_VCSPath VCS
Code Generation
Code Generation
♦ HDL File naming convention
! Based on the file type (entity, architecture, package, …)
! Split or combined
! Case control
! ...
♦ Coding style setting
! Keyword case control
! indentation
! ...
♦ HDL Generation options
! Language dependent, Script creation process
♦ The coding style can also be controlled from the editors (eg:
SM coding style) to abide by the Corporate standards as much
as possible
♦ The HDL code generation can be interrupted by holding down
the Esc key (only on Windows, not on Unix).
1-35 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation
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Options → VHDL...
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Options → VHDL...
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Options → Verilog...
1-38 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation
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Resource Settings
Resource Settings
User Resource Settings
1. Location specified by the -user_home command line switch if set.
2. Location specified by the HDS_USER_HOME environment variable if set.
3. The current working directory when the tool is invoked if found.
4. The user directory ($HOME on UNIX and Linux or user profile on
Windows) if found.
1-39 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
The HDL Designer Series supports user resources which can be set by each
individual user and team resources which are shared by all members of a team
working on the same project. When you invoke a HDL Designer Series tool for
the first time, Single User mode is set by default and only the user resources are
read. When this mode is set, the task manager and template manager display all
the available tasks and templates under My Tasks and My Templates nodes. You
can set Team Member mode and when this mode is set, you can also browse for
the location of the team preferences directory. When team member operating
mode is set, the task and template managers display tasks and templates under
separate My Tasks, Team Tasks, My Templates and Team Templates nodes.
If you have write access to the team resources directory location, you can set the
Team Administrator mode. This mode allows you to save tasks and templates as
shared team resources.
You must restart the application after changing between single user and team
member operating mode.
1-40 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation
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Several Wizards and predefined Tasks explained on the next pages will guide
you through the HDL Designer Flow.
Open a different
existing project
Create a new
project, which then
launches New
Project Wizard
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Directions
• Part 1: Setup the Design environment
o Invoke FPGA Advantage
o HDL Designer asks at startup which Project to load. Specify the first
option to “Continue with Project FPGAdv_Training.hdp”.
This will help you to concentrate on the design libraries to work with.
• Use the pulldown menu item Options > VHDL and click on the
Default Packages Tab. Delete the entries for unwanted package
entries and add the ieee.NUMERIC_STD package by clicking on the
ieee Library in the left pane and afterwards on the NUMERIC_STD
package in the right pane. Then confirm with a click on the Add
button.
OK the dialog box.
• The Design Hierarchy window allows you to see the whole design
hierarchy. At the moment you can only see the testbench itself in this
window. To see the full design hierarchy, simply select the
BCDCounter_tb unit in the Design Hierarchy window and click
the button in the Task Bar.
In this portion of the lab, you will create a new library mapping
called XYZLib that will contain a generic BCD Counter design.
• Switch back to the Project Manager usig the Project tab at the
bottom of the Design Explorer window.
• Click Next for the final step, defining the new library as default.
Then click Finish to complete the new library definition.
• Part 2: Get familiar with the design, browse the Design and Testbench
o Switch back to the library MyTestLib (use tab at the bottom). The
design hierarchy window displays the state exactly as it was before the
XYZLib was mapped. Hit "F5" (Refresh) and it will display correctly.
Close the flow chart editor window, but leave the block diagram
editor window open.
In the Design Explorer window at the Design Unit pane , select the
BCDCounter_tb object (which should have a yellow triangle in
front of the name). Select the pulldown menu item
Tasks > Generate > Run through components.
A Log Window will appear informing you of the status of the HDL
generation. For this lab, the HDL should generate without any errors.
To see the generated HDL files change the display mode at the
Design Units window. Use pulldown menu item
View > Mode > HDL Files. Note the presence of VHDL files for
both the BCDCounter_tb and BCDCounter_tester design objects.
Note that the HDL can also be generated by invoking ModelSim via
the Simulation Flow icon from the Design Explorer toolbar.
This will pop up a source window. View the Log Window to look for
any errors that occurred during the simulation run.
View the ModelSim Main Window for messages and the Wave
Window for the correct results.
Quit ModelSim.
o Click on the RTL Schematic icon to see the RTL circuitry generated
by Precision RTL.
o Now do the same thing with the Technology Schematic icon and try to
figure out the similarities/differences between the two views.
o To get information about the device utilization use the Area Report
file. To open it simply doubleclick in “Area Report” in the “Project
Files” window pane.
o To check whether the desired clock frequency is achieved you can use
the Timing Report. Is the specified clock frequency (100 MHz) met?
o When you are ready quit Precision RTL. Do not save project settings.
o Select the ModelSim tab and select the XYZLib library. Use
RMB > Expand All to see all the various files generated by ModelSim
Objectives
This module will cover the following topics:
♦ Advantages
! Can generate new blocks quickly
! Can use pre-defined blocks
! Underlying hierarchy/functionality can be defined later
! Each block can contain multiple and/or concurrent views
! Block interface defined “on the fly”
! Signal width defined in context
2-2 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
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2-3 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
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Here is shown the Block Editor Main Window. The user will place components,
blocks, input, and output ports in the window and then connect these together with
signals and busses. The block editor also contains some interesting features such
as Global Connectors, which connect to all blocks. This makes routing the signals
much easier. As signals and busses are added to the diagram these signals and
busses appear in the declarations for that unit, making it easier to see the signal
names and types. Other items that can be added to a block diagram include
comments and generics. Comments can be attached to specific items so that they
appear with that item in the generated HDL code. Generics can be used to control
the size of items for configurable units. When the block diagram is completed
HDL can be generated from the blocks and interconnections.
2-4 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
The Block Diagram Editor is very useful for creating a quick block level
description of a device. It is the tool that allows engineers to create usable
diagrams similar to the ones drawn on napkins at restaurants. Blocks do not need
to have well defined interfaces before they are placed within a block diagram. As
each block of the diagram is specified the interface is implied from the signals
connecting to the block. When specifying the behavior of the blocks in the
diagram, the interface for the lower level blocks can be inferred by the
connections of the higher level block diagram. The block diagram allows the user
to quickly specify the inputs, outputs, and block interconnect to build the device.
If the block diagram is done correctly it can give the user a good dataflow view of
the device. Block Diagrams can also be created from existing HDL code so that
the existing dataflow can be more easily seen.
! Block Objects
– Blocks
– Embedded Blocks
– Components
! Signal Objects
– Signals (one bit)
– Busses (multi-bit)
– Bundles (grouped signals)
! Port Objects
– Ports (In/Out/InOut/Buffer)
– Global Connectors
2-5 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
A user creating a block diagram can use either the toolbar buttons, or the Add
menu to add items to the block diagram. As can be seen from the Add menu the
items that can be placed on a block diagram include Blocks, Components, Signals,
Busses, Bundles, HDL Text, Global Connectors, and different types of ports.
Notes:
As already mentioned the types of blocks that can be placed in a block diagram are
Blocks and Components. Blocks have a very fluid interface that can easily be
changed by adding or removing a signal from the border of the Block.
Components have a more fixed interface. Components can be reused over and
over in lots of different block diagrams while blocks only appear where they are
defined. Blocks can be easily turned into a component.
2-7 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
An embedded view is saved as part of the block diagram or IBD view on which it
is instantiated and does not create a separate design unit. When HDL is generated,
concurrent code is generated for the embedded view in the same files as the
structural description of the design unit. An embedded view has an interface
described by the signals connected to the embedded block which represents it on
the block diagram or IBD view. An embedded block looks very similar to a block
but has no library name since it is always in the same name space as the view.
However, it does have a unique name and a number which determines the relative
ordering when there are multiple unconnected embedded blocks in the generated
HDL.
Block:
- Fluid Interface
- Library/Block/Instance names
Block Component:
- Fixed Interface
- Library/Comp./Instance names
Component - Moduleware Component
[External IP]
Embedded Block - External HDL
- Compiled outside
Embedded Block:
- No hierarchy created
Frame - Any view including HDL
Frames:
- For multiple instances
Enter HDL - For conditional structures
- For PORT MAPS
Context added automatically when necessary
2-8 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Signal
! Scalar values
! Recommend std_logic type
– ‘0’, ‘1’ for Synthesis
♦ Bus
! Vector array
! Recommend unsigned type
– “00100110” for Synthesis
♦ Bundle
! Vector of Signals and Busses
! Type is array of signal object names
! Useful for connecting similar signals
– Example: Control Signals
2-9 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Signals and busses provide the connection information within the block diagram
editor. Signals are scalar objects of a particular type such as std_logic or boolean.
Busses can be complex objects including arrays that include more than one signal.
These are typically unsigned, signed, or std_logic_vector. Bundles are a special
object that allow the designer to group a number of signals together to be treated
as a single object.
♦ Input Port
! Passes signals/busses from higher
level of design hierarchy
♦ Output Port
! Passes signals/busses to higher
level of design hierarchy
♦ InOut Port, Buffer Port
! Combines Input and Output Port
! Discourage use with Synthesis
♦ Global Connector
! Connects signal to all blocks on
same level of design
! Useful for global resets, clocks, etc.
2-10 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Ports are used to provide the interface information to other units. Ports specify the
name of the port to allow connection by name and also the type of the ports so that
consistency of information passing is achieved.
The types of ports include input ports, output ports which pass information only
one way, and inout ports which pass information both ways. Buffer ports are a
special case of an inout port that only allows one driver but makes it easier to read
output values. The only danger with buffer ports is that once used they have to be
used everywhere in the hierarchy on that signal. Global ports are very useful for
signals that connect to all blocks, such as clocks, VCC, GND, etc.
Add → ...
Signal stubs
Signal
Bus
Bundle
In Port
Out Port
Inout Port
Buffer Port
Global Connector
Signal : Scalar
Bus : Vector
Bundle : Arbitrary grouping of signals
Global connector : Common to blocks (incl. Embedded)
2-11 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Object Properties
Object Properties
♦ Object Properties: Textual information attached to a specific
object.
! Can belong to design objects, or to design view itself
! Different types of objects have different types of properties
! All HDL Designer Design View objects have properties
! Properties have various attributes:
– E.G.; Visibility - Whether or not property is displayed in editor
window
♦ Examples:
! Blocks
– Library, Name, and Instance Name
! Signals
– Name and Type
! Block Diagram
– Declarations
2-12 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
2-13 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
2-14 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Master
! Design Browser Pulldown:
– Options > Edit Master Preferences > Block Diagram…
! Settings for ALL Diagrams
2-15 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
You can set block diagram preferences by choosing Block Diagram from the
Master Preferences cascade of the Options menu in the design browser. Block
diagram master preferences take effect on the next block diagram you create.
However you can apply the current master preferences to an active diagram by
choosing Apply to Existing Objects or Apply to New and Existing Objects from
the Master Preferences cascade of the Options menu in the diagram.
2-16 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
You can set the appearance and signal visibility preferences for the active block
diagram by choosing Diagram Preferences from the Options menu in the block
diagram editor. When you edit these preferences for the active diagram, the dialog
box allows you to choose whether the preferences are applied to new objects or to
both new and existing objects in the diagram. You can save the preferences for the
active diagram as master preferences by choosing Update from Diagram in the
Master Preferences cascade of the Options menu.
Notes:
Creating a block diagram is similar to schematic editing when using components.
Components are placed and then wired together. When using blocks instead of
components however there are some differences. Components have a predefined
interface while blocks do not. Blocks gain their interface by the signals that are
connected to them. Blocks are not selected from a component library, they are
defined on the fly. Once all of the signals that connect to a block have their names
and types specified the block interface is defined. The interface can be changed
later as needed by adding or removing signals.
2-18 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Instantiating Blocks
Instantiating Blocks
♦ “Ghost” of block guides placement
♦ Keep placing blocks until RMB
♦ Block shape can be modified as
needed
♦ No interface information needed at
instantiation!
♦ Library and instance designations
added automatically
♦ Block may be “promoted” to a
Component
! Create Block
! Route Signals/Busses
! Object Properties…
– Convert to Component
! Edit Component Symbol
2-19 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
If you do not change the instance name, each block is given a unique instance
name by adding an integer to the default name (for example, I1, I2, I3). The
default base instance name for new blocks can be changed by setting a preference.
Each block must have a unique block name and instance name. However, a block
can be re-used as a component (with the same component name as the defining
block) but the instance name must be unique across all blocks and components in
the design.
The block and instance name cannot be the same when you are using VHDL but
can be given the same name if you are using Verilog.
Instantiating Components
Instantiating Components
♦ When the Add Component
command is selected the
Component Browser invokes
♦ Specify:
! Library
! Design Unit
! View
♦ Placed Component may be edited,
but only appearance changes
allowed (instance specific)
♦ Most editing done in Symbol Editor,
changes apply to ALL instances
♦ Interface is pre-defined by Symbol
♦ Components can not be converted
back to Blocks!
2-20 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
When you add a component, the component browser is displayed which allows
you to choose a component (including ModuleWare components and components
you have created) from an existing library and drag an instance of the component
on to a block diagram or IBD view.
If the instantiated component references any VHDL packages which are not
already referenced on the diagram, you are prompted whether to add them.
If you do not change the instance name, each new component is given a unique
instance name by adding an integer to the default name. For example, (I1, I2,
I3...). The default base instance name for a component is the same as for a new
block and can be changed by setting preferences.
2-21 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
You can add HDL text as an embedded view on a block diagram by adding an
embedded block and choosing Text from the Create Embedded View dialog box.
A default HDL text box is added on the block diagram with a comment line
containing the embedded block name and number.
You can edit the HDL text by double-clicking on the text to open a text edit box or
by using the Text tab of the Object Properties dialog box. Any valid HDL
statements for the hardware description language in use can be entered in free
format (including line breaks and indentation which are preserved on the diagram)
but each statement must be terminated by a semi-colon.
Routing Signals
Routing Signals
♦ Toolbar Icons:
! Signal
! Bus
! Bundle
♦ Other Methods:
! Pulldown: Add > Signal | Bus | Bundle
2-22 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Process:
! Select Design Browser Window
! Choose Pulldown:
– Options > Edit Master Preferences > Block Diagram...
! Choose Default Values Tab
! Make Changes
2-23 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
2-24 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Ripping From a Bus
You can rip part or all of a bus by adding a new signal or bus starting from any
point on the bus. The new net segment has the same name and properties as the
source bus. However, you can use the Object Properties dialog box to edit the use
properties (including the style, slice or element and visibility) for the ripped
segment.
Do not attempt to change the name of a ripped signal or connect a slice or element
of a bus directly to an output port. However, you can use embedded HDL text to
assign the slice or element to an alternative output signal.
♦ Connecting to Components
! Start or finish on Component “pin”
! Signal direction assigned by interface
! Signal name assigned by interface if not
previously named
! Signal type assigned by interface
2-25 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
2-26 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Signals or buses can be individually connected to a block or component by
dragging with the Left mouse button over the body of a block or over an existing
port or port map frame on a component.
You can also make a connection by overlapping a block or component with the
dangling net connectors on the end of existing signals or buses and then choosing
Connect from the Diagram or popup menus. This can be useful when you have
created a new child block diagram and want to add a block or component
connected to the nets created when the child diagram is initialized.
2-27 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
The template title block is read from the TitleBlock.tmpl file in the
../resources/misc installation subdirectory. However, you can set an alternative
location for the template in your general editing preferences.
The current template title block is automatically included at the lower right side on
a new diagram (including concurrent and hierarchical diagrams) when you create
a new graphic editor view unless this option is unset in your general editing
preferences. Note that the title block text can be included in the generated HDL by
choosing Include in HDL from the popup menu.
You can create your own title block template by grouping one or more comment
texts (which may optionally include internal variables) and choosing Save Title
Block from the File menu to save the title block at the location specified in your
preferences. For example, the default title block comprises ten grouped comment
texts and uses the internal variables %(library), %(unit), %(view), %(user), %(dd)
%(month) and %(year) for the library, design unit, design unit view, username and
modified date.
Adding Comments
Adding Comments
2-28 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
You can use the text tool button or choose Comment Text from the Add menu to
add comment text as annotation on a block diagram, flow chart, state diagram or
symbol. The cursor changes to a cross-hair which allows you to open a text entry
box by clicking at an empty location anywhere on the diagram and enter free-
format text. Any line feeds or blank lines you enter are preserved on the diagram.
The text edit box has its own scroll bars which allow the text to be scrolled
horizontally or vertically while editing.
2-29 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
You can associate comment text with the interface to a block by selecting the In
Block Interface cascade option and attaching the anchor to a block. When this
option is used, the note is included as comments in the generated VHDL entity or
Verilog module for the block. If the block is subsequently converted to a
component, any block interface comments are moved into the symbol for the
component. Any comments added before or after a block object are included
before or after the instantiation statement for the parent diagram.
You can also associate comment text with the diagram itself by selecting the At
File Start, After File Header or At File End cascade option. Comment text
attached in this way is included as comments at the specified position in the
generated HDL for the diagram.
Graphical Comments
Graphical Comments
♦ Custom Symbol Creation
! eg no longer restricted to
rectangles and common
gate symbols (and, or, alu,
mux)
♦ Comment Graphics
! adds common drawing
features to HDL Designer
diagrams
♦ Panels
! Define named areas on
diagram
! Can be dragged as OLE
! Can be printed
2-30 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
You can add comment graphics on a block diagram, flow chart, state diagram or
symbol by choosing Comment Graphics from the Add menu. The cascade menu
provides the following commands:
2-31 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
After the blocks have been placed, the signals and busses interconnected, the
concurrent statements specified, and the packages declared the design can be
saved in the library. When the save menu is selected the following dialog box will
appear. Select the library to save to, the Design Unit name, and the View name.
For Block Diagrams, Truth Tables, and Flow Charts the view names will default
to a reasonable name. For the VHDL Architectures and Verilog Modules the
designer should generate a reasonable name.
♦ Consistent presentation
♦ Enough information to
understand quickly
♦ Example:
! Interface signals are set off
from main circuit
! Signal and bus types
shown in interface portion
! Signal and bus types
hidden in main diagram
! Title Block separates
functionality from definition
2-32 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
2-33 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Note: for the labs in this training material, use type std_logic for single-bit signals
and unsigned for multiple-bit busses. To set the default signal types click in the
Design Manager’s main window on Options > Master Prefs > Block Diagram.
Choose the Default Values Tab and enter the values. All signals are active-high
unless otherwise noted.
Directions
• Part 1: Create a new block diagram within the XYZLib library called
BCDRegister.
o Look at the design hierarchy for the BCDRegister part in the Design
Explorer. What do you see?
o Is there an HDL file for the BCDRegister in the HDL Files view mode
in the Design Explorer window?
Why or why not?
________________________________________________________
________________________________________________________
carry_out_ones
std_logic
q_ones
unsigned(3:0)
reset clear
std_logic
q
load_in_ones load_in
unsigned(3:0)
XYZLib
cnten_ones cnten BCDCounter
std_logic
XYZLib Ones
BCDRegControl load_ones load spec
I2 std_logic carry_out
clk
std_logic data_out
unsigned(7:0)
load_en ripple_out
std_logic std_logic
clk_tens clk
std_logic
carry_out_tens
std_logic
q_tens
unsigned(3:0)
Project: FPGAdv_Training
<company name>
The BCD Register implements a cascadable
Title: BCDRegister Block Diagram two digit BCD Counter with reset and load
Path: XYZLib/BCDRegister/struct functionality.
Edited: by lynneh on 04 Nov 2003
Objectives
This module will cover the following topics:
Storage
Mealy
Combinational
Φ Clock
Inputs
Next Current
Output
state state
Input Output
Inputs Forming Forming
Logic Logic
Storage Combinational
3-2 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
The outputs of a Moore state machine are a function of its state only, therefore the
outputs only change if the state changes. However, if a Moore state contains an
assignment to an input signal, the state machine has an input dependency and its
outputs are a function of both the state and the inputs, that is it will have Mealy
behavior.
The outputs of a Mealy state machine are a function of its current state and inputs.
Changing the input has a corresponding affect on the outputs. When an input
condition is satisfied, a Mealy state machine performs specified actions, such as
changing the values of outputs and transitions from one state to another.
Output assignment
in the states
Moore Mealy
Mixed
Output assignment
in the transitions
Output assignment
in both states and
transitions
3-3 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Start state
State
condition Transition
Interrupt point
Link
priority
Junction
action
Link : to a state (incl. Hier) or to a junction
Junction : to simplify by factoring transitions
Interrupt : Applies to all states
Normal state Hierarchical state
State : of Start, Normal or Hierarchical types
3-4 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
The start state is the initial state of the state machine. Only one start state can exist
in any state machine. The start state may have associated state actions.
A simple state represents observable status that the state machine can exhibit at a
point in time. A simple state may have associated state actions.
Exit point
3-5 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
A state machine may comprise a number of hierarchical state diagrams. Each child
state diagram is represented by a hierarchical state in its parent diagram. You can
open down into a child state diagram by double-clicking on a hierarchical state or
by choosing Open Down from the Open cascade of the File menu (or popup
menu) to explicitly open the selected hierarchical state. A new child state diagram
is created and opened for edit if it does not already exist. A newly created child
state diagram comprises an entry point, a single state and an exit point connected
by transitions. You can edit a hierarchical state diagram in the same way as any
other state diagram including more hierarchical states as well as any other state
diagram objects (with the exception of interrupt points).
3-6 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
A wait state can be used to implement a multi-cycle wait in a synchronous state
machine. The number of clock cycles to wait for is specified in the state object
properties and is applied when the TIMEOUT pre-condition is used for a
transition exiting the wait state. The TIMEOUT pre-condition can be used on its
own to implement a simple delay or if enabled when a regular condition is
entered, it is ANDed with the condition. A wait state can have more than one exit
transitions. If the TIMEOUT pre-condition is unset for any of these transitions, the
state may be exited via this transition before the timeout has expired.
3-7 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
A separate timeout signal is generated for each concurrent state machine using the
form: <machine_name>_timeout
Local counter signals which are used by all wait states in the concurrent state
machines are generated using the form: <machine_name>_timer and
<machine_name>_next_timer
An entry flag is generated for each wait state using the form:
<machine_name>_to_<state_name>
If all the wait states in a concurrent state machine use integer wait values, the
VHDL signal types default to std_logic (or std_logic_vector) and have the width
required for the largest wait value. If any wait state has a parameterized (non-
integer) value, the scalar type, vector type and bounds of the timeout, counter and
entry flag signals must be specified.
Re-Leveling
Re-Leveling
3-8 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Adding hierarchy replaces the selected states by a new hierarchical state and
moves the selected states into the child hierarchical state diagram.
Removing hierarchy deletes the selected hierarchical state and replaces it by the
objects in the child hierarchical state diagram. The relative placement of the new
objects is preserved and centered on the original position of the hierarchical state.
They may therefore overlap existing objects on the parent diagram. If the child
diagram included other hierarchical states, their hierarchy is retained but can be
removed by another re-level operation.
Comments
Comments
3-9 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
WHEN s1 =>
CASE din(0) IS
WHEN '1' =>
next_state <= s3;
WHEN '0' =>
next_state <= s0;
Output assignment WHEN OTHERS =>
next_state <= s1;
END CASE;
3-10 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
A CASE style transition typically produces in a faster, parallel, multiplex-based
circuit whereas an IF style transition produces a serial, priority decoder-based
circuit. Also, more efficient decoding can often be achieved by concatenating
together signals of similar type and decoding the resulting concatenated variable
rather than each signal individually.
You can set decode options for the CASE style transitions leaving a state by using
the button on the States tab of the Object Properties dialog box in a state diagram
to display the CASE Settings dialog box.
The dialog box allows you to enter a CASE selector expression. You can then
enter expressions for each branch as object properties for the transitions leaving
the state. For example, the selector expression might be sigA & sigB with branch
expressions "00" and "01" | "11" on transitions leaving the state.
3-11 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
3-12 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Context Definition
Context Definition
Diagram → Package References...
Just double-click on
the Package List
3-13 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
3-14 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
3-15 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
For a synchronous state machine, you can enter the clock signal or choose from a
dropdown list of available input signals and choose the clock Edge sensitivity. For
a Verilog view, you can choose Rising or Falling. For a VHDL view, you can
choose Rising, Falling, Rising Last, Falling Last, Rising Edge or Falling Edge.
Alternatively for either language, you can choose Specify to enter any other valid
Condition. Refer to Clock Edge Expressions for more information about detecting
clock edges.
specify any additional signals required in the sensitivity list using the Sensitivity
entry box. (Multiple signals should be separated by an or operator.)
3 Processes
– Clocked
– Nextstate Merged with
– Output 2 Processes
3-16 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
You can specify whether HDL is generated using If, One-Hot or Case styles.
However, the One-Hot style is not available when using VHDL unless Hard state
machine encoding is selected in the encoding tab of the dialog box. By default,
three separate VHDL processes representing the clocked, next state and output
assignments are generated. However, you can choose to combine the
combinatorial outputs into the next state process by choosing the 2 Processes
options.
When you are using VHDL, you can set a state variable for the state machine by
automatically generating a type, specifying a type or choosing an output signal
port which describes the current state of the state machine in terms of an
enumerated type or constant value. The specified type can be one of the standard
predefined types or a type defined in a VHDL package.
If you choose Assign value to output port, you can choose from a dropdown list of
output signal names (including output, buffered or bidirectional ports).
When an unexpected
state is reached Default :
– current_state
– next_state
3-17 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
When designing a state machine with registered outputs, the 'Register state actions
on next state' option determines whether there is a one clock cycle delay at the
outputs or not. This delay is caused by registering the outputs with the
current_state signal. When registering with the next_state signal there is even
less delay at the registered outputs than at the combinatorial outputs. A drawback
of the next_state solution is that the synthesis tool usually uses scan flip flops to
realize this behavior. This could lead to problems when inserting scan chains for
testing purposes. But this usually does not apply to FPGA designs.
3-18 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
3-19 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
The Architecture Declarations (or Module Declarations) tab of the State Machine
Properties dialog box allows you to enter any valid HDL statements for the current
hardware description language in a free-format entry box. Signal declarations,
constants, variables, comments, procedures, functions or type definitions can be
included in the declaration.
is required when the declaration is a constant but is optional when you declare a
signal or variable.
3-20 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Global actions and state register statements can be specified separately for each
diagram in a set of concurrent state machines. Global actions for internal signals
are included in the clocked HDL and all other global actions are included in the
output code. State register statements are included in the generated HDL before
the state decoding statements in the clock process or always code. These
statements are inserted instead of the default assignment to the next state and are
typically used to determine whether a counter should be incremented or reset and
whether to update the state.
The concurrent statements are included in the generated HDL at the end of the
VHDL architecture or Verilog module and are applied to all diagrams in a set of
concurrent state machines.
3-21 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
When you are using VHDL, you can add or edit state machine process
declarations by choosing State Machine Properties from the Diagram menu or by
double clicking on the Process Declarations label on the state diagram.The
Process Declarations tab of the State Machine Properties dialog box allows you to
add or edit declaration statements in the dialog box. The Visible check box allows
you to select whether the declarations are displayed or hidden on the diagram.
Process declarations are placed immediately before the code for both the clocked
and output processes in the generated VHDL.
3-22 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
The Encoding tab of the State Machine Properties dialog box allows you to choose
automatic or manual encoding. When Auto mode is selected, attributes or values
are automatically generated. When Manual mode is selected, encoding values can
be entered by direct text editing on the state or by using the Encoding field in the
States tab of the Object Properties dialog box.
3-23 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
When describing a state machine using HDL, generally the synthesis tools will
optimize away all states that cannot be reached and generate a highly optimized
circuit. But sometimes the optimization is not acceptable. For example, if the
circuit powers up in an invalid state, or the circuit is in a extreme working
environment and a glitch sends it into an undesired state, the circuit may never get
back to its normal operating condition.
Therefore you can use "hard" encoded "safe" state machines: No matter how
many states you have, if you use the "bit-level" encoding scheme, the optimized
result will be "safe". This requires you to specify bit patterns for your states.
For example, use std_logic_vector (for VHDL) to define your state type, then you
can detect the undesired states either using the "others" (for VHDL) or "default"
(for Verilog) statement in the state decoding process or by explicitly defining if
current_state = (undesired states) or current_state /= (desired states).
3-24 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
When you are using Verilog, you can choose whether the range is included in the
state encoding parameter declaration by setting the Use Range in Encoded
Parameter check box. You can choose Hard Automatic or Hard Manual mode. If
you are using the Synplify synthesis tools you can also set a syn_encoding Pragma
with onehot, gray, sequential or other user specified style (optionally including the
keyword safe). When Hard is selected for either language, One-Hot HDL style is
available in the Generation tab when setting generation properties. The One-Hot
style is useful for use with synthesis tools which do not support automatic state
encoding. This option is not recommended for synthesis tools which can perform
efficient encoding automatically.
OUTPUT
INTERNAL
Information only
OUTPUT : from the interface
INTERNAL : from the arch. declarative part
Information only
For VHDL
3-25 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
You can change the signal status by clicking in the Status field and choosing
REGISTERED, COMBINATORIAL or (for output signals only) CLOCKED
from the pull down box. The default value is normally set in the signal declaration
but can be changed in the dialog box. When you set any signal to be registered or
clocked, a reset value must be specified in the dialog box. However, only the
default value can be changed for a combinatorial signal. The default value of a
signal when not otherwise specified can be set as a preference.
output
Inputs nextstate clocked
Notes:
Combinatorial actions are directly assigned to the output port - Outputs.
The suffix _int can be changed on the State Machine Properties - Signals Status
dialog.
Current state
Help → Bookcase
❏ Other Documents → “Predicting the Output of Finite State Machines”
3-27 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Clocked actions are applied and registered to an internal signal named
Outputs_cld.
The signal Outputs_cld which has the same value as the output (Outputs) may be
used in a transition condition, or in a Concurrent Statement.
The suffix _cld can be changed on the State Machine Properties - Signals Status
dialog.
Applies
clk
to Clocked and
reset Registered
z_comb Outputs
z_reg
z_clocked
current_state s0 s1 s2 s3 s0
next_state s1 s2 s3 s0 s1
3-28 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Both registered and clocked outputs get registers synthesized at the output signals.
The difference is the output assignment behavior. When using registered outputs it
is mandatory to specify a default value for the output. Otherwise the synthesis tool
will infer latches if the registered output isn't always assigned. The registered
output always gets the default value unless another value is assigned (see state S2
above).
When using clocked outputs the output "remembers" always the latest assigned
value until a new value is assigned. Therefore it is not necessary to specify a
default value. If a default value is specified anyway it results in the same behavior
than the registered solution.
3-29 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
clk
reset
z_comb
z_reg
z_clocked
current_state s0 s1 s2 s3 s0
next_state s1 s2 s3 s0 s1
3-30 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Register state actions on next state ó when do you want to use this option?
Whether you have this on or off depends on the timing of the circuit.
If you register on next_state, you are clocking the flip-flop in the same clock
period as the condition occurs. Since conditions can be asynchronous, they could
occur at any time. You may not know if there will be adequate setup and hold
times for the flip-flop to register/latch the signal value reliably. However, if you
know there is plenty of slack or if you know the inputs come from a previous
register, then using next_state is probably fine.
Also, when pipelining designs, you rely on registering the outputs on the next
clock edge in order to keep the outputs in the correct relative time-domain. So this
option is also appropriate in this case.
Execution Priority
(Highest at the Top)
Reset actions (jumps to Start State)
State actions
Global actions
3-31 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Delete Machine
Shared :
- Interface Open Machine
- Package list
Add Machine
- Concurrent Statements
- User Declarations
- Treated as a single Design Object (one HDL file generated, saved at the same
time,...)
Notes:
You can create a concurrent state machine from a state diagram using the item
"Concurrent State Machine" from the Add menu. A concurrent state machine is
created and a new state diagram opened with the same interface as the current
diagram. The package list and any concurrent statements, or status signals list are
shared by the concurrent state machines but global actions can be set separately. If
there are any other user declarations (which are interpreted as architecture
declarations in VHDL or as module declarations in Verilog) these are also shared
by the concurrent state machines.
3-33 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Each concurrent state machine is given a unique name by adding an integer to the
default name (for example, machine0, machine1, machine2...). However, the base
name for a new state machine can be set as a preference in the Default Values tab
of the State Machine Preferences dialog box.
You can change the name of the active concurrent state machine (which is used in
the generated HDL) by choosing Rename State Machine from the Diagram menu
to display a Rename dialog box. The name is also shown in the window title for
the state diagram.
Expression Builder
Expression Builder
3-34 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
The expression builder provides a palette which lists all the available ports and
locally defined signals together with template values in the syntax required by the
active diagram. It also provides buttons which can be used to insert appropriate
operators for the active language. The HDL expression builder can be used
whenever an input expression (condition) or an output assertion (action) is being
edited whether by direct text editing or in a dialog box. The expression builder
dialog box is normally displayed automatically unless you set the Do not display
automatically option in the dialog box. In automatic mode, the expression builder
is automatically displayed when a HDL expression is being edited and
automatically hidden when the edit is completed.
3-35 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
This tab can also be edited by choosing Diagram Preferences from the Options
menu in a state diagram. When you edit preferences for the active diagram, the
dialog box allows you to choose whether the preferences are applied to new
objects or to both new and existing objects in the state machine (including
concurrent or hierarchical diagrams). You can save the preferences for the active
diagram as master preferences by choosing Update from Diagram in the Master
Preferences cascade of the Options menu or apply the master preferences for
object appearance to the active diagram by choosing Apply to Existing Objects or
Apply to New and Existing Objects. However, you cannot apply the master
preferences for default values to the active diagram.
Polyline style
Correct HDL syntax entry
Spline style
3-36 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
3-37 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Directions
• Part 1: Create a Finite State Machine “beneath” the BCDRegControl block
o Open the BCDRegister block diagram you created in a previous lab.
Hint: Position the cursor within the Editor Window, click the RMB, and
select the popup menu item State Machine Properties...
o Select the Signals Status tab, and set the parameters as shown below:
Note the different output status settings and try to figure out why which
value was choosen. Be sure to use double quotes when entering the
reset values for the vector signals.
• Hint: You can copy the 3 states from CountOnes sub-diagram and
paste them to the CountTens sub-diagram, then change only the
names.
o Save the design. What changes do you see to the design structure in the
Design Browser?
o Select the pulldown menu item Tasks > Generate > Run Single
o What happens in the HDL Files view window of the Design Explorer?
o Double-click on the HDL file you just created to see the generated
code.
Use the left navigation pane of the DesignPad editor to view the
structure of the VHDL file. For example select the clocked process and
see the whole process displayed and highlighted at the main editor
window.
Objectives
This module will cover the following topics:
• Testing Methodology
• Data Preparation
• HDL Generation
• Simulation Data Compilation
• Invoking the Simulation Flow
• Interactive Simulation
• Simulation Windows
• Running the Simulator
• Creating Stimulus
• Troubleshooting
• Reusing Stimulus
Testing Methodology
Testing Methodology
♦ Interactive Testing
! Easy to find mistakes in smaller portion of design
! See inside “black box” of a larger design
! Testing testbenches
♦ Testbenches
! Static, formalized tests
4-2 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Simulation Process
Simulation Process
♦ Edit, and Save Design Unit Edit Design
Unit
♦ Generate HDL for graphical views
! Syntax check
♦ Compile Simulator Data from HDL Generate HDL
for graphical views
♦ Invoke Simulator
♦ Provide Stimulus
Compile HDL
! Interactive
! Stimulus File
♦ Monitor Results Invoke Simulator
♦ Troubleshoot
Simulation Flow
♦ Modify Design and Reiterate
Troubleshoot
4-3 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Invoking Simulation
Invoking Simulation
♦ Select Design Unit in Design
Browser:
! Toolbar: Simulator Flow
! Pulldown menu
Tasks > ModelSim Flow > Run...
♦ Select Design Unit in Edit
Window:
! Pulldown: Simulation > Start
Simulator…
! Toolbar: Simulator Flow
4-4 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
ModelSim Windows
ModelSim Windows
4-5 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
4-6 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Menu Tear-Offs
! Dashed Line at top of Pulldown
! Menu is placed as separate
Window on desktop
4-7 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Features
! Reflect current signal values
– Interface and internal Signals
– Text values
– May set radix
! Use for stimulating the design
– Assign signal values
– Assign clock signals
! View state variables
! View bus signals by bit
4-8 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
4-9 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Display Preferences
Display Preferences
♦ Signal Window
! Sub-windows resizable
! Pulldown: View > Justify Values
– Justify Values along right or left margin
! Pulldown: View > Filter
– Hide/Show Input, Output, Internal signals
– Applies to signals in all design units
! Pulldown: Add > Wave
– Display specified signals in Wave Window
• selected — display only those signals selected
• region — display signals in Signal Window
• design — display all signals in design
4-10 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
4-11 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Simulation Preferences
Simulation Preferences
♦ Affect several simulation defaults
♦ Pulldown:
Simulate > Simulation Options …
! Default Radix
! Default Run Length
! Default Force Type
! Suppress Warnings
! Assertion Prefs
– Break on
– Ignore which
! Waveform Prefs
– max. wlf size
– compress wlf
– max. wlf “recording” time
4-12 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
4-13 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Step Commands
Step Commands
♦ Step
! Move forward one line in HDL code
♦ Step -Over
! Same as Step
! Treats procedures as one line
♦ Continue
! Continues execution of previous
Run command
4-14 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Restart
! Restarts simulation, set Simulator time to Zero
! Clears waveform memory / file
! Clears forces
! Dialog allows keeping elements
– Preserve List, Wave Display Formats
– Breakpoints
– Logged Signals
– Virtual Definitions
4-15 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Interactive Stimulus
Interactive Stimulus
♦ User provides all external
stimulus
♦ Can be saved as a “dofile” for
future runs
♦ Tip: use aliases
! e.g. “alias f force”
! e.g. “alias r2 run 200”
♦ Process:
! Select signal in Signal window
! Select stimulus type:
– Force
– NoForce
– Clock
! Run simulation
4-16 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
4-17 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
4-18 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Interactive Troubleshooting
Interactive Troubleshooting
4-19 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Interactive break
! Stops simulation run at current point
! Handy for “runaway” simulation
♦ Pre-set Line Breakpoints
! Open Source window
! Click in left margin near line number
! Red dot appears
! Simulation will always stop at this
line
! Remove by clicking on red dot
red circle remains to indicate that
there was a breakpoint
! May only be placed at executable
(green) lines
! Line Breakpoints are implemented using the “bp” command and can
be reported by issuing “bp” at the command prompt
4-20 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
4-21 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Troubleshooting Techniques
Troubleshooting Techniques
♦ Endless Loops:
! Use Break icon to stop simulation
! Look in Source window to see where problem occurs
OR
! Reload simulation
♦ Unexpected Results:
! Place breakpoint at entry to expected HDL executable
! Monitor internal signals
! More debugging tools introduced later
4-22 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
4-23 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Reusing Stimulus
Reusing Stimulus
♦ Creating a Macro from a Simulation Run
! All actions reflected in Console
! Pulldown:
File > Transcript > Save Transcript As...
! Edit contents in any text editor
! Recommend: Save in ModelSim Downstream Data directory
(work_ms) of current design
– First directory browsed
♦ Saving Wave window formatting
! Pulldown: [Wave:] File > Save Format...
! Saved as a Macro
♦ Using a Macro
! Pulldown: Tools > Execute Macro…
! Choose desired Macro from browser window
! Automatically looks for files with “.do” extension
! Wave Format Files: File > Load Format… also works
4-24 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
4-25 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Directions
• Part 1: Preparing for Simulation
o Select the BCDRegister block diagram design in the Design Explorer’s
Design Unit view mode.
Note: If you have made any changes to this design since you last
saved, FPGA Advantage will ask you if you wish to save those
changes before generating HDL and invoking ModelSim.
o Once ModelSim has finished invoking, open the Source, Signal, and
Wave windows.
o You can drag one or multiple signals from the Signals to the Wave
window
Tip: Use the Wave window pulldown menu item Insert > Divider to
group the signals.
Note: Use the *.* option for the filetype when saving the file, cause
otherwise the file will have a .TXT appended (instead of .DO).
Use the Console pulldown menu item File > Transcript > Save
Transcript As to save the transcript window to the file
BCDRegTestSetup.do. Select the folder “work” to store the file.
Use the Wave window pulldown menu item File > Save Format...
to save its formatting in the file wave_BCDReg.do.
o Continue to run the simulation for 100ns chunks until you see the
data_out increment a few times. Notice how the various signals interact.
o Increase the Run Length to 50us. Run the simulation until you see the
counter roll over to 00. Notice the behavior of ripple_out.
o Now you want to check the 09 to10 rollover. Therefore set a signal
breakpoint on the data_out signal by selecting the signal in the Signals
window and issue RMB > Insert Breakpoint.
o Run the simulation using the “run -all” command. The simulation
stops at the next change of data_out. If you hit the “Continue”
button, the simulator proceeds to the next change of data_out.
Once your design counts correctly, you have finished this lab.
Objectives
This module will cover the following topics:
• What is Synthesis?
• Preparing for Synthesis
• Interface Basics
• Viewing Results
• Text Reports
• Schematic Viewers
• Accessing Vendor tools for place and route.
What is Synthesis?
What is Synthesis?
♦ Synthesis is a two step process with an optional third step.
The steps are:
! Step 1 — Translate synthesizable RTL HDL to generic gate level
netlist, i.e. technology independent gates. This involves a number
of processes. For example:
– constant folding and propagation
– loop unrolling
– dead code removal
– bit minimization
! Step 2 — Optimize and map generic gate level netlist to
technology gates utilizing any special architectural features
wherever possible. This optimization can be for area and/or
speed
! Step 3 (optional) — Timing optimization if timing constraints not
met
♦ Output from synthesis is an EDIF netlist ready for vendor
place and route tools.
5-2 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
– Multiplexer
– Adder
5-3 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Setup
clk
sel
op
Required
5-4 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
EDIF Netlist
5-5 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Synthesis Process
Synthesis Process
♦ Synthesis Flow for Precision Synthesis
! Prepare Design in Design Explorer
Build Design
! Choose Technology
! Read Source Files
! Apply Timing Constraints
Initiate Flow
! Optimize Design
! View Results
! Troubleshoot Configuration
! Write Netlist for Place & Route
Synthesize Design
Review
5-6 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
User-defined
synthesis
scripts
Post-synthesis
simulation netlist
format
5-7 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Notes:
5-9 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
5-10 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
5-11 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Results Folder
♦ The Design Bar synthesis steps can be executed from the Project Browser
through pop-up menus or double-clicking on objects
♦ The above is NOT a directory structure, but indicates the Project structure
only. The input files will have been read in from the HDS hdl directory.
5-12 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
5-13 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Compiling
Compiling
♦ Compile
! Analyze
! Elaborate
! Pre-Optimization
! FSM Detection / Extraction /
Optimization
! Modgen Detection / Extraction
5-14 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Don’t_touch
Preserve / Flatten hier
5-15 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Synthesizing
Synthesizing
♦ Synthesize
! Compile
! Optimization
! Timing Optimization
! Output Netlist and Vendor
Constraints
5-16 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Output Files
Output Files
5-17 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
5-18 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
5-19 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Schematic Viewer
Schematic Viewer
Hierarchy Browser
Schematic View
♦ Allows viewing, constraint entry and reporting
♦ Displays RTL, Technology and Critical Path views
5-20 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
View Schematic
View Schematic
♦ Clear schematics using
accurate symbols
♦ Display contents of LUTs
! optional
5-21 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
5-22 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Query Mode
Query Mode
5-23 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
5-24 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
5-25 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
IDEAL
CLOCK Latency
Source
Clock
Setup Constraint
Prop. Delay (MAX)
Dest.
Clock
Prop. Delay (MIN)
DATA
Hold Constraint
5-26 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
The worst-case timing relationships that are used to determine timing violations
are shown in this slide. Notice that, for example, the latest source clock edge is
used to measure delays for setup, while the setup constraint is measured against
the earliest possible destination clock edge.
This diagram makes clear the distinction between clock latency and clock
uncertainty.
Timing Report
Timing Report
5-27 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
5-28 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
5-29 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Area Reports
*******************************************************
***********************************************
Device Utilization for 2V40cs144
***********************************************
Resource Used Avail Utilization
-----------------------------------------------
BUFG xcv2 2 x
BUFGP xcv2 2 x
Number of ports : 19
Number of nets : 167
Number of instances : 154
Number of references to this view : 0
5-30 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
5-31 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Xilinx Implementation
Tools
Precision offers
Xilinx Analysis Tools
complete integration
to the ISE design
environment
5-32 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
5-33 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
5-34 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
IOB Mapping
IOB Mapping
♦ Performed Automatically by
Precision
♦ Registers are placed into RTL
IOBs unless a reg to reg
timing violation occurs
♦ Users can control IOB
insertion from the port
♦ Automatic replication of Technology
registers driving ports and
internal logic
5-35 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Summary of Module
Summary of Module
We have been through an introduction to Synthesis using
Precision covering the following areas:
♦ Basic synthesis theory
♦ How to prepare a design for synthesis
♦ Precision Interface Basics, simple flow through to gate
level
♦ How to view the results. Design Creation/Management
! Text Reports
! Schematic Viewers HDL
Designer
♦ How to access vendor place Precision
and route tools Synthesis
ModelSim
Simulation Synthesis
5-36 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
5-37 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation
Notes:
Directions
• Part 1: Preparing the BCDRegister design for synthesis
o If an HDL Designer window is not open, open one and bring up a
Design Explorer window with XYZLib, as in earlier Lab exercises.
o Select the BCDRegister design in the Design Units pane of the Design
Explorer Window.
o Click on the toolbar icon Run Precision Synthesis Flow. Note the
actions listed in the Log Window.
o Set the Precision Synthesis Settings as shown below. Use the following
settings for the first synthesis run:
Note that the entire Precision Synthesis window is kept grey while it is
compiling and synthesizing. You can see how well it is doing by the
animation of the icons in the Design Bar on the left.
OR
When the Design Browser comes up, you should see three blocks
and assorted nets connecting them. Each one of these blocks
corresponds with one of the components or blocks in your top level
BCDRegister design.
a. Single click in the Schematic Pane. Note that holding the cursor
over a block will display a popup with information on that object.
d. You can view the source HDL for the BCDRegController logic
by selecting an instance and click RMB > Trace to HDL Source.
f. When you are done viewing the design, go back to the Design
Centre by clicking on the Design Centre Tab at the bottom of the
Window.
OR
Go to the Design Bar and click on the ‘View Schematic’ icon in the
Design Analysis section of the Design Bar. (This is near the bottom
of the design Bar)
Since the design has been partially flattened during synthesis the
technology schematic has a completely different structure than the
RTL schematic. Not the whole design is displayed on the schematic
page.
o Zoom into the leftmost region of the schematic to see the input pads.
o Zoom out to see the whole schematic. Now every instance and net
which belongs to the clock tree is selected.
o Use the “View Trace” icon to display only the fragment of the design
which contains the actual selected items. In our example the clock tree.
First click on the highlighted net to select it, then click on the “View
Trace” icon.
o View the whole schematic again by reclicking the “View Trace” icon,
then use the “Unselect” icon to undo the selection. When you are done
viewing the design, close the schematic viewer window.
What are the area (in Function Generators, or FGs) and delay
(in ns) results for this optimization?
o Click on the Design Bar icon “View Critical Path”. How many
cells are in the longest path in your design?
o Exit Precision RTL Synthesis. Click the No button in the dialog box
asking if you would like to save the project.
Objectives
This module will cover the following topics:
6-2 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
6-3 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
Symbols are graphic representations of the interface of a device. Symbols show
the input and output ports and in some cases the input and output port types. They
are very useful for creating block diagrams of a system because they allow the
designer to visualize the interface as the designer is connecting signals and busses
to create the design. By having the symbol the designer knows exactly what
signals are needed to connect to the component to completely fill out its
connections.
♦ Block Designs
! “Open Down” design view uses parent Block
! Usually part of larger design
! Block must have view to convert
! Convert to Component to include in testbench
! Don’t convert if testing “in-place”
! Conversion cannot be undone!
! Symbol based on Block graphics
6-4 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
An "Unattached" design view is a design component which is "stand alone",
meaning nowhere instantiated. The automatically generated symbol for that
design view needs typically some graphical "fine tuning", e.g. resizing, moving
ports. This should be done prior to the first time the component is to be
instantiated.
6-5 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Edit Window:
! Select component
! Popup: Open > Symbol
6-6 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
6-7 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
! Design Unit
Notes:
The symbol editor looks very similar to other windows within HDL Designer. It
has similar menus and toolbars. When the symbol editor is invoked, a symbol
boundary is created. This boundary needs to be sized for the number of ports
required for the symbol. Keeping symbols as small as possible will allow more
functionality on a block diagram making it easier to follow the flow of the design.
After the boundary has been sized, add the input and output ports. Other port types
exists such as Inout and buffer for handling more complex IO.
Here you declare also also generics and parameters for components.
! Hide text:
– Select text to hide
– Popup: Hide Text
! Restore all hidden text on symbol:
– Select symbol
– Popup: Show Text
6-9 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Reposition Ports
! Drag and Drop
! Popup: Equidistant Ports
6-10 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Process:
! Select port(s) to modify
! Select port graphic type
– Popup: Clock | Not
! Types
– Clock > On adds Clock Designator
– Not > On adds Inverter Bubble
– (Clock | Not) > Off removes
selected bubble or clock symbol
6-11 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
6-12 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
6-13 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
6-14 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
Any graphical object must be totally enclosed by the boundary in order for it to be
part of the symbol.
Line Rectangle
Polyline Ellipse
Arc Circle
Polygon
Grouping
Order
Rotate
Flip
6-15 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
[RMB] → Appearance...
6-16 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Save As:
! Allows assignment to
different Library
! Allows new Design Unit,
View names
6-17 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
Saving a symbol is similar to saving any of the other HDL Designer design units.
Specify the library, the design unit or cell name, and the view name. The default
view name is symbol.sb.
6-18 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
6-19 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
6-20 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Features
! Sequential execution
! Concurrent Flow Charts
! Styles
– Wait Statements
• Testbenches
– Sensitivity List
• Synthesis
! Styles cannot be mixed in a single Flow Chart!
6-21 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Wait Block
♦ Start/End Point
♦ Loop Start/End
♦ Case Box
♦ Flow Arrow
6-22 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Action Box
! Sequential statements
! Assignments
! Object ID (default => “ax”)
♦ Condition Box
! Branches on value of condition
! Must branch forward in Flow Chart
! Object ID (default => “dx”)
! Swappable True/False assignment
6-23 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
Here are the primitive elements for a flow chart and the operations that they
perform. At the top of the slide is the action box. The action box consists of a
number of sequential statements that perform some actions like signal assignment,
variable assignment, or maybe a subprogram call. All of the statements are
performed sequentially.
The hierarchical action box works similarly to the hierarchical state box in that it
creates a level of hierarchy below the hierarchical state which represents another
flow chart. Again this is useful to break up complex operations into smaller
manageable pieces to make them easier to understand.
The condition box is used to branch control based on the result of a condition
expression. If the condition is true the true branch will be taken else the false
branch will be taken.
♦ Wait Box
! Inserts wait conditions
! Wait for
– time, forever, until
– clock edge
– signal
! Object ID (default => “wx”)
♦ Start Loop Box
! Beginning of loop statement
! Contains loop expression
! Object ID (default => “Ix”)
♦ End Loop Box
! Delineates end of loop
! Only method of returning
flow “upstream”
6-24 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
The wait box is used to suspend execution of the process until the wait box
condition has been satisfied. If the wait box has no condition then the wait
statement will wait forever. The syntax follows the wait syntax for VHDL
including a wait until expression, wait for time, and wait on signals.
The start loop and end loop boxes are used to surround a set of actions that will be
repeated. These actions will be repeated until the loop expression of the start loop
box is satisfied. The end loop box will mark the end of the loop.
♦ End Point
! Ends a flow chart
! May have multiple end points
6-25 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
The start point is used to mark where process execution will start after the process
has finished and is starting again, or because a signal in the sensitivity list has had
a change in value.
The end point is used to mark the end of execution for a process.
6-26 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
The case primitive is used to switch between a number of possible alternatives.
The decision box only switches between two alternatives but the case can switch
between a number of alternatives. The starting case primitive will have an
expression which will calculate a value. The case ports leaving the upper case box
will try to match the calculated values. If a match occurs that branch is taken. If no
match is found the others branch is taken. The value ports of the case statement
have to enumerate all possible values of the expression or an others port is
required.
6-27 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
This flow chart shows the wait statement style. The process will start at the start
primitive and continue execution to the first action box where signal clk is
assigned 0. The process will stop at the wait statement and wait for 10
nanoseconds. After the time has elapsed the process will continue to the next
action box and assign clk to value 1. The process will then wait again at the next
wait box for 10 nanoseconds. After the wait the process will start again at the start
primitive. There is an implied loop for all processes. To execute a process once
and stop, use a wait statement with no time or condition. This is a wait forever.
6-28 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
6-29 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
Flow charts can generate sequential or combinational HDL code. Sequential flow
charts are clocked by a clock, while combinational flow charts are not. A
sequential flow chart will need to have a clock signal specified to clock the flow
chart and need to know which edge of the clock is active. A sequential flow chart
can also have a reset signal. The reset signal name must be specified along with
the value of the reset signal that is active.
The sensitivity list for the flow chart can be set automatically, or specified
directly. To animate the flow chart so that the designer can watch the flow chart
action boxes highlight as execution continues, select the instrument HDL for
animation box. This will create HDL code with the animation data added.
6-30 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
The flow chart editor also has the concept of concurrent flow charts much like the
concurrent state machines. The concurrent flow charts share the same port
interface, architecture declarations, architecture concurrent statements, and
package declarations. Each concurrent flow chart creates a new process statement
within the architecture. The process declarations and sensitivity lists for each flow
chart are the only items that are separate between the concurrent flow charts. Use
the Add, Open, and Delete Concurrent Flow Chart toolbar buttons to manipulate
concurrent flow charts.
! Add
– Adds new concurrent flow chart
! Open
– Opens flow chart
– Choose from drop-down menu
! Delete
– Deletes flow chart
– Choose from drop-down menu
6-31 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
Here are the flow chart buttons to create, open, and delete concurrent flow charts.
The add button will create a new concurrent flow chart. The concurrent flow chart
will share all declarations except for process declarations and sensitivity list. The
open button will drop down a menu of the concurrent flow chart to open.
Concurrent flow charts are given unique labels for easy identification. The delete
button will delete a concurrent flow chart. This button also drops down a list of
concurrent flow charts. Select the concurrent flow chart to delete.
6-32 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
6-33 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation
Notes:
Note that you will receive less “hand-holding” as the labs progress. Consult your
instructor if you have questions about how to proceed.
For implementing the test bench functionality you can use some VHDL
templates from the $FPGADV_LABS/Lab_templates directory (you will be
given hints when this applies).
Directions
• Part 1: Edit the BCDRegister component symbol
o Edit the symbol so that:
o Ports display signal names but not signal types. Therefore click at the
Design Manager PD menu: Options > Master Preferences >
Symbol..., choose Miscellaneous Tab and click on VHDL Port
Display and make the necessary changes. Then switch to the Symbol
Editor and update your Diagram Preferences using the PD menu:
Options > Master Preferences > Apply to New and existing Objects.
o Select the pulldown menu item File > New > Test Bench...
Change
• Part 3: Create a flow chart to provide stimulus for the test bench
o Double-click the BCDRegister_tester block to open the Open Down
Create New View dialog box. Select a view type of Flow Chart. Click
Next, then Finish to close the dialog. A Flow Chart editor window will
appear.
• The above test routine uses a function to convert the internal decimal
counter value into a BCD counter value. This function needs to be
declared “somewhere”. Add the function incbcd_count to the
Process Declarations by opening the “Flowchart Properties” dialog
and select the “Process Declarations” tab:
If HDL was not generated for the BCDRegister_tester, identify why, and
then generate it.
Objectives
This module will cover the following topics:
• Graphical Troubleshooting
• Controlling Simulation from the Design Context
• Simulation Execution
• Breakpoints
• Using Animation
• Using Crossprobes
7-2 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
Simulation Toolbar
Simulation Toolbar
♦ When the Simulator is invoked from within HDL Designer,
additional simulation toolbars are added at the bottom of the
HDL Designer editor diagrams
♦ Block Diagram Editor Window Toolbar
Execution Breakpoints Signal Display Probes Instance
& Information Selection
7-3 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
7-4 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
Signal Information
Signal Information
♦ Signal Info
! Possible values for signal
! Current value of signal
! Driving signals and design units
♦ Highlight Object
! Highlights selected signal in Simulator
– Structure, Source, Signals, List, Wave
7-5 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
Simulation Execution
Simulation Execution
♦ Simulation execution similar to ModelSim icons
7-6 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Tradeoffs
! Animation Enabled
– Simulator Overhead
– Can use Animation at any time
– Extra animation code can be “stepped over” in
simulator Source window
! Animation Disabled
– Slightly faster Simulation
– Disable in debugged designs
7-7 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
When the HDL code is set up for animation there is additional information added
which "tells" ModelSim what happens next in the state diagram or flow chart.
Example Code:
-- pragma synthesis_off
hds_next <= 1;
-- pragma synthesis_on
The synthesis pragmas prevent the synthesis tools from implementing the code as
hardware. They simply ignore it.
7-8 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
Using Animation
Using Animation
♦ Graphical representation of
state/flow activity
♦ May display several design
units, levels of hierarchy
♦ Tracking control
! Stop/start simulation
– for time
– until event
– forever
! Step backwards/forwards
through simulation results
! Breakpoints
! Track cause of signal state
! Step over objects
! Trail length
7-9 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
7-10 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
Enabling Animation
Enabling Animation
♦ May turn animation on/off
during simulation
! Enabled on a design unit-by-
design unit basis
! All concurrent and hierarchical
elements within a design unit
enabled together
! Pulldown: Animation > Global
Capture On | Off
♦ Data Capture
♦ Clear Captured Events
♦ Show Animation
! Automatically enabled when
Data Capture enabled
7-11 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
In order to animate a flow chart, the flow chart must have been generated with the
Instrument HDL for Animation option enabled in the Generation tab of the
Flow Chart Properties dialog box.
In order to fully animate a state diagram, the state machine must have been
generated with the Instrument HDL for Animation option enabled in the
Generation tab of the State Machine Properties dialog box. If this option was not
enabled, the animation will show changes of state but full animation (for example,
transitions taken and moving by clock cycle) is not available.
You can enable animation for all instances in the current simulation hierarchy by
choosing Global Capture On from the Animation menu (or from the Animation
7-12 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
7-13 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
Breakpoints
Breakpoints
♦ Select breakpoints graphically
♦ Breakpoints work exactly as in simulator Source window
♦ Icons:
! Set Breakpoint — selected
! Delete Breakpoint — selected
! Delete All Breakpoints — in selected or in design
! Disable Breakpoints
– Does not delete existing breakpoints
! Enable Breakpoints
♦ Report Breakpoints:
! Pulldown: Simulation > Breakpoints > Report
7-14 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Transitions
! Process:
– Select Transition
– Click Add Breakpoint icon
– Red dot appears next to transition AND next state
! Break at transition
– When breakpointing on a transition
that comes from a hierarchical state
the breakpoint is shown in lower level diagram
7-15 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
Breakpoints can be added to any object which corresponds to a executable line in
the generated HDL. If you select an object which has no corresponding executable
HDL code, you are prompted to select another object.
If you set a breakpoint on a state name, HDL line breakpoints are added to all
transitions which set the state as the next state. For a hierarchical state machine,
these transitions may be in another state diagram but will be shown when
that diagram is displayed.
♦ Decision Box
! Breaks simulation before
condition evaluated
♦ Wait Box
! Breaks simulation before wait
statement executed
7-16 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
Activity Trails
Activity Trails
♦ Too many “Previous” states!
! Which state triggered when?
! Activity Trails Settings:
– Pulldown: Animation >
Activity Trails…
– Toolbar: Activity Trails
7-17 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
The current and previous steps (for a flow chart animation) or the current and
previous states plus the last transition (for a state machine animation) are normally
highlighted in the animation view.
The activity trail allows you to control how much additional animation activity is
displayed. If you are using ModelSim, you can specify the maximum number of
simulation events captured for each diagram during an animation run. When this
limit is exceeded, old events are discarded to reduce the total amount of stored
data. For a state machine, you can also choose whether to capture data about
evaluated conditions or active clock edges. If all the capture options are unset, no
data is saved, however, the animation is updated with the latest simulation data
when the simulator stops.
For a state machine, you can also choose whether conditions evaluated to be true
but not followed are highlighted in the activity trail. This may occur if a condition
is evaluated to be true but reverts to false before the next clock edge which would
cause the transition to be completed.
! Step Mode
– Icon changes to match mode
– State Machines only
! Step to specific time
! Go to beginning/end of history
7-18 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Process:
! Invoke simulation on design unit
! Select net to probe in block diagram
! Click Add Probe icon
7-19 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
Probe Properties
Enable/Disable
Cursor Tracking
The probes value is updated when you move the cursor in the
wave window
7-20 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
7-21 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
When you send a command to the simulator, the signal or process is identified by
a pathname that uniquely identifies its location in the design hierarchy. This path
is referenced relative to the component from which the current simulation was
invoked.
If your design hierarchy contains more than one occurrence of a component, you
can open down into this component from each separate instance. When driving
simulation from within such a component, it is necessary to specify the simulator
hierarchy path in order to uniquely identify the signals and blocks it contains. It is
also possible to open separate windows on each instance in which case each
instance can be animated separately.
Clear
Previous Error
Next Error
Previous Warning
Next Warning
Cross Reference to Source
7-22 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Variables
♦ Dataflow
♦ List
7-23 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
Process Window
Process Window
♦ Displays process activity
! Same as initial and always blocks in Verilog
♦ Possible states:
! Ready — scheduled to execute
! Wait — waiting for an event or time
! Done — no further scheduling
– wait forever
– initial block
♦ Execution order control
! Select a “Ready” process
! Process executed next
7-24 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
Variables Window
Variables Window
♦ Similar to Signals Window
♦ Displays process variables
! Choose process in Process Window
! Variables appear in Variable Window
♦ May drag variables to Wave and List Windows
7-25 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
Dataflow Window
Dataflow Window
♦ Dataflow view:
! Which processes drive
which signals?
! Who affects a special datapath
♦ Tracing Signals
! Driving processes on left
! Reading processes on right
! Find source of unknown ‘X’
♦ Tracing Processes
! Input signals on left
! Output Signals on right
♦ Embedded wave window (optional) shows related waveforms
♦ Other useful information:
! small dot at signal name shows trigger status (sensitivity list)
! shows hierarchy boundaries
7-26 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
Dataflow Example
Dataflow Example
♦ Want to show source for unknown ‘X’ at
signal “q” in wave window:
1. Drag signal from wave to dataflow window
2. Select ‘X’ Signal in Dataflow window and
issue “Trace > ChaseX” command
3. The signal is traced back through
processes and concurrent statements
1. until the source driver for the ‘X’ is found
2. 3.
7-27 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
Dot indicates
sensitiveness
Selected signals
name and path
Signal value
at selected time
7-28 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
7-29 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
7-30 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
List Window
List Window
♦ Tabular version of Wave Window
! Change in any variable or signal = new status line
7-31 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
7-32 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation
Notes:
2. The second shows how to use Text I/O from within a graphical testbench to
read stimuli from a textfile.
3. The third one shows howto write ModelSim assert messages to a file, which
is extremely useful when running log simulations.
In this lab, you will test and troubleshoot the BCD Register test bench you
created in an earlier lab using HDL Designer editor windows to control
simulation. If you have not completed Lab 6, your instructor can provide you with
a finished copy of the BCD Register design and it’s testbench.
Directions
o Once ModelSim has invoked, bring the editor windows for the
BCDRegister_tb design to the front. Add all signals in the Block
Diagram to the ModelSim wave window: Select all signals and click the
Add Wave button.
o Open the Flowchart diagrams and the State diagrams, arrange them and
the ModelSim wave window on the screen.
o Run the Simulation from within HDL Designer using the Simulation
Control Buttons.
o Using Animation and Crossprobing, test and debug your test bench
stimulus design. You will also want to use the Wave window from the
ModelSim environment to view the stimulus in its entirety.
o Tip: If you make changes to the design, you will not be able to edit
while Animation is enabled. You may turn off Animation, make your
edits, save, reload the design, then enable Animation and continue
testing.
The state diagram shows now the “count_Tens” state again white, cause
it has not been visited yet. Using the “Goto Next” Button to review the
simulation events state by state:
When you are satisfied that your test bench correctly tests the BCDRegister
design, exit ModelSim and close your editor windows.
When describing test benches in plain HDL or flow charts it is sometimes very
laborious to cover complex input patterns. Especially if they are produced by
another system, which isn’t part of the simulation.
The solution is the use of an ASCII file, which stores the input patterns at different
time stamps. The HDL testbench reads the stimuli from the file and applies it to
the Device Under Test (DUT). The file could have the following structure:
Another advantage of this solution is that when the stimuli change you only have
to edit the ASCII file. You can run the simulation without recompiling the HDL
code. This would have been necessary if you changed the stimuli in the HDL
testbench code.
Directions
• Part 1: Create the Library Mappings and open the Library Text.
o Move to the “Project Manager” and add a new regular Library
Mapping named “Text”, use $FPGADV_LABS as root directory.
o Open the Library and browse through the three design units and try to
understand the design structure.
2.) Select the “ModelSim Compile” task, then the whole design will be
compiled. (Ensure it is set for compile through components)
o Simulate the text_tb design and verify the correct behavior of the
output.
Directions
When invoking ModelSim directly from HDL Designer you may have missed up
to now the possibility to set additional compiler/simulation switches for
ModelSim. There is a option in HDL Designer’s “Tasks Bar” to define settings for
a certain task show the ModelSim compile/invocation dialog.
Objectives
This module will cover the following topics:
• BCD Register
• Current Status
• Improvements
• Using Generics and Parameters
• Adding HDL to State Machines and Flow Charts
• Declarations
• Statements
• Copying Design Units and Design Views
BCD Register
BCD Register
♦ Implemented Functionality:
! Reset
! Increment
! Counter overflow at 100
♦ Needed Functionality:
! Load
– Illegal values reset to 00
! Variable Overflow Limit
– e.g.; 12
! Need external variable
! VHDL: Use Generic
8-2 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Possible Uses:
! Multi-width objects
! Variable counters
! Delay modelling
8-3 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
VHDL generics are a VHDL feature used to pass information to an instance of an
entity. Verilog parameters can be used in a similar way when you are using the
Verilog language. You can declare VHDL generics and Verilog parameters as
properties of a block or as properties of the symbol which defines the interface to
a component. The declarations are specified as a list of names, types (for VHDL)
and default values. The values can be entered as discrete values or using
expressions.
You can change the VHDL generic or Verilog parameter mapping for each
instantiated block or component on a block diagram or IBD view. For example,
you can specify a different value for each instance of a component or you can
Symbol
8-4 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
8-5 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
Editing Generics
Editing Generics
♦ Modify:
! Select Generic to modify
! Make changes in edit fields
! Click Modify to incorporate
changes
! Click OK or Apply
♦ Remove
! Select Generic to remove
! Click Remove
! Click OK or Apply
8-6 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
8-7 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
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8-8 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
8-9 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
Mapped value
Notes:
Symbol
* x=60 #
x=x Tester
Rollover = x
Counter
Controller Counter
8-11 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
There are several ways to use Generics in a design, following as one example the
explanation of the above method to pass generic values through hierarchy:
8-12 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
8-13 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
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8-14 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
8-15 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
Exam ple
Control
Function_one{A:B}
Other_Function
Monitor
Check{2:0}
Delay
high
connectivity
connectivity
clock I I I I I I CK 20
m yReq[2:0] O I{2:1} I[0] I[2:1] RC 5
config[2:0] O O I I[5:3] RC 3
Signals ack{A:C}
status{A:B}[7:0]
I
I
O{A:B}
O
O{C}
I[3:0] I{B}
I RC
RC
7
3
data{0:2}[15:0] O I{0:1} I[15:8] RC 9
8-16 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
IBD will be extended with the ability to slice a design in smaller pieces allowing
the user to work only on his part of the design without carrying the whole design.
You'll be able to split a big table in smaller chunks or to merge small tables
together.
Note that the IBD approach is very efficient for bus-based designs. Be careful
while showing IBD because is some cases (like the UART) the block diagram is
much simpler than the table.
Example
Control
Function_one{A:B}
Other_Function
Monitor
Check{2:0}
Delay
clock I I I I I I CK 20
m yReq[2:0] O I{2:1} I[0] I[2:1] RC 5
config[2:0] O O I I[5:3] RC 3
ack{A:C} I O{A:B} O{C} I RC 7
status{A:B}[7:0] I O I[3:0] I{B} RC 3
data{0:2}[15:0] O I{0:1} I[15:8] RC 9
8-17 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
Add Signal
Add Bus
Add Net Slice
8-18 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
Truth Tables
Truth Tables
♦ Design Unit View
! Implemented as a spreadsheet
! Multiple inputs can affect
multiple outputs
♦ Useful for simple logic
! Larger Truth Tables better
implemented in HDL
♦ Features
! Conditionals
! Multiple lines per cell
! Default results
! HDL Generation control
8-19 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
8-20 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Auto generation of
input/output signal list
! Number of rows set by max
number of inputs or outputs
8-21 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
8-22 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Multiple Lines
! Cells default to single HDL
statement/value
! Affected cells appear “depressed”
! Useful for Additional
Conditions/Actions
! Process
– Select Cell
– Popup: Change To Multi-line | Change
To Single-line
8-23 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Additional Actions
! Allow assignment to internal
signals or variables
! Action must follow HDL syntax
! Useful for setting internal flags
8-24 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
8-25 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
8-26 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
DesignPad — Overview
DesignPad — Overview
♦ Full featured code editor
♦ Multiple-language support
! Language Plug-ins:
parser, syntax highlighting,
language templates
! Initial support for VHDL, Verilog, Tcl/Tk
! Fully customizable syntax highlighting
! Auto-completion of keywords, declarations, etc
! Full language syntax check
♦ Fully integrated with HDL Designer
! Automatic update of Design Manager/
Embedded Blocks when editing
! Instance components/ModuleWare
– simply drag ‘n drop
♦ Similar functionality to other HDL Designer editors
! Design navigation (open up/down), New…, Save…, HTML export, cross-
reference (error/warning, graphics/simulation/synthesis, ... )
8-27 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
8-28 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
8-29 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
8-30 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
8-31 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
8-32 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
8-33 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
A design unit can be copied to another library. When you attempt to copy
hierarchical objects, the Copy Hierarchy Options dialog box is displayed. The
dialog box allows you to choose whether to operate on the hierarchy beneath any
components in the hierarchy and choose the number of levels to descend in the
hierarchy. You can choose whether any referenced blocks and components are
copied to the target library or the copies are made in their library of origin. You
can also choose whether to make copies of referenced components from standard
libraries. Although you cannot explicitly copy a library, you can select any objects
in a library and copy them to another library. For example to copy an entire
library, you can create a new library by setting library mapping for a new library
name, open the new empty library and copy objects into it from an existing
library.
8-34 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
A design unit can be copied to another library or a design unit view can be copied
to another design unit. You are warned that any views containing instances of the
copied object must be manually updated if you want views in another library to
reference the new object. (References can only be automatically updated for views
within the copied hierarchy.) If you copy structural HDL text views, the library
references to child design units are not updated and may need to be manually
edited.
8-35 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
8-36 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation
Notes:
You don’t have to modify the state diagram and the testbench on your own, you
just copy the complete design views from the Lab_Templates library. For a better
understanding the changes which were made in the views are documented below.
Directions
• Part 1: Add the ability to load an 8-bit value into the BCDRegister design.
o This functionality takes the data on the data_in bus and loads it into the
BCD Counters on a rising clock edge when the load_en signal is
asserted high. The most significant nibble is sent to the Tens counter,
and the least significant is sent to the Ones counter. If an illegal value is
loaded into a counter, that counter should rolling over to “0000”.
If both load_en and ripple_in are asserted simultaneously, the load
operation has precedence.
• You don’t have to draw the state diagram on your own, just copy the
complete design view from the Lab_Templates library as described:
Open the Lab_Templates library, expand the contents and copy the
statemachine view fsm_complete to your BCDRegControl Design unit,
and set it the default view.
o Open the completed state diagram and browse through the hierarchies,
take the top-level diagram shown on the following page as orientation.
• Top Level:
o Tip: By giving the generic the same name for both blocks, you may
pass the generic down from the top level of the design and test for a
variety of values.
reset
counting
• You don’t have to modify the flowchart on your own, just copy the
complete design view from the Lab_Templates library:
o Open the Lab_Templates library, expand the contents and copy the
flowchart view lab9 to your BCDRegister_Tester Design unit, and set
it the default view.
o Open the completed flowchart, view the added test functionality and
browse through the hierarchies,
Use a rollover value of 59 in subsequent test runs. Notice that you have
to change both ocurrences of the rollover generic, at the
BCDRegControl and at the BCDRegister_Tester block.
o There are two ways to alter the value of generics, try both:
i. Reload the design and change the generic globally throughout the
design. Process:
o In variables window change the rollover value: PD > Edit > Change
o You are finished with this lab once you have verified correct operation
of the BCDRegister design.
Objectives
This module will cover the following topics:
Timing Constraints
Timing Constraints
♦ Timing constraints effectively define the time budget within
which the optimized logic must produce a stable output
♦ Precision supports Synopsys Design Constraint (SDC) format
timing constraints
♦ SDC constraints be read and / or applied
! Allows Precision to read ASIC IP constraint files
Notes:
Input to output
D Q
Register to output
D Q
Input to Register
D Q D Q
Register to Register
9-3 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Port Constraints
Port Constraints
♦ 3 types of Port Constraints
! Clock
! Input Delay
! Output Delay
♦ Can only be set using the SDC commands
9-4 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Clock Constraints
Clock Constraints
clock period
(20)
create_clock clk1 -period 20
create_clock clk1 -period 20 clk1
offset
create_clock clk1 -period 10 -waveform {5 15} (5)
create_clock clk2 -period 20 -waveform {5 15} clk2
duty cycle
create_clock clk1 -period 10 -waveform {0 5} (75%)
create_clock clk3 -period 20 -waveform {0 5} clk3
falling
edge
9-5 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
9-6 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Multiple clocks are quite common in today's circuit designs. Proper handling of
multiple clocks is a major improvement that CTE timing analysis brings over the
Leonardo timing engine. In the case of phase shifts between clocks of identical
frequency, this is largely a convenience of constraint nomenclature. The effect of
this phase shift can just as correctly be modeled as a latency between 2 real clocks
based on the same ideal clock as it can by two different ideal clocks.
For clocks of different frequency, it is necessary for the tool to find the clock
period where the clocks most closely approach each other. The timing report will
show the clock period where this occurs when reporting violations. For example,
worst case timing might be found at the 3rd rising edge of the source clock and the
6th rising edge of the destination clock. In general, the greatest common multiple
of the 2 clock periods will be used as the clock period for analysis. Clocks
without small integer common multiples are probably not related, and any paths
between these clocks are probably false.
Clk1
D Q D Q
Clk2
9-7 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
9-8 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Clock Propagation
Clock Propagation
9-9 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
D Q 4 ns 6 ns D Q
10 ns
Clk
9-10 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Output Constraints
Output Constraints
♦ Set as output delay
! Signal time after the rising clock edge that the output signal must
be valid
out1
D Q 3 ns 7 ns D Q
Clk
Clock Period = 10 ns
Output Delay = 7 ns
9-11 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Bi-Directional Constraints
Bi-Directional Constraints
♦ Must set both an input_delay and output_delay constraint
following the usual rules
2 constraints must
be set in IO ports
D Q 7 ns
Clk
En
Actual Chip
9-12 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
9-13 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Multi-cycle Paths
♦ Use to “relax” timing constraints on Clk
specified logic
♦ Can be applied “to”, “from” or Data
“through” any pin or port
Data changes every other clock cycle
♦ Use “get_pins” to help locate pins (see Multi-cycle path : data not used until
second clock edge
next slide)
9-14 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
9-15 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
It is important to understand the meaning of these object types in SDC. Some of
the names are less than intuitive.
• Clocks are ideal clock names that have been defined earlier in SDC, not
ports that drive clock pins.
9-16 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
9-17 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Setting Constraints
Setting Constraints
From Text files
♦ Query mode information viewing
and constraint setting can be done
on text files
! RTL (after compile)
! Missing constraint reports
! Place and route timing files
♦ Must click on object first
9-18 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
9-19 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
A_in 10 ns B_out
9-20 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Reporting on Constraints
Reporting on Constraints
♦ “report_constraints” command will list all Constraints Report
applied constraints on the design
9-21 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Constraint files
can be edited, and
added to the input
file list
♦ Constraints files
can be
automatically
generated from the
information in the
‘Precision
Synthesis Setup
Dialog Box’ within
HDL Designer
9-22 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Constraint entry — I'm not sure if you're a big fan of the spreadsheet-based
constraint editors, but we find the dialogs to be much nicer. Especially when you
can use the dialogs to set constraints on an entire bus. In fact, you could right-
click on the outputs folder to select the output delay for all outputs of your design.
The top portion of the dialog is for setting input or output delay, relative to which
edge of which clock, or you could set a false or multi-cycle path. The bottom
portion is for choosing pad type, pin location, and forced IOB mapping.
You can even right click on schematic objects and set their constraints right from
the schematic. Why should you have to get out of the schematic viewer, open the
constraints editor, and hunt around for that net you want to constrain when it's
already there in front of you on the schematic?
It's very easy to get more information from various schematic views.
Pop Quiz
Pop Quiz
6 C
D Q D Q
A 5 20 7 B
Clk
9-23 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
6 C
D Q D Q
A 5 20 7 B
Clk
9-24 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
9-25 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
9-26 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
The Xilinx NCF file is automatically generated during the optimise stage.
9-27 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Timing Optimization
Timing Optimization
9-28 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Report_Timing
Report_Timing
->report_timing -help
♦ Command line usage : "report_timing" [<report_file_name>]
[-append] -- append data to existing report file
report_timing command [-replace] -- replace existing report file (if present)
[-num_paths <integer>] -- number of paths to report
supports 35 switches [-capacitance]
[-fanout]
-- show capacitance values in report
-- include fanout paths
♦ Synopsys PrimeTime [-show_schematic]
[-show_nets]
-- show critical path schematic(s)
-- include net names in report
compatible command [-cell_names]
[-slew]
-- include cell names in report
-- include slew values in report
subset [-limit_value <string>] -- show only paths with slack less than this value
[-through <list>] -- report only paths through these nets or instances
! To, from, through, setup, [-from <list>] -- report only paths starting at this port, port_inst or instance
[-to <list>] -- report only paths ending at this port, port_inst or instance
hold, slew, all_clocks [-setup_flag] -- provide setup slack path detail report
[-physical] -- provide physical placement information
♦ Can be issued from the [-critical_paths] -- provide information for critical paths
command line interactively [-end_points]
[-start_points]
-- provide summary information
-- provide summary information
[-longest] -- not supported ... reports critical path
[-clock_frequency] -- report clock frequency estimates
[-hold_flag] -- provide hold slack path detail report
[-all_clocks] -- report worst path for each clock group
[-nworst <integer>] -- report only N worst paths per endpoint
[-npaths_per_startpoint <integer>]-- report only N worst paths per startpoint
[-margin_limit_slack <string>]-- report only paths with worse slack than indicated
[-summary] -- report summary
[-more_paths] -- get more, less critical paths
[-source_clock_path <integer>]-- show source clock path (Batch mode ONLY)
[-test_tech_cell_char] -- test option to test tech cell characterization
[-histogram] -- generate a histogram of slack paths
[-hist_num_bins <integer>]-- number of bins for histogram (default 10)
[-hist_max_slack <string>]-- max slack for histogram (default actual max slack)
[-hist_min_slack <string>]-- min slack for histogram (default -(actual max slack))
9-29 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Report_timing -source_clock_path
Report_timing -source_clock_path
9-30 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Report_timing -histogram
Report_timing -histogram
9-31 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
9-32 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
View Trace
Notes:
9-34 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Notes:
results A I
B C D J K L
E F M N
G H
After Auto-dissolve
TOP_LEVEL
A,B,D I,J
C K L
E F,G,H M N
9-36 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Hierarchy management ó adding ports where necessary to prevent the need for
flattening.
LUT1
9-37 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Fanout-based cross-hierarchical register replication.
Reg
9-38 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
Fanout-based cross-hierarchical register replication.
Synthesis Options
Synthesis Options
9-39 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
9-40 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation
Notes:
You will synthesize a part of that design, and investigate the effect of changing
constraints on that design. You will also take the design through to place and
route.
Directions
Part 1: Add a new Library Mapping for the full RTC Design.
• The design has been read in, and synthesized for the chosen device, now
lets investigate the design in various ways
Hint: use the Design Hierarchy panel, and expand ‘Clocks’. Moving the
cursor over a clock causes an information box to appear
No of Clocks:___________________________
Table 9-1.
Clock Domain Period Clock Domain Period
(ns) (ns)
• Look at the Timing Violation Report (Use the Design Analysis section in
the Design Bar to regenerate the report, don’t look at the report in the
Project Files in the Design Centre tab )
• Look at the Timing Report (Use the Design Analysis section in the Design
Bar to regenerate the report, don’t look at the report in the Project Files in
the Design Centre tab)
Note that the Timing report gives you information on the maximum
Frequency for each of the clocks, and a summary of the 10 most critical
timing paths. The worst path is shown in detail.
However the timing results are deceptive, as not all paths have been
considered.
• To find out which paths have been ignored we need to report timing with a
different command line switch.
the Project Files pane of the Design Centre. The result should look
something similar to the window below.
The lower of the two panes is the transcript window, and you need to
click in this window to be able to type in a command However first look
at what is in there. You may have extra lines in your window, where
you have been trying different things, but the 5 lines in the screen shot
above can be related directly to these instructions.
• report constraints: The full command here is the one that was
exercised when the ‘Report Timing Violations’ button from the
• report timing: The three report timing lines make up the three parts
of the timing report generated when the ‘Report Timing’ button
from the Bar was exercised. The first reports clock frequency, the
second lists the 10 summary critical paths, and the third the detail
listing of the most critical path. The three commands all wrote to the
same file, the first opening the file, and the other two appending to it.
If you used the report files in the Project Files panel rather than the
icons in the Design Bar, then you won’t see the report lines. This is
because the reports you were looking at were generated as part of the
synthesis operation, and you just opened them to view, but the icons
actually generate the reports.
Click in the lower half of the Transcript window, and enter the
following:
report_timing -clock_domain_crossing
The resulting report appears in the upper half of the Transcript window.
You will need to scroll through the window in order to see all the
output.
• The design has been read in, and compiled. compare the clocks with the last
time, they should be the same.
Each time that you add a constraint, the constraints file is updated. To
see this look at the transcript window.
Hint: Run Report timing from the Design Bar, then use transcript
window to copy earlier report_timing command for a summary of more
than 10 paths.
All of these violations existed for the first run, but were not considered
during the analysis due to the way the clock domains were defined.
• We will run the place and route to see if the design can meet timing even if
the synthesis timing report has errors.
o Open the ISE 5.2 section of the Design Bar, and click on Place and
Route.
o When this is finished go to the Design Centre window. There are now
various Xilinx report files visible.
• Now we are going to report on those paths which cross clock boundaries
again.
Click in the lower half of the Transcript window, and enter the following:
report_timing -clock_domain_crossing
The resulting report appears in the upper half of the Transcript window.
You will need to scroll through the window in order to see all the output.
o Click on the source D-type, and use the pull down menu to trace back to
the HDL source, and to the HDL Designer diagrams.
Part 4: Re-timing.
• The design has been read in, and compiled. compare the clocks with the last
time, they should be the same.
• Set the Clock constraints to the same values as those used in Part 2.
You could do this by repeating the section in Part 2, or you could apply the
actual constraints file that was written in Part 2. To do the latter:
This will open the folder and show several files, one of which is called
RTC_clock_constraints.sdc. Double click on this file to open it.
o The Project Files list will now show a constraints file below the
“Constraints Files”, as in the above screen view.
Click the RMB on this file to bring up the menu seen above. click on
‘Apply Constraints File’
Check that the constrains have been applied by looking at the some of
the clock constraints.
Look at the transcript. You will see that two commands were used, the
first to define the constraints file as an input file, and the second
applying the constraints to the design. What are these two commands?
o Select Optimization
in the left of the
dialog
The optimization
options will appear
on the right-hand
side of the box.
Click ‘OK’
We now have defined all clocks to be in the same domain, and asked for
re-timing to be done during synthesis.
Hint: Run Report timing from the Design Bar, then use transcript
window to copy earlier report_timing command for a summary of more
than 10 paths.
What differences have you seen from the previous run? _______________
____________________________________________________________
____________________________________________________________
• We will run the place and route to see if the design can meet timing even if
the synthesis timing report has errors.
o Open the ISE 5.2 section of the Design Bar, and click on Place and
Route.
o When this is finished go to the Design Centre window. There are now
various Xilinx report files visible.
We have still not correctly identified all constraints, as we did not define an offset
from clk for any of the internally generated clocks, but we know that there would
be an offset in reality, and these should be included.
Objectives
This module will cover the following topics:
• Top-Down Design
• HDL Designer Methodologies IBD / Block Based Design
• Maximizing Design Efficiency - Macrofunctions
• Vendor independent: ModuleWare
• Vendor tools: ALTERA Megawizard, XILINX CoreGenerator
• Intellectual Property
• Design Documentation using HTML Export
• Design Documentation using OLE
• Printing Diagrams
Top-Down Design
Top-Down Design
♦ Top-Down Design Flow:
! Concept
! Define design interface to external world
! Define high-level tasks
! Define interfaces between high-level tasks ?
! Design high-level tasks in behavioral VHDL
– Early Simulation of Dataflow
! Develop sub-tasks for each task
– Define sub-tasks RAM
I/O
– Define interfaces
CPU
– Develop sub-sub-tasks
– Iterate as necessary
♦ Advantages:
! Divides large designs into easily grasped
sections
! Tasks may be assigned to different work
groups early in design cycle
10-2 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
10-3 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
10-4 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
What is ModuleWare?
What is ModuleWare?
10-5 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
The above example shows a "drag and drop" instantiated multiplier, whose
parameters (input / output bus width) are automatically determined from the
connected signals. This is a great simplification compared to a manual
instantiation of a LPM multiplier.
MW — Dynamic # of Ports
MW — Dynamic # of Ports
♦ Available for:
! N-input & Variable width logic gates
! Split & Merge
♦ Simply drag top or bottom of part to increase/decrease
number of ports
♦ Alternatively change the setting in the dialog
10-6 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
MW — Settings Display
MW — Settings Display
♦ Summary of settings displayed in tooltip
♦ Also available in associated text block
! Default
! Custom using system variables
♦ User control over level of detail
! Master & Diagram preferences
! Per-object in parameters dialog
♦ Symbols also show main values as appropriate
Options>Master Preferences>Block Diagram...
10-7 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
10-8 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
10-9 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
MW — In-place Changes
MW — In-place Changes
10-10 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
MW — Language Support
MW — Language Support
♦ VHDL
! Supports std_ulogic & signed/unsigned in addition to std_logic
! Supported package combinations:
– ieee.std_logic_1164 plus...
– ieee.std_logic_arith / numeric_std
! “sign_type” parameter retained for arithmetic functions
! Type conversion automatically applied where necessary
♦ Verilog 2001
! Arithmetic parts support signed/unsigned types
! Options based on main style settings:
– Port Declarations ANSI-C or Combined
– @* or comma-separated sensitivity list
– New-style attributes or old-style pragmas
10-11 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ For
! Xilinx COREGen™
! Altera MegaWizard™
10-12 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
10-13 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
Altera MegaWizard
Altera MegaWizard
10-14 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
What is an IP?
What is an IP?
10-15 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
How to Instantiate an IP
How to Instantiate an IP
1. In Blockdiagram window:
Icon Add External IP
2. Specify path to IPs
Interface description
3. Select IP model -if
applicable
4. Set library which
contains precompiled
simulation model
10-16 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
10-17 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
For unrecognized
extensions only
10-18 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ The files are parsed and analyzed. Eventual warnings or errors can be reported at
that stage.
♦ The user decides which part of the design he’d like to import
10-19 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
10-20 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ The tool analyzes the context from the HDL files and may require additional
mappings
♦ The user will be prompted only if the Multiple libraries option is checked in the
General Tab
♦ The user can explicitly create the mapping or let the tool do it for him
10-21 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Result as specified:
! All design units reside in
one library
! All design units are HDL
views
! Full design hierarchy
visible
10-22 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
10-23 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
HTML Export
HTML Export
♦ The HTML export Target Directory
command can be
invoked from the File
menu or directly from
the toolbar menu in the
main window
File ⌫ HTML Export ...
Range
10-24 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
You can export an entire library or any design unit view (or hierarchy of views).
When it is used in a graphic editor, only the active view is exported. Export
HTML from the graphic editors is provided for updating existing views within an
exported hierarchy. However, it does not create the HTML frame set and other
supporting files. The HTML Export dialog box is displayed which allows you to
specify or browse for a target directory to contain the exported files. The HTML
Export dialog box also allows you to specify the graphics format which can be
JPEG or PNG. A compression percentage can be specified if you choose JPEG
(Joint Photographic Experts Group) format or a standard compression is used for
PNG (Portable Network Graphics) format.
♦ Navigation Frame
! Source Browser
! like HDS Design
Browser *
♦ Design Frame
! View / Navigate
*
– Multiple pages
! Information
– Ports / Declarations
– HDL Statements
! Side Data
! Generated HDL
10-25 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
The navigation frame displays the exported design hierarchy or library and can be
used in a similar way to the HDL Designer source browser. When a library has
been exported, you can expand and collapse each design unit to reveal their design
unit views including component symbols and non-default views. You can display
views by clicking on any item in the Navigation frame to display the
corresponding view in the Design frame.
The Diagram tab of the design frame displays design unit views described by
diagrams or tables as resizable graphics with hotspots connecting to other HTML
pages in the hierarchy. These hotspots can be used to open down into hierarchical
child views or you can use the button to move up through the design hierarchy. A
separate Information tab displays text information such as generation settings,
local declarations, compiler directives and package references. You can also use
choose separate tabs to display Side Data objects or the generated HDL for the
view.
Page boundaries
File → Page Setup...
10-26 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
The Boundaries tab provides options which allow you to control the display of
printer page boundaries. You can choose to show the boundaries in diagram editor
views and to include an optional page number which can be used to selectively
print a page or range of pages. The page boundaries are displayed as dotted
rectangles originating from the top left corner of the visible objects on the
diagram. You can choose whether the origin is automatically re-located when you
refresh the boundaries after making changes to the diagram.
The page boundaries are automatically refreshed when you change the page
settings or you can choose Refresh Page Boundaries from the File menu to update
the displayed boundaries after you have changed the diagram.
10-27 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
* The table editor views (truth table, tabular IO and IBD view) support OLE for
tools which recognize enhanced metafiles. These include Microsoft PowerPoint,
Excel and Word XP but not FrameMaker or older versions of Word.
10-28 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
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10-29 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
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10-30 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
Link to File
10-31 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
10-32 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
! Note: This lab just provides the more complex RTC design which
will be used for the advanced labs.
10-33 • Designing with FPGA Advantage: Top-Down Design Copyright © 2003 Mentor Graphics Corporation
Notes:
During this lab you will replace the BCD Counter design unit with a counter you
generate with XILINX’s Core Generator. Using this kind of logic generators
usually results in a significant productivity gain but there are some prerequisites
and “traps” you should be aware of. Therefore you will encounter some typical
problems during this lab but solutions and explanations are provided. You may
use them as guidelines for your own projects.
If you are using Altera technologies the same procedure can be done with the
Altera Megawizard.
Summary
• In the first section create a new library and copy the original BCDCounter
and testbench into it. Using the XILINX CoreGenerator create another
implementation of the BCD Counter and instantiate it in the testbench
design. Test, compare and troubleshoot the behavior of the two different
counter implementations.
• In the second section copy the BCDRegister design and testbench into the
new library, replace the BCD Counter design unit with the CoreGenerator
counter. Test and troubleshoot the behavior of the modified BCDRegister.
Directions — Section 1
o Select the BCDCounter_tb design unit and select “Copy” from the
popup menu.
o Browse the contents of the new library and check whether the
referenced Blocks and Components point to the new library BCD_Core
or to the originating library.
o When the Core Generator GUI is invoked take some time to browse
through the available functionalities. Then choose (doubleclick) the
“Binary Counter” from category “Basic Elements > Counters”.
o Use the configuration dialog to configure the counter for the desired
behavior. Note that a BCD counter can be modeled using a four bit
binary counter with rollover at 9. The “Threshold” setting generates the
“carry out” signal.
1.
2.
After having finished the setup generate the counter by clicking on the
“Generate” button in the “Binary Counter” dialog box.
o Close the “Core Generator Interface” dialog. You should see now a
Design Unit called bcd_core in the BCD_Core Library.
o Use an inverter from the Moduleware Library to invert the clear signal.
Use the following block diagram as a guideline:
o HDL Designer complains about the net “load_in” where the needed
type is “std_logic_vector”. This type of conflict always happens when
you use other data types (like unsigned) than std_logic in your design.
Core Generator always uses std_logic and std_logic_vector signals.
Therefore you have to convert the unsigned signal “load_in” to
o The conversion function used needs the ModelSim compiler use the
“-93” switch to compile the VHDL code according to the VDHDL93
standard.
If you see these errors follow all the following instructions, if not jump
to the instruction that says ‘Start Simulation’, this is on the next page.
o HDL Designer does not find the referenced simulation model for the
generated bcd_core design unit.This is caused by the fact that the
library containing the CoreGenerator’s simulation models is not
compiled for ModelSim
a. <on Windows only> Turn off the Read Only attribute of the
Modelsim.ini file to make it writable, the ModelSim.ini file is located in
the ModelSim installation directory. Ask your instructor for details, if
you have difficultiers to locate it.
This is necessary to allow the Xilinx compile script to add the library
mapping to the ModelSim.ini file.
This will compile the Spartan2 CoreGen library VHDL models for
ModelSim into the specified directory. If you want to see the program’s
options type “compxlib -help”
o Now run the Simulation Flow again. This time there should be no
errors.
o Start Simulation and compare the output of the two different counter
implementations.
o Note the slightly different behavior of the bcd_core signals prior to the
active reset signal!
In this lab, you will load a new design which implements a Real Time Clock,
which uses the BCDRegister design you created in earlier labs. You will simulate
it first using a provided VHDL testbench and then using a TCL implemented
graphical testbench.
Directions
Clock Divider
Registers Multiplexer
Decoder
The Real Time Clock (RTC) design stores the time in seconds,
minutes, hours, and the day of the week. Data can be input
synchronously to set the clock by asserting a chip enable input signal.
The current time is always available on the data_out bus, based on the
value of the addr input bus.The RTC can be reset to a default state. In
the presence of a 65 kHz clock signal, the RTC will constantly update
the time.
o Load sequence
o Read sequence
• Part 2: Simulate the RTC design using the provided RTC_tb testbench.
The RTC_Tester is a very simple Testbench which just runs the clock in
normal mode. No load functionality or output decoding is tested.
o Modify the testbench to see the output of all registers. One suggestion is
to rotate around the output of the registers.
• Part 3: Simulate the RTC design using the provided RTC_GUI TCL
testbench.
You can use the TCL testbench together with the VHDL testbench, you
don’t have to reset the simulator prior to invoking the TCL GUI.
o Run the TCL script by the pulldown command Tools > Execute Macro
in ModelSim Main window. Choose the file rtc_gui.tcl in the
$FPGADV_LABS/rtc/tcl_tb directory.
o When the window pops up click on the “Refresh Display” button to see
the actual clock values.
o Click the “Help” Button to see the functionality of the other buttons,
how to set the clock etc.
i. Reset design
This approach for building a testbench is very useful when user interaction
is needed during testing of a design. It’s also helpful to provide a “real”
product like behavior of the simulation.
Objectives
This module will cover the following topics:
Constraint-Based Optimization
Constraint-Based Optimization
♦ The optimization process is driven by
timing constraints Perform quick
optimization on all
hierarchy blocks
♦ Critical blocks are automatically
identified and reoptimized with more
effort
! Unconstrained designs are optimized for
Use Timing Analysis to
area
identify critical blocks
! Minimal run times are achieved with
relaxed constraints
Perform additional
optimization on and
between critical blocks
11-2 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
High-Level Optimization
High-Level Optimization
♦ State machines are extracted and
optimized + MUX
+
MUX
-
11-3 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
LeonardoSpectrum performs several high-level, technology independent
optimizations such as FSM, constant propagation and operator resource sharing.
Optimizations performed at the high-level often have the greatest impact on
quality of results.
♦ Logic restructuring
11-4 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
11-5 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Notes:
Full recognition and extraction of state machines in VHDL and Verilog, written in
1-process, 2-process, or 3-process styles.
Pipelining
Pipelining
♦ A method of speeding up synchronous logic by adding
pipeline registers:
Before pipelining:
After pipelining:
Advantage: Disadvantage:
♦ Circuit reg-reg time is decreased ♦ Greater Clock Latency on output signal
♦ less intuitive VHDL
11-7 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Pipelining in Precision
Pipelining in Precision
♦ In some technologies precision will automatically pipeline
multipliers given the correct input design:
Registers to be ‘absorbed’ into multiplier
User design, before synthesis
♦ Fully combinatorial multiplier
♦ Place ‘absorbing’ registers at
*
output of multiplier
♦ Place input and output registers
for optimal performance
Combinatorial multiplier
Notes:
11-9 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Technology Mapping
Technology Mapping
♦ Leverage superior analysis capabilities for best Quality of
Results
11-10 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Synthesis Options
Synthesis Options
11-11 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
11-12 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Timing
Timinganalysis
analysisbased
basedon
on
propagated constraints
propagated constraints
Only
Onlythe
theDCM
DCMinput
inputclock
clockisisconstrained
constrained
DCM
DCMoutput
outputconstraints
constraintsare
are
automatically
automaticallypropagated
propagatedfor
forTiming
Timing
Analysis
Analysis
11-13 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
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11-14 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
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11-15 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
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11-16 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
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11-17 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Setup_design
Setup_design
♦ Sets up the details about how a setup_design [<library_name>]
design is optimized [-manufacturer
<manufacturer’s_name>]
! Target technology
[-family <library_name>]
! Target frequency [-part <part_name>]
! optimizations [-speed <speed_grade>]
[-package <package_name>]
# Setup Technology Environment [-cim
setup_design -manufacturer "Xilinx" <[commercial|industrial|military]>]
setup_design -family "VIRTEX-II" [-btw <[best|typical|worst]>]
setup_design -part "2V40cs144" [-addio
setup_design -speed "6” [-vhdl
Setup_design –frequency 100
[-verilog
Setup_design -retiming
[-edif
# Add input files [-retiming
add_input_file {traffic.v} [-design <design_top>]
[-architecture <root_arch_name>]
# Complete the optimization process [-frequency <freq_mhz>]
compile [-search_path <search_pathnames>]
synthesize [-list_technology
[-reset]
11-18 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Add_input_file
Add_input_file
♦ Used to add all formats of add_input_file <file_list>
input files to a design [-format <file_type>]
[-work <library_name>]
! Constraint files [-insert_before <position_number>]|
! Edit netlist [-insert_after <position_number>]|
! RTL files [-replace]
[-search_path <pathname_list>]
11-19 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Compile
Compile
♦ Compile command has no
arguments or switches # Setup Technology Environment
setup_design -manufacturer "Xilinx"
setup_design -family "VIRTEX-II"
setup_design -part "2V40cs144"
♦ Will read and compile all the setup_design -speed "6"
input files
# Add input files
add_input_file {traffic.v}
11-20 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Synthesize
Synthesize
♦ Has no switches
# Setup Technology Environment
setup_design -manufacturer "Xilinx"
♦ Will optimize the design setup_design -family "VIRTEX-II"
! Must run “compile” first setup_design -part "2V40cs144"
setup_design -speed "6"
11-21 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Saving Netlists
Saving Netlists
♦ The “synthesize” command will automatically save an xdb
and edif netlist
11-22 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Report_area
! Reports device utilization and cell count
♦ Report_timing
! Primetime compatible includes over 35 switches
♦ Report_net
! Reports fanout, capacitance and slew on a net
♦ Report_missing_constraints
! Lists all clocks and ports that are not constrained
♦ Report_constraints
! Lists all the constraints set on a design
11-23 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
11-24 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Key Benefits
! Quickly view reference help for Precision commands
11-25 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ From the GUI use the pull-down menu “File > Run Script”
command
11-26 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
11-27 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Internal Clocks
Introduction
In this lab, you will use some of the capabilities within Precision for dealing with
Instantiated DCM or DLL elements from Virtex technologies.
Directions
o Add mapping for a new library Int_clk, using the following settings:
• Regular Library
• Library Name: Int_clk
• Directory: $FPGADV_LABS/synth_labs
• Downstream Data Directories for Precision
• No Version Management
• Not default library
o After adding the library, open it to see the clk_div design unit, do NOT
look at the source for this unit.
o Invoke the Precision Design Flow on the clk_div unit, using the
following settings:
• Technology: Virtex-II
• Device: 2V80fg256
• Speed Grade: -4
• Clock Frequency: Do NOT set
• Add IO Pads: yes
The default is to use the “worst case” scenario as if the flop were a
trigger flip flop and propagate a 2x period. This ensures that the design
is at least constrained should the user forget to constrain an internally
generated clock. If no constraints are provided to the P&R software,
then the FPGA may be failing in the “real world” timing, but nobody
would know until a strange failure mode occurred after the board had
been shipped. This can be seen in the RTL Schematic, as shown below.
Once you have found the BUFG that was inserted, close the schematic
window.
o Check the Precision timing report to verify that it has indeed seen the
10 ns clock period from the DCM.
o Implement a “report_timing”
on the D input pin of the register
called reg_data_out_slow(15).
(Look in the Technology
Schematic)
Source Clock:
_______________________
Destination Clock:
_______________________
o In the Design Centre, check the Xilinx User Constraints File to see the
input clock and internal clocks are both constrained correctly. They
should be seen to be separate, unrelated TIMESPEC’s
Check the Timing report to ensure that the 10ns constraint has been
used, based from the 20 ns reference constraint.
This example uses a multiplier which is enabled every 16 clock cycles. This is
sufficient to illustrate the difference between false path reporting and multicycle
path reporting.
Directions
o After adding the library, open it to see the multi design unit.
o Invoke the Precision Design Flow on the multi unit, using the
following settings:
• Technology: VirtexE
• Device: V50efg256
• Speed Grade: -6
• Add IO Pads: yes
• Clock Frequency: Do NOT set
• Output Formats: EDIF
• Run Options: ‘Compile’
You may notice that the critical path passes through a modgen
multiplier and has end-points at a register bank associated with the
output_cd.
In the RTL code, this path through the multiplier is enabled every 16
clock cycles. So we can set a multicycle path constraint to provide more
accurate timing information for synthesis and P&R.
The SDC standard for Constraints does allow the setting of multicycle
paths on a pin as well as an instance. The pin based methodology is
more explicit, but both styles will be covered here.
o Invoke the Precision Design Flow on the multi unit again, using the
same settings as before
The detailed critical path comes from the counter, to the clock enable
of the reg_output_cd.
• Open the Xilinx User Constraint File. You will see that it contains
a TIMESPEC that de-constrains a path involving pins on flip-flops,
making the 160 ns.
• Run embedded Place and Route using the ISE 5.2 bar in Precision.
Press the “Place & Route” button.
o Repeat Part 3, until the constraints file is created, but do not save the
constraints file.
There is a danger here that you are improperly constraining the design,
gp through P&R, pass timing (based on the constraints) yet still fail
required behaviour on the PCB. It is a common mistake when setting
constraints in tools that are not pin-based. You can correct this by
creating explicit paths with a -FROM option.
• Verify that the Timing report shows the output register in the critical
path again, as in Part 3.
• Open the Xilinx User Constraints File and observe the FROM/TO
TIMESPEC commands created by Precision.
Now the clock frequency is reliant only upon the very tightly coupled
implementation, and not the decoding of the counter to all of the clock
enables in this small example.
o Now run the ISE 5.2 Place & Route, and when it is finished, open the
timing report and confirm the clk critical path is now reported as the
counter only.
The purpose of this lab is to illustrate the benefits of being able to assemble a
complete design within the Precision environment.
Directions
o Set up the memory using the three pages to define the parameters and
the following options:
• component name: my_dpram
• depth: 256
• Data Width: 8
• Memory Type: Dual Port RAM
• Multiplexor Construction: LUT Based
• Input Options: Non-Registered
• Click on Generate.
When the generate process is complete an information message will
occur. Click on OK. Click on Dismiss.
• Look in the side data section to check that the file my_dpram.edn
has been generated, this will be used by Precision later on.
• Open the Design Hierarchy panel, and look at the hierarchy of the
component processor_if.
o Invoke the Precision Design Flow on the processor_if unit, using the
following settings:
• Technology: VirtexII
• Device: 2V40cs144
• Speed Grade: -4
It will override the ‘Add I/O pads’ setting for these 4 pins. All other
pins should have buffers added.
Look for the RAM Primitives from the Coregen netlist. The
assemble of the design ensures that the timing through the Coregen
blocks can be seen and taken into account in synthesis, not just in
P&R.
• Trace forward one level of logic and highlight the schematic to see
that it directly drives a LUT1 (inverter) and does not have and I/O
Buffer associated with it.
• Use the Design Browser to see whether a BUFGP has been inserted
for the wr_bar input (N.B. This is a clock).
• Check that the only I/O without buffers are those defined in the
Constraints file.
An EDIF netlist and binary database (.xdb) have been written into the
implementation directory. Now we will start to assemble the entire
design.
The SDC constraints file has the required NOPAD constraints for I/O
that have already been synthesized in the lower level. It also sets
constraints for the clocks.
• Press Synthesize.
• Examine the timing report. You will see that there is no timing
information available for the wr_bar because it is contained totally
within the black box.
By the two clock frequencies that you have seen (wr_bar when you
synthesized the processor_if, and sys_clk just here), it might appear that
the performance of the design should exceed the 33 MHz and 50 MHz
constraints in the SDC. However, with a black box hole in the design,
you cannot really be sure until you go through Place & Route. We will
not do this now, but will first assemble the design by adding the .xdb
file that we previously created.
• Click on the ‘Add Input File’ icon on the Design Bar, this brings up
an ‘open’ dialog window.
• Look in the Instances folder in the Design Hierarchy, you should see
that the Processor Interface is no longer a ‘black box’.
• Open the RTL schematic. If you look you will see that the top_level
is RTL, but the inside the processor_if block the design already
contains Xilinx primitives, from the previous synthesis.
• Synthesize.
• Check the timing report.
Objectives
This module will cover the following topics:
12-2 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
12-3 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
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12-4 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
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12-5 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
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12-6 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
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12-7 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
To compile the XILINX libraries open a Command Prompt (Windows) or a Unix
shell. Type the command as follows:
This will compile the Spartan2 CoreGen library VHDL models for ModelSim into
the specified directory.
Waveform Compare
Waveform Compare
♦ Quickly identify errors
! Focus on initial cause of failure
! Review results with waveform viewer or ASCII reports
♦ Fastest, most complete waveform compare
! Continuous compare
– With or without tolerances (leading, trailing or both)
! Clocked compare
– Rising or Falling edge
– Delayed Clock Compare
! Complex conditional compares based on logic values with or
without time offset
! Integrated with waveform database
♦ Interactive or batch mode
♦ Language independent
12-8 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
12-9 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
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12-10 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
The following is a script for a complex compare of waveforms:
set PrefCompare(defaultVHDLXMatches) XU
dataset open 0.wlf gold
dataset open 5.wlf test
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {Golden Simulation Results}
add wave -radix hex -r gold:/*
quietly WaveActivateNextPane
add wave -noupdate -divider {Test Simulation Results}
add wave -radix hex -r test:/*
quietly WaveActivateNextPane
add wave -noupdate -divider {Compare data if reset inactive}
Simulation Comparison
Simulation Comparison
12-11 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
12-12 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Notes:
Code Coverage
Code Coverage
♦ New Coverage Metrics
! Branch, Statement, Expression,
Condition
♦ Minimum Impact on Design Flow
! No instrumentation of Source
Code
! Lowest Possible Performance
Impact
♦ Fully Integrated with NEW GUI
! Results Displayed in Structure
Window per Instance
! Results Displayed in Source
Window Colorized for each
Metric
! New Flat View which can be
filtered
! Missed Code Window linked to
source window.
! New Reporting
♦ Phased Release of Metrics
12-14 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Branch or Decision coverage ó Measures the coverage of expressions and case
statements that affect the control flow of the HDL execution.
12-15 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Important notes about coverage statistics
• Package bodies are not instance-specific; we sum the counts for all
invocations no matter who the caller is. Also, all standard and accelerated
packages are ignored for coverage statistics calculation.
12-16 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
• The Stmt Count column contains the number of executable statements in
each file.
• The Stmt Hits column contains the number of executable statements that
have been executed in the current simulation.
• The Stmt Percent column is the current ratio of Stmt Hits to Stmt Count.
• The Stmt Graph is a bar chart displaying the Stmt Percent. If the Stmt
Percent is below 90%, the bar is red; over 90%, the bar is green. You can
change this threshold percentage by editing the PrefCoverage(cutoff)
preference variable.
• The Branch Hits column contains the number of executable branches that
have been executed in the current simulation.
• The Branch Percent column is the current ratio of Branch Hits to Branch
Count.
• The Branch Graph is a bar chart displaying the Branch Percent. If the
Branch Percent is below 90%, the bar is red; over 90%, the bar is green.
You can change this threshold percentage by editing the
PrefCoverage(cutoff) preference variable.
You can sort code coverage information for any column by clicking the column
heading. Clicking twice will reverse the order.
12-17 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
The Branch tab also includes a column for line numbers, as well as a column for
branch code (conditional "if/then/else" and "case" statements).
"XT" indicates that only the true condition of the branch was not executed.
"XF " indicates that only the false condition of the branch was not executed.
Fractional numbers indicate how many case statement labels were not executed.
For example, if only one of four case labels was executed, the Branch tab would
indicate "X 1/4."
always @ (x or y) begin
z = 0;
if (x == 0) z = 1;
end
12-18 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
The example contains three countable statements. The statement z = 0; is one
countable statement. The if statement, however, can be viewed as either one or
two countable statements. if (x == 0) z = 1; is two more countable statements.
This makes this coverage metric more useful than line coverage because with line
coverage it would be considered covered even if z = 1 did not get executed.
12-19 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Decision coverage or branch coverage measures the coverage of expressions and
case statements that affect the control flow of the HDL execution--for example:
if (z == 0) begin
...
else begin
...
End
This example contains a branch that could be exercised in one of two ways.
Branch coverage will report whether the if statement was evaluated as both true
and false during simulation. Note that decision coverage still applies if the else
statement doesn't exist, as in the following example:
if (z == 0) begin
...
end
The if statement can still be evaluated as both true and false; branch coverage will
still verify that both the explicit branch (z = 0) and the implicit branch (z = 1) are
executed. Branch coverage also applies to case statements:
case (z)
1: x = 0;
2: x = 10;
3: x = 20;
endcase
In this example, branch coverage will verify that each of the three branches of the
case statement is taken. In this particular example, however, the same information
could be obtained from statement coverage, since each leg of the case statement is
a separate statement. However, in the example:
case (z)
1,2: x = 0;
3: x = 10;
endcase
Combining Signals
Combining Signals
♦ Signals or busses can be combined
together into new busses
♦ These are created using “Virtual
Signals”
12-20 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Virtual Objects
Virtual Objects
♦ User Defined objects to generate context native to Engineer
♦ Objects created in the user-interface to display combinations
or expressions of logged signals in the design
♦ Multiple Object Types
! Virtual Signals
! Virtual Functions
! Virtual Types
! Virtual Regions
12-21 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Virtual objects are signal-like or region-like objects created in the GUI that do not
exist in the ModelSim simulation kernel.
Virtual Signals
Virtual Signals
♦ Create meaningful definitions
♦ Aliases For Combinations Of Signals
♦ Aliases For Subelements Of Signals
♦ Can Be Displayed In …
! Signals Window
! List Window
! Wave Window
♦ Accessed Using "examine”
♦ Set Using "force"
♦ Created by menu selections or "virtual signal" command
12-22 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Virtual signals are aliases for combinations or subelements of signals written to
the logfile by the simulation kernel. Virtual signals may be displayed by the
signals, list or wave window, accessed by the "examine" command, and set using
the "force" command.
Virtual signals may be created by menu selections in the signals, wave or list
windows, or created by the "virtual signal" command
12-23 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Examples of virtual signals:
Virtual Functions
Virtual Functions
♦ Create logical representations of existing signals
! Inverse Of A Signal
! A Type Conversion
! OR-Reduction
! XOR Of Two Vector Signals
♦ Logical Operations On Logged Signals
! Not Aliases of combinations or elements
♦ Can Be Displayed In …
! Signals Window
! List Window
! Wave Window (Expand Children)
♦ Accessed Using "examine”
! Can Not Be Set Using "force"
12-24 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Virtual functions behave in the GUI like signals but are not aliases of
combinations or elements of signals logged by the kernel. They consist of logical
operations on logged signals and may be dependent on simulation time. They may
be displayed in the signals, wave or list windows, accessed by the "examine"
command, but cannot be set by the "force" command.
12-25 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
Examples of virtual functions:
Creates a signal that is non-zero only high during times at which a signal
/chip/siga of the gate-level version of a design does not match /chip/siga of the rtl
version of a design.
12-26 • Designing with FPGA Advantage: Verification Methodology Copyright © 2003 Mentor Graphics Corporation
Notes:
In this lab, you will synthesize and Place & Route the RTC design. Then you will
import the gate-level netlist into HDL Designer and run the gatelevel simulation.
Then the gatelevel simulation will be automatically compared against the RTL
simulation.
Directions
o When ModelSim has started open the wave window and add all toplevel
signals to the wave window.
o Run the simulation for 100 us and verify that the Clock is working
correctly.
• Part 2: Synthesize and Place & Route the RTC design using the following
settings:
Select the RTC_out.vhd file from the shown directory and also the
RTC_out.sdf file at the SDF section of the dialog box.
o Click “OK”. There will be a new Design View, already set as default
view, under the RTC Design Unit:
o When ModelSim has started open the wave window and add all toplevel
signals to the wave window.
o In the wave window you see a comparison between the result of the first
simulation (GoldenResults) and the current simulation. The current
simulation uses delay information (stored in the SDF file) from the
P&R process. The output wave_out therefor shows a delay in the wave
window. During the comparison you receive a lot of differences due to
the delay of the “real” design. The next picture displays the wave
window and one of the differences due to the delay of the gate
simulation..
o Choose the reference dataset, and click on “Next >”. Before choosing
the signals, we need to set the tolerance.
o Now go back to the Comparason Wizard dialog and complete the setup
as before.
o The red lines in the wave window (indicator for waveform compare
errors) should disappear and ModelSim displays the following
messages in the main window:
o Quit ModelSim.
ModelSim Code Coverage allows you to identify which lines in your code are
being covered by the testbench. It is non-intrusive (instrumented code is not
required) and only minimally impacts simulation performance (<5%).
This lab introduces ModelSim’s Code Coverage feature, details the use of the
major Code Coverage commands, and shows how to append results from more
than one simulation run.
Directions
Remember to set the default view of RTC back to the ‘struct’ view, if you
have just been working with the gate level netlist.
o Open the RTC library, select the RTC_tb design unit and start
simulation by clicking on the “Simulation Flow” button. At the “Start
o When ModelSim starts you will see three additional window panes at
the ModelSim main window: The “Missed Coverage” “Current
Exclusions” and “Instance Coverage” windows. Since no simulation
has been run so far all reports are empty.
o Open the wave window and display all top level signals (rtc_tb) plus
the signals time_dd, time_hh, time_mm and time_ss from the rtc
design unit.
o Format all the 8-bit vector signals in the wave window with the display
radix “Hexadecimal”
o The “Instance Coverage” window shows poor coverage on all but two
instances.
This is due to the short simulation time, cause the minute, hour and day
registers of the clock were idle until now. Therefore they show little
coverage.
o Run the simulation five times for 10 ms and observe how the coverage
bars are rising. After a certain simulation time, the coverage percentage
of the most instances does no longer increase. Most of them show
between 40% and 80%, which is not acceptable unless you verified the
cause. During the following steps you will inspect some instances and
either correct the design/testbench or designate the “coverage miss” as
“feature”.
o Take some time to understand the coverage reports and try to find out
the reason for the coverage misses.
o The reason for the coverage misses is pretty obvious. The testbench did
not load the clock registers with new values. Therefore the
address_decoder and also the data_out_mux show coverage misses.
This is a “testbench problem” which can easily be solved by adding the
functionality to the testbench.
o In HDL Designer select the RTC_tb design unit and start the
“Simulation flow”. Run the simulation for 60 us.
Now you will see that both design units (address_decoder and
data_out_mux) show no more coverage misses.
The coverage misses at lines 47-48 and 52-54 are within the logic that
handles the rollover from 9 to 0 and produces the carry_out signal. But
in the RTC_Clock design none of the tens counters ever encounters a
rollover from 99 to 00. The Registers are forced to rollover at 59, 23
and 6. Therefore the reported coverage misses are a intended feature.
To get true coverage reports it is necessary to exclude these sections
from coverage reporting.
o Why wouldn’t it make sense to use the “Exclude Entire File” command,
since we excluded all reported lines? __________________________
o The coverage report of the tens counter should now show green bars for
Statement and Branch coverage.
time {command}
o Run the simulation for 100 ms and measure the time with Code
Coverage. Type the following at the VSIM command prompt:
o Save the setup of the waveform window: File > Save Format.
quit -sim
vsim rtc.rtc_tb
Restore the setup of the waveform window: File > Load Format.
vsim> quit -f
CONGRATULATIONS
You’ve got it!
Objectives
This module will cover the following topics:
A-2 • Designing with FPGA Advantage: Additional Block Diagram Features Copyright © 2003 Mentor Graphics Corporation
Notes:
A-3 • Designing with FPGA Advantage: Additional Block Diagram Features Copyright © 2003 Mentor Graphics Corporation
Notes:
Eg: If you rename a signal that enters a language block, the interface of the block is
modified but not the HDL. You get a warning that the HDL must be modified accordingly!
A-4 • Designing with FPGA Advantage: Additional Block Diagram Features Copyright © 2003 Mentor Graphics Corporation
Notes:
A-5 • Designing with FPGA Advantage: Additional Block Diagram Features Copyright © 2003 Mentor Graphics Corporation
Notes:
A-6 • Designing with FPGA Advantage: Additional Block Diagram Features Copyright © 2003 Mentor Graphics Corporation
Notes:
1- Double-click to edit
the properties
A-7 • Designing with FPGA Advantage: Additional Block Diagram Features Copyright © 2003 Mentor Graphics Corporation
Notes:
2- Create a bundle
A-8 • Designing with FPGA Advantage: Additional Block Diagram Features Copyright © 2003 Mentor Graphics Corporation
Notes:
A-9 • Designing with FPGA Advantage: Additional Block Diagram Features Copyright © 2003 Mentor Graphics Corporation
Notes:
Reconcile Interface
Reconcile Interface
Interface Discrepancy between the symbol and the block diagram (1)
A-10 • Designing with FPGA Advantage: Additional Block Diagram Features Copyright © 2003 Mentor Graphics Corporation
Notes:
A-11 • Designing with FPGA Advantage: Additional Block Diagram Features Copyright © 2003 Mentor Graphics Corporation
Notes:
Push down
A-12 • Designing with FPGA Advantage: Additional Block Diagram Features Copyright © 2003 Mentor Graphics Corporation
Notes:
Push down
A-13 • Designing with FPGA Advantage: Additional Block Diagram Features Copyright © 2003 Mentor Graphics Corporation
Notes:
A-14 • Designing with FPGA Advantage: Additional Block Diagram Features Copyright © 2003 Mentor Graphics Corporation
Notes:
Objectives
This module will cover the following topics:
B-2 • Designing with FPGA Advantage: HDL Import / HDL2Grapihcs Copyright © 2003 Mentor Graphics Corporation
Notes:
For unrecognized
extensions only
B-3 • Designing with FPGA Advantage: HDL Import / HDL2Grapihcs Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ The files are parsed and analyzed. Eventual warnings or errors can be reported at
that stage.
♦ The user decides which part of the design he’d like to import.
B-4 • Designing with FPGA Advantage: HDL Import / HDL2Grapihcs Copyright © 2003 Mentor Graphics Corporation
Notes:
B-5 • Designing with FPGA Advantage: HDL Import / HDL2Grapihcs Copyright © 2003 Mentor Graphics Corporation
Notes:
B-6 • Designing with FPGA Advantage: HDL Import / HDL2Grapihcs Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ Result as specified:
B-7 • Designing with FPGA Advantage: HDL Import / HDL2Grapihcs Copyright © 2003 Mentor Graphics Corporation
Notes:
B-8 • Designing with FPGA Advantage: HDL Import / HDL2Grapihcs Copyright © 2003 Mentor Graphics Corporation
Notes:
All
None
B-9 • Designing with FPGA Advantage: HDL Import / HDL2Grapihcs Copyright © 2003 Mentor Graphics Corporation
Notes:
None
All
B-10 • Designing with FPGA Advantage: HDL Import / HDL2Grapihcs Copyright © 2003 Mentor Graphics Corporation
Notes:
None
Name only
B-11 • Designing with FPGA Advantage: HDL Import / HDL2Grapihcs Copyright © 2003 Mentor Graphics Corporation
Notes:
B-12 • Designing with FPGA Advantage: HDL Import / HDL2Grapihcs Copyright © 2003 Mentor Graphics Corporation
Notes:
B-13 • Designing with FPGA Advantage: HDL Import / HDL2Grapihcs Copyright © 2003 Mentor Graphics Corporation
Notes:
B-14 • Designing with FPGA Advantage: HDL Import / HDL2Grapihcs Copyright © 2003 Mentor Graphics Corporation
Notes:
B-15 • Designing with FPGA Advantage: HDL Import / HDL2Grapihcs Copyright © 2003 Mentor Graphics Corporation
Notes:
Objectives
This module will cover the following topics:
More advanced capabilities are supported by the HDS interface but requiring some up-front
manual preparations (eg: MODULES with CVS)
C-2 • Designing with FPGA Advantage: Version Management Using HDL Designer Copyright © 2003 Mentor Graphics Corporation
Notes:
Verification
Verification Team
Team Designer-A
Designer-A
Work
Work Space
Space
V1.1 V1.3 V1.4
spc_ch5.vhd adrs_decode.v adrs_decode.v
Check In
Check Out
V1.4
V1.3
V1.2
Designer-B
Designer-A Check In V1.1 V1.1
Work
Work Space
Space
V1.0 V1.0
V1.1
spc_ch5.vhd adrs_decode.v
spc_ch5.vhd
Data Repository
Check Out
C-3 • Designing with FPGA Advantage: Version Management Using HDL Designer Copyright © 2003 Mentor Graphics Corporation
Notes:
V2.0
v2.0 v2.0 V2.0
Spec
v1.3 v1.5 Changed
v1.3 v1.2
v14
9. 4
V1.2
v1.1 v1.3 Release-1 to
V1.2
v1.1 v1.2 Verification
v1.0 Team
8. 28
v1.1
v1.0 v1.0 v1.0
memcntrl.vhd dt_latch.v spc_ch5.vhd adrs_decode.v
C-4 • Designing with FPGA Advantage: Version Management Using HDL Designer Copyright © 2003 Mentor Graphics Corporation
Notes:
Compare against
repository
C-5 • Designing with FPGA Advantage: Version Management Using HDL Designer Copyright © 2003 Mentor Graphics Corporation
Notes:
Setup
Setup
Options → Version Management...
Choose RCS, CVS, DesignSync,
VSS, SoS or ClearCase
Specify Repository
Directory
Including HDL,
default_view file and
Side Data Directory
♦ Do not include default_view file can keep your own default view in your workspace
C-6 • Designing with FPGA Advantage: Version Management Using HDL Designer Copyright © 2003 Mentor Graphics Corporation
Notes:
You can always choose which design objects will be under version management.
These will always include source design unit views and any associated design side
data but you can optionally include the default_view file when you check in a
design unit or hierarchy of design units. For example, you may choose not to
check in the default view file if different users are working on views of the same
design unit and want to use a different default view in their local workspace. This
option is always ignored when you check in a single design unit.
Check In
Check In
♦ Check In the selected objects (libraries, design units and design unit
views) to the repository using latest or specified version
Refer to notes
Latest/Specified Version
To transfer an
Optional Label existing label
Description (optional)
Notes:
You can optionally enable version management for user side data objects by
setting Side Data Directory. When this option is set, any user side data is also
checked in by default when you check in the corresponding design unit view.
Carefully use this option when the side data directory contains large binary files.
Check In (Cont.)
Check In (Cont.)
LOCKED
C-8 • Designing with FPGA Advantage: Version Management Using HDL Designer Copyright © 2003 Mentor Graphics Corporation
Notes:
Check Out
Check Out
♦ Check Out selected objects from repository using latest/specified
version
! will replace any “read-only” copies which exist in workspace
! cannot check out a file if it is already “editable”
Single Level
Or Hierarchy
Packages
Latest or
Specified Version
Notes:
Get
Get
♦ Get performs check-out without a “lock”, creating “read-only”
copies
! Check-out the selected objects from the repository using latest or
specified version as read only
! Not available for ClearCase
C-10 • Designing with FPGA Advantage: Version Management Using HDL Designer Copyright © 2003 Mentor Graphics Corporation
Notes:
Change Lock
Change Lock
♦ “Lock” makes selected objects in workspace “editable”
Lock or Unlock
C-11 • Designing with FPGA Advantage: Version Management Using HDL Designer Copyright © 2003 Mentor Graphics Corporation
Notes:
Label
Label
♦ Add/Remove/Overwrite a symbolic name for selected objects
! The label is used to identify a set of version controlled design
objects which may have different individual version numbers but
share a common label
Add/Remove/Overwrite a Label
User provides “Label”
C-12 • Designing with FPGA Advantage: Version Management Using HDL Designer Copyright © 2003 Mentor Graphics Corporation
Notes:
Synchronize
Synchronize
♦ Performs a check-out without a lock,
! existing “read-only” objects are overwritten
! existing “editable” objects ignored
! option to update workspace with
missing files
C-13 • Designing with FPGA Advantage: Version Management Using HDL Designer Copyright © 2003 Mentor Graphics Corporation
Notes:
Status
Status
♦ Show the status of selected object
editable or read-only
Labels/Tags
C-14 • Designing with FPGA Advantage: Version Management Using HDL Designer Copyright © 2003 Mentor Graphics Corporation
Notes:
History
History
♦ Show the version history of selected objects
Summary of Version,
Label, Author, Check-
in Date, Comment
Details
C-15 • Designing with FPGA Advantage: Version Management Using HDL Designer Copyright © 2003 Mentor Graphics Corporation
Notes:
♦ The generated HDL files can be versioned manually by the user if the
option is enabled Option → Version Management ...
♦ The generated HDL can be out of sync with the graphical source if no
generation has occurred after the last changes
C-16 • Designing with FPGA Advantage: Version Management Using HDL Designer Copyright © 2003 Mentor Graphics Corporation
Notes:
If you enable Allow management of generated HDL, the version management
commands can also be used for generated HDL files in the HDL browser. The
repository location for these files (when you are using RCS, CVS, DesignSync or
Visual SourceSafe) is a directory called _hdl which is created directly below the
normal repository location.
! get a library always get the whole of those currently in the repository.
C-17 • Designing with FPGA Advantage: Version Management Using HDL Designer Copyright © 2003 Mentor Graphics Corporation
Notes:
Objectives
This module will cover the following topics:
• Creating a Package
• External Package Source
• Using a Package
Creating a Package
Creating a Package
♦ Packages can be created in a HDL Designer library. First
create the package header and then if appropriate the package
body.
Notes:
D-3 • Designing with FPGA Advantage: Packages Copyright © 2003 Mentor Graphics Corporation
Notes:
Using a Package
Using a Package
♦ To use a particular
package:
! Select the library
! select the package
D-4 • Designing with FPGA Advantage: Packages Copyright © 2003 Mentor Graphics Corporation
Notes: