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Designing with FPGA Advantage

Student Workbook

November 2003

Copyright  Mentor Graphics Corporation 2003. All rights reserved. This document contains information
that is proprietary to Mentor Graphics Corporation and may not be duplicated in whole or in part in any
form without written consent from Mentor Graphics. In accepting this document, the recipient agrees to
make every reasonable effort to prevent the unauthorized use of this information.
This document is for information and instruction purposes. Mentor Graphics reserves the right to make
changes in specifications and other information contained in this publication without prior notice, and the
reader should, in all cases, consult Mentor Graphics to determine whether any changes have been
made.

The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in
written agreements between Mentor Graphics and its customers. No representation or other affirmation
of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor
Graphics whatsoever.

MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OR MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.

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CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS)
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This is an unpublished work of Mentor Graphics Corporation.

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The following are trademarks of Mentor Graphics Corporation:

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TM-iii
Mentor Graphics’ trademarks may only be used with express written permission from Mentor Graphics. Fair use of Mentor
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Other brand or product names that appear in Mentor Graphics product publications are trademarks or registered trademarks of
their respective holders.
Updated 12/4/02

TM-v
TM-vi
Table of Contents

TABLE OF CONTENTS

About This Training Workbook ..................................................................... xxiii

Module 1
FPGA Advantage Basics .....................................................................................1-1

HDL Design Flow with FPGA Advantage .........................................................1-2

FPGA Advantage Tools ......................................................................................1-4
A Quick Look at HDL Designer .........................................................................1-5
Why Use HDL Designer? ...................................................................................1-6
Design Creation Flow .........................................................................................1-7
A Quick Look at ModelSim ................................................................................1-8
A Quick Look at Precision RTL .........................................................................1-9
HDL Designer Philosophy ................................................................................1-10
Where Does HDL Designer Fit in the Design Flow? .......................................1-11
Preparing to Use HDL Designer .......................................................................1-12
The Design Manager .........................................................................................1-13
The Design Manager — Basic Layout .............................................................1-14
The Design Manager — Project Manager ........................................................1-16
Project Manager — My Project File .................................................................1-18
Project Manager — Shared Project Files ..........................................................1-19
Concept of Library/Unit/View ..........................................................................1-20
HDL Designer Design Data Structure ..............................................................1-21
How Does HDL Designer Find These Directories? .........................................1-22
Example Project File — Format .......................................................................1-23
Create and Modify Library Mappings ..............................................................1-24
Design Manager — Design Explorer ...............................................................1-25
Design Explorer — Design Units Mode ...........................................................1-26
Design Explorer — HDL Files Mode ...............................................................1-27
Design Explorer — Hierarchy Pane .................................................................1-28
Main Icons in the Design Explorer ...................................................................1-29
Manipulations in the Design Explorer ..............................................................1-31
Side Data SubWindow ......................................................................................1-32
Downstream SubWindow .................................................................................1-33

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TABLE OF CONTENTS

Resource Settings ..............................................................................................1-34

Main Settings: General .....................................................................................1-35
Main Settings: Text Editor ................................................................................1-36
Main Settings: User Variables ..........................................................................1-37
Code Generation ...............................................................................................1-39
Code Generation Preferences — VHDL ..........................................................1-40
Code Generation Preferences — Verilog .........................................................1-42
Resource Settings ..............................................................................................1-43
What is the Flow Through HDL Designer? ......................................................1-45
Getting Started Wizard .....................................................................................1-46
Create a Design Unit .........................................................................................1-47
Create a Design Unit — Bottom up ..................................................................1-48
Create a Design Unit — Top down ..................................................................1-50
Create a Design Unit View — Top down .........................................................1-51
Lab 1: Testing and Synthesizing a BCD Counter .............................................1-52
Lab 1: Testing and Synthesizing a BCD Counter .............................................1-53

Module 2
Block Diagram Basics .........................................................................................2-1

What is a Block Diagram? ..................................................................................2-2

Block Diagram Editor Window ..........................................................................2-3
When to Use Block Diagrams ............................................................................2-4
Block Diagram Design Objects ..........................................................................2-5
Design Objects: Blocks & Components .............................................................2-6
Design Objects: Embedded Blocks ....................................................................2-7
Design Objects: Summary 1 ...............................................................................2-8
Design Objects: Signals ......................................................................................2-9
Design Objects: Ports .......................................................................................2-10
Design Objects: Summary 2 .............................................................................2-11
Object Properties ..............................................................................................2-12
Editing Object Properties ..................................................................................2-13
Object Properties Dialog Box ...........................................................................2-14

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TABLE OF CONTENTS (Cont.)

Block Diagram Preferences ..............................................................................2-15

Setting Block Diagram Preferences ..................................................................2-16
Creating and Opening Block Diagrams ............................................................2-17
Adding Blocks to a Block Diagram ..................................................................2-18
Instantiating Blocks ..........................................................................................2-19
Instantiating Components .................................................................................2-20
Instantiating Embedded Blocks ........................................................................2-21
Routing Signals .................................................................................................2-22
Setting Signal Defaults .....................................................................................2-23
Individual Signal Properties .............................................................................2-24
Connecting Signals to Blocks ...........................................................................2-25
Connecting Signals to Objects ..........................................................................2-26
Design Objects: Comment Text Objects ..........................................................2-27
Adding Comments ............................................................................................2-29
Assigning Comment Locations .........................................................................2-30
Graphical Comments ........................................................................................2-31
Saving the Design .............................................................................................2-32
A Block Diagram Example ...............................................................................2-33
Lab 2: Building the BCD Register ....................................................................2-34
Lab 2: Building The BCD Register ..................................................................2-35

Module 3
Finite State Machine Basics ................................................................................3-1

State Machine Styles: Moore vs. Mealy .............................................................3-2

State Machine Styles: Moore / Mealy / Mixed ...................................................3-3
State Diagram Objects ........................................................................................3-4
State Diagram Objects: Hierarchy ......................................................................3-6
FSM Wait States .................................................................................................3-7
Re-Leveling ......................................................................................................3-10
Comments .........................................................................................................3-11
State Properties: IF / CASE, Actions ................................................................3-12
Transition Properties: Condition, Actions ........................................................3-14

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TABLE OF CONTENTS (Cont.)

Junction / Link Properties .................................................................................3-15

Context Definition ............................................................................................3-16
State Machine Properties ..................................................................................3-17
State Machine Properties: Generation ..............................................................3-18
State Machine Properties: Architecture Declarations .......................................3-24
State Machine Properties: Statement Blocks ....................................................3-26
State Machine Properties: Process Declaration ................................................3-28
State Machine Properties: Encoding VHDL .....................................................3-30
Creating “Hard” Encoded “Safe” State Machines ............................................3-32
State Machine Properties: Encoding Verilog ...................................................3-34
State Machine Properties: Signal Status ...........................................................3-35
Logic Location in Generated HDL ...................................................................3-36
Registered vs. Clocked Outputs ........................................................................3-39
How to Choose which Output Type? ................................................................3-40
Register State Actions on Current State ...........................................................3-41
Output Assignment Priority ..............................................................................3-43
Concurrent State Machines ...............................................................................3-44
Concurrent State Machines: Renaming ............................................................3-45
Expression Builder ............................................................................................3-46
State Machine Preferences: Default Values .....................................................3-47
Lab 3: Controlling the BCD Register ...............................................................3-49
Lab 3: Controlling the BCD Register ...............................................................3-50

Module 4
Interactive Testing Basics ...................................................................................4-1

Testing Methodology ..........................................................................................4-2

Simulation Process ..............................................................................................4-3
Invoking Simulation ...........................................................................................4-4
ModelSim Windows ............................................................................................4-5
ModelSim Interface: Console Window ...............................................................4-6
ModelSim Interface: Design Structure ................................................................4-7
ModelSim Interface: Signal Window ..................................................................4-8

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TABLE OF CONTENTS (Cont.)

ModelSim Interface: Wave Window ..................................................................4-9

Display Preferences ..........................................................................................4-10
Simulation Preferences .....................................................................................4-12
Running the Simulator ......................................................................................4-13
Step Commands ................................................................................................4-14
Restarting the Simulator ...................................................................................4-15
Interactive Stimulus ..........................................................................................4-16
Forcing Signal Values .......................................................................................4-17
Assigning Clock Signals ...................................................................................4-18
Interactive Troubleshooting ..............................................................................4-19
Using Line Breakpoints ....................................................................................4-20
Using Signal Breakpoints .................................................................................4-21
Troubleshooting Techniques ............................................................................4-22
Modifying the Original Design .........................................................................4-23
Reusing Stimulus ..............................................................................................4-24
Lab 4: Testing the BCD Register ......................................................................4-25
Lab 4: Testing the BCD Register ......................................................................4-26

Module 5
Synthesis Basics ...................................................................................................5-1

What is Synthesis? ..............................................................................................5-2

Synthesis Process ................................................................................................5-6
Precision Technology/Synthesis Options ...........................................................5-7
Running Precision Synthesis ..............................................................................5-8
Precision User Interface Basics ........................................................................5-10
Precision Design Bar ........................................................................................5-11
Project Files Management ................................................................................5-12
Adding Input Files ............................................................................................5-13
Compiling .........................................................................................................5-14
Design Hierarchy Browser ...............................................................................5-15
Synthesizing ......................................................................................................5-16
Output Files ......................................................................................................5-17

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TABLE OF CONTENTS (Cont.)

Precision Output Files + Limitations ................................................................5-18

Precision Design Analysis ................................................................................5-19
Schematic Viewer .............................................................................................5-20
View Schematic ................................................................................................5-21
Schematic Navigation with Strokes ..................................................................5-22
Query Mode ......................................................................................................5-23
Timing Reports from the Schematic .................................................................5-24
Report Timing Violations .................................................................................5-25
Precision Timing Analysis ................................................................................5-26
Timing Report ...................................................................................................5-27
Timing Report — Summary .............................................................................5-28
View Critical Path .............................................................................................5-29
Area Reports .....................................................................................................5-30
Place and Route Encapsulation .........................................................................5-31
Xilinx PnR Design Bar .....................................................................................5-32
Double-Click Launch of Analysis Tools ..........................................................5-33
.twr File to Schematic Cross Reference ............................................................5-34
IOB Mapping ....................................................................................................5-35
Summary of Module .........................................................................................5-36
Lab 5: Synthesizing the BCD Register .............................................................5-37
Lab 5: Synthesizing the BCD Register .............................................................5-38

Module 6
Preparing for Testing ..........................................................................................6-1

Test Bench Elements ..........................................................................................6-2

Why Use Components? ......................................................................................6-3
Preparing the Design: Components and Blocks .................................................6-4
Converting Blocks to Components .....................................................................6-5
Opening a Symbol Editor ...................................................................................6-6
Interface Description: Symbol ............................................................................6-7
Symbol Editor Main Window .............................................................................6-8
Editing Identifiers and Text ................................................................................6-9

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Table of Contents

TABLE OF CONTENTS (Cont.)

Editing Symbol Ports ........................................................................................6-10

Editing Symbol Port Graphics ..........................................................................6-11
Editing the Symbol Body ..................................................................................6-12
Symbol Editor: Useful ......................................................................................6-13
Symbol Editor: Custom Symbol .......................................................................6-14
Saving the Symbol ............................................................................................6-17
Updating Component Symbols .........................................................................6-18
Creating the Test Bench Design .......................................................................6-19
Generating a Test Bench Design ......................................................................6-20
What is a Flow Chart? ......................................................................................6-21
Flow Chart Design Objects ...............................................................................6-22
Design Objects: Action and Decision Boxes ....................................................6-23
Design Objects: Wait Boxes and Loops ...........................................................6-25
Design Objects: Start and End Points ...............................................................6-26
Design Objects: Case Boxes .............................................................................6-27
Flow Charts as Test Benches ............................................................................6-28
Flow Chart Object Properties Dialog Box ........................................................6-29
Flow Chart Generation Properties ....................................................................6-30
Using Concurrent Design Views ......................................................................6-31
Concurrent Flow Chart Toolbar Icons ..............................................................6-32
A Test Bench Example .....................................................................................6-33
Lab 6: Preparing a Test Bench ..........................................................................6-34
Lab 6: Preparing a Test Bench ..........................................................................6-35

Module 7
Advanced Troubleshooting .................................................................................7-1

Troubleshooting Designs Graphically ................................................................7-2

Simulation Toolbar .............................................................................................7-3
Assigning Signals to Simulation Windows ........................................................7-4
Signal Information ..............................................................................................7-5
Simulation Execution ..........................................................................................7-6
Preparing the Design for Animation ...................................................................7-7

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TABLE OF CONTENTS (Cont.)

Assigning State Variable to Simulation Windows .............................................7-8

Using Animation .................................................................................................7-9
Tracking State Changes ....................................................................................7-10
Enabling Animation ..........................................................................................7-11
Linking Design Windows .................................................................................7-13
Cause: Flow Chart / State Machine — Wave Window ....................................7-14
Breakpoints .......................................................................................................7-15
Breakpoints in State Machines .........................................................................7-16
Breakpoints in Flow Charts ..............................................................................7-18
Activity Trails ...................................................................................................7-19
Reviewing Animation History ..........................................................................7-21
Crossprobing Signal Values .............................................................................7-22
Probe: Block Diagram / IBD ............................................................................7-23
Choosing the Simulation Instance ....................................................................7-24
Debug: Log Window .......................................................................................7-25
More ModelSim Windows ................................................................................7-26
Process Window ...............................................................................................7-27
Variables Window ............................................................................................7-28
Dataflow Window .............................................................................................7-29
Dataflow Example ............................................................................................7-30
Dataflow Window Syntax .................................................................................7-31
Troubleshooting Large Designs ........................................................................7-32
List Window .....................................................................................................7-34
Lab 7: Troubleshooting the BCD Register Test Bench ....................................7-35
Lab 7: Advanced Debugging ............................................................................7-36

Module 8
Advanced Design Features .................................................................................8-1

BCD Register ......................................................................................................8-2

Generics and Parameters .....................................................................................8-3
Differences in Adding Generics to Blocks vs. Components ..............................8-5
Adding Generics to a Symbol .............................................................................8-6

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Table of Contents

November 2003
Table of Contents

TABLE OF CONTENTS (Cont.)

HDL Import: Step 3 — Context Definition ....................................................10-21

HDL Import: Imported Design .......................................................................10-22
Design Documentation using HTML Export .................................................10-23
HTML Export .................................................................................................10-24
HTML Export: Viewing the Exported HTML ...............................................10-25
Printing Diagrams: Page Setup .......................................................................10-27
Documentation using OLE: Overview ...........................................................10-28
Documentation using OLE: Requirements .....................................................10-29
Documentation using OLE: Drag Bar ............................................................10-30
Documentation using OLE: Panels .................................................................10-31
Documentation using OLE: Link or Copy ......................................................10-32
Documentation without OLE ..........................................................................10-33
Lab 10: Real Time Clock Design ...................................................................10-34
Lab 10: Top Down Design .............................................................................10-35

Module 11
Synthesis Methodology .....................................................................................11-1

Constraint-Based Optimization ........................................................................11-2

High-Level Optimization ..................................................................................11-3
Advanced FSM Optimization Features ............................................................11-4
Advanced FSM Optimization Settings .............................................................11-5
Advanced FSM Optimization ...........................................................................11-6
Pipelining ..........................................................................................................11-7
Pipelining in Precision ......................................................................................11-8
Technology Mapping ......................................................................................11-10
Synthesis Options ...........................................................................................11-11
Importing Coregen Blocks as EDIF Netlists ..................................................11-12
Automatic DCM Clock Constraint Propagation .............................................11-13
DCM Attribute Editing ...................................................................................11-14
Backannotated Timing Analysis .....................................................................11-15
The Precision Command Line ........................................................................11-16
Precision Script Basics ...................................................................................11-17

November 2003
About This Training Workbook

About This Training Workbook

This document is the Designing with FPGA Advantage V6.2 training workbook, which instructs in the
concepts necessary for efficient use of the Mentor Graphics FPGA Advantage tool set (HDL Designer,
ModelSim, Leonardo Spectrum) when designing FPGAs.

Audience
The information in this course is intended for FPGA designers who will use the FPGA Advantage tools
to design and test FPGAs and who have the prerequisite knowledge specified below.

What this course is not

• An exhaustive examination of the individual applications. Instead, this course focuses on using
the FPGA Advantage tools in a design flow.

• An explanation of FPGA technology or design.

Prerequisite Knowledge
• Students should have the ability to read, write, and understand simple HDL code fragments
• Students should understand basic schematic capture, digital simulation, and FPGA design
concepts.

• Students should be able to create simple schematic designs from a text specification.

About the References

Each component tool within FPGA Advantage contains online help and/or the complete online manual
set. Students are encouraged to refer to these materials during the course of the class.

Designing with FPGA Advantage xxiii

November 2003
About This Training Workbook

Software Compatibility
This training is designed to work with FPGA Advantage V6.2. While the basic concepts will work with
later releases, the various graphic user interfaces and some flow processes may change.

Documentation Compatibility
In every lab session, students may look at the online documentation to get additional information. The
online documents can be read using Acrobat Reader.

Lab Solutions
There are no explicit solutions provided since all Design Units of the Labs 1 to 10 are included in the
RTC design, which is provided in the training data. If solutions are needed, simply map the RTC
Library and copy the corresponding Design Units.

Training Data Contents

XYZLib
An FPGA Advantage library. This library is unmapped at the beginning of the first lab, and as such will
not appear in the Regular Library window.

MyTestLib
Another FPGA Advantage library. This library has been mapped via the FPGAdv_Training.hdp file,
and does appear in the Regular Library window.

TEXT
Another FPGA Advantage library. This library has not been mapped via the HDS.ini file, and does
appear in the Regular Library window. It contains an example for TextIO usage in testbenches.

RTC
An FPGA Advantage library. This library is unmapped at the beginning of the first lab, and as such will
not appear in the Regular Library window. It holds the complete RTC design used in Labs 11-13.

assembly, Int_clk and multiplier

Three FPGA Advantage libraries, which are used at Lab 11 for the synthesis methodology labs. These
libraries are unmapped at the beginning of the first lab, and as such will not appear in the Regular
Library window.

xxiv Designing with FPGA Advantage

November 2003
About This Training Workbook

Lab_Templates
An FPGA Advantage library. This library has been mapped via the FPGAdv_Training.hdp file, and
does appear in the Regular Library window. It holds templates and Design Units for Labs 6 and 8.

FPGAdv_Training.hdp
An initialization file for the HDL Designer tool. This file contains library mappings used by FPGA
Advantage. The file FPGAdv_Training.hdp-full holds all mappings needed for the training.

Timeline Table
When delivering the training class in four days it is very important to follow the timeline, especially
during the labs. 12 modules in four days means 3 modules per day. Ideally.
In reality at the end of day 1 three modules may not be covered until end of Lab 3 due to the extensive
module 1 and also the first lab, where students need to play around a little.

As a guideline for the lab timing use the following table:

Table 1. 1
Lab Duration your Lab Begin Lab End
in minutes Duration
1 60
2 45
3 45
4 70
5 50
6 70
7 90
8 40
9 60
10 60
11 60
12 70

Designing with FPGA Advantage xxv

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About This Training Workbook

xxvi Designing with FPGA Advantage

November 2003
Module 1
FPGA Advantage Basics

Objectives
This module will cover the following topics:

• The FPGA Design Flow

• HDL Designer
• ModelSim®
• Precision RTL
• Concept of Library/Unit/View
• Library Mapping
• The Design Explorer Window
• Preference Settings
• Code Generation
• Design Unit Creation

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HDL Design Flow with FPGA Advantage

♦ Create Design using conceptual tools:
! State Machines
Create Design
! Flow Charts
! Block Diagrams / Interface Based
Design (IBD)
Simulate RTL Synthesize RTL
! HDL
♦ Simulate to test functionality
(RTL) Analyze Static Timing

♦ Synthesize to target technology

♦ Analyze Static Timing
♦ Use FPGA vendor’s Place and Place and Route

Route tool to build design

database and extract true timing
♦ Simulate to verify post-route Simulate Gate Level Analyze Dynamic Timing

design (Gate Level)

Notes:
HDL Designer is key in the following design methodology.

The designer will create the design description with HDL Designer, creating block
diagrams, state machines, flow charts, truth tables, and HDL code to describe the
design. From HDL Designer the designer will generate HDL to feed the rest of the
design flow.

The HDL will be simulated with ModelSim first to verify the functionality of the
design.

Once the functionality is correct the designer will then synthesize the design with
Precision RTL to implement the design in the target technology.

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FPGA Advantage Basics

Once the synthesis process has been completed the designer will take the netlist
from synthesis and use vendor place and route tools to implement the design for
the actual device.

After this process has completed the designer will take the netlist and SDF timing
file from the place and route process and designate in HDL Designer the gate level
netlist as new design view to the toplevel design unit.

Then ModelSim is used again with the same testbench as used for functional
verification to verify the real timing of the chip at the gate level.

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FPGA Advantage Basics

FPGA Advantage Tools

♦ Three tools working together:
! HDL Designer
– Design Creation
– Data Management
Design Creation/Management
– Flow Control
! ModelSim
– RTL Simulation HDL Designer
– Gate Level Simulation
! Precision RTL
– Synthesis
– Static Timing Analysis Precision
ModelSim
♦ Tool Interaction RTL
! Flow Execution
! Downstream Data Preparation
Simulation Synthesis
! Simulation Control
! Crossprobing

Notes:
The FPGA Advantage 6.1 software includes also the synthesis tool Leonardo
Spectrum 2003.a. Existing users of Leonardo Spectrum can still use Spectrum as
synthesis tool. The documentation in this training workbook is based on Precision
RTL as synthesis tool, which does not mean that it is not possible to use Leonardo
Spectrum for synthesis with FPGA Advantage.

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FPGA Advantage Basics

A Quick Look at HDL Designer

♦ HDL Design Environment
! Design Flow Management
! Graphical & Text based design entry Design Creation/Management
! Design Visualization
! Version Control
♦ Windows, Linux, UNIX HDL Designer
♦ Windows Look and Feel
♦ Design Environments
! Block Diagrams / IBD
Precision
! State Machines ModelSim
RTL
! Flow Charts, Truth Tables
! HDL Models Simulation Synthesis
♦ Front End to other tools such as:
! ModelSim
! Precision RTL
! LeonardoSpectrum

Notes:
HDL Designer is a graphical design capture tool that allows designers to create
ASIC and FPGA designs using graphical techniques. Designers need only little
HDL knowledge to create very good designs quickly and easily. HDL Designer
executes on the Windows, Linux and UNIX platform and generates VHDL or
Verilog HDL descriptions from the graphical design input. The design is captured
graphically using blocks, graphical state machines, flowcharts, and truth tables.
These graphical descriptions are automatically converted to fast efficient HDL
descriptions.

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Why Use HDL Designer?

Graphical Block Based Text Based

Design Design Design
Designs can be represented Graphically as:
♦ Block Diagrams
♦ State Transition Diagrams
♦ Flow Charts
♦ Truth Tables … or Text Based as HDL files
1-5 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation

Notes:

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FPGA Advantage Basics

Design Creation Flow

HDL Designer
♦ Create new Design Unit in HDL Designer
! Determine modeling technique
– State Machine, Flow Chart, HDL, etc.
♦ Create behavior of Design Unit
! Edit dataflow graphically or text based
♦ Save Design Unit data
! Graphical and text data
♦ Generate HDL from graphical Design Unit
! Check HDL syntax
♦ Begin Simulation/Synthesis Flow
a) Generates HDL if necessary
b) Compiles data for downstream tool
c) Invokes downstream tool

Notes:
The typical procedure for creating a design within HDL Designer will be as shown
by this flow diagram. A new design unit will be created within HDL Designer by
opening a block diagram. The designer will then create the behavior of the unit by
placing blocks on the block diagram and connecting the blocks with signals and
busses. Next the behavior of each block is created with another block diagram,
state machine, truth table, flow chart, or HDL code. The design is saved and HDL
code generated from the design. Once the HDL generation process completes
satisfactorily the design is compiled for downstream tools such as ModelSim,
Precision RTL, or Design Compiler.

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A Quick Look at ModelSim

♦ VHDL/Verilog Simulator
♦ Complies with VHDL and Verilog Standards including
! VITAL, STD Math, VHDL93
! SDF 3.0, IEEE 1364 Verilog, PLI
♦ Single kernel execution for VHDL and Verilog
♦ Direct Compiled Code Design Creation/Management
♦ Foreign Language Interface
♦ 2 Troubleshoot viewpoints HDL
! HDL viewpoint Designer
(ModelSim)
! Design viewpoint ModelSim
(HDL Designer) Precision
RTL

Simulation Synthesis
1-7 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation

Notes:
What is ModelSim? It is a direct compiled VHDL/Verilog simulator. Direct
compiled means that it does not convert HDL to C/C++ and compile the C/C++
with a C compiler. Instead ModelSim generates the machine code directly from
the compiler. This provides the benefits of much faster compilation and some
speedup in runtime. ModelSim complies with VHDL and Verilog standards
including VITAL, Numeric Standard Math packages, VHDL93, SDF3.0, VITAL
2000 IEEE 1364, and PLI. ModelSim has a single kernel that executes both VHDL
and Verilog files or mixed VHDL/Verilog designs. This allows part of the design
to be in Verilog and part in VHDL. The single kernel allows VHDL to be called
from Verilog or Verilog to be called from VHDL. ModelSim also has a foreign
language interface to allow linking other C/C++ models into the simulation.

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A Quick Look at Precision RTL

♦ HDL Synthesis Tool Environment
♦ VHDL, Verilog, Netlist Input
♦ User Controllable Synthesis Flows
! Automatic Pushbutton Flow
! Interactive Controlled Flow
Design Creation/Management
♦ Static Timing Analysis
♦ Optimized EDIF Netlist Output
HDL
♦ ASIC, FPGA Designer
♦ UNIX, Linux, Windows Precision
RTL
ModelSim

Simulation Synthesis

Notes:

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HDL Designer Philosophy

♦ Automate Design Flow as much as possible
! Single-click Simulation/Synthesis of design units
! Ability to manage ALL design related data, including documentation,
customer specific tasks and all kinds of “non technical” data
♦ Constrain the designers workflow as little as possible
! HDL is the common data format
! Design entry graphical, text based or mixed
! Full user control over design data directory structure
! Implementation/Interfacing of version management systems
♦ Increase the designers productivity
! Different techniques to explore (large) designs
! Providing editors, IP’s or interfaces to Macro Generators for efficient
design entry
! Implemented Team Design support maximize synergy effects
regarding design reuse and environment setup

Notes:

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Where Does HDL Designer Fit in the

Design Flow?

Where Does HDL Designer Fit in the Design Flow?

Consider a typical design flow (i.e.: FPGA):

HDL Designer HDL Designer

Design

1
" VHDL
Verilog
Test
Bench
2 "
VHDL
Verilog

3
ModelSim

Precision RTL ModelSim Design Sequences

1. Capture RTL Design

"
EDIF
2. Capture Test Bench
3. Simulate RTL Design
4 7 4. Synthesize and Optimize Design

"
5. Place and Route Design
6
FPGA Vendor HDL 6. Generate Back-annotated VHDL
Place and Route Vital + SDF
7. Simulate Design with timing

5
EDIF

" Precision RTL HDL Designer Used Here

Notes:

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Preparing to Use HDL Designer

Each of these topics will be discussed in the following slides:

♦ Design Manager — Basic Layout

♦ Design Manager — Project Manager
♦ Project Manager — Project Files
♦ Concept of Library/Unit/View
♦ Design Manager — Design Explorer
♦ HDL Designer Design Data Structure

Notes:

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The Design Manager

♦ Main “cockpit” for controlling HDS design flows
♦ Full control over window, menu & toolbar visibility
♦ Represent, access & organize all aspects of the design
♦ Easy navigation of design
! Helps organization
! Aids understanding
♦ Management of design (tasks, filters, etc.)
♦ Tools & Flows
♦ Templates
♦ Version Control (individual repositories)

Notes:

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The Design Manager — Basic Layout

Menu Bar

# Access commands via:

# Menu Bar
# Tool Bar
# Shortcut Bar
Tool Bar # Popup Menu

Popup Menu [RMB] # Status bar provides

information about the
current status of the
associated window /
command / warning.

Status Bar
Shortcut Bar

Notes:
The design manager window is displayed when you invoke any HDL Designer
Series tool. The design manager window normally remains open throughout your
working session and cannot be closed. If the design manager is hidden below
other windows it can be popped to the top by choosing Design Manager from the
File menu in any graphic editor or DesignPad window.

• Menu Bar: A short message describing the associated command is

displayed in the status bar when the cursor is moved over any pulldown
menu item or toolbar button.

• Tool Bar: The most commonly used commands are available from toolbars
in each window. Four toolbars are normally displayed in the design

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manager. If not displayed, the toolbars can be enabled by setting Standard,

Design Manager, HDL and Tasks in the Toolbars cascade of the View
menu.

• Shortcut Bar: The shortcut bar provides quick access shortcuts for
common setup operations, design explorer operations, tasks and
viewpoints.

• Popup Menu: Many commands are also available in a context-sensitive

popup menu which is displayed when you press and release the right mouse
button.

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The Design Manager — Project Manager

♦ Edit/show library mappings within a

given project (.hdp) and open
alternative project files.
♦ Create new projects & specify the
libraries contained in your project
using a wizard.
♦ Libraries are grouped by type, by
default Regular work libraries are
expanded.
♦ Three different types of libraries are
available (see Notes).
♦ Open Design Explorer windows on
any number of libraries simply by
double-click or “Explore”.
♦ Perform data/design management
operations on mappings and
libraries

Notes:
When a HDL Designer Series tool is invoked for the first time, the default library
mapping project files (examples.hdp and shared.hdp) are loaded and shown in the
non-scrolling area of the project manager in the source browser Project tab.

A regular library contains graphical or HDL text source design objects. HDL can
be generated from the graphical objects and all design objects can be compiled.
The library mappings for a regular library includes separate locations for the
graphical or HDL text objects, one or more mappings for downstream data and
may also include version management mappings.

A protected library contains reference source design objects which cannot be

generated or compiled and is typically used for frozen design objects or libraries

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defining standard HDL types. The library mappings for a protected library
includes locations for the graphical or HDL text objects but no mappings for
downstream data or version management.

A downstream only library contains externally compiled design objects and is

typically used for vendor-supplied data. The library mappings specify the location
for downstream data only.

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Project Manager — My Project File

♦ “My Project” contains information about the libraries used in a
project
♦ It also contains a reference to a Shared project file (see next
page)
♦ Can display My Project and/or Shared Project mappings
♦ My mappings override Shared if there is a conflict
♦ New projects can be created using “New Project” wizard
♦ Open other projects using “Open Project”
♦ Can also close a project
♦ My Project file located by search path:
! Command line switch (-inifile)
! $HDS_LIBS environment variable
! Current working directory (if called hds.hdp)
! Preferences entry
! User directory
! Installation directory
1-15 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation

Notes:
The "My project" examples.hdp file stores library mapping information for the
default HDS examples project which includes an empty scratch library, example
designs and libraries containing support packages.

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Project Manager — Shared Project Files

♦ Shared project files typically contain:
! Mappings for project-wide libraries (vendor libraries, ieee, IP, etc)
! Mappings for project-wide VM repositories
♦ Shared Mappings shown by icon
♦ The location is stored in My Project
♦ Default location is in the Team Preferences tree:
$HDS_TEAM_HOME/shared.hdp
♦ To edit shared mappings, must switch
into “Edit Shared Project” (RMB over
Shared Project) mode:
! File maybe made read-only by
Project Manager
! Only Shared mappings are visible

Notes:
The shared.hdp file stores mapping for the ModuleWare component library and
standard VHDL packages. The libraries defined in this file are intended for shared
use and are usually maintained by a team or project administrator in multi-user
installations.

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Concept of Library/Unit/View

Concept of Library/Unit/View
HDL Designer is built on a concept of Library/Unit/View.
♦ This is analogous to the structure of Library/Entity/Architecture in
VHDL.
♦ There can only be one interface per Design Unit. Therefore, there can
only be one Design Unit of a given name per Library.
♦ There may be multiple views per Unit. The same View name may be
used in different Units.
♦ To use the same Unit name with a different interface, the new Unit
must be stored in a different Library.

library $ x $
y

unit a b a a

view rtl zzz rtl rtl zzz

x
1-17 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation

Notes:

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HDL Designer Design Data Structure

HDL Directory (Source / Generated)

arbitrary directory structure & filenames

1. Save
HDL Designer
Design Data Directory
contains graphical data,
side data & meta data
2. Generate directory structure
(for graphical views)

3. Compile
Downstream Data Directories
any number of downstream
directories for tasks which
require working directories

Notes:

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How Does HDL Designer Find These

Directories?

How Does HDL Designer Find These Directories?

Through the Library Mappings in a Project file. examples.hdp

The logical library name is mapped to a physical directory on the

disk for each of the directories:

[hdl] - HDL Directory Library

Mappings
Keywords in Project file

[hds] – HDL Designer Design Data Directory

[ModelSim] Optional
Mappings
[Precision] - Downstream Data Directories
[Leonardo]

Notes:

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Example Project File — Format

Logical Library Name

Downstream
Mapping
(tool dependent)

HDL Mapping Directory Location

HDL Designer
Design Data
Mapping

Library Type

Shared Mapping
1-20 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation

Notes:

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Create and Modify Library Mappings

♦ Create new Library using “New Library” Wizard
♦ Edit mappings using “Edit Mappings” Wizard or directly
♦ Two libraries must not have the same HDL/HDS mappings!
♦ Default assumes “Regular” library
♦ Default is to automatically create mappings based on Library name,
Root directory & default structure
♦ Downstream mappings created automatically when needed
♦ Changes saved to project file immediately

Notes:
It is possible to edit the mappings of an existing library, but in order to do this the
library must not be ëactive'.

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Design Manager — Design Explorer

♦ The Design Explorer allow you to explore the content of the
libraries within a project.
Change Design Explorer Mode

Double Click or use RMB: New Tabs for Libraries

Explore Library

Notes:
The Design Units mode displays the design partitioned into design units
containing the source graphical or HDL text views.

The right pane of the Design Explorer can be used to show the hierarchy beneath
any of the design objects shown in the content pane.

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Design Explorer — Design Units Mode

♦ Represents graphical
Library and text components as
Design Units
! Shows logical content
down to leaf-level
! Hierarchy shown in
separate pane
Views
♦ Shortcuts:
! Drag ‘n drop
Design Units
! Expand/Collapse:
<space>
! Show/Hide Hierarchy:
< ctrl>+<space>

Notes:
The Design Units mode displays the design partitioned into design units
containing the source graphical or HDL text views. This is the default mode.

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Design Explorer — HDL Files Mode

♦ Shows actual file structure

on disk under HDL mapping
♦ Also shows logical content
of files
♦ Source files indicated with
(“S”) organised in this
example into RTL/VHDL,
RTL/Verilog and TestBench
♦ Manage files and folders
within the HDL structure

Notes:
The HDL Files mode displays all the HDL files in the design including source
HDL text views and the HDL text generated from graphical views. Source HDL
text views are prefixed by an icon S in HDL Files mode. All other views are
generated files which should not be directly edited and are normally opened read-
only.

All commands used in this mode operate directly on the HDL files which may
contain multiple design objects. For example, deleting a single file, deletes all
design objects defined within that file.

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Design Explorer — Hierarchy Pane

♦ Shows the logical design hierarchy
from one or more specified root
points
♦ Default view used unless otherwise
specified for a given instance
♦ Hierarchy pane auto-hides if no
hierarchy displayed
♦ Shortcuts:
! Expand/Collapse: <space>
! Toggle Hierarchy: <ctrl>+<space>
! Drag ‘n drop or use Shortcut
♦ VHDL Configurations:
! Can show hierarchy from a
configuration
! Colour shows
use of
configuration

Notes:
The hierarchy below the top level design unit is shown in the right pane of the
design explorer by default. You can display hierarchy below any selected design
object by choosing Show Hierarchy from the Edit or popup menu, using the +
shortcut key or by dragging the object to the Design Hierarchy pane.

You can hide or show the hierarchy pane by setting Design Hierarchy in the
SubWindows cascade of the View menu or popup menu and hide it by choosing
Hide Design Hierarchy Window in the hierarchy pane popup menu.

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Main Icons in the Design Explorer

♦ Library ♦ State Diagram view
! Expanded ! Normal
! Collapsed
! Concurrent
♦ Block design unit
♦ ModuleWare
♦ Component design unit
♦ HDL Model
♦ Symbol ! VHDL entity
! VHDL architecture
♦ Block Diagram view ! VHDL package
VHDL package header
♦ IBD view !

! VHDL package body

♦ Flow Chart view ! Verilog
! Normal ! Verilog Include
! Concurrent ! Generate frame

♦ Truth Table view

Notes:
Icon Reference Page 1

For the complete reference browse to: "HDL Designer Series User Manual >
Design Explorer Notation"

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Main Icons in the Design Explorer

(Cont.)

Main Icons in the Design Explorer (Cont.)

♦ Icon overlay
! Don’t touch
! Default view
! Foreign view
! Gate level
! Top marker
! Read-only
! Reference
! Design Root

♦ Plain Text file

♦ Unknown DU

♦ Unknown view

Notes:
Icon Reference Page 2

For a complete reference browse to: "HDL Designer Series User Manual > Design
Explorer Notation"

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Manipulations in the Design Explorer

♦ On a design unit or design unit view basis
you can:
! Move, Copy [Ctrl+C]
– invalid locations indicated by
! Delete [Del]
! Rename [F2]
♦ The move and copy can be
hierarchical and through
components

Notes:
You can select objects in the source browser, side data browser or downstream
browser by clicking the left mouse button with the cursor over its icon or name.

You can move a design unit or a design unit view in the design explorer by
dragging with the left or right mouse button.

You can copy any design unit or a design unit view in the design explorer by
dragging with the right mouse button or the Ctrl + left mouse buttons.

When you use the right mouse button, a popup menu is displayed which includes
Copy Here option to make a copy at the position of the cursor and a Cancel
option to abort the operation.

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Side Data SubWindow

View → SubWindows → Side Data

♦ Design Data
! This part is used by HDS to store
some data that may be needed later
– edif file generated by CoreGen
– simulation result files
– sdf back-annotation file for gate
level simulation
– Tcl generated scripts
♦ User Data
! Reserved for the designer to store any kind of
design relative data
! Folders and sub-folders can be created by the user
! File can be copied or referenced
♦ The Side Data contents can be optionally versioned with the
source data
1-29 • Designing with FPGA Advantage: FPGA Design Basics Copyright © 2003 Mentor Graphics Corporation

Notes:
The side data browser displays the contents of the Design Data and User Data
directories which contain side data corresponding to the design unit view selected
in the design explorer (or corresponding to the default view when a design unit is
selected).

The side data browser can be displayed or hidden by setting Side Data in the
SubWindows cascade of the View or popup menu.

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Downstream SubWindow

Downstream SubWindow
View → SubWindows → Downstream

♦ Shows the objects (compiled

views, script, ini files, …) created
for and by the tools invoked from
HDS through various tasks

♦ It is tool dependent.
Use tabs to switch between
downstream tool data

Notes:
The downstream browser displays the contents of the compiled library directories
corresponding to the design data libraries currently open in the design explorer.

The downstream browser can be displayed or hidden by setting Downstream in

the SubWindows cascade of the View or popup menu.

As ModelSim or Precision create files it is sometimes necessary to ërefresh' these

windows to ensure they display the latest contents. There is a refresh option on
the popup menu active in the downstream windows. It is also possible to use the
Function key F5, this refreshes all the open windows.

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Resource Settings

Resource Settings
The Resource setting allows the user:
1. To set his design environment (text editor, 3rd party tools,…)
2. To define his graphical environment
3. To control the code generation to stick to the in-house coding style

♦ Tool Settings
! Compiler, Simulator, Synthesizer, Custom tools...
♦ General Preferences
! Text Editor, Check, Save, ...
♦ Editors
! Block Diagram, State Machine, Flow Chart, Truth Table, Symbol
♦ Code generation
! VHDL, Verilog
♦ Two levels of Resources:
! User Resources
! Team Resources

Notes:
The HDL Designer Series supports user resources which can be set by each
individual user and team resources which are shared by all members of a team
working on the same project.

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Main Settings: General

Options → Main…

♦ The General tab provides general

setup and configuration
preferences
! Automatically downcase design
unit names as they are entered
! Specify an alternative directory
for the temporary files created
during HDL compilation
! Specify the default measurement
units used for printing
! Set the default HDL language for
new views to be VHDL or Verilog

Notes:
The Main Settings dialog box is displayed when you choose Main from the
Options menu in any window.

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Main Settings: Text Editor

Options → Main… → Text

♦ The editor and the viewer can

be different
♦ A default text editor
“DesignPad” is provided
♦ Other editors can be added

Notes:
The Text tab of the Main Settings dialog box provides preferences for choosing
the editor and viewer used for HDL text views. The default editor and viewer are
set to use the built-in DesignPad text editor. However, you can choose from a
dropdown list of alternative supported editors and use the Setup buttons to modify
the editor or viewer commands used to invoke these tools.

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Main Settings: User Variables

Options → Main… → User Variables

♦ Allows to enter variables as name

and value pairs
♦ To use a variable, enter the
variable name preceded by the %
character
♦ i.e. define a variable site with the
value <location> and use the
variable %site to automatically
enter the location of your project
team in title blocks, HDL headers
and HTML title pages

Notes:
You can set user-defined internal variables by using the User Variables tab of the
Main Settings dialog box.

A number of default user variables are defined to specify the executable directory
pathname used by the default tasks to invoke downstream tools:

• task_DesignCompilerPath Design Compiler

• task_LeonardoPath LeonardoSpectrum
• task_ModelSimPath ModelSim

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Code Generation Preferences — Verilog

Options → Verilog...

Notes:

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Resource Settings
Resource Settings
User Resource Settings
1. Location specified by the -user_home command line switch if set.
2. Location specified by the HDS_USER_HOME environment variable if set.
3. The current working directory when the tool is invoked if found.
4. The user directory ($HOME on UNIX and Linux or user profile on
Windows) if found.

Team Resource Settings

The team resources include Generation Properties, HDL Filename Templates,
Version Management, Team Tasks and Team Templates setup options.
Team preferences should be read-only.
1. Location specified by the -team_home command line switch if set.
2. Location specified by the HDS_TEAM_HOME environment variable if set.
3. Location specified in the General tab of the Main Settings dialog box.
4. The current working directory when the tool is invoked if found.
5. The user directory ($HOME on UNIX and Linux or user profile on
Windows) if found.
If no resource files exist at any of these locations, a set of hard-coded defaults are used.

Notes:
The HDL Designer Series supports user resources which can be set by each
individual user and team resources which are shared by all members of a team
working on the same project. When you invoke a HDL Designer Series tool for
the first time, Single User mode is set by default and only the user resources are
read. When this mode is set, the task manager and template manager display all
the available tasks and templates under My Tasks and My Templates nodes. You
can set Team Member mode and when this mode is set, you can also browse for
the location of the team preferences directory. When team member operating
mode is set, the task and template managers display tasks and templates under
separate My Tasks, Team Tasks, My Templates and Team Templates nodes.

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If you have write access to the team resources directory location, you can set the
Team Administrator mode. This mode allows you to save tasks and templates as
shared team resources.

You must restart the application after changing between single user and team
member operating mode.

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What is the Flow Through HDL

Designer?

What is the Flow Through HDL Designer?

There are four basic steps in using HDL Designer:

1. Create / Open a project file.

2. Edit & Save Diagram or HDL Text.

! Diagrams are edited interactively, then saved as an ASCII file.
! Each object type has a defined naming convention.

3. Generate — Generate HDL for Diagram.

! HDL code is automatically generated for the diagram in ASCII
files.

4. Compile — Prepare HDL for downstream tools.

! The HDL code is compiled for simulation, or scripts are
generated to process the HDL code for use by downstream
tools such as synthesis.

Notes:
Several Wizards and predefined Tasks explained on the next pages will guide
you through the HDL Designer Flow.

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Getting Started Wizard

♦ Create / open a Project using the wizard on startup or use the
shortcuts or

Project which was

opened when you
last shut down

Open a different
existing project

Open the example

project which
comes with tool

Create a new
project, which then
launches New
Project Wizard

Notes:

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Create a Design Unit — Top down

Method 2
or

♦ Start by creating the

Design Unit interface
or symbol

♦ Save it into the library of your choice

Notes:

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Create a Design Unit View — Top down

Method 2 Open → New View ...

♦ Open a new view of your choice

♦ The interface defined previously is

available

Notes:

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Lab 1: Testing and Synthesizing a BCD

Counter

Lab 1: Testing and Synthesizing a BCD Counter

♦ Lab Goal: Test and synthesize a BCD counter

! Part 1: Create a library mapping & browse design

– Map local component library
– Testing environment is pre-configured
– Look at test routine
– Generate HDL code to ensure no syntax errors
! Part 2: Simulate the BCDCounter test bench
– Invoke ModelSim from Design Browser
– Run testbench on BCDCounter
! Part 3: Synthesize the BCDCounter design
– Invoke Precision RTL from Design Browser
– Synthesize using QuickSetup Tab
– Confirm and view resulting schematics, critical path

Notes:

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Lab 1: Testing and Synthesizing a BCD

Counter
Introduction
In this lab you will open an existing design in HDL Designer, run the test bench in
ModelSim, and synthesize the design in Precision RTL.

Directions
• Part 1: Setup the Design environment
o Invoke FPGA Advantage

Windows: Click on the ‘FPGAdv with LS & PS 6.2’ icon on the

desktop, if it exists, OR click the Start button, then select the menu
item Programs > FPGA Advantage 6.2 > FPGA Advantage. The
actual names used for the icon and the menu items will depend on
the options installed, check with your instructor if it is not clear.

UNIX: Ask your instructor for details.

o HDL Designer asks at startup which Project to load. Specify the first
option to “Continue with Project FPGAdv_Training.hdp”.

o To “clean up” the visible libraries, deselect the “Shared Project”

checkbox in the Project Manager window.

This will help you to concentrate on the design libraries to work with.

o Setup the default Packages you want to use in this Design.

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We want to use packages ieee.std_logic_1164 and ieee.numeric_std

but these may not both be the current default packages, so you may
need to change them.

• Use the pulldown menu item Options > VHDL and click on the
Default Packages Tab. Delete the entries for unwanted package
entries and add the ieee.NUMERIC_STD package by clicking on the
ieee Library in the left pane and afterwards on the NUMERIC_STD
package in the right pane. Then confirm with a click on the Add
button.
OK the dialog box.

o Open existing Libraries

There are two regular libraries visible. Omit the Lab_Templates

library for now, since it is intended for later use.

Open the MyTestLib Library by double-clicking on the library

name in the Project Manager window.

• A new Design Explorer tab shows

the contents of the MyTestLib
libray. Since this is a testbench
library, there are only two design
units present. The yellow triangle
denotes the toplevel design unit, which models structural VHDL.

• The Design Hierarchy window allows you to see the whole design
hierarchy. At the moment you can only see the testbench itself in this
window. To see the full design hierarchy, simply select the
BCDCounter_tb unit in the Design Hierarchy window and click
the button in the Task Bar.

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• The full design hierarchy is shown as follows:

• Notice the design unit printed in red. This denotes a “missing

component”. This is due to the BCDCounter which is instantiated
from the XYZLib library which is not yet mapped.

o Create a new Design Library called XYZLib.

In this portion of the lab, you will create a new library mapping
called XYZLib that will contain a generic BCD Counter design.

• Switch back to the Project Manager usig the Project tab at the
bottom of the Design Explorer window.

• Add a new library mapping using the New Library

taskbar icon.

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November 2003
FPGA Advantage Basics

• At the New Library wizard choose “Regular Library” and define

the mappings for the XYZLib as follows:

• Click Next for the final step, defining the new library as default.
Then click Finish to complete the new library definition.

• Part 2: Get familiar with the design, browse the Design and Testbench
o Switch back to the library MyTestLib (use tab at the bottom). The
design hierarchy window displays the state exactly as it was before the
XYZLib was mapped. Hit "F5" (Refresh) and it will display correctly.

o Open the BCDCounter_tb test bench design

In the Design Explorer window, expand the MyTestLib library by

clicking on the ‘+’ to the left of the library name (if not already done
so).

You will see two design objects, BCDCounter_tb and

BCDCounter_tester. Note that BCDCounter_tb has a yellow
triangle in front of it. What does this designate?________________

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FPGA Advantage Basics

Double-click on the BCDCounter_tb design object. A block

diagram editor will appear. Among other things, this window
contains a blue and a green block and a set of lines, or “wires”.

o Examine the BCD Counter design.

Double-click on the BCDCounter component in the block diagram

editor. The Design Pad editor containing a VHDL entity/architecture
will appear. Take a few minutes to understand how the BCD
Counter works.

Close the Design Pad editor.

o Examine the test bench stimulus generator.

Double-click on the blue block labeled “BCDCounter_tester.” A

flow chart editor window will appear containing a flowchart that
controls the stimulus used in the testbench. See if you can tell what
the flow chart is trying to do.

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FPGA Advantage Basics

Note that the flowchart editor window is labelled

(“process 0”). Find and click on the Open
Concurrent Flow Chart icon, and select process 1.
Now you may use the tabs at the bottom of the window to switch
between the different processes.

Close the flow chart editor window, but leave the block diagram
editor window open.

o Examine the test bench design file structure.

Go back to the Design Explorer and expand the various design

objects to see how they interrelate. Note the following:

Each block (colored blue) and component (colored green) has

one object below it with a blue arrow in front of the name. This
arrow denotes that the object is the “default view” for that block
or component.

Each component has a symbol object associated with it.

Drag the BCDCounter_tester design unit into the “Design

Hierarchy” window. There are two objects underneath the
BCDCounter_tester(flow) object.
Why isn’t one of them designated as the default? _____________

o Generate HDL code for the test bench.

In the Design Explorer window at the Design Unit pane , select the
BCDCounter_tb object (which should have a yellow triangle in
front of the name). Select the pulldown menu item
Tasks > Generate > Run through components.

A Log Window will appear informing you of the status of the HDL
generation. For this lab, the HDL should generate without any errors.

To see the generated HDL files change the display mode at the
Design Units window. Use pulldown menu item

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FPGA Advantage Basics

View > Mode > HDL Files. Note the presence of VHDL files for
both the BCDCounter_tb and BCDCounter_tester design objects.

Note that the HDL can also be generated by invoking ModelSim via
the Simulation Flow icon from the Design Explorer toolbar.

• Part 3: Simulate the BCD Counter test bench

o Invoke ModelSim on the testbench.

In the Design Explorer, switch back to the Design Units

view mode. Select the BCDCounter_tb design object, then
click on the Simulation Flow icon in the tool bar to launch
the ModelSim simulator. Click OK at the “Start ModelSim” dialog
box. Note that ModelSim will not invoke if the VHDL code has any
generation errors.

o Simulate the testbench.

If not already open, open the BCDCounter_tb diagram in HDL

Designer. You should see a new toolbar at the bottom.

Select the signals connected to the BCDCounter_tester and use the

add wave icon to add the selected signals to the wave window.

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FPGA Advantage Basics

Type “run –all” at the command prompt in the ModelSim main

window.

This will pop up a source window. View the Log Window to look for
any errors that occurred during the simulation run.

View the ModelSim Main Window for messages and the Wave
Window for the correct results.

Quit ModelSim.

Close the Block Diagram editor.

• Part 4: Synthesize the BCD Counter design.

o Open the XYZLib library and select the BCDCounter design unit at
the Design Units window pane.

o Click on the Precision Synthesis Flow icon in the tool bar to

synthesize the design. Be sure to use the “Synthesis Flow” task
icon which has two green triangles attached to it.

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FPGA Advantage Basics

o When the Precision Synthesis Settings dialog appears, choose the

following settings for synthesis:
Technology XILINX Spartan2

Click on the OK button.

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FPGA Advantage Basics

Once the design has synthesized successfully, observe the synthesis

results in the “Output Files” section of the “Project Files” window.

o Click on the RTL Schematic icon to see the RTL circuitry generated
by Precision RTL.

o Now do the same thing with the Technology Schematic icon and try to
figure out the similarities/differences between the two views.

o To get information about the device utilization use the Area Report
file. To open it simply doubleclick in “Area Report” in the “Project
Files” window pane.

What is the estimated utilization for the device?

o To check whether the desired clock frequency is achieved you can use
the Timing Report. Is the specified clock frequency (100 MHz) met?

Clock Frequency: ___________

Cross check this using the Timing Violation Report.

o When you are ready quit Precision RTL. Do not save project settings.

1-62 Designing with FPGA Advantage

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FPGA Advantage Basics

• Part 5: View downstream files in HDL Designer

In the HDL Designer you may want to see the Synthesis output files. This
can be done using the Downstream window.

o At the Design Explorer window select the XYZLib library.

o Open the Downstream window using the pulldown menu

View > SubWindows > Downstream

A new Downstream window opens, containing two tabs: ModelSim

and Precision

o Select the Precision tab

and select the XYZLib
library. Use
RMB > Expand All to
see all the various files
generated by Precision
RTL. (RMB means
Right Mouse Button)

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November 2003
FPGA Advantage Basics

o Select the ModelSim tab and select the XYZLib library. Use
RMB > Expand All to see all the various files generated by ModelSim

Congratulations! You have successfully tested and synthesized a design

using FPGA Advantage!

1-64 Designing with FPGA Advantage

November 2003
Module 2
Block Diagram Basics

Objectives
This module will cover the following topics:

• Introduction to Block Diagrams

• When To Use Block Diagrams
• Block Diagram Design Objects
• Working in the Block Diagram Editor
• Creating and Opening a Block Diagram
• Adding Blocks to a Block Diagram
• Routing Signals in a Block Diagram
• Saving the Block Diagram
• A Block Diagram Example

Designing with FPGA Advantage 2-1

November 2003
Block Diagram Basics

What is a Block Diagram?

♦ Similar to a Schematic
! Blocks represent collections of functionality/hierarchy
! Blocks connected by signals
! Provides a data flow view of the design
– Fast generation
– Easy to understand
! Models structural HDL code

♦ Advantages
! Can generate new blocks quickly
! Can use pre-defined blocks
! Underlying hierarchy/functionality can be defined later
! Each block can contain multiple and/or concurrent views
! Block interface defined “on the fly”
! Signal width defined in context

Notes:

2-2 Designing with FPGA Advantage

November 2003
Block Diagram Basics

Block Diagram Editor Window

♦ Standard HDL Designer Editor
Window
! Common Interface Throughout
♦ Edit window
! Path to block diagram object in
title bar
♦ Top Toolbar contains icons for
common tasks:
! Save block diagram
! Open design in ModelSim
! Zoom
♦ Bottom Toolbar contains icons
for editor-specific tasks:
! Place block
! Route wire
! Insert global connector

Notes:
Here is shown the Block Editor Main Window. The user will place components,
blocks, input, and output ports in the window and then connect these together with
signals and busses. The block editor also contains some interesting features such
as Global Connectors, which connect to all blocks. This makes routing the signals
much easier. As signals and busses are added to the diagram these signals and
busses appear in the declarations for that unit, making it easier to see the signal
names and types. Other items that can be added to a block diagram include
comments and generics. Comments can be attached to specific items so that they
appear with that item in the generated HDL code. Generics can be used to control
the size of items for configurable units. When the block diagram is completed
HDL can be generated from the blocks and interconnections.

Designing with FPGA Advantage 2-3

November 2003
Block Diagram Basics

When to Use Block Diagrams

♦ Want easy-to-see relationships between design elements
♦ Unsure of relationship between design elements
♦ Connect together different types of “design views”
♦ Used for higher levels of design hierarchy
♦ Sketching out ideas quickly

Notes:
The Block Diagram Editor is very useful for creating a quick block level
description of a device. It is the tool that allows engineers to create usable
diagrams similar to the ones drawn on napkins at restaurants. Blocks do not need
to have well defined interfaces before they are placed within a block diagram. As
each block of the diagram is specified the interface is implied from the signals
connecting to the block. When specifying the behavior of the blocks in the
diagram, the interface for the lower level blocks can be inferred by the
connections of the higher level block diagram. The block diagram allows the user
to quickly specify the inputs, outputs, and block interconnect to build the device.
If the block diagram is done correctly it can give the user a good dataflow view of
the device. Block Diagrams can also be created from existing HDL code so that
the existing dataflow can be more easily seen.

2-4 Designing with FPGA Advantage

November 2003
Block Diagram Basics

Block Diagram Design Objects

♦ Four types of design objects:
! Text Objects
– Comment Blocks

! Block Objects
– Blocks
– Embedded Blocks
– Components

! Signal Objects
– Signals (one bit)
– Busses (multi-bit)
– Bundles (grouped signals)

! Port Objects
– Ports (In/Out/InOut/Buffer)
– Global Connectors

Notes:
A user creating a block diagram can use either the toolbar buttons, or the Add
menu to add items to the block diagram. As can be seen from the Add menu the
items that can be placed on a block diagram include Blocks, Components, Signals,
Busses, Bundles, HDL Text, Global Connectors, and different types of ports.

Designing with FPGA Advantage 2-5

November 2003
Block Diagram Basics

Design Objects: Blocks & Components

♦ Default color: Blue ♦ Default color: Green

♦ Represents a “design unit” ♦ Represents a “design unit”
♦ Clock/Inversion Symbology ♦ Clock/Inversion Symbology
♦ Interface changes as ♦ Fixed interface
connections change ♦ Multiple Instances
♦ Unique instance or “proto- ♦ Blocks may be “promoted” to
component” Components
♦ Underlying “view” can be ♦ Edit appearance in Symbol
added later Editor
♦ Multiple views supported ♦ Displayed information:
♦ Edit appearance in place ! Source Library
♦ Displayed information: ! Component Name
! Source Library ! Instance Reference
! Block Name ! I/O interface
! Instance Reference
2-6 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation

Notes:
As already mentioned the types of blocks that can be placed in a block diagram are
Blocks and Components. Blocks have a very fluid interface that can easily be
changed by adding or removing a signal from the border of the Block.
Components have a more fixed interface. Components can be reused over and
over in lots of different block diagrams while blocks only appear where they are
defined. Blocks can be easily turned into a component.

A design unit that contains a reusable functional object definition or the

instantiation of this object on a block diagram or interface based design view. A
component has fixed interface ports defined by a symbol and may be described by
a child block diagram, interconnect table, state diagram, flow chart, truth table,
ModuleWare, HDL text, external HDL or foreign view.

2-6 Designing with FPGA Advantage

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Block Diagram Basics

Design Objects: Embedded Blocks

♦ Default color: Yellow
♦ Only exist within parent object
♦ May contain:
! HDL Text
! State Machines
! Flow Charts
! Truth Tables
♦ Interface defined by connected signals
♦ Embedded Blocks may not be
promoted to Components
♦ Displayed information:
! Block Name
! Instance Reference

Notes:
An embedded view is saved as part of the block diagram or IBD view on which it
is instantiated and does not create a separate design unit. When HDL is generated,
concurrent code is generated for the embedded view in the same files as the
structural description of the design unit. An embedded view has an interface
described by the signals connected to the embedded block which represents it on
the block diagram or IBD view. An embedded block looks very similar to a block
but has no library name since it is always in the same name space as the view.
However, it does have a unique name and a number which determines the relative
ordering when there are multiple unconnected embedded blocks in the generated
HDL.

Designing with FPGA Advantage 2-7

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Block Diagram Basics

Design Objects: Summary 1

Add → ...

Block:
- Fluid Interface
- Library/Block/Instance names
Block Component:
- Fixed Interface
- Library/Comp./Instance names
Component - Moduleware Component
[External IP]
Embedded Block - External HDL
- Compiled outside
Embedded Block:
- No hierarchy created
Frame - Any view including HDL
Frames:
- For multiple instances
Enter HDL - For conditional structures
- For PORT MAPS
Context added automatically when necessary
2-8 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation

Notes:

2-8 Designing with FPGA Advantage

November 2003
Block Diagram Basics

Design Objects: Signals

♦ Signal
! Scalar values
! Recommend std_logic type
– ‘0’, ‘1’ for Synthesis
♦ Bus
! Vector array
! Recommend unsigned type
– “00100110” for Synthesis
♦ Bundle
! Vector of Signals and Busses
! Type is array of signal object names
! Useful for connecting similar signals
– Example: Control Signals

Notes:
Signals and busses provide the connection information within the block diagram
editor. Signals are scalar objects of a particular type such as std_logic or boolean.
Busses can be complex objects including arrays that include more than one signal.
These are typically unsigned, signed, or std_logic_vector. Bundles are a special
object that allow the designer to group a number of signals together to be treated
as a single object.

Designing with FPGA Advantage 2-9

November 2003
Block Diagram Basics

Design Objects: Ports

♦ Input Port
! Passes signals/busses from higher
level of design hierarchy
♦ Output Port
! Passes signals/busses to higher
level of design hierarchy
♦ InOut Port, Buffer Port
! Combines Input and Output Port
! Discourage use with Synthesis
♦ Global Connector
! Connects signal to all blocks on
same level of design
! Useful for global resets, clocks, etc.

Notes:
Ports are used to provide the interface information to other units. Ports specify the
name of the port to allow connection by name and also the type of the ports so that
consistency of information passing is achieved.

The types of ports include input ports, output ports which pass information only
one way, and inout ports which pass information both ways. Buffer ports are a
special case of an inout port that only allows one driver but makes it easier to read
output values. The only danger with buffer ports is that once used they have to be
used everywhere in the hierarchy on that signal. Global ports are very useful for
signals that connect to all blocks, such as clocks, VCC, GND, etc.

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Block Diagram Basics

Design Objects: Summary 2

Add → ...

Signal stubs

Signal
Bus
Bundle

In Port
Out Port
Inout Port
Buffer Port

Global Connector

Signal : Scalar
Bus : Vector
Bundle : Arbitrary grouping of signals
Global connector : Common to blocks (incl. Embedded)
2-11 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation

♦ Two levels of Preferences

♦ Master
! Design Browser Pulldown:
– Options > Edit Master Preferences > Block Diagram…
! Settings for ALL Diagrams

♦ Specific Block Diagram

! Block Editor Pulldown:
– Options > Edit Diagram Preferences
! Appearance preferences only
! Settings for one specific Diagram (actual diagram)

Notes:
You can set block diagram preferences by choosing Block Diagram from the
Master Preferences cascade of the Options menu in the design browser. Block
diagram master preferences take effect on the next block diagram you create.
However you can apply the current master preferences to an active diagram by
choosing Apply to Existing Objects or Apply to New and Existing Objects from
the Master Preferences cascade of the Options menu in the diagram.

Designing with FPGA Advantage 2-15

November 2003
Block Diagram Basics

Setting Block Diagram Preferences

♦ Process:
! Open Preferences Dialog Box
! Select appropriate tab
! Select appropriate object
! Modify Values
♦ Changes apply to
! new objects
! existing objects
– Master prefs changes
• Block Editor Pulldown:
• Options > Master Preferences
– Specific diagram changes
• Preferences Dialog Box
♦ Be careful applying to existing objects!
! Will modify objects using default values

Notes:
You can set the appearance and signal visibility preferences for the active block
diagram by choosing Diagram Preferences from the Options menu in the block
diagram editor. When you edit these preferences for the active diagram, the dialog
box allows you to choose whether the preferences are applied to new objects or to
both new and existing objects in the diagram. You can save the preferences for the
active diagram as master preferences by choosing Update from Diagram in the
Master Preferences cascade of the Options menu.

2-16 Designing with FPGA Advantage

November 2003
Block Diagram Basics

Creating and Opening Block Diagrams

♦ Done from Design Browser
♦ Creating a Block Diagram *
! Pulldown:
File > New > Graphical View > Block Diagram
! Toolbar: *
New > Graphical View > Block Diagram
! Shortcut bar: New...
♦ Editing a Block Diagram
! Pulldown: File > Open File
! Toolbar: Open
! Double-click on Block Diagram view in
Design Browser
♦ From higher level Block:
! Double-click block
! Select Block
– Popup:
• Open As> <existing view name>
• Open As> New View...
2-17 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation

Notes:
Creating a block diagram is similar to schematic editing when using components.
Components are placed and then wired together. When using blocks instead of
components however there are some differences. Components have a predefined
interface while blocks do not. Blocks gain their interface by the signals that are
connected to them. Blocks are not selected from a component library, they are
defined on the fly. Once all of the signals that connect to a block have their names
and types specified the block interface is defined. The interface can be changed
later as needed by adding or removing signals.

Designing with FPGA Advantage 2-17

November 2003
Block Diagram Basics

Adding Blocks to a Block Diagram

Block [Crtl + F3] :

Block - Fluid Interface
Component - Library/Block/Instance names
Component [F3] :
- Fixed Interface
- Library/Comp./Instance names
<External IP>
Embedded Block - External HDL
- Compiled outside
Embedded Block [F4] :
- No hierarchy created
Frame
(For, If, Block) - Any view including HDL
Frame :
For [F6], If [Shift+F6], Block [Alt+F6]
Enter HDL
- Repeating/Conditional Instances

Notes:

2-18 Designing with FPGA Advantage

November 2003
Block Diagram Basics

Instantiating Blocks

Instantiating Blocks
♦ “Ghost” of block guides placement
♦ Keep placing blocks until RMB
♦ Block shape can be modified as
needed
♦ No interface information needed at
instantiation!
♦ Library and instance designations
added automatically
♦ Block may be “promoted” to a
Component
! Create Block
! Route Signals/Busses
! Object Properties…
– Convert to Component
! Edit Component Symbol

Notes:
If you do not change the instance name, each block is given a unique instance
name by adding an integer to the default name (for example, I1, I2, I3). The
default base instance name for new blocks can be changed by setting a preference.

Each block must have a unique block name and instance name. However, a block
can be re-used as a component (with the same component name as the defining
block) but the instance name must be unique across all blocks and components in
the design.

The block and instance name cannot be the same when you are using VHDL but
can be given the same name if you are using Verilog.

Designing with FPGA Advantage 2-19

November 2003
Block Diagram Basics

Instantiating Components

Instantiating Components
♦ When the Add Component
command is selected the
Component Browser invokes
♦ Specify:
! Library
! Design Unit
! View
♦ Placed Component may be edited,
but only appearance changes
allowed (instance specific)
♦ Most editing done in Symbol Editor,
changes apply to ALL instances
♦ Interface is pre-defined by Symbol
♦ Components can not be converted
back to Blocks!
2-20 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation

Notes:
When you add a component, the component browser is displayed which allows
you to choose a component (including ModuleWare components and components
you have created) from an existing library and drag an instance of the component
on to a block diagram or IBD view.

If the instantiated component references any VHDL packages which are not
already referenced on the diagram, you are prompted whether to add them.

If you do not change the instance name, each new component is given a unique
instance name by adding an integer to the default name. For example, (I1, I2,
I3...). The default base instance name for a component is the same as for a new
block and can be changed by setting preferences.

2-20 Designing with FPGA Advantage

November 2003
Block Diagram Basics

Instantiating Embedded Blocks

♦ Instantiation similar to Blocks
♦ Name and Instance designations assigned automatically
♦ Editing graphics/text similar to Blocks
♦ Underlying view “embedded” in parent object
♦ May not be converted to a Component later!

Notes:
You can add HDL text as an embedded view on a block diagram by adding an
embedded block and choosing Text from the Create Embedded View dialog box.
A default HDL text box is added on the block diagram with a comment line
containing the embedded block name and number.

You can edit the HDL text by double-clicking on the text to open a text edit box or
by using the Text tab of the Object Properties dialog box. Any valid HDL
statements for the hardware description language in use can be entered in free
format (including line breaks and indentation which are preserved on the diagram)
but each statement must be terminated by a semi-colon.

Designing with FPGA Advantage 2-21

November 2003
Block Diagram Basics

Routing Signals

Routing Signals
♦ Toolbar Icons:
! Signal
! Bus
! Bundle
♦ Other Methods:
! Pulldown: Add > Signal | Bus | Bundle

♦ May enable automatic port instantiation

! Signal Icon changes to show port
♦ Signals with the same name are connected automatically
within Block Diagram

Notes:

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Block Diagram Basics

Setting Signal Defaults

♦ Can be done separately for signals and busses
♦ May set default name
♦ May set default array bounds for busses
♦ Recommended type settings for VHDL:
! Signals: std_logic
! Busses: unsigned

♦ Process:
! Select Design Browser Window
! Choose Pulldown:
– Options > Edit Master Preferences > Block Diagram...
! Choose Default Values Tab
! Make Changes
2-23 • Designing with FPGA Advantage: Block Diagram Basics Copyright © 2003 Mentor Graphics Corporation

Notes:

Designing with FPGA Advantage 2-23

November 2003
Block Diagram Basics

Individual Signal Properties

Control the signal visibility
on the schematic

Determines the scope of any

action performed on the signal
(e.g.: rename, …)

Notes:
Ripping From a Bus

You can rip part or all of a bus by adding a new signal or bus starting from any
point on the bus. The new net segment has the same name and properties as the
source bus. However, you can use the Object Properties dialog box to edit the use
properties (including the style, slice or element and visibility) for the ripped
segment.

Do not attempt to change the name of a ripped signal or connect a slice or element
of a bus directly to an output port. However, you can use embedded HDL text to
assign the slice or element to an alternative output signal.

2-24 Designing with FPGA Advantage

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Block Diagram Basics

Connecting Signals to Blocks

♦ Connecting to Blocks/Embedded Blocks
! Start or finish on Block boundary
! Signal added to Block interface
automatically
! Start of route on block creates Output
! End of route on block creates Input

♦ Connecting to Components
! Start or finish on Component “pin”
! Signal direction assigned by interface
! Signal name assigned by interface if not
previously named
! Signal type assigned by interface

Notes:

Designing with FPGA Advantage 2-25

November 2003
Block Diagram Basics

Connecting Signals to Objects

♦ Unconnected signals have “open”
terminator
♦ All signals with the same name in
a diagram are connected!
! Warning is issued
! Signals attached to global
connectors imply ports on all
blocks at that level of hierarchy

♦ Connecting unconnected signals

! Select
– object signal is attached to, or
– signal
! Choose one of following:
– Pulldown: Edit > Connect
– Popup: Connect

Notes:
Signals or buses can be individually connected to a block or component by
dragging with the Left mouse button over the body of a block or over an existing
port or port map frame on a component.

You can also make a connection by overlapping a block or component with the
dangling net connectors on the end of existing signals or buses and then choosing
Connect from the Diagram or popup menus. This can be useful when you have
created a new child block diagram and want to add a block or component
connected to the nets created when the child diagram is initialized.

2-26 Designing with FPGA Advantage

November 2003
Block Diagram Basics

Design Objects: Comment Text Objects

♦ Default Color: Wheat
♦ Graphic text and notes
♦ Does not generate functional HDL
♦ Will generate comments in HDL
♦ Title Box is a group of Comment Text Boxes
♦ Template is customizable:
! $HDS_TEAM_VER\title_block.tmpl (default)
! specify other PD:Options>Main>Diagram

Notes:
The template title block is read from the TitleBlock.tmpl file in the
../resources/misc installation subdirectory. However, you can set an alternative
location for the template in your general editing preferences.

The current template title block is automatically included at the lower right side on
a new diagram (including concurrent and hierarchical diagrams) when you create
a new graphic editor view unless this option is unset in your general editing
preferences. Note that the title block text can be included in the generated HDL by
choosing Include in HDL from the popup menu.

You can create your own title block template by grouping one or more comment
texts (which may optionally include internal variables) and choosing Save Title

Designing with FPGA Advantage 2-27

November 2003
Block Diagram Basics

Block from the File menu to save the title block at the location specified in your
preferences. For example, the default title block comprises ten grouped comment
texts and uses the internal variables %(library), %(unit), %(view), %(user), %(dd)
%(month) and %(year) for the library, design unit, design unit view, username and
modified date.

2-28 Designing with FPGA Advantage

November 2003
Block Diagram Basics

Adding Comments

Add → Comment Text

Type text here

Notes:
You can use the text tool button or choose Comment Text from the Add menu to
add comment text as annotation on a block diagram, flow chart, state diagram or
symbol. The cursor changes to a cross-hair which allows you to open a text entry
box by clicking at an empty location anywhere on the diagram and enter free-
format text. Any line feeds or blank lines you enter are preserved on the diagram.
The text edit box has its own scroll bars which allow the text to be scrolled
horizontally or vertically while editing.

Designing with FPGA Advantage 2-29

November 2003
Block Diagram Basics

Assigning Comment Locations

Comments can be attached to an object

User-defined comment location

in the generated code

RMB → Include in HDL

Notes:
You can associate comment text with the interface to a block by selecting the In
Block Interface cascade option and attaching the anchor to a block. When this
option is used, the note is included as comments in the generated VHDL entity or
Verilog module for the block. If the block is subsequently converted to a
component, any block interface comments are moved into the symbol for the
component. Any comments added before or after a block object are included
before or after the instantiation statement for the parent diagram.

You can also associate comment text with the diagram itself by selecting the At
File Start, After File Header or At File End cascade option. Comment text
attached in this way is included as comments at the specified position in the
generated HDL for the diagram.

2-30 Designing with FPGA Advantage

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Block Diagram Basics

Graphical Comments

Graphical Comments
♦ Custom Symbol Creation
! eg no longer restricted to
rectangles and common
gate symbols (and, or, alu,
mux)
♦ Comment Graphics
! adds common drawing
features to HDL Designer
diagrams
♦ Panels
! Define named areas on
diagram
! Can be dragged as OLE
! Can be printed

Notes:
You can add comment graphics on a block diagram, flow chart, state diagram or
symbol by choosing Comment Graphics from the Add menu. The cascade menu
provides the following commands:

Line, Polyline, Polygon, Arc, Rectangle, Ellipse, Circle and Bitmap.

Designing with FPGA Advantage 2-31

November 2003
Block Diagram Basics

Saving the Design

♦ File > Save
♦ Save design as
! Library
! Design Unit
(entity/module name)
! View (architecture)

Notes:
After the blocks have been placed, the signals and busses interconnected, the
concurrent statements specified, and the packages declared the design can be
saved in the library. When the save menu is selected the following dialog box will
appear. Select the library to save to, the Design Unit name, and the View name.
For Block Diagrams, Truth Tables, and Flow Charts the view names will default
to a reasonable name. For the VHDL Architectures and Verilog Modules the
designer should generate a reasonable name.

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Block Diagram Basics

A Block Diagram Example

♦ Consistent presentation
♦ Enough information to
understand quickly
♦ Example:
! Interface signals are set off
from main circuit
! Signal and bus types
shown in interface portion
! Signal and bus types
hidden in main diagram
! Title Block separates
functionality from definition

Notes:

Designing with FPGA Advantage 2-33

November 2003
Block Diagram Basics

Lab 2: Building the BCD Register

Lab Goal: Create a block diagram for a two-digit BCD Register

♦ Part 1: Placing the components

! Use XYZLib Library so design will be reusable
! Set Block Diagram Preferences to save effort
! Open a new block diagram BCDRegister
! Instantiate BCD Counters
! Create a new control block
♦ Part 2: Routing wires
! Add signals and busses for design view interface
! Route signals on block diagram
! Note that control block interface doesn’t need to be pre-defined
! Hide signal/bus types
♦ Part 3: Save the Design
! Save the design

Notes:

2-34 Designing with FPGA Advantage

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Block Diagram Basics

Lab 2: Building The BCD Register

Introduction
In this lab, you will create a block diagram for a two-digit BCD Register, using
the BCDCounter design you tested in the previous lab.

Note: for the labs in this training material, use type std_logic for single-bit signals
and unsigned for multiple-bit busses. To set the default signal types click in the
Design Manager’s main window on Options > Master Prefs > Block Diagram.
Choose the Default Values Tab and enter the values. All signals are active-high
unless otherwise noted.

Directions
• Part 1: Create a new block diagram within the XYZLib library called
BCDRegister.

o Open a new Block Diagram using PD>File>New>Graphical

View>Block Diagram. Alternatively you can use the New...
icons (PD = pulldown menu)

o Save the design by choosing the Library XYZLib and specifying

BCDRegister as Design Unit name.

Note that there is no need to specify pathnames, since the Library

Mapping mechanism takes care of physical locations.

Designing with FPGA Advantage 2-35

November 2003
Block Diagram Basics

• Part 2: Placing the Components

o You may refer to the diagram at the end of this lab for an example if
you wish.

o Instantiate two BCDCounter components from XYZLib.

Designate one BCDCounter as “Ones” and the other as “Tens”.

o Add a new block called BCDRegControl.

• Part 3: Routing Wires

o Add wires, busses, and ports as shown in the Block Diagram on the
following page.

o Add a clock designation to the BCDRegControl clk input pin.

o Add an inversion bubble to the BCDRegControl reset input pin.

• Part 4: Saving the Design

Do NOT use “Save As” since you already specified the Design Unit and
View name during the first save operation.

o Look at the design hierarchy for the BCDRegister part in the Design
Explorer. What do you see?

o Is there an HDL file for the BCDRegister in the HDL Files view mode
in the Design Explorer window?
Why or why not?

________________________________________________________

Example Block Diagram

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Block Diagram Basics

carry_out_ones
std_logic
q_ones
unsigned(3:0)

reset clear
std_logic
q
load_in_ones load_in
unsigned(3:0)
XYZLib
cnten_ones cnten BCDCounter
std_logic
XYZLib Ones
BCDRegControl load_ones load spec
I2 std_logic carry_out

reset clk_ones clk

std_logic std_logic

clk
std_logic data_out
unsigned(7:0)
load_en ripple_out
std_logic std_logic

data_in reset clear

unsigned(7:0) std_logic
q
ripple_in load_in_tens load_in
std_logic unsigned(3:0)
XYZLib
cnten_tens cnten BCDCounter
std_logic
Tens
load_tens load spec
std_logic carry_out

clk_tens clk
std_logic

carry_out_tens
std_logic
q_tens
unsigned(3:0)

Project: FPGAdv_Training
<company name>
The BCD Register implements a cascadable
Title: BCDRegister Block Diagram two digit BCD Counter with reset and load
Path: XYZLib/BCDRegister/struct functionality.
Edited: by lynneh on 04 Nov 2003

Designing with FPGA Advantage 2-37

November 2003
Block Diagram Basics

2-38 Designing with FPGA Advantage

November 2003
Module 3
Finite State Machine Basics

Objectives
This module will cover the following topics:

• Introduction to Finite State Machines

• State Machine Styles
• State Machine Preferences
• Finite State Machine Design Objects
• Design Object Properties
• HDL Code Generation Preferences
• Setting Signal Status
• Concurrent State Machines
• Re-Leveling
• A Finite State Machine Example

Designing with FPGA Advantage 3-1

November 2003
Finite State Machine Basics

State Machine Styles: Moore vs. Mealy

Moore
Combinational
Φ Clock
Combinational
Next Current
Inputs Output
state state
Input Output
Forming Forming
Logic Logic

Storage

Mealy
Combinational
Φ Clock
Inputs

Next Current
Output
state state
Input Output
Inputs Forming Forming
Logic Logic

Storage Combinational
3-2 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation

Notes:
The outputs of a Moore state machine are a function of its state only, therefore the
outputs only change if the state changes. However, if a Moore state contains an
assignment to an input signal, the state machine has an input dependency and its
outputs are a function of both the state and the inputs, that is it will have Mealy
behavior.

The outputs of a Mealy state machine are a function of its current state and inputs.
Changing the input has a corresponding affect on the outputs. When an input
condition is satisfied, a Mealy state machine performs specified actions, such as
changing the values of outputs and transitions from one state to another.

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Finite State Machine Basics

State Machine Styles: Moore / Mealy /

Mixed

State Machine Styles: Moore / Mealy / Mixed

Output assignment
in the states

Moore Mealy
Mixed
Output assignment
in the transitions
Output assignment
in both states and
transitions

Notes:

Designing with FPGA Advantage 3-3

November 2003
Finite State Machine Basics

State Diagram Objects

Add → ...

Start state

State

condition Transition
Interrupt point
Link
priority

Junction

action
Link : to a state (incl. Hier) or to a junction
Junction : to simplify by factoring transitions
Interrupt : Applies to all states
Normal state Hierarchical state
State : of Start, Normal or Hierarchical types
3-4 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation

Notes:
The start state is the initial state of the state machine. Only one start state can exist
in any state machine. The start state may have associated state actions.

A simple state represents observable status that the state machine can exhibit at a
point in time. A simple state may have associated state actions.

A hierarchical state represents a child state diagram within a hierarchical state

machine. A hierarchical state cannot have associated state actions.

A transition is the change of state that occurs when an associated condition is

satisfied. Transitions may also include transition actions and have a transition
priority.

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Finite State Machine Basics

A junction represents a connection to transitions which are common to more than

one state.

An interrupt point is an implicit connection to all states on the diagram.

A named link represents a direct transition to the named state or junction.

Designing with FPGA Advantage 3-5

November 2003
Finite State Machine Basics

State Diagram Objects: Hierarchy

Add → ... State Diagram Objects: Hierarchy

– Multiple Entry points

Hierarchical State allowed
– Can exit with a link
– Multiple levels of
hierarchy allowed
Entry point

Exit point

Notes:
A state machine may comprise a number of hierarchical state diagrams. Each child
state diagram is represented by a hierarchical state in its parent diagram. You can
open down into a child state diagram by double-clicking on a hierarchical state or
by choosing Open Down from the Open cascade of the File menu (or popup
menu) to explicitly open the selected hierarchical state. A new child state diagram
is created and opened for edit if it does not already exist. A newly created child
state diagram comprises an entry point, a single state and an exit point connected
by transitions. You can edit a hierarchical state diagram in the same way as any
other state diagram including more hierarchical states as well as any other state
diagram objects (with the exception of interrupt points).

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Finite State Machine Basics

FSM Wait States

♦ FSM remains in a given state for a specified number of clock cycles
♦ Applies to Synchronous FSMs only
♦ Supports parameterised wait values
♦ Transitions from Wait State can be expressions or simple/complex TIMEOUT
conditions

Notes:
A wait state can be used to implement a multi-cycle wait in a synchronous state
machine. The number of clock cycles to wait for is specified in the state object
properties and is applied when the TIMEOUT pre-condition is used for a
transition exiting the wait state. The TIMEOUT pre-condition can be used on its
own to implement a simple delay or if enabled when a regular condition is
entered, it is ANDed with the condition. A wait state can have more than one exit
transitions. If the TIMEOUT pre-condition is unset for any of these transitions, the
state may be exited via this transition before the timeout has expired.

Designing with FPGA Advantage 3-7

November 2003
Finite State Machine Basics

FSM Wait States (Cont.)

♦ Wait States support IF-style transition decoding only
♦ On-entry to a Wait State, counter is set & counts down on each clock edge.
TIMEOUT asserted when counter reaches zero
♦ Counter is NOT reset by Implicit or Explicit loop-backs
♦ Any number of Wait states allowed
♦ The same timeout & counter signals are used for each Wait state in the same
concurrent machine
♦ Can specify the VHDL type for the Timeout and other counter signals in Master
Preferences and for each concurrent FSM
♦ Can also specify the bounds for the counter signal if parameterised (non-integer)
wait values are used

Notes:
A separate timeout signal is generated for each concurrent state machine using the
form: <machine_name>_timeout

Local counter signals which are used by all wait states in the concurrent state
machines are generated using the form: <machine_name>_timer and
<machine_name>_next_timer

An entry flag is generated for each wait state using the form:
<machine_name>_to_<state_name>

If all the wait states in a concurrent state machine use integer wait values, the
VHDL signal types default to std_logic (or std_logic_vector) and have the width

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Finite State Machine Basics

required for the largest wait value. If any wait state has a parameterized (non-
integer) value, the scalar type, vector type and bounds of the timeout, counter and
entry flag signals must be specified.

Designing with FPGA Advantage 3-9

November 2003
Finite State Machine Basics

Re-Leveling

Diagram → Re-Level → Add hierarchy Add or remove hierarchy

Diagram → Re-Level → Remove hierarchy

Notes:
Adding hierarchy replaces the selected states by a new hierarchical state and
moves the selected states into the child hierarchical state diagram.

Removing hierarchy deletes the selected hierarchical state and replaces it by the
objects in the child hierarchical state diagram. The relative placement of the new
objects is preserved and centered on the original position of the hierarchical state.
They may therefore overlap existing objects on the parent diagram. If the child
diagram included other hierarchical states, their hierarchy is retained but can be
removed by another re-level operation.

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Finite State Machine Basics

Comments

Add → Comment Text

Consistently with the Block Editor

you can:

– on-line edit the comment

(double-click on it)
– use your own text editor
([RMB] → Send to Editor)

Notes:

Designing with FPGA Advantage 3-11

November 2003
Finite State Machine Basics

State Properties: IF / CASE, Actions

WHEN s1 =>
IF (din(0) = '1') THEN
next_state <= s3;
- Simple State ELSIF (din(0) = '0') THEN
- Hierarchical State next_state <= s0;
ELSE
- Start State next_state <= s1;
END IF;

WHEN s1 =>
CASE din(0) IS
WHEN '1' =>
next_state <= s3;
WHEN '0' =>
next_state <= s0;
Output assignment WHEN OTHERS =>
next_state <= s1;
END CASE;

else / when others

Notes:
A CASE style transition typically produces in a faster, parallel, multiplex-based
circuit whereas an IF style transition produces a serial, priority decoder-based
circuit. Also, more efficient decoding can often be achieved by concatenating
together signals of similar type and decoding the resulting concatenated variable
rather than each signal individually.

You can set decode options for the CASE style transitions leaving a state by using
the button on the States tab of the Object Properties dialog box in a state diagram
to display the CASE Settings dialog box.

The dialog box allows you to enter a CASE selector expression. You can then
enter expressions for each branch as object properties for the transitions leaving

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Finite State Machine Basics

the state. For example, the selector expression might be sigA & sigB with branch
expressions "00" and "01" | "11" on transitions leaving the state.

Designing with FPGA Advantage 3-13

November 2003
Finite State Machine Basics

Transition Properties: Condition,

Actions

Transition Properties: Condition, Actions

Several transitions can be selected at a time and
conditions / actions applied to all of them!

Notes:

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Finite State Machine Basics

Junction / Link Properties

You can specify a name
– It does not appear in the
generated HDL
– Can be a link target

The target can be :

– a valid state
– a junction

Notes:

Designing with FPGA Advantage 3-15

November 2003
Finite State Machine Basics

Context Definition

Context Definition
Diagram → Package References...

Just double-click on
the Package List

Notes:

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Finite State Machine Basics

State Machine Properties

Diagram → State Machine Properties...

[RMB] → State Machine Properties...

Notes:

Designing with FPGA Advantage 3-17

November 2003
Finite State Machine Basics

State Machine Properties: Generation

An asynchronous machine
requires a propagation delay

Name : can be any input signal

defined at the design units interface
Edge :
– Rising
– Falling
– Specify (eg: rising_edge(clk))

Name : can be any input signal

defined at the design units interface
Mode :
– synchronous
– asynchronous
Level :
– Low
– High
Name : can be any input signal
– Specify
defined in the drop down list
Add Pragma (*) : (*) : using keyword (pragma / synopsys / exemplar)
Options → VHDL... → Style → Pragma Setup Level :
– sync_set_reset_local
Verilog... - Low
– async_set_reset_local
- High
Second Reset :
- Specify
– Name, Condition, Action

Notes:
For a synchronous state machine, you can enter the clock signal or choose from a
dropdown list of available input signals and choose the clock Edge sensitivity. For
a Verilog view, you can choose Rising or Falling. For a VHDL view, you can
choose Rising, Falling, Rising Last, Falling Last, Rising Edge or Falling Edge.
Alternatively for either language, you can choose Specify to enter any other valid
Condition. Refer to Clock Edge Expressions for more information about detecting
clock edges.

You can optionally enter a Synchronous or Asynchronous reset signal or choose

from a dropdown list of available input or internal signals and choose to trigger
the reset on a High or Low Level signal (or choose Specify to enter any other valid
reset Condition). If you have specified a Verilog, reset condition, you must also

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Finite State Machine Basics

specify any additional signals required in the sensitivity list using the Sensitivity
entry box. (Multiple signals should be separated by an or operator.)

Designing with FPGA Advantage 3-19

November 2003
Finite State Machine Basics

State Machine Properties: Generation

(Cont.)

State Machine Properties: Generation (Cont.)

The hard encoding scheme
must be selected to access
the One-Hot option

3 Processes
– Clocked
– Nextstate Merged with
– Output 2 Processes

Default: HDL Designer generates a enumerated type

with a type enumeration for each state
Specify Type :
– A custom type can be used
– Hard encoding is necessary (see later)
Assign value to output port: The specified port
type is used. The current_state is assigned to
that port.

Notes:
You can specify whether HDL is generated using If, One-Hot or Case styles.

However, the One-Hot style is not available when using VHDL unless Hard state
machine encoding is selected in the encoding tab of the dialog box. By default,
three separate VHDL processes representing the clocked, next state and output
assignments are generated. However, you can choose to combine the
combinatorial outputs into the next state process by choosing the 2 Processes
options.

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Finite State Machine Basics

When you are using VHDL, you can set a state variable for the state machine by
automatically generating a type, specifying a type or choosing an output signal
port which describes the current state of the state machine in terms of an
enumerated type or constant value. The specified type can be one of the standard
predefined types or a type defined in a VHDL package.

If you choose Assign value to output port, you can choose from a dropdown list of
output signal names (including output, buffered or bidirectional ports).

Designing with FPGA Advantage 3-21

November 2003
Finite State Machine Basics

State Machine Properties: Generation

(Cont.)

State Machine Properties: Generation (Cont.)

Instead of current state

applies to extra clocked or registered outputs

Additional code necessary

Only with Case for animation
HDL style

When an unexpected
state is reached Default :
– current_state
– next_state

Notes:
When designing a state machine with registered outputs, the 'Register state actions
on next state' option determines whether there is a one clock cycle delay at the
outputs or not. This delay is caused by registering the outputs with the
current_state signal. When registering with the next_state signal there is even
less delay at the registered outputs than at the combinatorial outputs. A drawback
of the next_state solution is that the synthesis tool usually uses scan flip flops to
realize this behavior. This could lead to problems when inserting scan chains for
testing purposes. But this usually does not apply to FPGA designs.

3-22 Designing with FPGA Advantage

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Finite State Machine Basics

State Machine Properties (Cont.)

Information can be entered:

– in the tabs
– directly on the schematic

Notes:

Designing with FPGA Advantage 3-23

November 2003
Finite State Machine Basics

State Machine Properties: Architecture

Declarations

State Machine Properties: Architecture Declarations

User defined architecture

declarative section

Notes:
The Architecture Declarations (or Module Declarations) tab of the State Machine
Properties dialog box allows you to enter any valid HDL statements for the current
hardware description language in a free-format entry box. Signal declarations,
constants, variables, comments, procedures, functions or type definitions can be
included in the declaration.

Typically a VHDL declaration, comprises a keyword (signal, constant or variable)

followed by a name, type and value. The specified type must be one of the
standard predefined types or a type defined in a VHDL package. An initial value

3-24 Designing with FPGA Advantage

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Finite State Machine Basics

is required when the declaration is a constant but is optional when you declare a
signal or variable.

Designing with FPGA Advantage 3-25

November 2003
Finite State Machine Basics

State Machine Properties: Statement

Blocks

State Machine Properties: Statement Blocks

Global Actions placed at the
beginning of the output process

Concurrent Statements placed

at the end of the SM architecture

The default assignment of

current_state must be repeated
if you use this section !!!

Notes:
Global actions and state register statements can be specified separately for each
diagram in a set of concurrent state machines. Global actions for internal signals
are included in the clocked HDL and all other global actions are included in the
output code. State register statements are included in the generated HDL before
the state decoding statements in the clock process or always code. These
statements are inserted instead of the default assignment to the next state and are
typically used to determine whether a counter should be incremented or reset and
whether to update the state.

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Finite State Machine Basics

The concurrent statements are included in the generated HDL at the end of the
VHDL architecture or Verilog module and are applied to all diagrams in a set of
concurrent state machines.

Designing with FPGA Advantage 3-27

November 2003
Finite State Machine Basics

State Machine Properties: Process

Declaration

State Machine Properties: Process Declaration

clocked and output process

common declarations

Notes:
When you are using VHDL, you can add or edit state machine process
declarations by choosing State Machine Properties from the Diagram menu or by
double clicking on the Process Declarations label on the state diagram.The
Process Declarations tab of the State Machine Properties dialog box allows you to
add or edit declaration statements in the dialog box. The Visible check box allows
you to select whether the declarations are displayed or hidden on the diagram.
Process declarations are placed immediately before the code for both the clocked
and output processes in the generated VHDL.

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Finite State Machine Basics

Separate process declarations can be specified for each diagram in a set of

concurrent state diagrams.

Designing with FPGA Advantage 3-29

November 2003
Finite State Machine Basics

State Machine Properties: Encoding

VHDL

State Machine Properties: Encoding VHDL

Used when creating “safe” state machines

Notes:
The Encoding tab of the State Machine Properties dialog box allows you to choose
automatic or manual encoding. When Auto mode is selected, attributes or values
are automatically generated. When Manual mode is selected, encoding values can
be entered by direct text editing on the state or by using the Encoding field in the
States tab of the Object Properties dialog box.

The TYPE_ENCODING, TYPE_ENCODING_STYLE or syn_encoding

attributes must be declared in a referenced package. Type encoding attributes for
LeonardoSpectrum are provided in the exemplar standard package library. The

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Finite State Machine Basics

syn_encoding attributes support the Synplify synthesis tools and should be

defined by referencing the appropriate Synplify package.

Designing with FPGA Advantage 3-31

November 2003
Finite State Machine Basics

Creating “Hard” Encoded “Safe” State

Machines

Creating “Hard” Encoded “Safe” State Machines

♦ A safe state machine needs a hard coded state vector
! Every state is declared as a constant, the value of the state
register is explicitly defined
! This prevents the synthesis tool from optimizing redundant
states
♦ HDL Designer does this automatically, when “Hard” encoding
and “Mode: Auto” is selected.
! When using “Mode: Manual” the state encoding must be
specified at every state. This is useful when designing state
machines with Output = State (no output decode logic)

Notes:
When describing a state machine using HDL, generally the synthesis tools will
optimize away all states that cannot be reached and generate a highly optimized
circuit. But sometimes the optimization is not acceptable. For example, if the
circuit powers up in an invalid state, or the circuit is in a extreme working
environment and a glitch sends it into an undesired state, the circuit may never get
back to its normal operating condition.

Therefore you can use "hard" encoded "safe" state machines: No matter how
many states you have, if you use the "bit-level" encoding scheme, the optimized
result will be "safe". This requires you to specify bit patterns for your states.

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Finite State Machine Basics

For example, use std_logic_vector (for VHDL) to define your state type, then you
can detect the undesired states either using the "others" (for VHDL) or "default"
(for Verilog) statement in the state decoding process or by explicitly defining if
current_state = (undesired states) or current_state /= (desired states).

Designing with FPGA Advantage 3-33

November 2003
Finite State Machine Basics

State Machine Properties: Encoding

Verilog

State Machine Properties: Encoding Verilog

Notes:
When you are using Verilog, you can choose whether the range is included in the
state encoding parameter declaration by setting the Use Range in Encoded
Parameter check box. You can choose Hard Automatic or Hard Manual mode. If
you are using the Synplify synthesis tools you can also set a syn_encoding Pragma
with onehot, gray, sequential or other user specified style (optionally including the
keyword safe). When Hard is selected for either language, One-Hot HDL style is
available in the Generation tab when setting generation properties. The One-Hot
style is useful for use with synthesis tools which do not support automatic state
encoding. This option is not recommended for synthesis tools which can perform
efficient encoding automatically.

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Finite State Machine Basics

State Machine Properties: Signal Status

OUTPUT

INTERNAL

For CLOCKED and REGISTERED signals

For COMBINATORIAL and REGISTERED signals

Information only
OUTPUT : from the interface
INTERNAL : from the arch. declarative part
Information only
For VHDL

Notes:
You can change the signal status by clicking in the Status field and choosing
REGISTERED, COMBINATORIAL or (for output signals only) CLOCKED
from the pull down box. The default value is normally set in the signal declaration
but can be changed in the dialog box. When you set any signal to be registered or
clocked, a reset value must be specified in the dialog box. However, only the
default value can be changed for a combinatorial signal. The default value of a
signal when not otherwise specified can be set as a preference.

Designing with FPGA Advantage 3-35

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Finite State Machine Basics

Logic Location in Generated HDL

COMBINATORIAL
Current state

Input Output Outputs

Forming State Forming
Logic Variable Logic

Inputs nextstate clocked output

Outputs assigned in the output process

REGISTERED Current state

Outputs
Outputs_int

Input Output Outputs

Forming State Forming Output
Logic Variable Logic Register

output
Inputs nextstate clocked

Outputs <= Outputs_int; in the clocked process

Notes:
Combinatorial actions are directly assigned to the output port - Outputs.

Registered actions are applied to an internal signal called Outputs_int.

This assignment is done in a process labeled "output". The signal Outputs_int is

registered to produce the signal Outputs in a process labeled "clocked". The signal
Outputs is an output port and cannot be read inside the architecture. The
unregistered signal Outputs_int is available inside the architecture.

The suffix _int can be changed on the State Machine Properties - Signals Status
dialog.

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Finite State Machine Basics

Logic Location in Generated HDL (Cont.)

CLOCKED Next state

Current state

Input Output Outputs

Forming State Forming Output
Logic Variable Logic Register

Inputs nextstate clocked

Outputs_cld

Continuous assignment (outside any process)

Outputs <= Outputs_cld ;

Help → Bookcase
❏ Other Documents → “Predicting the Output of Finite State Machines”
3-27 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation

Notes:
Clocked actions are applied and registered to an internal signal named
Outputs_cld.

This assignment is done in a process labeled "clocked". The signal Outputs_cld is

then assigned directly to the output port - Outputs in a concurrent assignment .
This is different from the Registered approach. The most noticeable difference is
the absence of the "output" process. More significantly, the clocked signal
Outputs_cld may be read inside the architecture and there is also no requirement
to provide a Default Value.

The signal Outputs_cld which has the same value as the output (Outputs) may be
used in a transition condition, or in a Concurrent Statement.

Designing with FPGA Advantage 3-37

November 2003
Finite State Machine Basics

The suffix _cld can be changed on the State Machine Properties - Signals Status
dialog.

3-38 Designing with FPGA Advantage

November 2003
Finite State Machine Basics

Registered vs. Clocked Outputs

Applies
clk
to Clocked and
reset Registered
z_comb Outputs
z_reg

z_clocked
current_state s0 s1 s2 s3 s0

next_state s1 s2 s3 s0 s1

Different behavior at Current_State S2:

Combinatorial and Registered Outputs change to their default value
Clocked Outputs hold their value until a new value is assigned

Notes:
Both registered and clocked outputs get registers synthesized at the output signals.
The difference is the output assignment behavior. When using registered outputs it
is mandatory to specify a default value for the output. Otherwise the synthesis tool
will infer latches if the registered output isn't always assigned. The registered
output always gets the default value unless another value is assigned (see state S2
above).

When using clocked outputs the output "remembers" always the latest assigned
value until a new value is assigned. Therefore it is not necessary to specify a
default value. If a default value is specified anyway it results in the same behavior
than the registered solution.

Designing with FPGA Advantage 3-39

November 2003
Finite State Machine Basics

How to Choose which Output Type?

♦ Clocked is a good choice if you need to work with the

registered signal inside the FSM. For example, as a
counter or flag, as mentioned earlier.

Clocked is the best fail-safe choice because, since it is

clocked (<out>_cld is actually a clocked signal) it
always holds its value.
♦ Registered is appropriate if you need to work with the
combinatorial version of the signal inside the FSM and
just want to retime the outputs. This can be useful for
pipelining.
♦ Combinatorial is appropriate if the signal does not
need retiming or to be registered.

Notes:

3-40 Designing with FPGA Advantage

November 2003
Finite State Machine Basics

Register State Actions on Current State

Diagram → State Machine Properties...
Unchecked
by default!

clk
reset
z_comb
z_reg

z_clocked
current_state s0 s1 s2 s3 s0

next_state s1 s2 s3 s0 s1

One clock period delay is added to the Clocked and Registered

Outputs versus Combinatorial Output.

Notes:
Register state actions on next state ó when do you want to use this option?

Whether you have this on or off depends on the timing of the circuit.

If you register on next_state, you are clocking the flip-flop in the same clock
period as the condition occurs. Since conditions can be asynchronous, they could
occur at any time. You may not know if there will be adequate setup and hold
times for the flip-flop to register/latch the signal value reliably. However, if you
know there is plenty of slack or if you know the inputs come from a previous
register, then using next_state is probably fine.

Designing with FPGA Advantage 3-41

November 2003
Finite State Machine Basics

Also, when pipelining designs, you rely on registering the outputs on the next
clock edge in order to keep the outputs in the correct relative time-domain. So this
option is also appropriate in this case.

3-42 Designing with FPGA Advantage

November 2003
Finite State Machine Basics

Output Assignment Priority

A few actions impact the

value of the outputs.

The actions are prioritized

as shown below.

Execution Priority
(Highest at the Top)
Reset actions (jumps to Start State)

Interrupt transition actions

Normal transition actions

State actions

Global actions

Notes:

Designing with FPGA Advantage 3-43

November 2003
Finite State Machine Basics

Concurrent State Machines

Delete Machine
Shared :
- Interface Open Machine
- Package list
Add Machine
- Concurrent Statements
- User Declarations

Separated : Add → Concurrent State Machine [Ctrl+F2]

- Global Actions
- HDL generation options
- State encoding

- Treated as a single Design Object (one HDL file generated, saved at the same
time,...)

- Can’t create links between concurrent state machines

- State name must be unique
3-32 • Designing with FPGA Advantage: Finite State Machine Basics Copyright © 2003 Mentor Graphics Corporation

Notes:
You can create a concurrent state machine from a state diagram using the item
"Concurrent State Machine" from the Add menu. A concurrent state machine is
created and a new state diagram opened with the same interface as the current
diagram. The package list and any concurrent statements, or status signals list are
shared by the concurrent state machines but global actions can be set separately. If
there are any other user declarations (which are interpreted as architecture
declarations in VHDL or as module declarations in Verilog) these are also shared
by the concurrent state machines.

3-44 Designing with FPGA Advantage

November 2003
Finite State Machine Basics

Concurrent State Machines: Renaming

Diagram → Rename State Machine...

Default name is machine0 as

defined in the Preferences

Notes:
Each concurrent state machine is given a unique name by adding an integer to the
default name (for example, machine0, machine1, machine2...). However, the base
name for a new state machine can be set as a preference in the Default Values tab
of the State Machine Preferences dialog box.

You can change the name of the active concurrent state machine (which is used in
the generated HDL) by choosing Rename State Machine from the Diagram menu
to display a Rename dialog box. The name is also shown in the window title for
the state diagram.

Designing with FPGA Advantage 3-45

November 2003
Finite State Machine Basics

Expression Builder

Double click to edit

(Expression Builder pops up)

Notes:
The expression builder provides a palette which lists all the available ports and
locally defined signals together with template values in the syntax required by the
active diagram. It also provides buttons which can be used to insert appropriate
operators for the active language. The HDL expression builder can be used
whenever an input expression (condition) or an output assertion (action) is being
edited whether by direct text editing or in a dialog box. The expression builder
dialog box is normally displayed automatically unless you set the Do not display
automatically option in the dialog box. In automatic mode, the expression builder
is automatically displayed when a HDL expression is being edited and
automatically hidden when the edit is completed.

3-46 Designing with FPGA Advantage

November 2003
Finite State Machine Basics

State Machine Preferences: Default

Values

State Machine Preferences: Default Values

Options → Master Preferences → State Machine...

Actions and conditions are

applied to ALL States and
Transitions

Will also be applied to

vectored signals !!!

Notes:
This tab can also be edited by choosing Diagram Preferences from the Options
menu in a state diagram. When you edit preferences for the active diagram, the
dialog box allows you to choose whether the preferences are applied to new
objects or to both new and existing objects in the state machine (including
concurrent or hierarchical diagrams). You can save the preferences for the active
diagram as master preferences by choosing Update from Diagram in the Master
Preferences cascade of the Options menu or apply the master preferences for
object appearance to the active diagram by choosing Apply to Existing Objects or
Apply to New and Existing Objects. However, you cannot apply the master
preferences for default values to the active diagram.

Designing with FPGA Advantage 3-47

November 2003
Finite State Machine Basics

State Machine Preferences (Cont.)

Options → Master Preferences → State Machine...

Polyline style
Correct HDL syntax entry

Spline style

Signal status explained later

Notes:

3-48 Designing with FPGA Advantage

November 2003
Finite State Machine Basics

Lab 3: Controlling the BCD Register

♦ Lab Goal: Create a State Machine to control the two-digit BCD
Register created in the previous lab

! Part 1: Creating the FSM

! Part 2: Initializing the FSM

! Part 3: Implement the Counting Functionality

! Part 4: Generate HDL

Notes:

Designing with FPGA Advantage 3-49

November 2003
Finite State Machine Basics

Lab 3: Controlling the BCD Register

Introduction
In this lab, you will create a finite state machine to control the BCDRegister
design you began in an earlier lab. If you haven’t finished Lab 2, your instructor
can provide you with a completed copy of the design before you continue.

Directions
• Part 1: Create a Finite State Machine “beneath” the BCDRegControl block
o Open the BCDRegister block diagram you created in a previous lab.

o Double-click on the BCDRegControl block. Select a file type of

“State Diagram” in the Open Down Create New View dialog box.
Click “Next”. At the final wizard dialog keep the default view name
“fsm.sm” and finish the process.

o A State Machine Editor Window will appear.

• Part 2: Initialize the State Machine Diagram

o Open the State Machine Object Properties dialog box.

Hint: Position the cursor within the Editor Window, click the RMB, and
select the popup menu item State Machine Properties...

3-50 Designing with FPGA Advantage

November 2003
Finite State Machine Basics

o Select the Generation tab, and the parameters as shown below:

It is always a good idea to think about the characteristic statemachine

settings first, before implementing the control behavior.

Designing with FPGA Advantage 3-51

November 2003
Finite State Machine Basics

o Select the Signals Status tab, and set the parameters as shown below:

Note the different output status settings and try to figure out why which
value was choosen. Be sure to use double quotes when entering the
reset values for the vector signals.

• Part 3: Implement the BCDRegControl counting functionality

o Implement the BCDRegControl as shown in the following diagrams:

3-52 Designing with FPGA Advantage

November 2003
Finite State Machine Basics

Top level diagram:

• Hint: Start State is “Wait State”.

Designing with FPGA Advantage 3-53

November 2003
Finite State Machine Basics

CountOnes sub-level diagram:

CountTens sub-level diagram:

• Hint: You can copy the 3 states from CountOnes sub-diagram and
paste them to the CountTens sub-diagram, then change only the
names.

3-54 Designing with FPGA Advantage

November 2003
Finite State Machine Basics

o Save the design. What changes do you see to the design structure in the
Design Browser?

• Part 4: Generate HDL for your design

o Select the BCDRegControl in the Design Browser.

o Select the pulldown menu item Tasks > Generate > Run Single

o What happens in the HDL Files view window of the Design Explorer?

o Double-click on the HDL file you just created to see the generated
code.
Use the left navigation pane of the DesignPad editor to view the
structure of the VHDL file. For example select the clocked process and
see the whole process displayed and highlighted at the main editor
window.

• Part 5: Repeat Part 4 for the BCDRegister design.

Designing with FPGA Advantage 3-55

November 2003
Finite State Machine Basics

3-56 Designing with FPGA Advantage

November 2003
Module 4
Interactive Testing Basics

Objectives
This module will cover the following topics:

• Testing Methodology
• Data Preparation
• HDL Generation
• Simulation Data Compilation
• Invoking the Simulation Flow
• Interactive Simulation
• Simulation Windows
• Running the Simulator
• Creating Stimulus
• Troubleshooting
• Reusing Stimulus

Designing with FPGA Advantage 4-1

November 2003
Interactive Testing Basics

Testing Methodology

Testing Methodology
♦ Interactive Testing
! Easy to find mistakes in smaller portion of design
! See inside “black box” of a larger design
! Testing testbenches

♦ Testbenches
! Static, formalized tests

! Test entire design in a single pass

– provide input stimuli
– observe output behavior
– report violations
! Compare synthesized results with original results
– can be done automatically with Waveform Compare
! Use Code Coverage to determine the percentage of tested code

Notes:

4-2 Designing with FPGA Advantage

November 2003
Interactive Testing Basics

Simulation Process

Simulation Process
♦ Edit, and Save Design Unit Edit Design
Unit
♦ Generate HDL for graphical views
! Syntax check
♦ Compile Simulator Data from HDL Generate HDL
for graphical views
♦ Invoke Simulator
♦ Provide Stimulus
Compile HDL
! Interactive
! Stimulus File
♦ Monitor Results Invoke Simulator
♦ Troubleshoot
Simulation Flow
♦ Modify Design and Reiterate

Troubleshoot

Notes:

Designing with FPGA Advantage 4-3

November 2003
Interactive Testing Basics

Invoking Simulation

Invoking Simulation
♦ Select Design Unit in Design
Browser:
! Toolbar: Simulator Flow
! Pulldown menu
Tasks > ModelSim Flow > Run...
♦ Select Design Unit in Edit
Window:
! Pulldown: Simulation > Start
Simulator…
! Toolbar: Simulator Flow

Notes:

4-4 Designing with FPGA Advantage

November 2003
Interactive Testing Basics

ModelSim Windows

Notes:

Designing with FPGA Advantage 4-5

November 2003
Interactive Testing Basics

Step Commands
♦ Step
! Move forward one line in HDL code
♦ Step -Over
! Same as Step
! Treats procedures as one line

♦ Continue
! Continues execution of previous
Run command

Notes:

4-14 Designing with FPGA Advantage

November 2003
Interactive Testing Basics

Restarting the Simulator

♦ Restart
! Restarts simulation, set Simulator time to Zero
! Clears waveform memory / file
! Clears forces
! Dialog allows keeping elements
– Preserve List, Wave Display Formats
– Breakpoints
– Logged Signals
– Virtual Definitions

Notes:

Designing with FPGA Advantage 4-15

November 2003
Interactive Testing Basics

Interactive Stimulus

Interactive Stimulus
♦ User provides all external
stimulus
♦ Can be saved as a “dofile” for
future runs
♦ Tip: use aliases
! e.g. “alias f force”
! e.g. “alias r2 run 200”

♦ Step through HDL

! Select Design Unit in Structure
Window
! Console Pulldown: View > Source
! Use Step icons in Source Toolbar
! Blue Arrow shows current step

♦ Find Next | Previous Transition

! Select Signal in Wave Window
! Toolbar: Find Transition
! Moves to next/previous transition
on selected signal

Notes:

Designing with FPGA Advantage 4-19

November 2003
Interactive Testing Basics

Using Line Breakpoints

♦ Interactive break
! Stops simulation run at current point
! Handy for “runaway” simulation
♦ Pre-set Line Breakpoints
! Open Source window
! Click in left margin near line number
! Red dot appears
! Simulation will always stop at this
line
! Remove by clicking on red dot
red circle remains to indicate that
there was a breakpoint
! May only be placed at executable
(green) lines
! Line Breakpoints are implemented using the “bp” command and can
be reported by issuing “bp” at the command prompt
4-20 • Designing with FPGA Advantage: Interactive Testing Basics Copyright © 2003 Mentor Graphics Corporation

Notes:

4-20 Designing with FPGA Advantage

November 2003
Interactive Testing Basics

Using Signal Breakpoints

♦ Signal Breakpoint stops the Simulation when the specified
signal changes or gets a specific value
♦ Select Signal in Wave or Signals
Window: RMB > Insert Breakpoint
! Results in “Break on Signal Change”
♦ Set Signal Breakpoint condition
! Main Window > Tools > Breakpoints…
! Modify Breakpoint Condition
♦ Optionally set Breakpoint Commands
! Executed when Simulation suspended
due to Breakpoint condition
! e.g. force signal to specific value
♦ Signal Breakpoints are implemented using
the “when” command and can be reported
by issuing “when” at the command prompt

Notes:

Designing with FPGA Advantage 4-21

November 2003
Interactive Testing Basics

Troubleshooting Techniques

Troubleshooting Techniques
♦ Endless Loops:
! Use Break icon to stop simulation
! Look in Source window to see where problem occurs

OR
! Reload simulation

! Stop simulation just before problem point

Lab 4: Testing the BCD Register

♦ Lab Goal: Interactively test the BCD Register design unit you
created in previous labs

! Part 1: Preparing for Simulation

– Invoke the ModelSim simulator
– Prepare the simulation environment
– Reset the design and configure clocked signals
– Save the initialization steps in a macro

! Part 2: Test the Counter Functionality

! Part 3: Using Signal Breakpoints

! Part 4: Troubleshoot the Design

Notes:

Designing with FPGA Advantage 4-25

November 2003
Interactive Testing Basics

Lab 4: Testing the BCD Register

Introduction
In this lab, you will interactively prepare and test the BCD Register design you
created in earlier labs. If you have not completed Lab 3, your instructor can
provide you with a finished copy of the BCD Register design.

Directions
• Part 1: Preparing for Simulation
o Select the BCDRegister block diagram design in the Design Explorer’s
Design Unit view mode.

o Invoke ModelSim by clicking on the Simulation Flow toolbar

icon. Click “OK” at the “Start ModelSim” dialog box.

Note: If you have made any changes to this design since you last
saved, FPGA Advantage will ask you if you wish to save those
changes before generating HDL and invoking ModelSim.

o Once ModelSim has finished invoking, open the Source, Signal, and
Wave windows.

o Make sure that the “bcdregister” design unit is selected in the

ModelSim Structure window.

o You can drag one or multiple signals from the Signals to the Wave
window

4-26 Designing with FPGA Advantage

November 2003
Interactive Testing Basics

o Display and arrange the following signals in the Wave window:

Note: data_out, q_ones, and q_tens should be formatted as

hexadecimal literals, while everything else should be formatted as
binary logicals.

Tip: Use the Wave window pulldown menu item Insert > Divider to
group the signals.

Designing with FPGA Advantage 4-27

November 2003
Interactive Testing Basics

o Zoom out the Wave window so that approximately 2 us of wave data

can be seen.

o Set the Run Length variable to 100ns.

o To force Signals, select them in the

Signals window and use PullDown
menu Edit > Force for a single
stimulus or Edit > Clock for a
repeating stimulus. Define clk with
the following settings:

Tip: You can define any signal as a

clock if it needs to produce
repeating pulses during the
simulation.

o Force reset to ‘0’ and run the

simulation for 100 ns to reset the
design.

o Force reset to ‘1’ and run the

simulation for another 100ns. Make
sure the BCD Register is not
counting.

4-28 Designing with FPGA Advantage

November 2003
Interactive Testing Basics

o Define ripple_in as a clock with the following settings:

o Save the simulation setup as a dofile

Note: Use the *.* option for the filetype when saving the file, cause
otherwise the file will have a .TXT appended (instead of .DO).

Use the Console pulldown menu item File > Transcript > Save
Transcript As to save the transcript window to the file
BCDRegTestSetup.do. Select the folder “work” to store the file.

Use the Wave window pulldown menu item File > Save Format...
to save its formatting in the file wave_BCDReg.do.

• Part 2: Testing the “count” functionality

o Run the simulation for 100ns.

o Is there any activity on the data_out bus?

o Continue to run the simulation for 100ns chunks until you see the
data_out increment a few times. Notice how the various signals interact.

Designing with FPGA Advantage 4-29

November 2003
Interactive Testing Basics

o Increase the Run Length to 50us. Run the simulation until you see the
counter roll over to 00. Notice the behavior of ripple_out.

• Part 3: Use Signal Breakpoints

o Restart the Simulation using the Restart icon. Reset the default
Run Length to 100 ns from 50 us

o Get your saved initialization settings by using the Console pulldown

menu item Tools > Execute Macro..., then selecting the
BCDRegTestSetup.do file you saved earlier.

o Now you want to check the 09 to10 rollover. Therefore set a signal
breakpoint on the data_out signal by selecting the signal in the Signals
window and issue RMB > Insert Breakpoint.

o Run the simulation using the “run -all” command. The simulation
stops at the next change of data_out. If you hit the “Continue”
button, the simulator proceeds to the next change of data_out.

o Specify the Breakpoint condition: PD > Tools > Breakpoints Select

Breakpoint, click on “Modify” and specify the breakpoint condition.

4-30 Designing with FPGA Advantage

November 2003
Interactive Testing Basics

o Run the simulation again using the “Continue” command. The

simulator will stop when the data_out signal reaches the value 09.

• Part 4: Troubleshooting the design

o If the design didn’t work as planned, spend some time trying to fix the
problems. Be sure to note the problems you encountered and how you
went about debugging and fixing them. Your instructor will ask you to
discuss this with the class following this lab.

Once your design counts correctly, you have finished this lab.

Hint: Try formatting the data_out, q_ones and q_tens as decimal or

unsigned. What is the main difference between hexadecimal and decimal
formatting?

• When you have finished investigating the simulation, quit ModelSim.

Designing with FPGA Advantage 4-31

November 2003
Interactive Testing Basics

4-32 Designing with FPGA Advantage

November 2003
Module 5
Synthesis Basics

Objectives
This module will cover the following topics:

Notes:

5-4 Designing with FPGA Advantage

Precision Technology/Synthesis Options

♦ The default device technology, type, and global frequency can be

set in the Task window by selecting the flow and choosing
Settings from the pull-down menu

User-defined
synthesis
scripts

Post-synthesis
simulation netlist
format

Notes:

Designing with FPGA Advantage 5-7

November 2003
Synthesis Basics

Running Precision Synthesis

♦ Precision can be launched from the task menu or toolbar
after selecting the design in the design explorer
♦ Uncheck compile and synthesize in the Synthesis Settings if
you wish to import or set user constraints in Precision

Un-checking will simply launch

Precision and import the HDL
If not chosen, same
directory used every time.
5-8 • Designing with FPGA Advantage: Synthesis Basics Copyright © 2003 Mentor Graphics Corporation

Notes:

5-8 Designing with FPGA Advantage

November 2003
Synthesis Basics

Running Precision Synthesis (Cont.)

♦ The Precision synthesis flow will generate two files

in the downstream data directory used to setup the
Precision project: add_files.tcl and precision.tcl

Input File List

Results Folder

♦ The Design Bar synthesis steps can be executed from the Project Browser
through pop-up menus or double-clicking on objects
♦ The above is NOT a directory structure, but indicates the Project structure
only. The input files will have been read in from the HDS hdl directory.

Notes:

5-12 Designing with FPGA Advantage

November 2003
Synthesis Basics

Adding Input Files

♦ Mixed Language Support
! VHDL
! Verilog
! EDIF
! XDB
♦ Automatic Top-Level Design Detection

Notes:

Designing with FPGA Advantage 5-13

November 2003
Synthesis Basics

Compiling

Compiling
♦ Compile
! Analyze
! Elaborate
! Pre-Optimization
! FSM Detection / Extraction /
Optimization
! Modgen Detection / Extraction

♦ Done automatically if the

‘compile’ box is ticked in the
Precision Synthesis Settings
when invoking the flow.

Notes:

5-14 Designing with FPGA Advantage

November 2003
Synthesis Basics

Design Hierarchy Browser

Set clock constraint

Report clock frequency

♦ Display netlist hierarchy

♦ Set Constraints Set IO constraints
♦ Reference Schematics
Report_timing -from
♦ Generate Reports
Set fanout
Preserve_net
Assign to LOWSKEW

Don’t_touch
Preserve / Flatten hier

Notes:

Designing with FPGA Advantage 5-15

November 2003
Synthesis Basics

Synthesizing

Synthesizing
♦ Synthesize
! Compile
! Optimization
! Timing Optimization
! Output Netlist and Vendor
Constraints

♦ Done automatically if the

‘Synthesize’ box is ticked in
the Precision Synthesis
Settings when invoking the
flow.

Hierarchy Browser
Schematic View
♦ Allows viewing, constraint entry and reporting
♦ Displays RTL, Technology and Critical Path views

Notes:

5-20 Designing with FPGA Advantage

November 2003
Synthesis Basics

View Schematic

View Schematic
♦ Clear schematics using
accurate symbols
♦ Display contents of LUTs
! optional

Notes:

Designing with FPGA Advantage 5-21

November 2003
Synthesis Basics

Schematic Navigation with Strokes

Precision Timing Analysis

IDEAL
CLOCK Latency

Source
Clock
Setup Constraint
Prop. Delay (MAX)

Dest.
Clock
Prop. Delay (MIN)

DATA

Hold Constraint

♦ Based on timing engine from Mentor Graphics Velocity product

! ASIC golden signoff timing analysis
♦ Provides interactive timing analysis
! Users can issue commands to request particular timing paths
♦ Supports complex constraints and circuit conditions
! Multiple-clocks, clock propagation, Edge based constraints, latches

Notes:
The worst-case timing relationships that are used to determine timing violations
are shown in this slide. Notice that, for example, the latest source clock edge is
used to measure delays for setup, while the setup constraint is measured against
the earliest possible destination clock edge.

This diagram makes clear the distinction between clock latency and clock
uncertainty.

5-26 Designing with FPGA Advantage

November 2003
Synthesis Basics

Timing Report

♦ Timing report includes:

! Clock Frequency report
(shown above right)
! Critical path report
(shown on right)
! Timing summary report
(see next page)

November 2003
Synthesis Basics

Area Reports

Area Reports *******************************************************

Library: work Cell: uart View: INTERFACE

*******************************************************

***********************************************
Device Utilization for 2V40cs144
***********************************************
Resource Used Avail Utilization

Device Utilization Report

-----------------------------------------------
IOs 19 88 21.59%
Function Generators 58 512 11.33%
CLB Slices 36 256 14.06%
Dffs or Latches 71 776 9.15%
Block RAMs 0 4 0.00%
Block Multipliers 0 4 0.00%

-----------------------------------------------

Cell Library References Total Area

BUFG xcv2 2 x
BUFGP xcv2 2 x

Detailed Cell Report FD

FDC
xcv2 17 x
xcv2 1 x
1 17 Dffs or Latches
1 1 Dffs or Latches
FDE xcv2 24 x 1 24 Dffs or Latches
FDR xcv2 4 x 1 4 Dffs or Latches
FDRE xcv2 5 x 1 5 Dffs or Latches
FDS xcv2 12 x 1 12 Dffs or Latches
IBUF xcv2 3 x

Number of ports : 19
Number of nets : 167
Number of instances : 154
Number of references to this view : 0

Accumulated Totals Total accumulated area :

Number of Dffs or Latches : 71
Number of Function Generators : 58
Number of MUX CARRYs : 3
Number of MUXF5 : 1
Number of gates : 58
Number of accumulated instances : 154

Notes:

5-30 Designing with FPGA Advantage

November 2003
Synthesis Basics

Place and Route Encapsulation

♦ Place and Route Integrated for
Altera and Xilinx

♦ Place and Route Tools

Launched from Task Bar or
from Project Files Browser

♦ Integrated with Quartus II

♦ Integrated with Xilinx Design

Manager, FloorPlanner, and
Placement Viewer

Notes:

Designing with FPGA Advantage 5-31

November 2003
Synthesis Basics

Xilinx PnR Design Bar

Xilinx Implementation
Tools

Precision offers
Xilinx Analysis Tools
complete integration
to the ISE design
environment

Notes:

5-32 Designing with FPGA Advantage

November 2003
Synthesis Basics

Double-Click Launch of Analysis Tools

Precision Project Browser

Double-click will launch

Floorplanner on the final ncd file
from par

Double-click will launch Timing

Analyzer in the Trace timing report
for viewing

All other reports displayed in

Precision's text editor

Notes:

Designing with FPGA Advantage 5-33

Summary of Module

Summary of Module
We have been through an introduction to Synthesis using
Precision covering the following areas:
♦ Basic synthesis theory
♦ How to prepare a design for synthesis
♦ Precision Interface Basics, simple flow through to gate
level
♦ How to view the results. Design Creation/Management
! Text Reports
! Schematic Viewers HDL
Designer
♦ How to access vendor place Precision
and route tools Synthesis
ModelSim

Simulation Synthesis

Notes:

5-36 Designing with FPGA Advantage

November 2003
Synthesis Basics

Lab 5: Synthesizing the BCD Register

♦ Lab Goal: Synthesize the BCD Register using ‘push button’
flow.

! Part 1: Preparing the Design

! Part 2: Using Precision push button

! Part 3: Viewing the Results

! Part 4: Run Place and Route

Notes:

Designing with FPGA Advantage 5-37

November 2003
Synthesis Basics

Lab 5: Synthesizing the BCD Register

Introduction
In this lab, you will synthesize the BCD Register you created in earlier labs using
HDL Designers Quick Setup Flow Tab. You will browse the RTL and technology
schematics, try crossprobing and various synthesis settings.

Directions
• Part 1: Preparing the BCDRegister design for synthesis
o If an HDL Designer window is not open, open one and bring up a
Design Explorer window with XYZLib, as in earlier Lab exercises.

o Select the BCDRegister design in the Design Units pane of the Design
Explorer Window.

o Click on the toolbar icon Run Precision Synthesis Flow. Note the
actions listed in the Log Window.

o Set the Precision Synthesis Settings as shown below. Use the following
settings for the first synthesis run:

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Synthesis Basics

Note that the entire Precision Synthesis window is kept grey while it is
compiling and synthesizing. You can see how well it is doing by the
animation of the icons in the Design Bar on the left.

• Part2: Examine the synthesized design.

o View the pre-technology mapping design in the RTL Design Browser.

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Synthesis Basics

Click on the RTL Schematic in the Project Files panel.

Go to the Design Bar and click on Design Analysis at the bottom of

the bar, this opens up the Analysis options in the Design Bar. Now
click on the ‘View RTL Schematic’ icon in the Design Bar.

When the Design Browser comes up, you should see three blocks
and assorted nets connecting them. Each one of these blocks
corresponds with one of the components or blocks in your top level
BCDRegister design.

a. Single click in the Schematic Pane. Note that holding the cursor
over a block will display a popup with information on that object.

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b. Double-click on the largest of the blocks, which should be your

BCDRegController block. Double-clicking on the object will
open the underlying schematic view, if any.

c. Take a minute or two to view the BCDRegController logic. This

is a direct graphic representation of the HDL you created in an
earlier lab. Note that it is a multipage schematic, so you will need
to see it all you will need to look at the other pages. You can this
by using the Next Page and Previous Page arrows in the Design
Bar, or by using the ‘Strokes’ on the LMB.

d. You can view the source HDL for the BCDRegController logic
by selecting an instance and click RMB > Trace to HDL Source.

e. Return to the top level of the design by clicking on the

BCDRegister(struct_XRTL) line in the Design Hierarchy on
the left hand side of the Design Browser,

or RMB > Open Up,

or use the ‘Strokes’ command on the LMB. Then examine one of

the BCDRegister blocks.

f. When you are done viewing the design, go back to the Design
Centre by clicking on the Design Centre Tab at the bottom of the
Window.

o Now look at the technology schematic:

Double click on the Technology Schematic in the Project Files panel.

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Synthesis Basics

Go to the Design Bar and click on the ‘View Schematic’ icon in the
Design Analysis section of the Design Bar. (This is near the bottom
of the design Bar)

Since the design has been partially flattened during synthesis the
technology schematic has a completely different structure than the
RTL schematic. Not the whole design is displayed on the schematic
page.

The information about schematic page count is displayed at the

window title:

Navigate through the different schematics using the built-in “stroke”

functionality. Click LMB, drag to the right, release the LMB and the
schematic viewer will display the next schematic page. A stroke

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Synthesis Basics

drawn in the reverse direction will show the previous page.

Alternatively use the Previous Page and Next Page arrows in the
Design Bar on the left (circled above).

To display the whole design in a single schematic deselect the

“Multiple Page Schematic” option in the Schematic Viewer Popup
Window:

Precision has powerful abilities to explore the design, as an example use

tracing of nets and fragment viewing to extract information about the clock
tree in the design:

o Zoom into the leftmost region of the schematic to see the input pads.

o Select the cell named “BUFGP” (clock buffer), select “Trace

Forward > 1 Level” from the popup menu.

o Zoom out to see the whole schematic. Now every instance and net
which belongs to the clock tree is selected.

o Use the “View Trace” icon to display only the fragment of the design
which contains the actual selected items. In our example the clock tree.
First click on the highlighted net to select it, then click on the “View
Trace” icon.

Only the items selected will now be visible.

View Trace Unselect

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Synthesis Basics

o View the whole schematic again by reclicking the “View Trace” icon,
then use the “Unselect” icon to undo the selection. When you are done
viewing the design, close the schematic viewer window.

• Part 3: Viewing the results

o Open up the Design Analysis section of the Design bar and use
the analysis generated by the Report Area and the Report
Timing icons to answer the following questions:

What are the area (in Function Generators, or FGs) and delay
(in ns) results for this optimization?

How many flip-flops are required for this design?

Were there any critical path violations?

o Open the transcript window, by

using the menu option View >
Transcript Window.

o Find a warning (identified with

blue circles in the left margin).
Double-click on the dot to
display a source window showing the HDL associated with the
warning. Note the warning and whether or not you think it will
cause problems with your design. Close the source window
when you are done.

o Click on the Design Bar icon “View Critical Path”. How many
cells are in the longest path in your design?

o Close the schematic viewer.

o Exit Precision RTL Synthesis. Click the No button in the dialog box
asking if you would like to save the project.

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Module 6
Preparing for Testing

Objectives
This module will cover the following topics:

• Test Bench Elements

• Converting Blocks to Components
• Working with the Component Symbol Editor
• Creating a Test Bench Design
• Creating Test Bench Stimulus
• Creating and Opening a Flow Chart
• Flow Chart Design Objects
• Special Flow Chart Capabilities
• Using Concurrent Design Views
• A Test Bench Example

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Test Bench Elements

♦ Requirements for Test Bench
! Prepare design for inclusion in test bench
– Create/Open Library containing test bench design
– Convert design to component (if necessary)
– Edit top-level symbol (optional)

! Test bench design

– Block Diagram
• Design under test (component)
• Stimulus (block)

! Test bench stimulation

– Self-contained — no external stimulus necessary
– Checks design output against expected results
– May be HDL code, flowchart, or FSM

Notes:

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Why Use Components?

♦ Clearly defined interface
♦ Multiple instantiations of a single object
♦ Change to source object affects all instances
♦ Can belong to any library
♦ Easy to include in a testbench design
♦ Port names don’t need to match external signals

Notes:
Symbols are graphic representations of the interface of a device. Symbols show
the input and output ports and in some cases the input and output port types. They
are very useful for creating block diagrams of a system because they allow the
designer to visualize the interface as the designer is connecting signals and busses
to create the design. By having the symbol the designer knows exactly what
signals are needed to connect to the component to completely fill out its
connections.

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Preparing the Design: Components and

Blocks

Preparing the Design: Components and Blocks

♦ Component Designs
! “Unattached” design view always generates a component
symbol when saved
! Ready for placement in testbench
! May want to edit symbol

♦ Block Designs
! “Open Down” design view uses parent Block
! Usually part of larger design
! Block must have view to convert
! Convert to Component to include in testbench
! Don’t convert if testing “in-place”
! Conversion cannot be undone!
! Symbol based on Block graphics

Notes:
An "Unattached" design view is a design component which is "stand alone",
meaning nowhere instantiated. The automatically generated symbol for that
design view needs typically some graphical "fine tuning", e.g. resizing, moving
ports. This should be done prior to the first time the component is to be
instantiated.

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♦ Component Identifiers Symbol corresponds to Entity in VHDL
Library
!

! Design Unit

♦ Edit Package List

♦ Reposition Identifier Text
♦ Ports (from underlying block)
! Name
! Type
! Mode
– IN | OUT | INOUT | Buffer
♦ Reposition Ports Library
♦ Add/Remove Port Graphics Design Unit
! Inverter, Clock
♦ Resize Symbol Body
♦ Change Symbol Body Shape
6-8 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation

Notes:
The symbol editor looks very similar to other windows within HDL Designer. It
has similar menus and toolbars. When the symbol editor is invoked, a symbol
boundary is created. This boundary needs to be sized for the number of ports
required for the symbol. Keeping symbols as small as possible will allow more
functionality on a block diagram making it easier to follow the flow of the design.
After the boundary has been sized, add the input and output ports. Other port types
exists such as Inout and buffer for handling more complex IO.

Here you declare also also generics and parameters for components.

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Editing Identifiers and Text

♦ Component Identifiers
! Library
– Only saved to defined Library
! Renaming Design Unit
– From Symbol Editor
• Pulldown: File > Save As…
– From Design Explorer
• Pulldown | Popup: Edit > Rename
♦ Reposition Identifier Text
! Drag and Drop to move any text

! Hide text:
– Select text to hide
– Popup: Hide Text
! Restore all hidden text on symbol:
– Select symbol
– Popup: Show Text

Notes:

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Editing Symbol Ports

♦ Reposition Ports
! Drag and Drop
! Popup: Equidistant Ports

Notes:

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Editing Symbol Port Graphics

♦ Graphical information only
! Does not change functionality!
! Handy reminder when placing
components from a shared library

♦ Process:
! Select port(s) to modify
! Select port graphic type
– Popup: Clock | Not
! Types
– Clock > On adds Clock Designator
– Not > On adds Inverter Bubble
– (Clock | Not) > Off removes
selected bubble or clock symbol

Notes:

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Editing the Symbol Body

♦ Resize Symbol Body
! Drag and Drop

♦ Change Symbol Body Shape

! Popup: Autoshapes
! Choose pre-defined shape

Notes:

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Symbol Editor: Useful

[RMB] → Equidistant Ports

Will correct the port spacing automatically !

Notes:

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Symbol Editor: Custom Symbol

Diagram → Custom Symbol

You can customize the shape

inside the boundary

[RMB] → Custom Symbol

Notes:
Any graphical object must be totally enclosed by the boundary in order for it to be
part of the symbol.

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Symbol Editor: Custom Symbol (Cont.)

Line Rectangle
Polyline Ellipse
Arc Circle
Polygon

Bitmaps Add → Comment Graphics

Grouping
Order
Rotate
Flip
6-15 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation

Notes:

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Symbol Editor: Custom Symbol (Cont.)

[RMB] → Appearance...

Notes:

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Saving the Symbol

♦ Save
! Save under existing Library
and Design Unit
! Methods:
– Pulldown: Save
– Toolbar: Save

♦ Save As:
! Allows assignment to
different Library
! Allows new Design Unit,
View names

Notes:
Saving a symbol is similar to saving any of the other HDL Designer design units.
Specify the library, the design unit or cell name, and the view name. The default
view name is symbol.sb.

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Updating Component Symbols

♦ After Editing and Saving:
! Newly instantiated components reflect changes
! Previously instantiated components not changed
! Generate HDL marks error in Log Window
! Changes to Port Name/Type/Mode on symbol:
– Popup: Reconcile Interface
– Give symbol precedence
– May need to Update too
! Any changes to symbol:
– Popup: Update Symbol
– Symbol updated in place

Notes:

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Creating the Test Bench Design

♦ Block Diagram Elements
! Component under test
! Block containing Test Stimulus
! Signal Routing should be internal
! Stimulus block interface mirrors
component under text
♦ Test Stimulus
! May use flowchart, HDL, FSM
! Concurrent flowcharts allowed
– Example: Clock generator
! Generated HDL Stimulus isn’t
synthesized, so more flexibility
– Assertions
– Wait Statements
– Behavioral Code

Notes:

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Generating a Test Bench Design

♦ May be done automatically
♦ Process:
! In the design explorer select the
design unit to test
! Pulldown: File > New > Test
Bench…
! Specify Library into which the
testbench objects will be saved
! Test bench name (Block Diagram)
! Tester Block
– Creates Block with mirrored
DUT interface
– connects Tester Block
automatically with DUT
♦ Tester Block can be any view type
! e.g. HDL, Flowchart, State Machine

Notes:

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What is a Flow Chart?

♦ A Flow Chart consists of:
! A set of HDL instructions
! Flow Control
– Loops
– Case Statements
– Decision Boxes (IF-THEN-ELSE)

♦ Features
! Sequential execution
! Concurrent Flow Charts
! Styles
– Wait Statements
• Testbenches
– Sensitivity List
• Synthesis
! Styles cannot be mixed in a single Flow Chart!

Notes:

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Flow Chart Design Objects

♦ Action Box
! Flat
! Hierarchical
♦ Decision Box

♦ Wait Block

♦ Start/End Point

♦ Loop Start/End

♦ Case Box

♦ Flow Arrow
6-22 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation

Notes:

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Design Objects: Action and Decision

Boxes

Design Objects: Action and Decision Boxes

♦ Action Box
! Sequential statements
! Assignments
! Object ID (default => “ax”)

♦ Hierarchical Action Box

! Creates hierarchical flow chart
! Flow Chart within Flow Chart

♦ Condition Box
! Branches on value of condition
! Must branch forward in Flow Chart
! Object ID (default => “dx”)
! Swappable True/False assignment

Notes:
Here are the primitive elements for a flow chart and the operations that they
perform. At the top of the slide is the action box. The action box consists of a
number of sequential statements that perform some actions like signal assignment,
variable assignment, or maybe a subprogram call. All of the statements are
performed sequentially.

The hierarchical action box works similarly to the hierarchical state box in that it
creates a level of hierarchy below the hierarchical state which represents another
flow chart. Again this is useful to break up complex operations into smaller
manageable pieces to make them easier to understand.

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The condition box is used to branch control based on the result of a condition
expression. If the condition is true the true branch will be taken else the false
branch will be taken.

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Design Objects: Wait Boxes and Loops

♦ Wait Box
! Inserts wait conditions
! Wait for
– time, forever, until
– clock edge
– signal
! Object ID (default => “wx”)
♦ Start Loop Box
! Beginning of loop statement
! Contains loop expression
! Object ID (default => “Ix”)
♦ End Loop Box
! Delineates end of loop
! Only method of returning
flow “upstream”
6-24 • Designing with FPGA Advantage: Preparing for Testing Copyright © 2003 Mentor Graphics Corporation

Notes:
The wait box is used to suspend execution of the process until the wait box
condition has been satisfied. If the wait box has no condition then the wait
statement will wait forever. The syntax follows the wait syntax for VHDL
including a wait until expression, wait for time, and wait on signals.

The start loop and end loop boxes are used to surround a set of actions that will be
repeated. These actions will be repeated until the loop expression of the start loop
box is satisfied. The end loop box will mark the end of the loop.

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Design Objects: Start and End Points

♦ Start Point
! Designates entry into design view
or level of hierarchy
! Only one start point per concurrent
flow chart and level of hierarchy
allowed

♦ End Point
! Ends a flow chart
! May have multiple end points

Notes:
The start point is used to mark where process execution will start after the process
has finished and is starting again, or because a signal in the sensitivity list has had
a change in value.

The end point is used to mark the end of execution for a process.

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Design Objects: Case Boxes

♦ Case
! Automatically adds End Case
box
! Case expression
! Add “ports” for values
! Default port is “others”
! Object ID (default => “cx”)

♦ Multiple Case Boxes can be

nested but all branches of a
specific Case Box have to
meet in the same End Case
Box

Notes:
The case primitive is used to switch between a number of possible alternatives.
The decision box only switches between two alternatives but the case can switch
between a number of alternatives. The starting case primitive will have an
expression which will calculate a value. The case ports leaving the upper case box
will try to match the calculated values. If a match occurs that branch is taken. If no
match is found the others branch is taken. The value ports of the case statement
have to enumerate all possible values of the expression or an others port is
required.

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Flow Charts as Test Benches

♦ “Wait for time” statements
are not synthesizable

♦ ‘Wait for signal” statements

can replace sensitivity list

♦ When End Point reached,

execution loops back to
Start point
! Ex: clock signal generator

♦ Wait with no time will wait

forever
! Recommend: place at end of
testbench

Notes:
This flow chart shows the wait statement style. The process will start at the start
primitive and continue execution to the first action box where signal clk is
assigned 0. The process will stop at the wait statement and wait for 10
nanoseconds. After the time has elapsed the process will continue to the next
action box and assign clk to value 1. The process will then wait again at the next
wait box for 10 nanoseconds. After the wait the process will start again at the start
primitive. There is an implied loop for all processes. To execute a process once
and stop, use a wait statement with no time or condition. This is a wait forever.

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Flow Chart Object Properties Dialog Box

♦ Tabs for each Object type
! Actions
! Decisions
! Wait
! Loops
! Cases
! Comment Text

Notes:

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Flow Chart Generation Properties

♦ Suggested Settings
for Testbenches
! FlowChart
– Combinatorial
! Sensitivity List
– Auto
! Animation
– Instrument HDL
for animation

Notes:
Flow charts can generate sequential or combinational HDL code. Sequential flow
charts are clocked by a clock, while combinational flow charts are not. A
sequential flow chart will need to have a clock signal specified to clock the flow
chart and need to know which edge of the clock is active. A sequential flow chart
can also have a reset signal. The reset signal name must be specified along with
the value of the reset signal that is active.

The sensitivity list for the flow chart can be set automatically, or specified
directly. To animate the flow chart so that the designer can watch the flow chart
action boxes highlight as execution continues, select the instrument HDL for
animation box. This will create HDL code with the animation data added.

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Using Concurrent Design Views

♦ Some types of Design Views may have
concurrent elements
! Treated as a single View
! Executed simultaneously, cause implemented
in concurrent processes
! Processes may be renamed in specific
editor window

♦ Examples for using concurrency in Flow Charts

! Clock Generator
! Interrupt Processing
♦ State Machines can also use concurrency

Notes:
The flow chart editor also has the concept of concurrent flow charts much like the
concurrent state machines. The concurrent flow charts share the same port
interface, architecture declarations, architecture concurrent statements, and
package declarations. Each concurrent flow chart creates a new process statement
within the architecture. The process declarations and sensitivity lists for each flow
chart are the only items that are separate between the concurrent flow charts. Use
the Add, Open, and Delete Concurrent Flow Chart toolbar buttons to manipulate
concurrent flow charts.

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Concurrent Flow Chart Toolbar Icons

♦ Flow Chart Toolbar Icons:

! Add
– Adds new concurrent flow chart

! Open
– Opens flow chart
– Choose from drop-down menu

! Delete
– Deletes flow chart
– Choose from drop-down menu

Notes:
Here are the flow chart buttons to create, open, and delete concurrent flow charts.
The add button will create a new concurrent flow chart. The concurrent flow chart
will share all declarations except for process declarations and sensitivity list. The
open button will drop down a menu of the concurrent flow chart to open.
Concurrent flow charts are given unique labels for easy identification. The delete
button will delete a concurrent flow chart. This button also drops down a list of
concurrent flow charts. Select the concurrent flow chart to delete.

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A Test Bench Example

♦ All signals are internal
♦ Test stimulus block interface mirrors design under test

Notes:

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Preparing for Testing

Lab 6: Preparing a Test Bench

♦ Lab Goal: Create a test bench for the BCD Register design

! Part 1: Editing the BCDRegister symbol

! Part 2: Creating the test bench

! Part 3: Creating a flow chart to provide test stimulus

! Part 4: Checking and saving the test bench

Notes:

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Lab 6: Preparing a Test Bench

Introduction
In this lab, you will create a test bench for the BCD Register design you created
in earlier labs. If you have not finished the BCD Register design, your instructor
can provide you with a finished version upon request.

Note that you will receive less “hand-holding” as the labs progress. Consult your
instructor if you have questions about how to proceed.
For implementing the test bench functionality you can use some VHDL
templates from the $FPGADV_LABS/Lab_templates directory (you will be
given hints when this applies).

Directions
• Part 1: Edit the BCDRegister component symbol
o Edit the symbol so that:

Symbol body text is easily read.

The symbol body is a practical size.

Pins are evenly and adequately spaced.

The clk and reset signals have the

appropriate symbols.

o Ports display signal names but not signal types. Therefore click at the
Design Manager PD menu: Options > Master Preferences >
Symbol..., choose Miscellaneous Tab and click on VHDL Port
Display and make the necessary changes. Then switch to the Symbol
Editor and update your Diagram Preferences using the PD menu:
Options > Master Preferences > Apply to New and existing Objects.

o Save the symbol when you have finished.

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• Part 2: Create a test bench for the BCDRegister

o In the Design Explorer, select the BCDRegister design.

o Select the pulldown menu item File > New > Test Bench...

o Configure the dialog box as shown below:

Change

o OK the dialog box.

o Open the BCDRegister_tb block diagram in the MyTestLib library.

o Optionally, you may reorganize the BCDRegister_tb block diagram to

suit your taste.

• Part 3: Create a flow chart to provide stimulus for the test bench
o Double-click the BCDRegister_tester block to open the Open Down
Create New View dialog box. Select a view type of Flow Chart. Click
Next, then Finish to close the dialog. A Flow Chart editor window will
appear.

o Rename the Flowchart Process to “Tester” using PD: Diagram >

Rename Flow Chart

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o Implement a flow chart to test your BCDRegister design. Use the

following diagrams as a guide.

• Test the reset functionality:

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Preparing for Testing

• Report on the results of the test:

Hint: Include the text from the template file test_clear1.txt

• Prepare to test the increment function:

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• Increment the counter and check the results:

Hint: Include the text from the templatefile increment_test.txt

• The above test routine uses a function to convert the internal decimal
counter value into a BCD counter value. This function needs to be
declared “somewhere”. Add the function incbcd_count to the
Process Declarations by opening the “Flowchart Properties” dialog
and select the “Process Declarations” tab:

Hint: Include function text from the file function_incbcd_count.txt

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• Close the loop and end the test bench:

o Open the “Flowchart Properties” dialog, select the “Generation” tab

and check the ‘Instrument HDL for animation’ box. This will allow
this flow chart to be animated during simulation.

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o The testbench should also generate a clock signal to drive the

BCDRegister. Open a concurrent flow chart using the “PD: Add >
Concurrent Flow Chart” menu entry. Implement a clock generator
running at 20 MHz in the newly opened concurrent flow chart, using
the following diagram as a guide:

• Part 4: Declare the Constant

clk_prd in the Flow Chart
Properties Dialog box:

• To animate this clock process, go

to the “Generation” tab and turn
on animation, as before.

• Part 5: Save the BCDReg_tb design and generate HDL

o Save the BCDRegister_tester design.

Generate HDL for the BCDRegister_tb design to ensure that it is

syntactically correct. Was HDL also generated for the BCDRegister_tester
design as well?

If HDL was not generated for the BCDRegister_tester, identify why, and
then generate it.

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Module 7
Advanced Troubleshooting

Objectives
This module will cover the following topics:

• Graphical Troubleshooting
• Controlling Simulation from the Design Context
• Simulation Execution
• Breakpoints
• Using Animation
• Using Crossprobes

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Advanced Troubleshooting

Troubleshooting Designs Graphically

♦ Traditional Approach — Debug HDL
models
! Examine code
! Step through simulation line-by-line
! Which of multiple instances is visible?
! Hard to debug flow-oriented designs
♦ Solution
! Debug concepts, not code
! Run Simulator in Design context
! Tools:
– State Machine animation
– Flow Chart animation
– Block Diagram probing
– Simulation Execution
– Breakpoints
– Simulation replay

Notes:

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Advanced Troubleshooting

Simulation Toolbar

Simulation Toolbar
♦ When the Simulator is invoked from within HDL Designer,
additional simulation toolbars are added at the bottom of the
HDL Designer editor diagrams
♦ Block Diagram Editor Window Toolbar
Execution Breakpoints Signal Display Probes Instance
& Information Selection

♦ Flow Chart Window Simulation Toolbar Linking

Execution Breakpoints Animation Windows

♦ State Machine Windows Simulation Toolbar

Signal Display Linking
Execution Breakpoints & Information Animation Windows

Notes:

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Advanced Troubleshooting

Assigning Signals to Simulation

Windows

Assigning Signals to Simulation Windows

♦ Adds or removes selected signals to Simulation Wave and
List windows

Notes:

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Advanced Troubleshooting

Signal Information

Signal Information
♦ Signal Info
! Possible values for signal
! Current value of signal
! Driving signals and design units

♦ Highlight Object
! Highlights selected signal in Simulator
– Structure, Source, Signals, List, Wave

Notes:

Designing with FPGA Advantage 7-5

November 2003
Advanced Troubleshooting

Simulation Execution

Simulation Execution
♦ Simulation execution similar to ModelSim icons

♦ Run for Time allows choice of several presets

! Initial choices: run 100, run 200, run 300, run 400
! “Choose” item allows any time increment
! Last selected Time moves to top of list
– Includes “Choose” specified times

Notes:

7-6 Designing with FPGA Advantage

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Advanced Troubleshooting

Preparing the Design for Animation

♦ Enabling Animation
! State Machine | Flow Chart Object Properties:
– Instrument HDL for Animation enabled
– Must set in every design view to be animated
• Child views are set with parent

♦ Tradeoffs
! Animation Enabled
– Simulator Overhead
– Can use Animation at any time
– Extra animation code can be “stepped over” in
simulator Source window
! Animation Disabled
– Slightly faster Simulation
– Disable in debugged designs

Notes:
When the HDL code is set up for animation there is additional information added
which "tells" ModelSim what happens next in the state diagram or flow chart.
Example Code:

-- pragma synthesis_off
hds_next <= 1;
-- pragma synthesis_on

The synthesis pragmas prevent the synthesis tools from implementing the code as
hardware. They simply ignore it.

Designing with FPGA Advantage 7-7

November 2003
Advanced Troubleshooting

Assigning State Variable to Simulation

Windows

Assigning State Variable to Simulation Windows

♦ Adds or removes the State Variable signal to both the
Simulation Wave and List windows

Notes:

7-8 Designing with FPGA Advantage

November 2003
Advanced Troubleshooting

Using Animation

Using Animation
♦ Graphical representation of
state/flow activity
♦ May display several design
units, levels of hierarchy
♦ Tracking control
! Stop/start simulation
– for time
– until event
– forever
! Step backwards/forwards
through simulation results
! Breakpoints
! Track cause of signal state
! Step over objects
! Trail length

Notes:

Designing with FPGA Advantage 7-9

November 2003
Advanced Troubleshooting

Tracking State Changes

♦ Track by color:
! Red — Current state or
last transition followed
! Yellow — Previous state or
transition followed
! Blue — Previously visited
states or transitions
! Green —
– Transitions evaluated but
not followed
– Not used with actions on
transitions

Notes:

7-10 Designing with FPGA Advantage

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Advanced Troubleshooting

Enabling Animation

Enabling Animation
♦ May turn animation on/off
during simulation
! Enabled on a design unit-by-
design unit basis
! All concurrent and hierarchical
elements within a design unit
enabled together
! Pulldown: Animation > Global
Capture On | Off
♦ Data Capture
♦ Clear Captured Events
♦ Show Animation
! Automatically enabled when
Data Capture enabled

Notes:
In order to animate a flow chart, the flow chart must have been generated with the
Instrument HDL for Animation option enabled in the Generation tab of the
Flow Chart Properties dialog box.

In order to fully animate a state diagram, the state machine must have been
generated with the Instrument HDL for Animation option enabled in the
Generation tab of the State Machine Properties dialog box. If this option was not
enabled, the animation will show changes of state but full animation (for example,
transitions taken and moving by clock cycle) is not available.

You can enable animation for all instances in the current simulation hierarchy by
choosing Global Capture On from the Animation menu (or from the Animation

Designing with FPGA Advantage 7-11

November 2003
Advanced Troubleshooting

cascade of the Options menu in the design manager). An animation view is

automatically shown for any state diagrams or flow charts which are opened after
this option has been set.

7-12 Designing with FPGA Advantage

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Advanced Troubleshooting

Linking Design Windows

♦ Linked windows allow simulation control to affect all animated
design views
♦ Step/Move commands in one diagram show the
corresponding movements in all linked diagrams

Notes:

Designing with FPGA Advantage 7-13

November 2003
Advanced Troubleshooting

Cause: Flow Chart / State Machine —

Wave Window

Cause: Flow Chart / State Machine — Wave Window

♦ The cause button “synchronizes” the
displayed time frame in all open
windows
♦ Example 1:
! Place the cursor in Wave window
at a specific time
! Click on cause
! The State Diagram shows the
current state
♦ Example 2:
! Step through the states in the Enable/Disable
cursor tracking
State Diagram Cause
! Click on cause
! The Wave window displays the
cursor at the time frame where the
selected state was reached
♦ Can enable/disable automatic
tracking of cursor

Notes:

7-14 Designing with FPGA Advantage

November 2003
Advanced Troubleshooting

Breakpoints

Breakpoints
♦ Select breakpoints graphically
♦ Breakpoints work exactly as in simulator Source window
♦ Icons:
! Set Breakpoint — selected
! Delete Breakpoint — selected
! Delete All Breakpoints — in selected or in design
! Disable Breakpoints
– Does not delete existing breakpoints
! Enable Breakpoints
♦ Report Breakpoints:
! Pulldown: Simulation > Breakpoints > Report

Notes:

Designing with FPGA Advantage 7-15

November 2003
Advanced Troubleshooting

Breakpoints in State Machines

♦ States
! Process:
– Select state
– Click Add Breakpoint icon
– Red dot appears next to state
! Break when state in question is set as next state

♦ Transitions
! Process:
– Select Transition
– Click Add Breakpoint icon
– Red dot appears next to transition AND next state
! Break at transition
– When breakpointing on a transition
that comes from a hierarchical state
the breakpoint is shown in lower level diagram

Notes:
Breakpoints can be added to any object which corresponds to a executable line in
the generated HDL. If you select an object which has no corresponding executable
HDL code, you are prompted to select another object.

Breakpoints added to a HDL line in the ModelSim Source window are

automatically added to the corresponding source object in the graphical view. Line
breakpoints may be corrected by up to ten lines if the selected object does not
correspond to an executable line in the simulator.

If you set a breakpoint on a state name, HDL line breakpoints are added to all
transitions which set the state as the next state. For a hierarchical state machine,

7-16 Designing with FPGA Advantage

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Advanced Troubleshooting

these transitions may be in another state diagram but will be shown when
that diagram is displayed.

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November 2003
Advanced Troubleshooting

Breakpoints in Flow Charts

♦ Action Box
! Breaks simulation when process
entered but before executing
statements

♦ Decision Box
! Breaks simulation before
condition evaluated

♦ Wait Box
! Breaks simulation before wait
statement executed

Notes:

7-18 Designing with FPGA Advantage

November 2003
Advanced Troubleshooting

Activity Trails

Activity Trails
♦ Too many “Previous” states!
! Which state triggered when?
! Activity Trails Settings:
– Pulldown: Animation >
Activity Trails…
– Toolbar: Activity Trails

♦ Sets animation tracking depth

! Choose depth
– From start
– From Time
– Fixed number of “Blue”
states
– No Tracking
! Mark Conditions

Notes:
The current and previous steps (for a flow chart animation) or the current and
previous states plus the last transition (for a state machine animation) are normally
highlighted in the animation view.

The activity trail allows you to control how much additional animation activity is
displayed. If you are using ModelSim, you can specify the maximum number of
simulation events captured for each diagram during an animation run. When this
limit is exceeded, old events are discarded to reduce the total amount of stored
data. For a state machine, you can also choose whether to capture data about
evaluated conditions or active clock edges. If all the capture options are unset, no
data is saved, however, the animation is updated with the latest simulation data
when the simulator stops.

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November 2003
Advanced Troubleshooting

For a state machine, you can also choose whether conditions evaluated to be true
but not followed are highlighted in the activity trail. This may occur if a condition
is evaluated to be true but reverts to false before the next clock edge which would
cause the transition to be completed.

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Advanced Troubleshooting

Reviewing Animation History

♦ May “step” through states visited in
simulation
! Step by States — change to new state
! Step by Event — active transition
! Step by Clock — next clock pulse
♦ Controls:
! Step forward/backward

! Step Mode
– Icon changes to match mode
– State Machines only
! Step to specific time

November 2003
Advanced Troubleshooting

Process Window

Process Window
♦ Displays process activity
! Same as initial and always blocks in Verilog
♦ Possible states:
! Ready — scheduled to execute
! Wait — waiting for an event or time
! Done — no further scheduling
– wait forever
– initial block
♦ Execution order control
! Select a “Ready” process
! Process executed next

Notes:

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November 2003
Advanced Troubleshooting

Variables Window

Variables Window
♦ Similar to Signals Window
♦ Displays process variables
! Choose process in Process Window
! Variables appear in Variable Window
♦ May drag variables to Wave and List Windows

♦ Includes Generics and Constants

♦ May change value of variable

! Similar to forcing signals

♦ Parentheses show values of

vector signals

Notes:

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Advanced Troubleshooting

Dataflow Window

♦ Dataflow view:
! Which processes drive
which signals?
! Who affects a special datapath
♦ Tracing Signals
! Driving processes on left
! Reading processes on right
! Find source of unknown ‘X’
♦ Tracing Processes
! Input signals on left
! Output Signals on right
♦ Embedded wave window (optional) shows related waveforms
♦ Other useful information:
! small dot at signal name shows trigger status (sensitivity list)
! shows hierarchy boundaries
7-26 • Designing with FPGA Advantage: Advanced Troubleshooting Copyright © 2003 Mentor Graphics Corporation

Notes:

Designing with FPGA Advantage 7-29

November 2003
Advanced Troubleshooting

drivers, readers or both

! Trace cursor to selected

inputs previous event

! Trace to driver of selected

unknown ‘X’ signal

! Clear Dataflow Window

Notes:

Designing with FPGA Advantage 7-33

November 2003
Advanced Troubleshooting

List Window

List Window
♦ Tabular version of Wave Window
! Change in any variable or signal = new status line

♦ Drag signals and variables from windows

Notes:

7-34 Designing with FPGA Advantage

November 2003
Advanced Troubleshooting

Lab 7: Troubleshooting the BCD

Lab 7: Troubleshooting the BCD Register Test Bench

♦ Lab Goal: Test and troubleshoot the BCD Register design and
the test bench you created in the previous lab.

! Part 1: Setting up the ModelSim Environment

! Part 2: Running and Debugging the BCDRegister design using

the BCDRegister_tb design

! Part 3: Using Animation, Breakpoints and Crossprobing as

enhanced troubleshooting features

Notes:

Designing with FPGA Advantage 7-35

November 2003
Advanced Troubleshooting

Lab 7: Advanced Debugging

This lab contains three exercises.

1. The first one demonstrates the graphical troubleshooting techniques, that

come with HDL Designer and ModelSim.

2. The second shows how to use Text I/O from within a graphical testbench to
read stimuli from a textfile.

3. The third one shows howto write ModelSim assert messages to a file, which
is extremely useful when running log simulations.

Troubleshooting the BCD Register Test Bench

Introduction

In this lab, you will test and troubleshoot the BCD Register test bench you
created in an earlier lab using HDL Designer editor windows to control
simulation. If you have not completed Lab 6, your instructor can provide you with
a finished copy of the BCD Register design and it’s testbench.

Directions

• Part 1: Setting up the ModelSim environment

o Make sure you have enabled Instrument HDL for Animation in the
BCDRegister_tester and in the BCDReg_control design.

o Select and open the BCDRegister_tb Block Diagram in the Design

Explorer. Be sure to open all flow charts in the design.

o Run the simulation flow by clicking on the ModelSim Flow button in

the Block Diagram to invoke ModelSim.

o Once ModelSim has invoked, bring the editor windows for the
BCDRegister_tb design to the front. Add all signals in the Block

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Advanced Troubleshooting

Diagram to the ModelSim wave window: Select all signals and click the
Add Wave button.

• Part 2: Running and Debugging the BCDRegister_tester testbench and the

BCDRegister_tb design.

o Open the Flowchart diagrams and the State diagrams, arrange them and
the ModelSim wave window on the screen.

o Enable Animation, Activity Trails, and link the design windows.

o Run the Simulation from within HDL Designer using the Simulation
Control Buttons.

o Using Animation and Crossprobing, test and debug your test bench
stimulus design. You will also want to use the Wave window from the
ModelSim environment to view the stimulus in its entirety.

o Tip: If you make changes to the design, you will not be able to edit
while Animation is enabled. You may turn off Animation, make your
edits, save, reload the design, then enable Animation and continue
testing.

o Use also the possibility to travel in the past of the

simulation by using the “VCR”-like controls of
the diagrams. Use the Cause button to
synchronize the diagrams with the wave window.

o If you encountered problems, troubleshoot the design and/or the test

bench as necessary.

Designing with FPGA Advantage 7-37

November 2003
Advanced Troubleshooting

• Part 3: Controlling simulation execution using breakpoints.

o If you happened to be a lucky or even perfect designer with no
bug in the design, assume that the rollover from 09 to 10 does not
work. To locate the behavior set a breakpoint in the statemachine
on the transition to “Count_Tens”. Hint: The breakpoint is not
shown at the top level statediagram since the related state is
hierarchical. Open the “Count_Ones” sub diagram and locate the
breakpoint. Reset your simulation and issue the “Run forever”
command. When the simulation stops at the breakpoint the
source window is opened showing the actual line of HDL code.

o Repeat adding breakpoints to different objects, such as transitions,

states, conditions. Try also setting breakpoints to different objects in the
flow chart. After setting a breakpoint you can continue the simulation
using the “Run forever” or “Continue” button.

o Disable and enable Breakpoints temporarily by clicking on the red dot

in the ModelSim source window or by using the “Disable Breakpoints”
button in the HDL Designer diagrams:.

• Part 4: Navigating through the simulation past.

o Assume that the behavior of the BCDRegister would be wrong. Again
we assume that the rollover from 09 to 10 doesn’t work. In the last
exercise you ran the simulation again to find the critical event, but that
can be very time consuming when dealing with large designs. FPGA
Advantage has a better solution to do that: Animation History.

o Locate the first rollover of signal data_out from 09 to 10

in the wave window. Set the cursor approx. 200ns before
the transition occurs. To synchronize the Statediagram
and Flowchart window to the same time event click on the
“Cause” button in the wave window.

7-38 Designing with FPGA Advantage

November 2003
Advanced Troubleshooting

The state diagram shows now the “count_Tens” state again white, cause
it has not been visited yet. Using the “Goto Next” Button to review the
simulation events state by state:

o Try the similar functionality in the Flowchart diagram.

When you are satisfied that your test bench correctly tests the BCDRegister
design, exit ModelSim and close your editor windows.

Graphical Testbench using Stimuli from a Text File

Introduction

When describing test benches in plain HDL or flow charts it is sometimes very
laborious to cover complex input patterns. Especially if they are produced by
another system, which isn’t part of the simulation.

The solution is the use of an ASCII file, which stores the input patterns at different
time stamps. The HDL testbench reads the stimuli from the file and applies it to
the Device Under Test (DUT). The file could have the following structure:

Table 7-1. Stimulifile

Time Input A Input B
100 0 0
250 1 1
300 1 0
500 1 1

Another advantage of this solution is that when the stimuli change you only have
to edit the ASCII file. You can run the simulation without recompiling the HDL

Designing with FPGA Advantage 7-39

November 2003
Advanced Troubleshooting

code. This would have been necessary if you changed the stimuli in the HDL
testbench code.

Directions

• Part 1: Create the Library Mappings and open the Library Text.
o Move to the “Project Manager” and add a new regular Library
Mapping named “Text”, use $FPGADV_LABS as root directory.

o Open the Library and browse through the three design units and try to
understand the design structure.

o Select the text_tb design unit and compile it:

1.) At the Task-Bar select the “Tasks” bar.

2.) Select the “Generate” task to generate the HDL for

all the design. (Ensure it is set to “Run through
components”)

2.) Select the “ModelSim Compile” task, then the whole design will be
compiled. (Ensure it is set for compile through components)

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Advanced Troubleshooting

o Open the text_tester design unit.

The stimuli file “in_out_vectors.txt” is declared without specifying a

path. It has to be placed in the ModelSim downstream data directory.

o Enable the Downstream Data window:

Designing with FPGA Advantage 7-41

November 2003
Advanced Troubleshooting

o Locate the file “in_out_vectors.txt” in

the ModelSim downstream data
directory. Open it in a text editor by
doubleclicking on the file label. The
first column contains the time stamp,
the second the input vector.

o Simulate the text_tb design and verify the correct behavior of the
output.

o Do not close ModelSim.

o Edit the file “in_out_vectors.txt”, i.e. append some lines with

additional test vectors. Save the file.

o Back in ModelSim: Restart the simulation and simulate again.

o Did the altered stimuli take effect? ____________________

Writing ModelSim Assert Messages to a File

Introduction

When running long simulations with countless assert messages it is sometimes

necessary to write them into a file. This file can be used for further processing to
filter out specific messages. A simple solution would be to save the transcript to a
file, but the transcript also contains lots of other “unwanted” information. There is
a simulator switch called “-assertfile filename“. Then ModelSim automatically
writes the asserts into the specified file. When using the -assertfile switch the
assert messages are not written to the transcript.

Directions

When invoking ModelSim directly from HDL Designer you may have missed up
to now the possibility to set additional compiler/simulation switches for
ModelSim. There is a option in HDL Designer’s “Tasks Bar” to define settings for
a certain task show the ModelSim compile/invocation dialog.

7-42 Designing with FPGA Advantage

November 2003
Advanced Troubleshooting

o Right click on the “ModelSim Simulate” task.

Choose “Setting” from the popup menu.

o At the “ModelSim Invoke Settings” dialog

click on the “Design” tab.

o Add the additional simulator argument

“-assertfile assert.txt” at the bottom of the
dialog as follows:

o Click “OK” to exit the dialog box.

o From now on ModelSim will write the assert

messages to the specified file.

o Start the simulation on the BCDRegister_tb

design unit, open the wave window and display all signals.

o Simulate the design using the “run -all” command.

o Observe the transcript window.

Do you see any assert messages? _________

o The file containing the assert messages is located in the ModelSim

downstream data directory. This is the default location when no
pathname is specified.

o Open the file in HDL Design Browser by doubleclicking on its label in

the downstream data directory.

Designing with FPGA Advantage 7-43

November 2003
Advanced Troubleshooting

If the file is not visible press the “F5” key to

refresh the window contents.

o View the file and note the syntax how the

assert messages are printed.

7-44 Designing with FPGA Advantage

November 2003
Module 8
Advanced Design Features

Objectives
This module will cover the following topics:

• BCD Register
• Current Status
• Improvements
• Using Generics and Parameters
• Adding HDL to State Machines and Flow Charts
• Declarations
• Statements
• Copying Design Units and Design Views

Designing with FPGA Advantage 8-1

November 2003
Advanced Design Features

BCD Register

BCD Register
♦ Implemented Functionality:
! Reset
! Increment
! Counter overflow at 100

♦ Needed Functionality:
! Load
– Illegal values reset to 00
! Variable Overflow Limit
– e.g.; 12
! Need external variable
! VHDL: Use Generic

Notes:

8-2 Designing with FPGA Advantage

November 2003
Advanced Design Features

Generics and Parameters

♦ What are Generics? Symbol
! Pass information into HDL models
! VHDL: Generics
! Assigned to blocks or symbols
(VHDL: Entity)

♦ Possible Uses:
! Multi-width objects
! Variable counters
! Delay modelling

Notes:
VHDL generics are a VHDL feature used to pass information to an instance of an
entity. Verilog parameters can be used in a similar way when you are using the
Verilog language. You can declare VHDL generics and Verilog parameters as
properties of a block or as properties of the symbol which defines the interface to
a component. The declarations are specified as a list of names, types (for VHDL)
and default values. The values can be entered as discrete values or using
expressions.

You can change the VHDL generic or Verilog parameter mapping for each
instantiated block or component on a block diagram or IBD view. For example,
you can specify a different value for each instance of a component or you can

Designing with FPGA Advantage 8-3

November 2003
Advanced Design Features

specify a variable value which is declared as a generic or parameter on a higher

level view.

8-4 Designing with FPGA Advantage

November 2003
Advanced Design Features

Differences in Adding Generics to

Blocks vs. Components

Differences in Adding Generics to Blocks vs. Components

♦ Block has only one instance
! Generic added directly to Block
shape in Block Diagram
! done in Block’s Object Properties
Form
♦ Component has multiple Instances
! Generic added to Symbol with default
value
! Symbols default value can be
changed on specific Instance in
Block Diagram (Generic Map)

Symbol

Notes:

Designing with FPGA Advantage 8-5

November 2003
Advanced Design Features

Adding Generics to a Symbol

♦ Process:
! Select the symbol
! Open the Object
Properties dialog box
! Select Generic
Declarations tab
! Define the Generic
– Name: Required
– Type: VHDL
– Value: Default, if desired
! Click the Add button
! Click OK or Apply

Notes:

8-6 Designing with FPGA Advantage

November 2003
Advanced Design Features

Editing Generics

Editing Generics
♦ Modify:
! Select Generic to modify
! Make changes in edit fields
! Click Modify to incorporate
changes
! Click OK or Apply

♦ Remove
! Select Generic to remove
! Click Remove
! Click OK or Apply

Notes:

Designing with FPGA Advantage 8-7

November 2003
Advanced Design Features

Generics in Design Views

♦ Appear as text attached to Component in Design View
♦ Default position set in Symbol Editor
♦ Position may be modified in Block Diagram
! Select Generic text, and drag to new location

Notes:

8-8 Designing with FPGA Advantage

November 2003
Advanced Design Features

Setting Generics for an Instantiated

Component

Setting Generics for an Instantiated Component

♦ Process:
! Open Object Properties Dialog for component
! Select Generics tab
! Select Generic to modify
! Enter new value
! Click OK or Apply

Notes:

Designing with FPGA Advantage 8-9

November 2003
Advanced Design Features

Adding Generics to a Block

♦ Process:
! Select the Block
! Open the Object
Properties dialog box
! Select Block tab -
Generic Decls
! Define the Generic
– Name: Required
– Type: VHDL
– Value: Default, if desired
! Click the Add button
! Click OK or Apply

Notes:

8-10 Designing with FPGA Advantage

November 2003
Advanced Design Features

Adding Generics to a Block (Cont.)

Generic declaration assigned to component

Generic Declaration Default value

Mapped value

The mapped value can be used to

change the generic declaration. For
example to pass values down through
the hierarchy.
8-10 • Designing with FPGA Advantage: Advanced Design Features Copyright © 2003 Mentor Graphics Corporation

Notes:

Designing with FPGA Advantage 8-11

November 2003
Advanced Design Features

Passing Generics/Parameters Through

Hierarchy

Passing Generics/Parameters Through Hierarchy

♦ Useful when a Parameter affects several design units
! Ex.: BCD Register Rollover Generic affects Design & Testbench
* => Generic declaration
Symbol # => Generic mapping
* x=100
Testbench

Symbol
* x=60 #
x=x Tester

BCD Register Rollover = x

Rollover = x

Counter

Controller Counter

Notes:
There are several ways to use Generics in a design, following as one example the
explanation of the above method to pass generic values through hierarchy:

At the top-level symbol BCDRegister_tb the generic x is declared with a value of

100. At the lower-level symbol BCDRegister the same generic x is declared with
a default value of 60, but the instantiated component BCDRegister does not use
this default value cause the actual value is mapped (x = x) from the parent symbol
BCDRegister_tb. That value is again passed down from BCDRegister to the
BCDRegControl block's generic Rollover, which therefore inherits the value 100
of the top-level symbol. The same mechanism applies to the Tester block.

8-12 Designing with FPGA Advantage

November 2003
Advanced Design Features

With that approach it is possible to have a consistent behavior of the Rollover

generic in the whole design: With a single change of the generic x at the top-level
symbol every Rollover occurrence at the lower-level blocks is updated.

Designing with FPGA Advantage 8-13

Adding HDL Text to Design Units: State Machines (Cont.)

User defined architecture

declarative section

Notes:

Designing with FPGA Advantage 8-17

November 2003
Advanced Design Features

Interface Based Design (IBD)

♦ Interface Based Design (IBD)

! Customer driven technology
! Solves interconnect creation problems
! Supports top down and bottom up design Synthesis
! Productive, text based capture Properties
! Clear, concise documentation
Components
IBD
IBDcomplements
complementsthetheblock
blockdiagram
diagram
approach
approach for designs withhigh
for designs with

Exam ple

Control

Function_one{A:B}

Other_Function

Monitor

Check{2:0}

Tim ing Model

Delay
high
connectivity
connectivity

clock I I I I I I CK 20
m yReq[2:0] O I{2:1} I[0] I[2:1] RC 5
config[2:0] O O I I[5:3] RC 3
Signals ack{A:C}
status{A:B}[7:0]
I
I
O{A:B}
O
O{C}
I[3:0] I{B}
I RC
RC
7
3
data{0:2}[15:0] O I{0:1} I[15:8] RC 9

Notes:
IBD will be extended with the ability to slice a design in smaller pieces allowing
the user to work only on his part of the design without carrying the whole design.
You'll be able to split a big table in smaller chunks or to merge small tables
together.

Note that the IBD approach is very efficient for bus-based designs. Be careful
while showing IBD because is some cases (like the UART) the block diagram is
much simpler than the table.

8-18 Designing with FPGA Advantage

November 2003
Advanced Design Features

Interface Based Design: Example

Example

Control

Function_one{A:B}

Other_Function

Monitor

Check{2:0}

Tim ing Model

Delay
clock I I I I I I CK 20
m yReq[2:0] O I{2:1} I[0] I[2:1] RC 5
config[2:0] O O I I[5:3] RC 3
ack{A:C} I O{A:B} O{C} I RC 7
status{A:B}[7:0] I O I[3:0] I{B} RC 3
data{0:2}[15:0] O I{0:1} I[15:8] RC 9

♦ A 6 line table for a full complex design !!!

♦ Code generation from IBD
♦ Block diagram generation from IBD
♦ Automatic IBD generation
! from a block diagram
! at import

Notes:

Designing with FPGA Advantage 8-19

November 2003
Advanced Design Features

IBD Editor: Overview

IBD Editor: Overview
♦ You can add the objects you want to connect together
Add External IP
! Block and component in the columns
! Signals in the rows
Add Component Add ModuleWare
♦ The components can also
be dragged & dropped from
another window
Add Embedded Block
Add Block
Add Frame
Add a Synthesis
Property

Add Port Map Expression

Add Signal

Add Bus
Add Net Slice

Notes:

8-20 Designing with FPGA Advantage

November 2003
Advanced Design Features

Truth Tables

Truth Tables
♦ Design Unit View
! Implemented as a spreadsheet
! Multiple inputs can affect
multiple outputs
♦ Useful for simple logic
! Larger Truth Tables better
implemented in HDL
♦ Features
! Conditionals
! Multiple lines per cell
! Default results
! HDL Generation control

Notes:

Designing with FPGA Advantage 8-21

November 2003
Advanced Design Features

Truth Table Elements

Input Signals Output Signals

Input Signal Output Signal

Values Values

8-24 Designing with FPGA Advantage

November 2003
Advanced Design Features

Truth Table Features

♦ Default Condition
! Row with no specified input values
! Used if no other rows evaluate TRUE
! Recommended — Prevents latches in
Synthesis

♦ Multiple Lines
! Cells default to single HDL
statement/value
! Affected cells appear “depressed”
! Useful for Additional
Conditions/Actions
! Process
– Select Cell
– Popup: Change To Multi-line | Change
To Single-line

Notes:

Designing with FPGA Advantage 8-25

November 2003
Advanced Design Features

More Truth Table Features

♦ Additional Conditions
! Allow use of internal signals or
variables
! Action must follow HDL syntax
! Useful for sampling internal
flags

Lab 8: Completing the BCD Register

♦ Lab Goal: Implement the variable count limit and load
functions in the BCD Register design created in previous labs

! Part 1: Add load and rollover functionality to the BCDRegister

design

! Part 2: Modify BCDRegister_tester to include both load and

rollover

! Part 3: Run the BCDRegister_tb test bench

! Part 4: Change the value of rollover generics in ModelSim and

test the new behavior

Notes:

8-38 Designing with FPGA Advantage

November 2003
Advanced Design Features

Lab 8: Completing the BCD Register

Introduction
In this lab, you will modify the BCD register you created in an earlier lab to
include load functionality. You will also add a generic to allow the register to “roll
over” to zero at an assigned value. Finally, you will modify the test bench you
created for the BCD Register in an earlier lab to test the new functionality.

You don’t have to modify the state diagram and the testbench on your own, you
just copy the complete design views from the Lab_Templates library. For a better
understanding the changes which were made in the views are documented below.

Directions
• Part 1: Add the ability to load an 8-bit value into the BCDRegister design.
o This functionality takes the data on the data_in bus and loads it into the
BCD Counters on a rising clock edge when the load_en signal is
asserted high. The most significant nibble is sent to the Tens counter,
and the least significant is sent to the Ones counter. If an illegal value is
loaded into a counter, that counter should rolling over to “0000”.
If both load_en and ripple_in are asserted simultaneously, the load
operation has precedence.

• Part 2: Add a generic, “rollover,” to your BCDRegister

o This functionality sets a roll-over value for the counter, between 0 and
99, via a generic. When the value is reached (or exceeded by an illegal
load operation) during incrementing, reset the BCD Register to “00”.
The default value for rollover should be 99.

• You don’t have to draw the state diagram on your own, just copy the
complete design view from the Lab_Templates library as described:
Open the Lab_Templates library, expand the contents and copy the
statemachine view fsm_complete to your BCDRegControl Design unit,
and set it the default view.

Designing with FPGA Advantage 8-39

November 2003
Advanced Design Features

o Open the completed state diagram and browse through the hierarchies,
take the top-level diagram shown on the following page as orientation.

• Top Level:

8-40 Designing with FPGA Advantage

November 2003
Advanced Design Features

• Part 3: Modify BCDRegister_tester to test the added functionality.

o You will need to use a generic (rollover) for the BCDRegister_tester
block. For this lab, you will set both values before running the test
bench.

o Tip: By giving the generic the same name for both blocks, you may
pass the generic down from the top level of the design and test for a
variety of values.

o The stimulus design should include the following tests:

reset

counting

correct roll-over operation

loading legal numbers

loading illegal numbers

correct counting after loading (including illegal values)

• You don’t have to modify the flowchart on your own, just copy the
complete design view from the Lab_Templates library:

o Open the Lab_Templates library, expand the contents and copy the
flowchart view lab9 to your BCDRegister_Tester Design unit, and set
it the default view.

o Open the completed flowchart, view the added test functionality and
browse through the hierarchies,

• Part 4: In Design Explorer select the BCDRegister_tb component and

generate Tasks > Generate > Run Through Components.

o Are there any errors? ____________________

o What is the reason? ____________________

Designing with FPGA Advantage 8-41

November 2003
Advanced Design Features

• Part 5: Add the generic rollover to the BCDRegControl and

BCDRegister_Tester blocks. For the first approach use the decimal value
99 which must be entered in BCD syntax as 1001 1001.

o Open the BCDRegister Block Diagram, select the BCDRegControl

Block and open the Object Properties dialog. At the Blocks tab click on
the Generic Declarations button and add the generic rollover as
shown below. Then save and close the diagram.

o Open the BCDRegister_tb Block Diagram, select the

BCDRegister_tester Block and add the generic rollover using the
same procedure like before.

8-42 Designing with FPGA Advantage

November 2003
Advanced Design Features

• Part 6: Run the completed BCDRegister_tb test bench.

Run the simulation to see if your design shows correct rollover and load
behavior. If not use animation and crossprobing to locate errors.

Use a rollover value of 59 in subsequent test runs. Notice that you have
to change both ocurrences of the rollover generic, at the
BCDRegControl and at the BCDRegister_Tester block.

o There are two ways to alter the value of generics, try both:

i. Reload the design and change the generic globally throughout the
design. Process:

Designing with FPGA Advantage 8-43

November 2003
Advanced Design Features

Load the design by selecting the “Simulate” button and the

BDCRegister_tb design will be reloaded with all rollover generics
substituted with the value you provided. Simulate the design to
check the rollover behavior.

ii. Alternatively change the value of the generic directly in ModelSim.

A generic in ModelSim is treated like a variable. Therefore you have
to select a process of the owning design unit to make it “visible”.
Process:

o In structure window select the design unit

o In process window make all processes visible: PD > View In Region

o In variables window change the rollover value: PD > Edit > Change

8-44 Designing with FPGA Advantage

November 2003
Advanced Design Features

o Repeat the procedure for the BCDRegControl generic.

o You are finished with this lab once you have verified correct operation
of the BCDRegister design.

Designing with FPGA Advantage 8-45

November 2003
Advanced Design Features

8-46 Designing with FPGA Advantage

November 2003
Module 9
Synthesis Constraints

Objectives
This module will cover the following topics:

• Setting Timing Constraints

• Debugging Critical Paths
• Using Report Delay
• Using Schematic Viewer
• How hierarchy is handled
• Using register retiming.

Designing with FPGA Advantage 9-1

November 2003
Synthesis Constraints

Timing Constraints

Timing Constraints
♦ Timing constraints effectively define the time budget within
which the optimized logic must produce a stable output
♦ Precision supports Synopsys Design Constraint (SDC) format
timing constraints
♦ SDC constraints be read and / or applied
! Allows Precision to read ASIC IP constraint files

♦ Timing constraints are used to find paths that don’t make

timing — Think of constraints as a filter that catch the paths
you need to fix
♦ Timing constraints are also used when running timing reports
♦ The most critical path is the path with the largest time deficit
with respect to the constraint it is being compared too
IT IS NOT THE LONGEST PATH
9-2 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation

Notes:

9-2 Designing with FPGA Advantage

November 2003
Synthesis Constraints

Four Types of Timing Paths

Input to output

D Q
Register to output

D Q
Input to Register

D Q D Q
Register to Register

Notes:

Designing with FPGA Advantage 9-3

November 2003
Synthesis Constraints

Port Constraints

Port Constraints
♦ 3 types of Port Constraints
! Clock
! Input Delay
! Output Delay
♦ Can only be set using the SDC commands

♦ We’ll look at each one of them individually

Notes:

9-4 Designing with FPGA Advantage

November 2003
Synthesis Constraints

Clock Constraints

clock period
(20)
create_clock clk1 -period 20
create_clock clk1 -period 20 clk1

offset
create_clock clk1 -period 10 -waveform {5 15} (5)
create_clock clk2 -period 20 -waveform {5 15} clk2

duty cycle
create_clock clk1 -period 10 -waveform {0 5} (75%)
create_clock clk3 -period 20 -waveform {0 5} clk3

create_clock clk1 -period 10 -waveform {5 20}

create_clock clk4 -period 20 -waveform (5 20} clk4

falling
edge

Create_clock <portname> -period val –waveform {edgelist} –domain name

Notes:

Designing with FPGA Advantage 9-5

November 2003
Synthesis Constraints

Multiple Clocks and Clock Domains

♦ If different clocks propagate to the source and destination
registers, constraints can still be checked if the clocks are
synchronous.
! Clocks can differ in phase — modeled as a latency adjustment.
! Clocks can differ in frequency, which requires the closest
approach of edges to be found and used for analysis.

♦ Clocks that are asynchronous are said to be in different clock

domains.
! Timing paths between registers controlled by clocks in different
domains are not analyzed.
! SDC (and Synopsys) do not support clock domains directly —
Precision has extended the standard to include this concept.

Notes:
Multiple clocks are quite common in today's circuit designs. Proper handling of
multiple clocks is a major improvement that CTE timing analysis brings over the
Leonardo timing engine. In the case of phase shifts between clocks of identical
frequency, this is largely a convenience of constraint nomenclature. The effect of
this phase shift can just as correctly be modeled as a latency between 2 real clocks
based on the same ideal clock as it can by two different ideal clocks.

For clocks of different frequency, it is necessary for the tool to find the clock
period where the clocks most closely approach each other. The timing report will
show the clock period where this occurs when reporting violations. For example,
worst case timing might be found at the 3rd rising edge of the source clock and the
6th rising edge of the destination clock. In general, the greatest common multiple

9-6 Designing with FPGA Advantage

November 2003
Synthesis Constraints

of the 2 clock periods will be used as the clock period for analysis. Clocks
without small integer common multiples are probably not related, and any paths
between these clocks are probably false.

Designing with FPGA Advantage 9-7

November 2003
Synthesis Constraints

Specifying Multiple Clocks

♦ Asynchronous clocks should be specified in different “clock domains”
♦ Use the “-domain” switch
♦ Automatically “false_paths” all paths between domains
Create_clock clk1 –period 20 –waveform {0 10} –domain domain1
Create_clock clk2 –period 20 –waveform {0 10} –domain domain2
D Q D Q

Clk1

D Q D Q

Clk2

♦ Synchronous clocks should be specified in the same “clock domains”

♦ Use the “-domain” switch
♦ The worst case timing relationship will be calculated between clocks
Create_clock clk1 –period 20 –waveform {0 10} –domain domain1
Create_clock clk2 –period 20 –waveform {0 10} –domain domain1

Notes:

9-8 Designing with FPGA Advantage

November 2003
Synthesis Constraints

The Clock Constraint Editor

♦ The clock constraint editor is built into the

hierarchy browser
♦ All internal and external clocks will be
displayed

Notes:

Designing with FPGA Advantage 9-9

November 2003
Synthesis Constraints

Clock Propagation

Muxed Clocks are not propagated during D

Q Q
D D
Q Q
D

timing analysis. Users must define the internal MUXED Clock

clock. Auto constraint generation will
Clk1
generate a constraint for muxed clocks. Clk2
Sel

Registered clocks are not propagated during

timing analysis Users must define the internal Q
D D
Q Q
D D
Q

clock. Auto constraint generation will create Registered Clock

an internal clock of of ½ the frequency
Clk1 D
Q Q
D

Gated clocks are not propagated from the

primary input ports. A single clock definition
is required to be defined on the output pin of Q
D D
Q Q
D D
Q
the gate. Auto constraint generation will create
Gated Clock
an internal clock.
Clk1
Sel

Notes:

9-10 Designing with FPGA Advantage

November 2003
Synthesis Constraints

Input Port Constraint

♦ Set as Input_delay
! Signal will “arrive” X ns after the rising clock edge
♦ Must specify a clock edge
! rising is default
Input delay
Inputisdelay
the indirect
is te indirect
constraint ononthethe
output Logic constrained to clock
constraint outputlogic
logic
of a “virtual” neighbour chip period - input delay
of a "vitual" neighbor chip

D Q 4 ns 6 ns D Q

10 ns
Clk

Virtual Chip Actual Chip

Create_clock clk –period 10

set_input_delay 4 load -clock clk

Notes:

Designing with FPGA Advantage 9-11

November 2003
Synthesis Constraints

Output Constraints

Output Constraints
♦ Set as output delay
! Signal time after the rising clock edge that the output signal must
be valid

output delay is an indirect

constraint on the input logic of
a "vitual" neighbor chip

out1
D Q 3 ns 7 ns D Q

Actual Chip Virtual Chip

Clk
Clock Period = 10 ns
Output Delay = 7 ns

create_clock clk –period 10

set_output_delay 7 out1 -clock clk

Notes:

9-12 Designing with FPGA Advantage

November 2003
Synthesis Constraints

Bi-Directional Constraints

Bi-Directional Constraints
♦ Must set both an input_delay and output_delay constraint
following the usual rules

2 constraints must
be set in IO ports

D Q 7 ns

Clk

En
Actual Chip

Create_clock clk –period 10

set_input_delay 3 none –clock clk
set_output_delay 7 none -clock clk

Notes:

Designing with FPGA Advantage 9-13

November 2003
Synthesis Constraints

Port Constraint Editor

♦ Port constraints applied to the design
hierarchy browser
♦ Must specify clock edge
♦ Editor allows easy application of a single
point path constraint

Notes:

9-14 Designing with FPGA Advantage

November 2003
Synthesis Constraints

False and Multi-cycle Paths

Set_false_path –from Reg_a/Q –to Reg_b/D

False Paths Due to external timing

♦ Use to “relax” timing constraints on conditions timing can be
specified logic relaxed on this logic

♦ Can be applied “to”, “from” or D Q 7 ns D Q

“through” any node in any combination

Clk Reg_A Reg_B

Multi-cycle Paths
♦ Use to “relax” timing constraints on Clk
specified logic
♦ Can be applied “to”, “from” or Data
“through” any pin or port
Data changes every other clock cycle
♦ Use “get_pins” to help locate pins (see Multi-cycle path : data not used until
second clock edge
next slide)

Set_multicycle_path –from Reg_a/Q –to Reg_b/D –value 2

set_multicycle_path -to [get_pins I2/reg_clk_cnt*/in] -value 2

Notes:

Designing with FPGA Advantage 9-15

November 2003
Synthesis Constraints

Get_… Object Typing Commands

get_clocks Defined IDEAL clocks.

get_ports Primary input and output ports.
get_cells Instance names of blocks or primitives.
get_pins Pins on instances.
get_nets Design interconnect.
get_libs A collection of library cells.
get_lib_cells A cell in a library.
get_lib_pins A pin on a library cell.

These commands imply the set of object types that SDC

recognizes and their relationship to each other.

Notes:
It is important to understand the meaning of these object types in SDC. Some of
the names are less than intuitive.

• Clocks are ideal clock names that have been defined earlier in SDC, not
ports that drive clock pins.

• Ports are top-level IOs. There is no facility to reference hierarchical ports.

• Cells are what practically everyone calls instances. What practically
everyone calls cells are called lib_cells in SDC.

• Pins exist on instances of library cells.

Constraining Combinatorial Logic

A_in 10 ns B_out

♦ Must create a “virtual clock” to value of specified delay

! Clock definition not assigned to a port
♦ Input and output constraints of 0 ns relative to this clock

Create_clock –name virtual_clock –period 10

Set_input_delay 0 a_in –clock virtual_clock
Set_output_delay 0 b_out –clock virtual_clock

Notes:

Designing with FPGA Advantage 9-21

November 2003
Synthesis Constraints

Reporting on Constraints

Reporting on Constraints
♦ “report_constraints” command will list all Constraints Report
applied constraints on the design

♦ Report_missing_constraints” will list all

unconstrained ports and clocks in the
design
! Analyses designs for missing components
! Finds blocked and internal clocks
! Finds unconstrained ports.
! Unconstrained ports and clocks are not analyzed

♦ Commands can be issued

from the “Analyze” design Missing Constraints Report
bar or the command line.

Notes:

9-22 Designing with FPGA Advantage

November 2003
Synthesis Constraints

Using Constraint Files

♦ Constraints
entered in GUI are
saved to a
constraint file

♦ Constraint files
can be edited, and
added to the input
file list

♦ Constraints files
can be
automatically
generated from the
information in the
‘Precision
Synthesis Setup
Dialog Box’ within
HDL Designer

Notes:
Constraint entry — I'm not sure if you're a big fan of the spreadsheet-based
constraint editors, but we find the dialogs to be much nicer. Especially when you
can use the dialogs to set constraints on an entire bus. In fact, you could right-
click on the outputs folder to select the output delay for all outputs of your design.

The top portion of the dialog is for setting input or output delay, relative to which
edge of which clock, or you could set a false or multi-cycle path. The bottom
portion is for choosing pad type, pin location, and forced IOB mapping.

You can even right click on schematic objects and set their constraints right from
the schematic. Why should you have to get out of the schematic viewer, open the

Designing with FPGA Advantage 9-23

November 2003
Synthesis Constraints

constraints editor, and hunt around for that net you want to constrain when it's
already there in front of you on the schematic?

You don't need to be an expert on the tool to use it.

It's very easy to get more information from various schematic views.

Of course, it's all about lowering the overall design risk.

9-24 Designing with FPGA Advantage

November 2003
Synthesis Constraints

Pop Quiz

♦ Specify the timing constraints for this design

6 C

D Q D Q
A 5 20 7 B

Clk

Notes:

Designing with FPGA Advantage 9-25

November 2003
Synthesis Constraints

Pop Quiz — Answer

6 C

D Q D Q
A 5 20 7 B

Clk

# Constrain Synchronous paths

Create_clock clk –period 20 –domain main
Set_input_delay a 15 –clock clk
Set_output_delay b 13 –clock clk

# Constrain A to C Asynchronous Path

Create_clock virtual_clock –period 11 –domain main
Set_input_delay a 0 –clock virtual_clock
Set_output_delay c 0 –clock virtual_clock

Notes:

9-26 Designing with FPGA Advantage

November 2003
Synthesis Constraints

IOB Mapping Port Constraints

♦ Ports can be constrained

from the design browser,
find window or schematic
viewer
♦ Constraint will override
automatic IO insertion

Notes:

Designing with FPGA Advantage 9-27

November 2003
Synthesis Constraints

Vendor Constraints — Related Clocks

Precision SDC Clock Constraint
create_clock wr_bar -period 100 –domain domain1
Create_clock clk –name –domain domain1

Precision Generated Xilinx NCF Constraint

NET "wr_bar" TNM_NET = "xmplr_wr_bar";
TIMESPEC "TS_clk_main" = PERIOD "xmplr_wr_bar" 100.000000 ns HIGH 50.000000 %;
NET "clk" TNM_NET = "xmplr_clk";
TIMESPEC "TS_clk_1" = PERIOD "xmplr_clk" TS_clk_main / 10 ;

Xilinx Trace Timing Report from Precision NCF Constraint

===============================================================================
Timing constraint: TS_clk_main = PERIOD TIMEGRP "xmplr_wr_bar" 100 nS HIGH 50
33 items analyzed, 0 timing errors detected.
Minimum period is 46.500ns.
-------------------------------------------------------------------------------
Slack: 5.350ns (requirement - (data path - negative clock skew))
Source: serial_control_inst/reg_FSM_current_state_current_state_i
Destination: cpu_if_inst_register_file_inst/reg_baud_reg_i(2)
Requirement: 10.000ns
Data Path Delay: 4.650ns (Levels of Logic = 4)
Negative Clock Skew: 0.000ns
Source Clock: clk_int rising at 90.000ns
Destination Clock: wr_bar_int rising at 100.000ns

Notes:
The Xilinx NCF file is automatically generated during the optimise stage.

9-28 Designing with FPGA Advantage

November 2003
Synthesis Constraints

Vendor Constraints — Unrelated Clocks

Precision SDC Clock Constraint
create_clock wr_bar -period 100 –domain domain1
Create_clock clk –name –domain domain2

Precision Generated Xilinx NCF Constraint

NET "wr_bar" TNM_NET = "xmplr_wr_bar";
TIMESPEC "TS_clk_wr_bar" = PERIOD "xmplr_wr_bar" 100.000000 ns HIGH 50.000000 %;
NET "clk" TNM_NET = "xmplr_clk";
TIMESPEC "TS_clk_clk" = PERIOD "xmplr_clk" 10.000000 ns HIGH 50.000000 %;

Xilinx Trace Timing Report from Precision NCF Constraint

================================================================================
Timing constraint: TS_clk_wr_bar = PERIOD TIMEGRP "xmplr_wr_bar" 100 nS HIGH

9 items analyzed, 0 timing errors detected.

Minimum period is 4.003ns.
--------------------------------------------------------------------------------
Slack: 95.997ns (requirement - (data path - negative clock skew)
Source: cpu_if_inst_register_file_inst/reg_tx_pending
Destination: cpu_if_inst_register_file_inst/reg_tx_data_i(2)
Requirement: 100.000ns
Data Path Delay: 4.003ns (Levels of Logic = 4)
Negative Clock Skew: 0.000ns
Source Clock: wr_bar_int rising at 0.000ns
Destination Clock: wr_bar_int rising at 100.000ns

♦ Creates a table of “slack bins” x number of nets with that
slack
! A slack bin is a slack range
! # of bins and range can be customized

Notes:

Designing with FPGA Advantage 9-33

November 2003
Synthesis Constraints

View Multiple Critical Paths

♦ Can display up to 10 critical paths in different colors

> report_timing -critical_paths -num_paths 2 -show_schematic

Notes:

9-34 Designing with FPGA Advantage

November 2003
Synthesis Constraints

Fan-in / Fan-out Fragments

View Trace

Trace Backward -> 2 Levels

♦ Filter on any selected net or instance

♦ Trace forward or back from any selected net or instance
♦ Incrementally grow filtered schematic with a double-click
9-33 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation

Notes:

Designing with FPGA Advantage 9-35

November 2003
Synthesis Constraints

HyperLinking Files and Schematics

♦ Messages/Warnings/Errors
Linked to HDL Source File

♦ Objects/Nodes in the Report

Files Linked to Design Browser

Notes:

9-36 Designing with FPGA Advantage

November 2003
Synthesis Constraints

Graphical Find Command

♦ Allows filtered search of netlist objects

♦ Cross reference to schematics, RTL or HDL Designer
♦ Set constraints from find window
9-35 • Designing with FPGA Advantage: Synthesis Constraints Copyright © 2003 Mentor Graphics Corporation

Notes:

Designing with FPGA Advantage 9-37

November 2003
Synthesis Constraints

Automatic Hierarchy Management

Before Auto-dissolve
♦ Precision will automatically
dissolve hierarchy to improve TOP_LEVEL

results A I

B C D J K L

E F M N

G H

After Auto-dissolve

TOP_LEVEL

A,B,D I,J

C K L

E F,G,H M N

Notes:
Hierarchy management ó adding ports where necessary to prevent the need for
flattening.

9-38 Designing with FPGA Advantage

November 2003
Synthesis Constraints

Timing Driven LUT Buffering &

Hierarchical LUT Merging

Timing Driven LUT Buffering & Hierarchical LUT Merging

♦ LUTs buffered during timing ♦ Combines logic across
optimization hierarchy boundaries

♦ Buffer LUTs inserted across ♦ Eliminates need to flatten

hierarchy to improve place and hierarchical designs for
route performance

Before LUT Buffering Before LUT Merging

Block A Block B Block A Block B
LUT3
LUT3 LUT2

High Fanout Net

After LUT Buffering

Block A Block B After LUT Merging
LUT3
LUT1 Block A Block B
LUT4

LUT1

Notes:
Fanout-based cross-hierarchical register replication.

Designing with FPGA Advantage 9-39

November 2003
Synthesis Constraints

Constraint-Driven Register Replication

and Retiming

Constraint-Driven Register Replication and Retiming

♦ Registers replicated during ♦ Push Registers across
timing optimization combinatorial logic to improve
the performance of the circuit
♦ Registers tunneled across
hierarchy to improve place and
route Before Register ReTiming

Reg Reg Reg

Before Register Replication 8 ns 12 ns

Block A Block B
Reg

After Register ReTiming

High Fanout Net
Reg

After Register Replication

Block A Block B
Reg Reg
Reg
10 ns 10 ns
Reg

Reg

Notes:
Fanout-based cross-hierarchical register replication.

9-40 Designing with FPGA Advantage

November 2003
Synthesis Constraints

Synthesis Options

♦ One form for all synthesis

options

♦ Used to customize the

flow and tool look and feel

♦ Found at “Tools > Set

Options”

Notes:

Designing with FPGA Advantage 9-41

November 2003
Synthesis Constraints

Lab 9: Synthesizing the RTC_Clock

♦ Lab Goal:

! Part 1: Synthesizing without Constraints

! Part 2: Synthesizing with different Clock Domain settings

! Part 3: Synthesizing using re-timing

Notes:

9-42 Designing with FPGA Advantage

November 2003
Synthesis Constraints

Lab 9: Synthesizing the RTC_Clock

Introduction
In this lab, you will load a new design which implements a Real Time Clock,
which uses the BCDRegister design you created in earlier labs.

You will synthesize a part of that design, and investigate the effect of changing
constraints on that design. You will also take the design through to place and
route.

Note: This design is provided in the

RTC Library. To be able to read the
contents of the RTC library you will
have to create Library Mappings, then
you only have to open it, browse
through the design to understand what
it does and synthesize the RTC_Clock
design unit.

Directions
Part 1: Add a new Library Mapping for the full RTC Design.

o Go back to the “Project Manager” window. You just have to specify

the library name and the root directory of the design as shown in the
screenview above, the paths to HDL and downstream directories get the
defaults.

o Open the RTC library and browse the Design.

You will synthesize the RTC_Clock design several times using different
constraints settings and note the results. From that table you can easily see
their impact and compare the synthsis results with the “real” P&R results.

Designing with FPGA Advantage 9-43

November 2003
Synthesis Constraints

Part 2: Synthesize the RTC_Clock without setting any Constraints.

• Invoke Precision Spectrum on the RTC_Clock design.

Use the flow button on the toolbar, and fill in the settings dialog

o Use the Xilinx Spartan2 technology: Part: 2s15cs144, Speed Grade

-6, Design Frequency: 90MHz, Add IO Pads, output format: EDIF,
Run Options: ‘Compile’, ‘Synthesize’.

• The design has been read in, and synthesized for the chosen device, now
lets investigate the design in various ways

• Consider how clocks have been interpreted.

o How many clocks have been identified, and what domains are they
connected to, and what period has been specified?

Hint: use the Design Hierarchy panel, and expand ‘Clocks’. Moving the
cursor over a clock causes an information box to appear

No of Clocks:___________________________
Table 9-1.
Clock Domain Period Clock Domain Period
(ns) (ns)

o Are the clock periods as you expect? ___________

o Why are they the values you see? _____________________________

_________________________________________________________
_________________________________________________________

9-44 Designing with FPGA Advantage

November 2003
Synthesis Constraints

• Review the constraints report, showing what constraints have been

generated automatically.

o Do these match the table above? _____________

o Is there a Domain for each clock? ______________

Explain this: ____________________________________

• Look at the Timing Violation Report (Use the Design Analysis section in
the Design Bar to regenerate the report, don’t look at the report in the
Project Files in the Design Centre tab )

o Number of timing violations found: ______________

• Look at the Timing Report (Use the Design Analysis section in the Design
Bar to regenerate the report, don’t look at the report in the Project Files in
the Design Centre tab)

Note that the Timing report gives you information on the maximum
Frequency for each of the clocks, and a summary of the 10 most critical
timing paths. The worst path is shown in detail.

However the timing results are deceptive, as not all paths have been
considered.

• To find out which paths have been ignored we need to report timing with a
different command line switch.

o First we need to locate the transcript

window. This is the window in which
you can see all the commands, and
which allows you to type in commands
directly.

You open this by using View >

Transcript Window as show to the
right. or double click on ‘Log File’ in

Designing with FPGA Advantage 9-45

November 2003
Synthesis Constraints

the Project Files pane of the Design Centre. The result should look
something similar to the window below.

The lower of the two panes is the transcript window, and you need to
click in this window to be able to type in a command However first look
at what is in there. You may have extra lines in your window, where
you have been trying different things, but the 5 lines in the screen shot
above can be related directly to these instructions.

• dofile: Precision is running the setup dofile created by HDL

Designer, defining the technology, reading in the HDL files,
compiling and synthesizing the design. All of the separate
commands are in the dofile, which is why they are not seen here.

• report constraints: The full command here is the one that was
exercised when the ‘Report Timing Violations’ button from the

9-46 Designing with FPGA Advantage

November 2003
Synthesis Constraints

Design Bar was exercised.The results of the report were written to a

file.

• report timing: The three report timing lines make up the three parts
of the timing report generated when the ‘Report Timing’ button
from the Bar was exercised. The first reports clock frequency, the
second lists the 10 summary critical paths, and the third the detail
listing of the most critical path. The three commands all wrote to the
same file, the first opening the file, and the other two appending to it.

If you used the report files in the Project Files panel rather than the
icons in the Design Bar, then you won’t see the report lines. This is
because the reports you were looking at were generated as part of the
synthesis operation, and you just opened them to view, but the icons
actually generate the reports.

o Now we are going to report on those paths which cross clock

boundaries, none of these will have been considered when the tool was
generating the timing reports earlier.

Click in the lower half of the Transcript window, and enter the
following:

report_timing -clock_domain_crossing

The resulting report appears in the upper half of the Transcript window.
You will need to scroll through the window in order to see all the
output.

How many paths cross clock boundaries? __________________

• Exit Precision Synthesis and DO NOT save the project.

Part 3: Changing Clock domain settings.

• Invoke Precision Spectrum on the RTC_Clock design.

Use the flow button on the toolbar, and fill in the settings dialog,
but do not initiate synthesis this time, only compile.

Designing with FPGA Advantage 9-47

November 2003
Synthesis Constraints

o Use the Xilinx Spartan2 technology: Part: 2s15cs144, Speed Grade

-6, Design Frequency: 90MHz, Add IO Pads, output format: EDIF,
Run Options: ‘Compile’.

• The design has been read in, and compiled. compare the clocks with the last
time, they should be the same.

• Now we are going to alter the clock

domains, this has to be done before
synthesis.

o In the Design hierarchy pane,

select one of the internal clocks
with the RMB, a pull-down menu
will appear, click on the Set
Clock Constraints option.
o A Constraints Dialog will appear

o Un-tick the Asynchronous Domain option,

and choose ClockDomain0 from the pull-
down menu below it.
o At the moment we will leave the Clock
period as twice that of clk. It is true the
generated clocks cannot be as fast because of
the way that they are generated.
Click ‘OK’
Note that a file has now appeared in the
Project Files area, under the Constraint Files.

o Repeat this seven times, once for every internal clock.

Each time that you add a constraint, the constraints file is updated. To
see this look at the transcript window.

We now have defined all clocks to be in the same domain, and

synchronous to each other. This is true, as they are all generated from
the initial input clock.

9-48 Designing with FPGA Advantage

November 2003
Synthesis Constraints

• In the ‘Design’ Section of the Design Bar click on Synthesize icon to

synthesize the design in the chosen technology.

• Look at the Timing Violation Report

o Number of timing violations found: ______________

• Look at the Timing Report

o Number of timing paths that are not met: ______________________

Hint: Run Report timing from the Design Bar, then use transcript
window to copy earlier report_timing command for a summary of more
than 10 paths.

o Slack for most critical path: _________________

o Slack for second critical path: ________________

o Slack for third critical path: ________________

All of these violations existed for the first run, but were not considered
during the analysis due to the way the clock domains were defined.

• We will run the place and route to see if the design can meet timing even if
the synthesis timing report has errors.

o Open the ISE 5.2 section of the Design Bar, and click on Place and
Route.

o When this is finished go to the Design Centre window. There are now
various Xilinx report files visible.

o Open the Xilinx Timing Report:

How many timing violations are there?_____________________

• Now we are going to report on those paths which cross clock boundaries
again.

Designing with FPGA Advantage 9-49

November 2003
Synthesis Constraints

Click in the lower half of the Transcript window, and enter the following:

report_timing -clock_domain_crossing

The resulting report appears in the upper half of the Transcript window.
You will need to scroll through the window in order to see all the output.

How many paths cross clock boundaries? __________________

• Look at the critical path.

o Click on the source D-type, and use the pull down menu to trace back to
the HDL source, and to the HDL Designer diagrams.

o Do the same for the destination D-type.

• Exit Precision Synthesis and DO NOT save the project.

9-50 Designing with FPGA Advantage

November 2003
Synthesis Constraints

Part 4: Re-timing.

• Invoke Precision Spectrum on the RTC_Clock design.

Use the flow button on the toolbar, and fill in the settings dialog,
but do not initiate synthesis, only compile.

o Use the Xilinx Spartan2 technology: Part: 2s15cs144, Speed Grade

-6, Design Frequency: 90MHz, Add IO Pads, output format: EDIF,
Run Options: ‘Compile’.

• The design has been read in, and compiled. compare the clocks with the last
time, they should be the same.

• Set the Clock constraints to the same values as those used in Part 2.
You could do this by repeating the section in Part 2, or you could apply the
actual constraints file that was written in Part 2. To do the latter:

o Double click on the Constraints Files

icon shown in the Project Files.

o A File select dialog appears, in which

each of the implementation folders can be
seen.

The present run will be the highest

implementation. Double click on the
folder of the previous implementation,
(this should be RTC_clock_impl_2 if you
have followed the lab instructions exactly)

Designing with FPGA Advantage 9-51

November 2003
Synthesis Constraints

This will open the folder and show several files, one of which is called
RTC_clock_constraints.sdc. Double click on this file to open it.

o The Project Files list will now show a constraints file below the
“Constraints Files”, as in the above screen view.

Click the RMB on this file to bring up the menu seen above. click on
‘Apply Constraints File’

Check that the constrains have been applied by looking at the some of
the clock constraints.

Look at the transcript. You will see that two commands were used, the
first to define the constraints file as an input file, and the second
applying the constraints to the design. What are these two commands?

defining input: _____________________________________________

applying constraints ________________________________________

• Alter the Re-timing option

o Go to the menu item Tools > Set Options. This opens the Synthesis
Options dialog box.

9-52 Designing with FPGA Advantage

November 2003
Synthesis Constraints

o Select Optimization
in the left of the
dialog

The optimization
options will appear
on the right-hand
side of the box.

Click on Retiming option to add it to the options in operation.

Click ‘OK’

We now have defined all clocks to be in the same domain, and asked for
re-timing to be done during synthesis.

• In the ‘Design’ Section of the Design Bar click on Synthesize icon to

synthesize the design in the chosen technology.

• Look at the Timing Violation Report

o Number of timing violations found: ______________

• Look at the Timing Report

o Number of timing paths that are not met: ______________________

Hint: Run Report timing from the Design Bar, then use transcript
window to copy earlier report_timing command for a summary of more
than 10 paths.

o Slack for most critical path: _________________

o Slack for second critical path: ________________

o Slack for third critical path: ________________

What differences have you seen from the previous run? _______________
____________________________________________________________
____________________________________________________________

Designing with FPGA Advantage 9-53

November 2003
Synthesis Constraints

• We will run the place and route to see if the design can meet timing even if
the synthesis timing report has errors.

o Open the ISE 5.2 section of the Design Bar, and click on Place and
Route.

o When this is finished go to the Design Centre window. There are now
various Xilinx report files visible.

o Open the Xilinx Timing Report:

How many timing violations are there?_____________________

We have still not correctly identified all constraints, as we did not define an offset
from clk for any of the internally generated clocks, but we know that there would
be an offset in reality, and these should be included.

We also did not include input or output constraints

Comment on design constraints used: In this exercise we have deliberately set a

high clock frequency, which would not, in fact, be needed, to show the problems
you may see in synthesis. In fact the final design (see next lab) would only need a
clock of 65536Hz, so asking for the design to work at 90MHz is unnecessary, and
very much over constraining the design. Over constraint is one of the issues that
causes you to have problems.

9-54 Designing with FPGA Advantage

November 2003
Module 10
Top-Down Design

Objectives
This module will cover the following topics:

• Top-Down Design
• HDL Designer Methodologies IBD / Block Based Design
• Maximizing Design Efficiency - Macrofunctions
• Vendor independent: ModuleWare
• Vendor tools: ALTERA Megawizard, XILINX CoreGenerator
• Intellectual Property
• Design Documentation using HTML Export
• Design Documentation using OLE
• Printing Diagrams

Designing with FPGA Advantage 10-1

November 2003
Top-Down Design

Top-Down Design

Top-Down Design
♦ Top-Down Design Flow:
! Concept
! Define design interface to external world
! Define high-level tasks
! Define interfaces between high-level tasks ?
! Design high-level tasks in behavioral VHDL
– Early Simulation of Dataflow
! Develop sub-tasks for each task
– Define sub-tasks RAM
I/O
– Define interfaces
CPU
– Develop sub-sub-tasks
– Iterate as necessary
♦ Advantages:
! Divides large designs into easily grasped
sections
! Tasks may be assigned to different work
groups early in design cycle

Notes:

10-2 Designing with FPGA Advantage

November 2003
Top-Down Design

Using FPGA Advantage for Top-Down

Design

Using FPGA Advantage for Top-Down Design

♦ Process
! Use Block Diagram for top level of design
! Create functional blocks to represent tasks
! Create I/O ports, connect to high-level blocks
! Create interconnections between high-level blocks
– Design high-level blocks in behavioral HDL
! Simulate Dataflow
– If OK, replace behavioral with RTL HDL on block by block basis
! Convert blocks with multiple instances to components
! Open Down into blocks to create lower-level views
– May be any Design Unit Type (State Machine, Block Diagram, etc)
! Repeat process for lower-level views as necessary

Notes:

Designing with FPGA Advantage 10-3

November 2003
Top-Down Design

Mixing Top-Down with Bottom-Up

Design

Mixing Top-Down with Bottom-Up Design

♦ Use library components(1) for common functions
! ModuleWare - glue logic up to Register level
! LPMs
♦ Use technology specific(2) macrofunctions
! Altera Megawizard - complex logic, vendor specific
! Xilinx Cores - complex logic, vendor specific
♦ Use complex IP(3) for standard applications
! PCI, Bluetooth, USB, DSP, Microprocessors... (3)

♦ Use Generics/Parameters to create n-bit wide (2)

components
! Design Reuse
! scalability of Design (1)

♦ Build higher-level components from existing

components
! E.g.; BCD Register from BCD Counters

Notes:

10-4 Designing with FPGA Advantage

November 2003
Top-Down Design

November 2003
Top-Down Design

MW — In-place Changes

♦ Directly invert and change mode of ports via popup

Altera MegaWizard

Same procedure as with Xilinx

Notes:

10-14 Designing with FPGA Advantage

Libraries/directories

HDL Import: Step 3 — Target Libraries/directories

♦ The user defines the target library

♦ Black-boxes are detected. They can be resolved by
pointing to the relevant HDS library (eg: io_lib)
♦ The remaining BB will be marked in the browser

Notes:

10-20 Designing with FPGA Advantage

November 2003
Top-Down Design

HDL Import: Step 3 — Context Definition

Options ⌫ HDL Import … ⌫ General Tab

Make sure we have a mapping

for all the libraries referenced
in the original HDL files

♦ The tool analyzes the context from the HDL files and may require additional
mappings
♦ The user will be prompted only if the Multiple libraries option is checked in the
General Tab

Notes:

Designing with FPGA Advantage 10-21

November 2003
Top-Down Design

HDL Import: Imported Design

♦ Result as specified:
! All design units reside in
one library
! All design units are HDL
views
! Full design hierarchy
visible

This is a great means to

ease understanding the
structure of a
foreign/legacy desgin

Notes:

10-22 Designing with FPGA Advantage

November 2003
Top-Down Design

Design Documentation using HTML

Export

Design Documentation using HTML Export

♦ Ability to “publish” the

design and associated
information in the form of
HTML pages which can be
traversed using common
WEB browsers
♦ It is very useful for design
reviews
♦ It is especially helpful for
great documentation on PC
AND UNIX
♦ It is a document you can
ship to anybody because
you can control its content

Notes:

Designing with FPGA Advantage 10-23

November 2003
Top-Down Design

HTML Export

HTML Export
♦ The HTML export Target Directory
command can be
invoked from the File
menu or directly from
the toolbar menu in the
main window
File ⌫ HTML Export ...

Range

♦ From the File menu in

the different editors

Notes:
You can export an entire library or any design unit view (or hierarchy of views).
When it is used in a graphic editor, only the active view is exported. Export
HTML from the graphic editors is provided for updating existing views within an
exported hierarchy. However, it does not create the HTML frame set and other
supporting files. The HTML Export dialog box is displayed which allows you to
specify or browse for a target directory to contain the exported files. The HTML
Export dialog box also allows you to specify the graphics format which can be
JPEG or PNG. A compression percentage can be specified if you choose JPEG
(Joint Photographic Experts Group) format or a standard compression is used for
PNG (Portable Network Graphics) format.

10-24 Designing with FPGA Advantage

November 2003
Top-Down Design

HTML Export: Viewing the Exported

HTML

HTML Export: Viewing the Exported HTML

♦ Navigation Frame
! Source Browser
! like HDS Design
Browser *
♦ Design Frame
! View / Navigate
*
– Multiple pages
! Information
– Ports / Declarations
– HDL Statements
! Side Data
! Generated HDL

Notes:
The navigation frame displays the exported design hierarchy or library and can be
used in a similar way to the HDL Designer source browser. When a library has
been exported, you can expand and collapse each design unit to reveal their design
unit views including component symbols and non-default views. You can display
views by clicking on any item in the Navigation frame to display the
corresponding view in the Design frame.

The Diagram tab of the design frame displays design unit views described by
diagrams or tables as resizable graphics with hotspots connecting to other HTML
pages in the hierarchy. These hotspots can be used to open down into hierarchical

Designing with FPGA Advantage 10-25

November 2003
Top-Down Design

child views or you can use the button to move up through the design hierarchy. A
separate Information tab displays text information such as generation settings,
local declarations, compiler directives and package references. You can also use
choose separate tabs to display Side Data objects or the generated HDL for the
view.

10-26 Designing with FPGA Advantage

November 2003
Top-Down Design

Printing Diagrams: Page Setup

Page boundaries
File → Page Setup...

♦ You choose up-front the page options

♦ You can display (or not) the boundaries Page number
and page number in the editor
♦ You see what you print out
♦ It applies to all the editors (you don’t see
the boundaries for the tables)
♦ You can add page connectors

Notes:
The Boundaries tab provides options which allow you to control the display of
printer page boundaries. You can choose to show the boundaries in diagram editor
views and to include an optional page number which can be used to selectively
print a page or range of pages. The page boundaries are displayed as dotted
rectangles originating from the top left corner of the visible objects on the
diagram. You can choose whether the origin is automatically re-located when you
refresh the boundaries after making changes to the diagram.

The page boundaries are automatically refreshed when you change the page
settings or you can choose Refresh Page Boundaries from the File menu to update
the displayed boundaries after you have changed the diagram.

Designing with FPGA Advantage 10-27

November 2003
Top-Down Design

Documentation using OLE: Overview

♦ HDL Designer Series diagram editor views (block diagram, state
diagram and flow chart) support the Windows OLE (Object
Linking and Embedding) standards.(*)
♦ This views can be imported into any OLE compatible PC
documentation tool:
! Microsoft Office applications
! Adobe FrameMaker
♦ The interface used for importing OLE objects varies between
tools:
! Direct import by drag & drop
! Insert Object or Import Object command
♦ What does OLE mean in practice ?
! Your documentation is truly automatically updated when you modify
the view in HDL Designer.
! You can also modify your view directly from the document.
! It is a real dynamic document!

Notes:
* The table editor views (truth table, tabular IO and IBD view) support OLE for
tools which recognize enhanced metafiles. These include Microsoft PowerPoint,
Excel and Word XP but not FrameMaker or older versions of Word.

10-28 Designing with FPGA Advantage

November 2003
Top-Down Design

Documentation using OLE:

Requirements

Documentation using OLE: Requirements

♦ A few requirements before you can use OLE
! The hds.hdp file that contains the library mapping information
must be saved in a standard location which can be accessed
from the documentation tool
! The environment variable HDS_LIBS which sets an alternative
location for the hds.ini file can’t be used while using OLE
! HDS_PREFS which sets the full pathname to the user preference
file .hdsPrefs can’t be used while using OLE

♦ OLE works directly from the documentation tool to insert an
object:
Insert → Object...

Link to File

Notes:

10-32 Designing with FPGA Advantage

November 2003
Top-Down Design

Documentation without OLE

♦ On PC, you can also use the Copy Picture command to copy the
entire diagram to the System Clipboard.

Diagram → Copy Picture

Notes:

Designing with FPGA Advantage 10-33

November 2003
Top-Down Design

Lab 10: Real Time Clock Design

♦ Lab Goal: Open and simulate a Real Time Clock (RTC) design
which uses the BCD Register design completed in an earlier
lab

! Part 1: Browse the RTC design to understand the Structure

! Part 2: Simulate the RTC design using the provided Testbench

! Part 3: Use a TCL implemented graphical Testbench to simulate

the design.

! Note: This lab just provides the more complex RTC design which
will be used for the advanced labs.

Notes:

10-34 Designing with FPGA Advantage

November 2003
Top-Down Design

Lab 10: Top Down Design

Introduction
This lab is in three sections, looking at different aspects of top down design. You
don’t have to complete all of them. Your instructor will provide you the timeframe
to complete the lab. Therefore choose the section first which is of most interest for
your work.

Implementing the BCD Counter using a Logic

Generator
This project uses the same design but another design approach compared to the
regular labs.

During this lab you will replace the BCD Counter design unit with a counter you
generate with XILINX’s Core Generator. Using this kind of logic generators
usually results in a significant productivity gain but there are some prerequisites
and “traps” you should be aware of. Therefore you will encounter some typical
problems during this lab but solutions and explanations are provided. You may
use them as guidelines for your own projects.

If you are using Altera technologies the same procedure can be done with the
Altera Megawizard.

Summary

This lab comprises two main sections:

• In the first section create a new library and copy the original BCDCounter
and testbench into it. Using the XILINX CoreGenerator create another
implementation of the BCD Counter and instantiate it in the testbench
design. Test, compare and troubleshoot the behavior of the two different
counter implementations.

Designing with FPGA Advantage 10-35

November 2003
Top-Down Design

• In the second section copy the BCDRegister design and testbench into the
new library, replace the BCD Counter design unit with the CoreGenerator
counter. Test and troubleshoot the behavior of the modified BCDRegister.

Directions — Section 1

• Part 1: Setup the Design environment

o Open existing Libraries (if not already open)

Open the MyTestLib Library

o Create a new Library called BCD_Core using the Design Managers

New Library... icon and use $FPGADV_LABS as root directory.

• Part 2: Switch to the MyTestLib Library and copy the whole

BCDCounter_tb design unit hierarchy

o Select the BCDCounter_tb design unit and select “Copy” from the
popup menu.

o Select the BCD_Core

Library and select “Paste
Special” from the popup
menu and fill the dialog as
follows:
When “Copy through
components” is checked, all
instantiated components are
copied to the new location.
Otherwise they are only
referenced to the originating
library.

o Browse the contents of the new library and check whether the
referenced Blocks and Components point to the new library BCD_Core
or to the originating library.

• Part 3: Create the bcd_core counter using Core Generator

10-36 Designing with FPGA Advantage

November 2003
Top-Down Design

o To start the CoreGenerator click in the Design Managers

Shortcut Bar on the “Tasks” tab and whitin that on the
“Xilinx Core Generator” icon.

o Modify the Coregenerator Interface

dialog as shown on the right:
Then start the tool by clicking on the
“Invoke Core Generator” button.

o When the Core Generator GUI is invoked take some time to browse
through the available functionalities. Then choose (doubleclick) the
“Binary Counter” from category “Basic Elements > Counters”.

o Use the configuration dialog to configure the counter for the desired
behavior. Note that a BCD counter can be modeled using a four bit
binary counter with rollover at 9. The “Threshold” setting generates the
“carry out” signal.

1.
2.

Designing with FPGA Advantage 10-37

November 2003
Top-Down Design

After having finished the setup generate the counter by clicking on the
“Generate” button in the “Binary Counter” dialog box.

o Exit the “Binary Counter” dialog box and Core Generator.

o Close the “Core Generator Interface” dialog. You should see now a
Design Unit called bcd_core in the BCD_Core Library.

• Part 4: Instantiate the bcd_core component in the BCDCounter_tb block

diagram.

o Use an inverter from the Moduleware Library to invert the clear signal.
Use the following block diagram as a guideline:

o Generate HDL for the BCDCounter_tb design.

o Did HDL generate successfully? If not why: _____________________

o HDL Designer complains about the net “load_in” where the needed
type is “std_logic_vector”. This type of conflict always happens when
you use other data types (like unsigned) than std_logic in your design.
Core Generator always uses std_logic and std_logic_vector signals.
Therefore you have to convert the unsigned signal “load_in” to

10-38 Designing with FPGA Advantage

November 2003
Top-Down Design

std_logic_vector. There are several possibilities to convert a data type

in HDL Designer, here use the “Port Map Frame” functionality.

o Select the bcd_core component in the BCDCounter_tb block diagram.

select from the popup menu “Port Map Frame > Enable”. All signals
are automatically connected to the component through port mapping.
Separate the load_in signal from the component by dragging it from the
port to the Port Map Frame. Then add the conversion function to the
port map list:

o The conversion function used needs the ModelSim compiler use the
“-93” switch to compile the VHDL code according to the VDHDL93
standard.

Therefore right-click on the “ModelSim Compile” task at the task bar

and choose the “Settings” entry. At the “VHDL” tab enable the
“93 Language Syntax” and “OK” the dialog box.

o Generate again HDL for the BCDCounter_tb design.

o Did HDL now generate successfully? If not why: _________________

o Run the Simulation Flow to start simulation on the BCDCounter_tb

design unit.There may be some compiler errors like:

Designing with FPGA Advantage 10-39

November 2003
Top-Down Design

** Error: (vcom-19) Failed to access library

'xilinxcorelib' at "xilinxcorelib".

If you see these errors follow all the following instructions, if not jump
to the instruction that says ‘Start Simulation’, this is on the next page.

o HDL Designer does not find the referenced simulation model for the
generated bcd_core design unit.This is caused by the fact that the
library containing the CoreGenerator’s simulation models is not
compiled for ModelSim

o The following procedures compile the CoreGenerator library. This has

only to be done once at the first usage of CoreGenerator components.
Usually this task is performed by a system administrator.

o Compile the CoreGenerator library for use with ModelSim.

Xilinx has provided a compile utility which performs the compilation.

a. <on Windows only> Turn off the Read Only attribute of the
Modelsim.ini file to make it writable, the ModelSim.ini file is located in
the ModelSim installation directory. Ask your instructor for details, if
you have difficultiers to locate it.
This is necessary to allow the Xilinx compile script to add the library
mapping to the ModelSim.ini file.

b. Open a Command Prompt (Windows) or a Unix shell. Type the

command as follows:
compxlib -s mti_se -f spartan2:c -l vhdl -o $FPGADV_LABS\xilinx_libs

This will compile the Spartan2 CoreGen library VHDL models for
ModelSim into the specified directory. If you want to see the program’s
options type “compxlib -help”

c. <on Windows only> Turn on the Read Only attribute of the

Modelsim.ini file.

o Now run the Simulation Flow again. This time there should be no
errors.

10-40 Designing with FPGA Advantage

November 2003
Top-Down Design

o Start Simulation and compare the output of the two different counter
implementations.

o Note the slightly different behavior of the bcd_core signals prior to the
active reset signal!

o The behavior of the carry_out/q_treshold signal is also different at the

end of the simulation. This is due to the count enable signal is not actice
at that moment. Try setting this signal active and observe the behavior.

o Discuss the results with your instructor.

o When you have finished, exit ModelSim.

Directions — Section 2 (Optional)

o Copy the BCDRegister design and testbench into the BCD_Core

library, replace the BCD Counter design unit with the CoreGenerator
counter.
Test and troubleshoot the behavior of the modified BCDRegister

o When you have finished, exit ModelSim.

Designing with FPGA Advantage 10-41

November 2003
Top-Down Design

Simulate the RTC Design using a TCL Testbench

Introduction

In this lab, you will load a new design which implements a Real Time Clock,
which uses the BCDRegister design you created in earlier labs. You will simulate
it first using a provided VHDL testbench and then using a TCL implemented
graphical testbench.

Directions

• Part 1: Open the RTC library and browse the design.

The design consists of:

i. A Clock Divider that accepts a signal from an external 65 kHz

oscillator, and sends out a trigger pulse every 2**16 clock cycles.
Assume the oscillator signal will be provided by the simulation tool.

ii. A Clock Multiplexer which allows to select a “simulation clock” to

speed up simulation time, because “real time” simulation of the
clock would be impossible. => a good tip to use in your designs...

iii. A decoder and multiplexer to control input and output.

iv. A block of BCD Registers

There are 8 internal BCD Registers in the RTC:

Clock Registers and assigned decoder adresses:

Seconds (0-59) - Addr 00,

Minutes(0-59) - Addr 01,

Hours (0-23) - Addr 10,

Day (0-6) - Addr 11

10-42 Designing with FPGA Advantage

November 2003
Top-Down Design

v. Top Level Design:

Clock Divider
Registers Multiplexer

Decoder

The Real Time Clock (RTC) design stores the time in seconds,
minutes, hours, and the day of the week. Data can be input
synchronously to set the clock by asserting a chip enable input signal.
The current time is always available on the data_out bus, based on the
value of the addr input bus.The RTC can be reset to a default state. In
the presence of a 65 kHz clock signal, the RTC will constantly update
the time.

o Load sequence

The load sequence is synchronous. To load data into a register, first

assign the required address value on the addr bus, then assign the
data to load on the data_in bus, followed by asserting the ce signal
low. Assert the ce signal high again to stop the load sequence.

o Read sequence

The current value of the register corresponding to the current addr

bus value is constantly reflected on the data_out bus.

Designing with FPGA Advantage 10-43

November 2003
Top-Down Design

• Part 2: Simulate the RTC design using the provided RTC_tb testbench.
The RTC_Tester is a very simple Testbench which just runs the clock in
normal mode. No load functionality or output decoding is tested.

o Modify the testbench to see the output of all registers. One suggestion is
to rotate around the output of the registers.

• Part 3: Simulate the RTC design using the provided RTC_GUI TCL
testbench.

You can use the TCL testbench together with the VHDL testbench, you
don’t have to reset the simulator prior to invoking the TCL GUI.

o Run the TCL script by the pulldown command Tools > Execute Macro
in ModelSim Main window. Choose the file rtc_gui.tcl in the
$FPGADV_LABS/rtc/tcl_tb directory.

o When the window pops up click on the “Refresh Display” button to see
the actual clock values.

o Click the “Help” Button to see the functionality of the other buttons,
how to set the clock etc.

o Use the TCL testbench to verify (again) the correct functionality:

i. Reset design

ii. Rollover to next digit

iii. Set Clock with legal values

10-44 Designing with FPGA Advantage

November 2003
Top-Down Design

iv. Set Clock with illegal values

This approach for building a testbench is very useful when user interaction
is needed during testing of a design. It’s also helpful to provide a “real”
product like behavior of the simulation.

Designing with FPGA Advantage 10-45

November 2003
Top-Down Design

10-46 Designing with FPGA Advantage

November 2003
Module 11
Synthesis Methodology

Objectives
This module will cover the following topics:

• Synthesizing complex structure

• State Machine synthesis
• Pipelining
• CLKDLL/DCM usage
• Writing scripts and using the command line

Designing with FPGA Advantage 11-1

November 2003
Synthesis Methodology

Constraint-Based Optimization

Constraint-Based Optimization
♦ The optimization process is driven by
timing constraints Perform quick
optimization on all
hierarchy blocks
♦ Critical blocks are automatically
identified and reoptimized with more
effort
! Unconstrained designs are optimized for
Use Timing Analysis to
area
identify critical blocks
! Minimal run times are achieved with
relaxed constraints

Perform additional
optimization on and
between critical blocks

Notes:

11-2 Designing with FPGA Advantage

November 2003
Synthesis Methodology

High-Level Optimization

High-Level Optimization
♦ State machines are extracted and
optimized + MUX

♦ Constants are propagated

through hierarchy -

♦ Resource sharing of operators is

performed MUX

+
MUX
-

Notes:
LeonardoSpectrum performs several high-level, technology independent
optimizations such as FSM, constant propagation and operator resource sharing.
Optimizations performed at the high-level often have the greatest impact on
quality of results.

Designing with FPGA Advantage 11-3

November 2003
Synthesis Methodology

Advanced FSM Optimization Features

♦ Automatic extraction of Verilog

state machines

♦ Logic restructuring

♦ Detection and removal of

equivalent states

♦ Detailed FSM reporting

♦ Excellent Quality of Results

Notes:

11-4 Designing with FPGA Advantage

November 2003
Synthesis Methodology

Advanced FSM Optimization Settings

♦ Enabled under Tools > Set Options > Input

♦ Auto Encoding (default)
! binary < 6 bits < One hot < 128 bits < gray
♦ Turn off Advanced FSM Optimization where specific hard
encoding has been identified in the design
♦ Option to ensure ‘safe state machines’ generated
♦ Enter Precision before compiling in order to set these options

Notes:

Designing with FPGA Advantage 11-5

November 2003
Synthesis Methodology

Advanced FSM Optimization

Precision FSM Report

♦ Detailed reporting of FSM Optimization:

! Automatic extraction and optimization of VHDL and Verilog FSMs
! Detection and removal of equivalent, unreachable and terminal states
11-6 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation

Notes:
Full recognition and extraction of state machines in VHDL and Verilog, written in
1-process, 2-process, or 3-process styles.

11-6 Designing with FPGA Advantage

November 2003
Synthesis Methodology

Pipelining

Pipelining
♦ A method of speeding up synchronous logic by adding
pipeline registers:
Before pipelining:

After pipelining:

Advantage: Disadvantage:
♦ Circuit reg-reg time is decreased ♦ Greater Clock Latency on output signal
♦ less intuitive VHDL

Notes:

Designing with FPGA Advantage 11-7

November 2003
Synthesis Methodology

Pipelining in Precision

Pipelining in Precision
♦ In some technologies precision will automatically pipeline
multipliers given the correct input design:
Registers to be ‘absorbed’ into multiplier
User design, before synthesis
♦ Fully combinatorial multiplier
♦ Place ‘absorbing’ registers at
*
output of multiplier
♦ Place input and output registers
for optimal performance
Combinatorial multiplier

After Precision synthesis

♦ Pipelined multiplier
♦ Registered ‘absorbed’ into
multipler *
♦ No difference in latency as
registers on output were initially
present in the HDL
Pipelined multiplier
♦ No change in source HDL
11-8 • Designing with FPGA Advantage: Synthesis Methodology Copyright © 2003 Mentor Graphics Corporation

Notes:

11-8 Designing with FPGA Advantage

November 2003
Synthesis Methodology

Pipelining in Precision (Cont.)

♦ There is an optimal number of register stages that can be
added to a multiplier

Optimal # of pipeline stages = Log2(input data bus width)

♦ Common values are shown in the table below.

Input data bus width Pipeline stages

8 3
16 4
32 5
64 6
128 7

Notes:

Designing with FPGA Advantage 11-9

November 2003
Synthesis Methodology

Technology Mapping

Technology Mapping
♦ Leverage superior analysis capabilities for best Quality of
Results

♦ Multi-pass optimization has been automated

♦ Automation is based entirely on timing constraints

! Start with quick area pass
! Run additional passes if needed

♦ Eliminates unnecessary optimization

! Learns about design to improve iteration run times
! Knows when to quit!

Notes:

11-10 Designing with FPGA Advantage

November 2003
Synthesis Methodology

Synthesis Options

♦ One form for all synthesis

options

♦ Used to customize the flow

and tool look and feel

♦ Found at “Tools > Set

Options”

Notes:

Designing with FPGA Advantage 11-11

November 2003
Synthesis Methodology

Importing Coregen Blocks as EDIF

Netlists

Importing Coregen Blocks as EDIF Netlists

♦ Coregen .edn netlists can be

added to the input file list
! Handled by HDL Designer

♦ Coregen blocks are read in and

don’t_touched

♦ Allows Precision to generate

accurate area / delay estimates

Notes:

11-12 Designing with FPGA Advantage

November 2003
Synthesis Methodology

Automatic DCM Clock Constraint

Propagation

Automatic DCM Clock Constraint Propagation

-- CTE report timing..
-- CTE report timing..
CTE Critical Path Report
-- CTE Setup Analysis..CTE Critical Path Report
-- CTE Setup
Analyze Setup Slacks
Analysis..
Analyze Setup Slacks
-- CPU Time Used: 0 sec.
----CTE
CPUget
Time Used:
true 0 sec.
worst setup path..
-- CTE get
Critical pathtrue
#1, worst
(path setup
slack path..
= -0.18):
Critical path #1, (path slack = -0.18):
SOURCE CLOCK: name: IP1/reg_dout(63)/C period: 2.500000
SOURCE CLOCK:
Times name: IP1/reg_dout(63)/C
are relative to the 4th risingperiod:
edge 2.500000
DEST Times
CLOCK:are relative
name: CLK_INtoperiod:
the 4th10.000000
rising edge
DEST CLOCK:
Times name: CLK_IN
are relative period:
to the 10.000000
2nd rising edge
Times are relative to the 2nd rising edge
NAME GATE DELAY ARRIVAL DIR
NAME
IP1/reg_dout(63)/C GATE
FDC DELAY ARRIVALupDIR
0.00
IP1/reg_dout(63)/C
IP1/reg_dout(63)/Q FDC
FDC 0.85 0.00 upup
0.85
IP blocks IP1/reg_dout(63)/QOBUF_F_24
dout1_obuf(63)/I
dout1_obuf(63)/I
dout1_obuf(63)/O
FDC
OBUF_F_24
OBUF_F_24
0.85
1.83
0.85 upup
0.85
0.85 upup
2.68
dout1_obuf(63)/O
dout1(63) OBUF_F_24
(port) 1.83 2.68 upup
2.68
dout1(63) (port) 2.68 up
Edge separation: 2.50
Edge constraint:
Setup separation: - 2.50
0.00
Setup constraint: - 0.00
---------
Data required time: ---------
2.50
Dataarrival
Data required time:
time: - 2.50
2.68
Data arrival time: -
---------2.68
Slack (VIOLATED): ---------
-0.18
Slack (VIOLATED): -0.18

Timing
Timinganalysis
analysisbased
basedon
on
propagated constraints
propagated constraints
Only
Onlythe
theDCM
DCMinput
inputclock
clockisisconstrained
constrained
DCM
DCMoutput
outputconstraints
constraintsare
are
automatically
automaticallypropagated
propagatedfor
forTiming
Timing
Analysis
Analysis

Notes:

Designing with FPGA Advantage 11-13

November 2003
Synthesis Methodology

DCM Attribute Editing

♦ Precision allows “on-the-fly”

editing of DCM attributes

♦ Once modified timing analysis

can be performed immediately

♦ Edits done from schematic

viewer, find window or design
browser

Notes:

11-14 Designing with FPGA Advantage

November 2003
Synthesis Methodology

Backannotated Timing Analysis

♦ Can annotate .dly file timing data onto Precision database
! Must set environment variable “PAR_BELDLYRPT” to 1
♦ Allows incremental timing analysis with actual data
♦ Could re-optimize if missing timing
♦ Simprims timing analysis flow coming

Notes:

Designing with FPGA Advantage 11-15

November 2003
Synthesis Methodology

The Precision Command Line

The pulldown command “view
transcript” or double-clicking on
the “log file” in the project browser
will display the transcript window
which provides an interactive
command line

Precision can be invoked at the

command line in shell mode using
the “-shell switch”

> precision -shell

Notes:

11-16 Designing with FPGA Advantage

November 2003
Synthesis Methodology

Precision Script Basics

Precision Script File

The “setup_design” command is # Setup Technology Environment
used to configure details about setup_design -manufacturer "Xilinx"
setup_design -family "VIRTEX-II"
how synthesis is performed setup_design -part "2V40cs144"
setup_design -speed "6"

The “add_input_file” command # Add input files

Saving Netlists

Saving Netlists
♦ The “synthesize” command will automatically save an xdb
and edif netlist

♦ other netlist formats can be generated using “write”

! The “-format” switch is only necessary if a non-standard suffix is
used

> write design_name.v –format verilog

Notes:

11-22 Designing with FPGA Advantage

November 2003
Synthesis Methodology

Interactive Reporting Commands

♦ Report_area
! Reports device utilization and cell count

♦ Report_timing
! Primetime compatible includes over 35 switches

♦ Report_net
! Reports fanout, capacitance and slew on a net

♦ Report_missing_constraints
! Lists all clocks and ports that are not constrained

♦ Report_constraints
! Lists all the constraints set on a design

Notes:

Designing with FPGA Advantage 11-23

November 2003
Synthesis Methodology

Block-Based Design Script

Single Block Assembled Design
# Setup Technology Environment # Setup Technology Environment
setup_design -manufacturer "Xilinx" setup_design -manufacturer "Xilinx"
setup_design -family "VIRTEX-II" setup_design -family "VIRTEX-II"
setup_design -part "2V40cs144" setup_design -part "2V40cs144"
setup_design -speed “6” setup_design -speed "6“
setup_design -addio=false Setup_design -addio

# Add input files # Add input files

add_input_file {block_a.vhd} add_input_file {block_a.xdb}
add_input_file {block_b.xdb}
# Setup timing constraints add_input_file {block_c.xdb}
setup_design –frequency 100 add_input_file {block_d.xdb}
add_input_file {top.vhd}
# Complete the optimization process
compile # Setup timing constraints
synthesize setup_design –frequency 100

# Compile the design

Must compile the design first prior Compile

to synthesize to allow setting # Don’t Touch sub-blocks

dont_touch {U1 U2 U3 U4}
don’t_touch constraints on pre-
optimized sub-blocks # Complete the optimization process
synthesize

Notes:

11-24 Designing with FPGA Advantage

November 2003
Synthesis Methodology

Double-Click Help Reference

Double-click on a To automatically launch

command typed on the the on-line reference
command line or in a manual help for that
command file command

♦ Key Benefits
! Quickly view reference help for Precision commands

Notes:

Designing with FPGA Advantage 11-25

November 2003
Synthesis Methodology

Executing Script Files

♦ From the GUI use the pull-down menu “File > Run Script”
command

♦ From the command line use the “source” command

& source run.tcl

Notes:

11-26 Designing with FPGA Advantage

November 2003
Synthesis Methodology

Lab 11: Advanced Synthesis

♦ Lab Goal: Investigate some of the more advanced synthesis
features.

! Part 1: Internal Clocks.

! Part 2: Multiple Paths and False Paths

! Part 3: Design Assembly for Xilinx.

Notes:

Designing with FPGA Advantage 11-27

November 2003
Synthesis Methodology

Lab 11: Further Synthesis Opportunities

This lab is in three exercises, looking at different aspects of synthesis. Neither of
these use the RTC design that has been developed so far, so if you have not
finished the previous work at this point you will not be prevented from working
on this lab.

Internal Clocks
Introduction

In this lab, you will use some of the capabilities within Precision for dealing with
Instantiated DCM or DLL elements from Virtex technologies.

Directions

• Part 1: Prepare the design.

o Open FPGAdvantage, continuing with previous project.

o Add mapping for a new library Int_clk, using the following settings:
• Regular Library
• Library Name: Int_clk
• Directory: $FPGADV_LABS/synth_labs
• Downstream Data Directories for Precision
• No Version Management
• Not default library

o After adding the library, open it to see the clk_div design unit, do NOT
look at the source for this unit.

o Invoke the Precision Design Flow on the clk_div unit, using the
following settings:
• Technology: Virtex-II
• Device: 2V80fg256
• Speed Grade: -4
• Clock Frequency: Do NOT set
• Add IO Pads: yes

11-28 Designing with FPGA Advantage

November 2003
Synthesis Methodology

• Output Formats: EDIF

• Run Options: ‘Compile’

• Part 2: Set Constraints.

o Precision opens, and the design is compiled. Examine the resulting
Clocks folder in the Design Hierarchy panel of the Design Centre.

How many clocks are displayed?________________

• Double click on the input clock called “clk” to bring up the

schematic.
• Trace forward two levels of logic from the clk input and view the
trace schematic.
• Trace the DCM instantiation to the HDL Source to verify the 2x
multiplication block that has been implemented as intended. You
should see the DCM_one_output connected to the clk2x output of
the DCM.
• Close the HDL editor and schematic viewer.
o Set a 20 nanosecond clock period constraint on the signal clk.

By setting a clock period of 20 ns on the input of the DCM, Precision

will automatically propagate a 10 ns clock period out of the DCM
clk2x output. The internal clock in this design is actually generated
from a flip-flop that is driven by the clk2x output of the DCM. By
default, Precision will propagate a clock period constraint from the
clock pin of a Flop if the Q output of the flop drives an internal clock
network.

The default is to use the “worst case” scenario as if the flop were a
trigger flip flop and propagate a 2x period. This ensures that the design
is at least constrained should the user forget to constrain an internally
generated clock. If no constraints are provided to the P&R software,
then the FPGA may be failing in the “real world” timing, but nobody

Designing with FPGA Advantage 11-29

November 2003
Synthesis Methodology

would know until a strange failure mode occurred after the board had
been shipped. This can be seen in the RTL Schematic, as shown below.

o Set clock constraints on the clkx internal

clock. Set it to 160 ns and use the “Clock
Buffer” pull-down to select a BUFG
element.

Note that we are setting these as

asynchronous clock domains.

• Part 3: Synthesize and investigate results.

o Now synthesize the design.

o View the Technology Schematic to see the

inserted BUFG driven by a flop.

Once you have found the BUFG that was inserted, close the schematic
window.

o Check the Precision timing report to verify that it has indeed seen the
10 ns clock period from the DCM.

What part of the timing report showed you this?______________

11-30 Designing with FPGA Advantage

November 2003
Synthesis Methodology

o Implement a “report_timing”
on the D input pin of the register
called reg_data_out_slow(15).
(Look in the Technology
Schematic)

What clock periods have been

used for the source and
destination clocks?

Source Clock:
_______________________

Destination Clock:
_______________________

o In the Design Centre, check the Xilinx User Constraints File to see the
input clock and internal clocks are both constrained correctly. They
should be seen to be separate, unrelated TIMESPEC’s

o Run Place & Route.

Check the Timing report to ensure that the 10ns constraint has been
used, based from the 20 ns reference constraint.

Precision seamlessly handles cascaded DCM configurations as well as the

use of the CLKFX output for complex clocking.

o Exit Precision, do not save project settings.

Designing with FPGA Advantage 11-31

November 2003
Synthesis Methodology

Multiple Paths and False Paths

Introduction

This example uses a multiplier which is enabled every 16 clock cycles. This is
sufficient to illustrate the difference between false path reporting and multicycle
path reporting.

Directions

• Part 1: Prepare the design.

o Add mapping for the library multiplier, using the following settings:
• Regular Library
• Library Name: multiplier
• Directory: $FPGADV_LABS/synth_labs
• Downstream Data Directories for Precision
• No Version Management
• Not default library

o After adding the library, open it to see the multi design unit.

o Invoke the Precision Design Flow on the multi unit, using the
following settings:
• Technology: VirtexE
• Device: V50efg256
• Speed Grade: -6
• Add IO Pads: yes
• Clock Frequency: Do NOT set
• Output Formats: EDIF
• Run Options: ‘Compile’

• Part 2: Synthesis with no multipath or false path constraints.

o Precision opens, and the design is compiled.

• Set a 10 nanosecond clock period constraint on the signal clk.

• Synthesize the design.

11-32 Designing with FPGA Advantage

November 2003
Synthesis Methodology

• Examine the timing report.

What is the reported clk frequency for the clk________________

You may notice that the critical path passes through a modgen
multiplier and has end-points at a register bank associated with the
output_cd.

o Open up the RTL code for the multiplier.

How often is the path actually enabled?______________

In the RTL code, this path through the multiplier is enabled every 16
clock cycles. So we can set a multicycle path constraint to provide more
accurate timing information for synthesis and P&R.

The SDC standard for Constraints does allow the setting of multicycle
paths on a pin as well as an instance. The pin based methodology is
more explicit, but both styles will be covered here.

o Exit Precision, do not save project settings

• Part 3: Synthesis with pin-based constraints.

Due to the effects of mapping, constraints must be set on an RTL database,
not a post-synthesis database. Setting constraints after Synthesis can be
used for design exploration, but may lead to constraints that do not relate to
the RTL.

o Invoke the Precision Design Flow on the multi unit again, using the
same settings as before

Designing with FPGA Advantage 11-33

November 2003
Synthesis Methodology

o Set the constraints:

• Set a 10 nanosecond clock period

constraint on the signal clk.

• Locate the instance of the flip-flop

reg_output_cd(31) in the Design
Hierarchy Browser.

• Select the ‘in’ input, and with a RMB

select “Set Pin Constraints...”.

• Set a Multicycle path of 16 cycles,

don’t worry about the clk

• Open up the Constraints File,

multi_constraints.sdc. You should see two
entries. One is the clock definition, the other a
multicycle path constraint for bit 31 of the bus.

• Edit the ‘31’ and replace it with the wild card

‘*’ so that the same constraint will apply to all
bits of the bus.

• Save and close the Constraints File.

• Press ‘Compile’ to apply the new constraint
file.

o Synthesize, checking the timing reports:

• Synthesize the design

• Examine the timing report
What is the reported clk frequency for the clk________________

The detailed critical path comes from the counter, to the clock enable
of the reg_output_cd.

11-34 Designing with FPGA Advantage

November 2003
Synthesis Methodology

NAME GATE DELAY ARRIVAL DIR

modgen_counter_reg_q(0)/C FDC 0.00 up
modgen_counter_reg_q(0)/Q FDC 2.55 2.55 up
ix854/I3 LUT4 2.55 up
ix854/O LUT4 4.22 6.78 dn
reg_output_cd(0)/CE FDCE 6.78 dn

The advanced timing analysis engine of Precision has taken the

multicycle and false path constraints into account when reporting the
estimated clock frequency.

• Open the Xilinx User Constraint File. You will see that it contains
a TIMESPEC that de-constrains a path involving pins on flip-flops,
making the 160 ns.

o Place and Route, checking the timing reports:

• Run embedded Place and Route using the ISE 5.2 bar in Precision.
Press the “Place & Route” button.

• When P&R is complete, open the Xilinx timing report.

What is the minimum period for the clk domain?
________________

What is the maximum period for the deconstrained domain? ______

o Exit Precision, do not save project settings.

• Part 4: Synthesis with instance based constraints.

An instance-based constraint does not contain any pins, and presents a
much coarser constraint methodology. It can, however, be used to explicitly
specify -to and -from paths to achieve the same result as pin-based
constraints.

o Repeat Part 3, until the constraints file is created, but do not save the
constraints file.

Designing with FPGA Advantage 11-35

November 2003
Synthesis Methodology

• Continue editing the constraints file to remove the pin-based nature

of the multicycle path constraint:

set_multicycle_path 16 -to { reg_output_cd(*)/in }

becomes
set_multicycle_path 16 -to { reg_output_cd(*) }

Close and save the Constrains file.

• Compile and synthesize the design.

What is the reported clk frequency for the clk________________

By only specifying a -TO instance constraint (we removed the pin),

we have incorrectly included the Clock enable pin path to all of the
reg_output_cd flip-flops. The path now reported will end at input
flip-flops.
NAME GATE DELAY ARRIVAL DIR
modgen_counter_reg_q(0)/C FDC 0.00 up
modgen_counter_reg_q(0)/Q FDC 2.55 2.55 up
ix854/I3 LUT4 2.55 up
ix854/O LUT4 4.22 6.78 dn
reg_cff(0)/CE FDCE 6.78 dn

There is a danger here that you are improperly constraining the design,
gp through P&R, pass timing (based on the constraints) yet still fail
required behaviour on the PCB. It is a common mistake when setting
constraints in tools that are not pin-based. You can correct this by
creating explicit paths with a -FROM option.

o Set -from option, and synthesize.

• Edit the constraints file, multi_constraints.sdc to create a beginning

of a path from reg_cff and reg_dff:

set_multicycle_path 16 -to { reg_output_cd(*)}

becomes
set_multicycle_path 16 -from { reg_cff(*) } -to { reg_output_cd(*) }
set_multicycle_path 16 -from { reg_dff(*) } -to { reg_output_cd(*) }

11-36 Designing with FPGA Advantage

November 2003
Synthesis Methodology

• Close and save the Constrains file, recompile and resynthesize.

What is the reported clk frequency for the clk________________

• Verify that the Timing report shows the output register in the critical
path again, as in Part 3.

This is the correct way to define multicycle paths on an instance

basis

• Open the Xilinx User Constraints File and observe the FROM/TO
TIMESPEC commands created by Precision.

Because pin-based constraints require fewer constraints in the

downstream tools, they may be preferable to these instance-based
ones, but the choice is yours.

o Exit Precision, do not save project settings

• Part 5: Adding a false path.

We will add a pin-based false path to the clock enabling flop in this design
to illustrate setting a false path. Repeat part 4 upto the point of editing the
constraints file.

o Edit the constraints file, multi_constraints.sdc to add a false path to

every clock enable pin of the multicycle-based registers. (This could be
done via the Design Hierarchy pull down menus as seen earlier)

set_false_path -to { reg_output_cd(*)/ce }

set_false_path -to { reg_cff(*)/ce }
set_false_path -to { reg_dff(*)/ce }

This is a nonsensical constraint, but we are using it simply as an

example of the process.

o Compile and synthesize the design.

What is the reported clk frequency for the clk________________

Designing with FPGA Advantage 11-37

November 2003
Synthesis Methodology

Now the clock frequency is reliant only upon the very tightly coupled
implementation, and not the decoding of the counter to all of the clock
enables in this small example.

o Now run the ISE 5.2 Place & Route, and when it is finished, open the
timing report and confirm the clk critical path is now reported as the
counter only.

o Exit Precision, do not save project settings.

Design Assembly for Xilinx

Introduction

The purpose of this lab is to illustrate the benefits of being able to assemble a
complete design within the Precision environment.

First we are going to generate a sub-block processor interface. This processor

interface consists of some I/O that will connect internally, and some I/O that go
directly to the FPGA pins. Precision enables the user to selectively decide which
I/O will have physical buffers added. We use the “NOPAD” command to do this.

Directions

• Part 1: Prepare the design.

o Add mapping for the library multiplier, using the following settings:
• Regular Library
• Library Name: assembly
• Directory: $FPGADV_LABS/synth_labs
• Downstream Data Directories for Modelsim and Precision
• No Version Management
• Not default library

11-38 Designing with FPGA Advantage

November 2003
Synthesis Methodology

o After adding the library, open it to

see the design units.

o Create a coregen part to be used by

the processor interface

• Activate the Xilinx CORE

Generator from the Task pane
of the Design Manager window.

Ensure the settings are as shown

here, then click on the Invoke
CORE Generator button at the
bottom of the dialog.

The Xilinx tool dialog will open.

o Create a coregen part to be used by the processor interface, choosing

the options shown below. Double click on the Distributed Memory
line.

o Set up the memory using the three pages to define the parameters and
the following options:
• component name: my_dpram
• depth: 256
• Data Width: 8
• Memory Type: Dual Port RAM
• Multiplexor Construction: LUT Based
• Input Options: Non-Registered

Designing with FPGA Advantage 11-39

November 2003
Synthesis Methodology

• Dual Port Address: Non-Registered

• Layout: Create RPM
• Output Options Non-registered. no latency
• Initial Contents: No initial contents.
• Reset: There are no reset options

• Click on Generate.
When the generate process is complete an information message will
occur. Click on OK. Click on Dismiss.

• Close the Xilinx Window.

• Click on ‘Done’ on the HDL Coregen dialog.
o Check that the component my_dpram now exists in the library
‘assembly’.

• Look in the side data section to check that the file my_dpram.edn
has been generated, this will be used by Precision later on.

• Open the Design Hierarchy panel, and look at the hierarchy of the
component processor_if.

o Invoke the Precision Design Flow on the processor_if unit, using the
following settings:

Within the Setup tab

• Technology: VirtexII

• Device: 2V40cs144

• Speed Grade: -4

• Add IO Pads: yes

• Clock Frequency: 50 MHz

• Output Formats: EDIF

11-40 Designing with FPGA Advantage

November 2003
Synthesis Methodology

• Run Options: ‘Compile’, ‘Synthesize’

Within the General tab

• Constraints files:Include SDC Constraints files.

• Do not alter any other settings in this tab.
The SDC constraints file is simply to save time setting the NOPAD
constraints. It contains four lines to prevent buffers being added to
blocks that will connect internally.

set_attribute -name NOPAD -value "TRUE" -port rst_n

set_attribute -name NOPAD -value "TRUE" -port address_two(*)
set_attribute -name NOPAD -value "TRUE" -port flag
set_attribute -name NOPAD -value "TRUE" -port read_data(*)

It will override the ‘Add I/O pads’ setting for these 4 pins. All other
pins should have buffers added.

• Part 2: Synthesize sub-block.

o Precision opens, and the design is compiled and synthesized.
Investigate the results.

• What files are listed as Input files?

_______________________________________________________

• Open the technology Schematic.

• Find the dpram instantiation and double-click on it to open down
into it.

Look for the RAM Primitives from the Coregen netlist. The
assemble of the design ensures that the timing through the Coregen
blocks can be seen and taken into account in synthesis, not just in
P&R.

• Locate the rst_n port in the design browser.

Designing with FPGA Advantage 11-41

November 2003
Synthesis Methodology

• Trace forward one level of logic and highlight the schematic to see
that it directly drives a LUT1 (inverter) and does not have and I/O
Buffer associated with it.

• Use the Design Browser to see whether a BUFGP has been inserted
for the wr_bar input (N.B. This is a clock).

• Check that the only I/O without buffers are those defined in the
Constraints file.

o Examine the timing report.

What is the estimated performance for wr_bar?________________

An EDIF netlist and binary database (.xdb) have been written into the
implementation directory. Now we will start to assemble the entire
design.

o Exit Precision, do not save project settings

• Part 3: Synthesizing the Top level.

o Invoke the Precision Design Flow on the top_level unit only - use the

single level only option , and the following settings:

Within the Setup tab

• Technology: VirtexII
• Device: 2V40cs144
• Speed Grade: -4
• Add IO Pads: \ yes
• Clock Frequency: Do not define.
• Output Formats: EDIF
• Run Options: ‘Compile’

Within the General tab

• Constraints files: Include SDC Constraints files.
• Do not alter any other settings in this tab.

11-42 Designing with FPGA Advantage

November 2003
Synthesis Methodology

The SDC constraints file has the required NOPAD constraints for I/O
that have already been synthesized in the lower level. It also sets
constraints for the clocks.

set_attribute -name NOPAD -value TRUE -port data(*)

set_attribute -name NOPAD -value TRUE -port address(*)
##################
# Clocks
##################
create_clock { sys_clk } -domain sys_clk_domain -name sys_clk -
period 20.000000 -waveform { 0.000000 10.000000 }
create_clock { wr_bar } -domain wr_bar_domain -name wr_bar -period
30.00000 -waveform { 0.000000 15.000000 }
#Illustrative constraints to demonstrate pin2pin effects
set_input_delay 11 -clock wr_bar wr_en
set_input_delay 11 -clock wr_bar rd_bar
set_input_delay 11 -clock wr_bar data(*)
set_input_delay 11 -clock wr_bar address(*)
set_output_delay 7 -clock wr_bar data(*)
# With a 30 ns clock period, 11 ns input delay and 7 ns output
delay, we have a Tpd of 12 ns

o Precision opens, and the design is compiled. Investigate the Design

Hierarchy before synthesis.

• What clocks are identified at this point? ___________________

• Open the “Instances Folder in the Design Hierarchy, and open the
sub-folder “Black Boxes”. You will see that the processor interface
is merely a black box.

o Synthesize this single level and investigate results.

• Press Synthesize.
• Examine the timing report. You will see that there is no timing
information available for the wr_bar because it is contained totally
within the black box.

What is the reported frequency for sys_clk? ________________

There is not frequency for wr_bar, as no logic is seen to be driven by

it, because of the black box methodology.

Designing with FPGA Advantage 11-43

November 2003
Synthesis Methodology

By the two clock frequencies that you have seen (wr_bar when you
synthesized the processor_if, and sys_clk just here), it might appear that
the performance of the design should exceed the 33 MHz and 50 MHz
constraints in the SDC. However, with a black box hole in the design,
you cannot really be sure until you go through Place & Route. We will
not do this now, but will first assemble the design by adding the .xdb
file that we previously created.

• Part 4: Assembling the design.

o Add the xdb file from the Processor_if synthesis run.

• Click on the ‘Add Input File’ icon on the Design Bar, this brings up
an ‘open’ dialog window.

• Choose the file

processor_if_rtl/processor_if_impl_1/processor_if.xdb to open.
This will involve going up one level, and then down again.

• Check that it is now one of the input files.

o Compile the design, and check that the black box has been correctly
added.

• Check the Clocks, which signals are now defined as clocks?

________________________________________________

• Look in the Instances folder in the Design Hierarchy, you should see
that the Processor Interface is no longer a ‘black box’.

• Open the RTL schematic. If you look you will see that the top_level
is RTL, but the inside the processor_if block the design already
contains Xilinx primitives, from the previous synthesis.

o Complete the design.

• Synthesize.
• Check the timing report.

11-44 Designing with FPGA Advantage

November 2003
Synthesis Methodology

What is the reported frequency for sys_clk? ________________

What is the reported frequency for wr_bar? ________________

Note that Precision is reporting on the whole external system

performance pin-to-pin that passes through the DPRAM elements.
There may be a little negative slack that you might not have been
aware of in the system, and the Xilinx timing analysis does not report
on because the wr_bar is a clock!

• Run Xilinx P&R tools inside Precision by pressing the

“Place & Route” button. This will confirm the assembly of the
entire design by Precision.

o Exit Precision, do not save project settings. Exit HDL Designer.

Designing with FPGA Advantage 11-45

November 2003
Synthesis Methodology

11-46 Designing with FPGA Advantage

November 2003
Module 12
Verification Methodology

Objectives
This module will cover the following topics:

• Post-Place and Route Gate-Level Verification

• Compiling Vendor Libraries
• Simulation Comparison using ModelSim Waveform Compare
• Code Coverage
• Virtual Signals and Functions

Designing with FPGA Advantage 12-1

November 2003
Verification Methodology

Post-Place and Route Timing Analysis

♦ Most accurate timing analysis
! Uses delays computed by vendor P&R tools
! Verify timing on routed design meets constraints
! Final checks on design before commit to silicon

♦ Reasons for gate-level simulation

! RTL simulation generally has no information about gate timing
! Initial values of Signals, Variables and Registers may be different
! Design initialization of enumerated data types may be different

♦ Uses test bench as final check

! Compare RTL Design against Gate-Level Design

Notes:

12-2 Designing with FPGA Advantage

November 2003
Verification Methodology

Post Layout Timing Verification using

FPGA Advantage

Post Layout Timing Verification using FPGA Advantage

♦ When RTL design and verification is finished, a final comprehensive
simulation is run with the output waveformfile saved e.g. RTL_gold.wlf
♦ Perform Synthesis and Place & Route, instruct P & R tool to write a
VHDL/Verilog netlist of the implemented design
♦ Import gate level HDL and SDF as alternative views in HDL Designer
! Be sure to import the HDL netlist to the correct Design Unit
♦ For simulation use same test bench as for RTL design
! Problems may arise, when the toplevel RTL design uses abstract data types,
cause the P&R tool does only use std_logic scalar and vector data types
! To avoid this there are two possible solutions
– use only std_logic scalar and vector data types at the toplevel design unit
(recommended)
– use a wrapper Design Unit which “translates” the data types
♦ Automatically compare the gatelevel simulation with the previously saved
RTL_gold.wlf RTL simulation
! Use ModelSim waveform compare functionality for clocked or continuous
comparison

Notes:

Designing with FPGA Advantage 12-3

November 2003
Verification Methodology

Gate-Level Simulation Process

♦ Do final RTL simulation on RTC_tb

♦ Perform Synthesis on RTC

♦ Perform Place & Route on RTC

! Setting has to be made in Precision
Synthesis Options
! instruct P&R tool to write a
VHDL/Verilog netlist of the
implemented design

Notes:

12-4 Designing with FPGA Advantage

November 2003
Verification Methodology

Import Gate Level into HDL Designer

♦ Back annotate your design by importing a VHDL or Verilog
gate level netlist created from a P&R tool by choosing
“Import Gate Level…” from the popup menu
♦ Select the path to the HDL netlist and to the SDF file

Notes:

Designing with FPGA Advantage 12-5

November 2003
Verification Methodology

Import Gate Level into HDL Designer

(Cont.)

Import Gate Level into HDL Designer (Cont.)

♦ The gate-level netlist and SDF file
get imported into the selected
Design Unit
♦ The new View is set as
“Default View”, thus the test
bench can be simulated instantly
♦ The Design Unit’s icon gets a
little marker denoting that there
is a gate-level view underneath
♦ The Side Data window shows the
associated SDF file

Notes:

12-6 Designing with FPGA Advantage

November 2003
Verification Methodology

Prerequisites for Gate Level Simulation

♦ Technology Libraries must be available in ModelSim
! SIMPRIM (XILINX)
! alt_vtl (ALTERA)
♦ Howto get them into ModelSim:
! Import Library dialog
– get precompiled library from
FPGA vendor
– ModelSim: File > Import Library
! Use compile script
– get compile script from
FPGA vendor
– Execute script:
ModelSim: Macro > Execute Macro
! Xilinx provides a tool called “compxlib” to compile the libraries
for various technologies, HDL languages and simulators.
(available with ISE 5.x and later)

Notes:
To compile the XILINX libraries open a Command Prompt (Windows) or a Unix
shell. Type the command as follows:

compxlib -s mti_se -f spartan2:c -l vhdl -o

$FPGADV_LABS\xilinx_libs

This will compile the Spartan2 CoreGen library VHDL models for ModelSim into
the specified directory.

If you want to see the program's options type "compxlib -help".

Designing with FPGA Advantage 12-7

November 2003
Verification Methodology

Waveform Compare

Waveform Compare
♦ Quickly identify errors
! Focus on initial cause of failure
! Review results with waveform viewer or ASCII reports
♦ Fastest, most complete waveform compare
! Continuous compare
– With or without tolerances (leading, trailing or both)
! Clocked compare
– Rising or Falling edge
– Delayed Clock Compare
! Complex conditional compares based on logic values with or
without time offset
! Integrated with waveform database
♦ Interactive or batch mode
♦ Language independent

Notes:

12-8 Designing with FPGA Advantage

November 2003
Verification Methodology

Waveform Compare — Continuous and

Clocked

Waveform Compare — Continuous and Clocked

Notes:

Designing with FPGA Advantage 12-9

November 2003
Verification Methodology

Complex Conditional Compare

Compare data only

when reset equal 1
200 units before
data

Compare data only

when reset equal 1

Notes:
The following is a script for a complex compare of waveforms:

set PrefCompare(defaultVHDLXMatches) XU
dataset open 0.wlf gold
dataset open 5.wlf test
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {Golden Simulation Results}
add wave -radix hex -r gold:/*
quietly WaveActivateNextPane
add wave -noupdate -divider {Test Simulation Results}
add wave -radix hex -r test:/*
quietly WaveActivateNextPane
add wave -noupdate -divider {Compare data if reset inactive}

12-10 Designing with FPGA Advantage

November 2003
Verification Methodology

compare start gold test

# test delayed when condition:
#compare if reset is inactive 20ns before and data change
compare signal -tolL {3 ns} -tolT {2 ns} -label
reset_inactive_20nsbefore /tst_pseudo/chip/data -when {#-200
reset==1}
#compare if reset inactive
compare signal -tolL {3 ns} -tolT {2 ns} -label reset_inactive
/tst_pseudo/chip/data -when {reset==1}
compare run
compare info
compare info ñprimaryonly
compare info ñsecondaryonly

Designing with FPGA Advantage 12-11

November 2003
Verification Methodology

Simulation Comparison

♦ There is a very easy way to validate the post-synthesis (eventually back-annotated

simulation results using the waveform comparison feature of ModelSim 5.7)

♦ Use Menu Tools > Waveform Compare > Comparison Wizard …

♦ Then you follow the wizard indications …

♦ Select the previously saved waveform file from

the“golden” RTL simulation

November 2003
Verification Methodology

• ModelSim reports incorrect coverage of case statements where multiple

expressions match the same alternative. To get the correct behavior, you
must remove optimizations of case statements by specifying the -
coverBranch argument when you compile your design. See the vcom
command or vlog command for further details.

• Package bodies are not instance-specific; we sum the counts for all
invocations no matter who the caller is. Also, all standard and accelerated
packages are ignored for coverage statistics calculation.

Designing with FPGA Advantage 12-17

November 2003
Verification Methodology

Code Coverage: File Coverage Overview

♦ The file coverage overview provides a quick impression on

how comprehensive the test bench has tested the design.
♦ It also helps to find redundant code in the design
♦ The percentage of coverage (default 90%) that shows a green
bar is set via a TCL parameter $PrefCoverage(cutoff)

Notes:
• The Stmt Count column contains the number of executable statements in
each file.

• The Stmt Hits column contains the number of executable statements that
have been executed in the current simulation.

• The Stmt Percent column is the current ratio of Stmt Hits to Stmt Count.
• The Stmt Graph is a bar chart displaying the Stmt Percent. If the Stmt
Percent is below 90%, the bar is red; over 90%, the bar is green. You can
change this threshold percentage by editing the PrefCoverage(cutoff)
preference variable.

12-18 Designing with FPGA Advantage

November 2003
Verification Methodology

• The Branch Count column contains the number of executable branches in

each file.

• The Branch Hits column contains the number of executable branches that
have been executed in the current simulation.

• The Branch Percent column is the current ratio of Branch Hits to Branch
Count.

• The Branch Graph is a bar chart displaying the Branch Percent. If the
Branch Percent is below 90%, the bar is red; over 90%, the bar is green.
You can change this threshold percentage by editing the
PrefCoverage(cutoff) preference variable.

You can sort code coverage information for any column by clicking the column
heading. Clicking twice will reverse the order.

Designing with FPGA Advantage 12-19

November 2003
Verification Methodology

Code Coverage: Source Window Display

Notes:
The Branch tab also includes a column for line numbers, as well as a column for
branch code (conditional "if/then/else" and "case" statements).

"X" indicates the branch was not executed.

"XT" indicates that only the true condition of the branch was not executed.

"XF " indicates that only the false condition of the branch was not executed.
Fractional numbers indicate how many case statement labels were not executed.
For example, if only one of four case labels was executed, the Branch tab would
indicate "X 1/4."

12-20 Designing with FPGA Advantage

November 2003
Verification Methodology

Statement Execution Coverage

♦ For Line coverage the line z=0; is one countable line, the same
if using Statement Coverage
♦ For line coverage the line if (x==0)z=1; z=1 will be counted as a
hit regardless if x==0 is true or false. If you employ Statement
execution metrics z=1; will be counted only if x==0 is true

always @ (x or y) begin
z = 0;
if (x == 0) z = 1;
end

Notes:
The example contains three countable statements. The statement z = 0; is one
countable statement. The if statement, however, can be viewed as either one or
two countable statements. if (x == 0) z = 1; is two more countable statements.
This makes this coverage metric more useful than line coverage because with line
coverage it would be considered covered even if z = 1 did not get executed.

Statement coverage would also allow multiple statements to be coded on a single

line and still be analyzed correctly.

Designing with FPGA Advantage 12-21

November 2003
Verification Methodology

Branch or Decision Coverage

♦ Branch Coverage measures the coverage of
expressions and case statements that effect
control flow if (x == 0)
z = 1;
♦ Branch coverage reports if the if x==0 branch else begin
was tested true or false
z = 0;
end
♦ For case statements Branch coverage will
report if x was tested 1, 2 or 3. The first case
line 1,2:z=1, 1 and 2 will be reported separately
case (x)

♦ For this same case example, Statement 1,2: z= 1;

coverage would report the first case line 1,2: 3: z=0;
z=1; if x was 1 or 2.
endcase
Branch coverage is needed in addition to
Statement coverage

Notes:
Decision coverage or branch coverage measures the coverage of expressions and
case statements that affect the control flow of the HDL execution--for example:

if (z == 0) begin
...
else begin
...
End

This example contains a branch that could be exercised in one of two ways.
Branch coverage will report whether the if statement was evaluated as both true

12-22 Designing with FPGA Advantage

November 2003
Verification Methodology

and false during simulation. Note that decision coverage still applies if the else
statement doesn't exist, as in the following example:

if (z == 0) begin
...
end

The if statement can still be evaluated as both true and false; branch coverage will
still verify that both the explicit branch (z = 0) and the implicit branch (z = 1) are
executed. Branch coverage also applies to case statements:

case (z)
1: x = 0;
2: x = 10;
3: x = 20;
endcase

In this example, branch coverage will verify that each of the three branches of the
case statement is taken. In this particular example, however, the same information
could be obtained from statement coverage, since each leg of the case statement is
a separate statement. However, in the example:

case (z)
1,2: x = 0;
3: x = 10;
endcase

statement execution coverage will consider the line 1,2: x = 0; covered if a is 1 or

2. Branch coverage analysis is needed to verify that z has been both 1 and 2 during
simulation.

Designing with FPGA Advantage 12-23

November 2003
Verification Methodology

Combining Signals

Combining Signals
♦ Signals or busses can be combined
together into new busses
♦ These are created using “Virtual
Signals”

Notes:

12-24 Designing with FPGA Advantage

November 2003
Verification Methodology

Virtual Objects

Virtual Objects
♦ User Defined objects to generate context native to Engineer
♦ Objects created in the user-interface to display combinations
or expressions of logged signals in the design
♦ Multiple Object Types
! Virtual Signals
! Virtual Functions
! Virtual Types
! Virtual Regions

Notes:
Virtual objects are signal-like or region-like objects created in the GUI that do not
exist in the ModelSim simulation kernel.

Designing with FPGA Advantage 12-25

November 2003
Verification Methodology

Virtual Signals

Virtual Signals
♦ Create meaningful definitions
♦ Aliases For Combinations Of Signals
♦ Aliases For Subelements Of Signals
♦ Can Be Displayed In …
! Signals Window
! List Window
! Wave Window
♦ Accessed Using "examine”
♦ Set Using "force"
♦ Created by menu selections or "virtual signal" command

Notes:
Virtual signals are aliases for combinations or subelements of signals written to
the logfile by the simulation kernel. Virtual signals may be displayed by the
signals, list or wave window, accessed by the "examine" command, and set using
the "force" command.

Virtual signals may be created by menu selections in the signals, wave or list
windows, or created by the "virtual signal" command

12-26 Designing with FPGA Advantage

November 2003
Verification Methodology

Create Meaningful Definitions with

Virtual Signals

Create Meaningful Definitions with Virtual Signals

virtual signal -install sim:/testbench { /chipa/alu/a(19 downto 13) &

/chipa/decode/inst & /chipa/mode } stuff

/chipa/mode is of type integer

/chipa/alu/a is of type std_logic_vector
/chipa/decode/inst is a user-defined enumeration
Produces sim:/testbench/stuff which is a record type

add wave sim:/testbench/stuff

added to the waveform window

virtual signal { chip.instruction[23:21] } address_mode

Produce alias chip.address_mode

Notes:
Examples of virtual signals:

virtual signal -install sim:/testbench { /chipa/alu/a(19

downto 13) & /chipa/decode/inst & /chipa/mode } stuff

Assuming /chipa/mode is of type integer and /chipa/alu/a is of type

std_logic_vector, and /chipa/decode/inst is a user-defined enumeration, this
example creates a signal sim:/testbench/stuff which is a record type with three
fields corresponding to the three specified signals.

Designing with FPGA Advantage 12-27

November 2003
Verification Methodology

virtual signal { chip.instruction[23:21] } address_mode

This creates a three-bit signal, chip.address_mode, as an alias to the specified

bits.

12-28 Designing with FPGA Advantage

November 2003
Verification Methodology

Virtual Functions

Virtual Functions
♦ Create logical representations of existing signals
! Inverse Of A Signal
! A Type Conversion
! OR-Reduction
! XOR Of Two Vector Signals
♦ Logical Operations On Logged Signals
! Not Aliases of combinations or elements
♦ Can Be Displayed In …
! Signals Window
! List Window
! Wave Window (Expand Children)
♦ Accessed Using "examine”
! Can Not Be Set Using "force"

Notes:
Virtual functions behave in the GUI like signals but are not aliases of
combinations or elements of signals logged by the kernel. They consist of logical
operations on logged signals and may be dependent on simulation time. They may
be displayed in the signals, wave or list windows, accessed by the "examine"
command, but cannot be set by the "force" command.

An example would be a virtual function defined as the inverse of a given signal, a

type conversion on a signal, or a the OR-reduction of the XOR of two vector
signals.

Designing with FPGA Advantage 12-29

November 2003
Verification Methodology

Virtual Function Examples

virtual function {not /chip/section1/clk } clk_n
/chip/section1/clk_n becomes inverse

virtual function -install /chip { (std_logic_vector) chip.vlog.rega } rega_slv

Converts and installs into /chip

virtual function {/chip/addr[11:0] == 0xfab } addr_eq_fab

Boolean Signal true when signal equals hex FAB

virtual function {gate:/chip/siga XOR rtl:/chip/siga} siga_diff

High when /chip/siga of the gate-level version of a design does not
match /chip/siga of the rtl version of a design.

add wave siga_diff

adds the above function to the waveform window

Notes:
Examples of virtual functions:

virtual function { not /chip/section1/clk } clk_n

Creates a signal /chip/section1/clk_n which is the inverse of /chip/section1/clk.

virtual function -install /chip { (std_logic_vector)

chip.vlog.rega } rega_slv

Creates a std_logic_vector equivalent of a verilog register "rega" and installs it as

/chip/rega_slv.

12-30 Designing with FPGA Advantage

November 2003
Verification Methodology

virtual function { /chip/addr[11:0] == 0xfab } addr_eq_fab

Creates a boolean signal /chip/addr_eq_fab that is true when /chip/addr[11:0] is

equal to hex "fab", and false otherwise. It is ok to mix VHDL signal path notation
with Verilog part-select notation.

virtual function { gate:/chip/siga XOR rtl:/chip/siga) }

siga_diff

Creates a signal that is non-zero only high during times at which a signal
/chip/siga of the gate-level version of a design does not match /chip/siga of the rtl
version of a design.

Designing with FPGA Advantage 12-31

November 2003
Verification Methodology

Lab 12: Verification Methods

♦ Lab Goal: Perform verification methods that help testing the
design thoroughly

! Part 1: Perform Gate-Level Verification

! Part 2 : Compare RTL vs. Gate-Level Simulation

! Part 3: Code Coverage Lab

Notes:

12-32 Designing with FPGA Advantage

November 2003
Verification Methodology

Lab 12: Verification Methods

Gate-Level Verification
Introduction

In this lab, you will synthesize and Place & Route the RTC design. Then you will
import the gate-level netlist into HDL Designer and run the gatelevel simulation.
Then the gatelevel simulation will be automatically compared against the RTL
simulation.

Directions

• Part 1: Perform the “golden” RTL simulation.

Open the RTC
Library, and start
ModelSim on the
RTC_tb Design
Unit and name the
waveformfile
RTL_gold.wlf.

o When ModelSim has started open the wave window and add all toplevel
signals to the wave window.

o Run the simulation for 100 us and verify that the Clock is working
correctly.

o Quit ModelSim. The waveform file is automatically saved at exit.

Designing with FPGA Advantage 12-33

November 2003
Verification Methodology

• Part 2: Synthesize and Place & Route the RTC design using the following
settings:

Using these settings the synthesis process

AND the Place & Route run are performed.
At the end you can inspect the output files
of Precision and the P&R tool in the Project
Files section of Precision.

(Note: if the Place and Route doesn’t run

automatically, check that the path is
correctly set in the Precision Synthesis
settings in HDL Designer. $Xilinx doesn’t
seem to work, it should be the full path
name to the Xilinx installation).

Close Precision without saving the project.

12-34 Designing with FPGA Advantage

November 2003
Verification Methodology

• Part 3: Import the VHDL netlist into HDL Designer

Switch to HDL Designer and in Design Explorer select the RTC Design
Unit. Use RMB: Import Gate Level ... to import the VHDL and SDF file,
which was generated by the P&R tool.

Select the RTC_out.vhd file from the shown directory and also the
RTC_out.sdf file at the SDF section of the dialog box.

o Click “OK”. There will be a new Design View, already set as default
view, under the RTC Design Unit:

Designing with FPGA Advantage 12-35

November 2003
Verification Methodology

• Part 4: Run the Gate-Level simulation

o Start the Gate-Level simulation by selecting the RTC_tb Unit and
using the Simulation Flow button. Name the waveform file gate.wlf at
the “Start ModelSim” dialog box.

o When ModelSim has started open the wave window and add all toplevel
signals to the wave window.

o Run the simulation for 10 us

• Part 5: Perform Waveform Compare

o From the ModelSim main window choose option Tools > Waveform
Compare > Comparison Wizard. Browse to the golden simulation
results from the previous simulation run “RTL_gold.wlf” and click on
“Next >”.

12-36 Designing with FPGA Advantage

November 2003
Verification Methodology

Choose Specify Comparison by Signal on the next form:

Choose the signal “data_out” as comparison signal, click on Next >.

Answer NO in the next form. Finally click on Compute Differences Now

and Finish.

o In the wave window you see a comparison between the result of the first
simulation (GoldenResults) and the current simulation. The current
simulation uses delay information (stored in the SDF file) from the
P&R process. The output wave_out therefor shows a delay in the wave
window. During the comparison you receive a lot of differences due to
the delay of the “real” design. The next picture displays the wave

Designing with FPGA Advantage 12-37

November 2003
Verification Methodology

window and one of the differences due to the delay of the gate
simulation..

The delay of 10 ns is acceptable for this simulation since we have a

clock period of 50 ns. Therefore these differences should not be
reported as errors. During the next steps you will set a trailing tolerance
to allow 40 ns delay. Then compare again to see if there are still
violations.

o Execute Tools → Waveform Compare → End Comparison. Start the

comparison wizard again (see before). This time you will compare the
signals with a tolerance of 40 ns for the trailing edge. The design has no
delay longer than 40 ns to the signal data_out attached.

o Choose the reference dataset, and click on “Next >”. Before choosing
the signals, we need to set the tolerance.

o Open the comparison options with Tools → Waveform Compare →

Options… Select the Comparison Method tab. Change the Trailing

12-38 Designing with FPGA Advantage

November 2003
Verification Methodology

Tolerance to 40 ns to allow the “real” design to settle. Execute the form

with OK.

o Now go back to the Comparason Wizard dialog and complete the setup
as before.

o The red lines in the wave window (indicator for waveform compare
errors) should disappear and ModelSim displays the following
messages in the main window:

# Computing waveform differences from time 0 ns to 10 us

# Found 0 differences.

o Quit ModelSim.

Code Coverage Lab

Introduction

ModelSim Code Coverage allows you to identify which lines in your code are
being covered by the testbench. It is non-intrusive (instrumented code is not
required) and only minimally impacts simulation performance (<5%).

This lab introduces ModelSim’s Code Coverage feature, details the use of the
major Code Coverage commands, and shows how to append results from more
than one simulation run.

Directions

• Part 1: Disable Compiler code optimization to get true coverage reports.

o At the HDL Designer Task bar right click on the
“ModelSim Compile” icon and choose the “Settings”
command from the popup menu. At the “ModelSim
Compile Settings” dialog box choose the “VHDL” tab.

Designing with FPGA Advantage 12-39

November 2003
Verification Methodology

o At the “Additional Options” field enter the compile

option “-O0” (Capital O, Zero)

o Click “OK” to close the dialog.

Since a compiler option was changed it is necessary to ensure that the

HDL code is recompiled next time when simulation is started. By
default the HDL code is compiled only when the source code has
changed.

o At the HDL Designer’s Design Manager window click on the Tasks

menu and choose the “Set Compile always” option.

• Part 2: Simulate the RTC_tb design using the ModelSim CodeCoverage

option. Inspect the design instances for statement and branch coverage.

Remember to set the default view of RTC back to the ‘struct’ view, if you
have just been working with the gate level netlist.

o Open the RTC library, select the RTC_tb design unit and start
simulation by clicking on the “Simulation Flow” button. At the “Start

12-40 Designing with FPGA Advantage

November 2003
Verification Methodology

ModelSim” dialog add the simulator argument “-coverage” to enable

Code Coverage analysis during the simulation:

o When ModelSim starts you will see three additional window panes at
the ModelSim main window: The “Missed Coverage” “Current
Exclusions” and “Instance Coverage” windows. Since no simulation
has been run so far all reports are empty.

o Open the wave window and display all top level signals (rtc_tb) plus
the signals time_dd, time_hh, time_mm and time_ss from the rtc
design unit.

o Format all the 8-bit vector signals in the wave window with the display
radix “Hexadecimal”

o Run the simulation for 50 us.

o The “Instance Coverage” window shows poor coverage on all but two
instances.

This is due to the short simulation time, cause the minute, hour and day

Designing with FPGA Advantage 12-41

November 2003
Verification Methodology

registers of the clock were idle until now. Therefore they show little
coverage.

o Run the simulation five times for 10 ms and observe how the coverage
bars are rising. After a certain simulation time, the coverage percentage
of the most instances does no longer increase. Most of them show
between 40% and 80%, which is not acceptable unless you verified the
cause. During the following steps you will inspect some instances and
either correct the design/testbench or designate the “coverage miss” as
“feature”.

• Part 3: Raise coverage by changing the design or testbench.

o First observe the address_decode and data_out_mux instances:

o Select the address_decode instance in the Workspace-Instance

window. Use RMB > View Source to open the HDL Source window.
You can use the ModelSim’s different analysis capabilities to get
information about the coverage misses:

o Take some time to understand the coverage reports and try to find out
the reason for the coverage misses.

o The reason for the coverage misses is pretty obvious. The testbench did
not load the clock registers with new values. Therefore the
address_decoder and also the data_out_mux show coverage misses.
This is a “testbench problem” which can easily be solved by adding the
functionality to the testbench.

12-42 Designing with FPGA Advantage

November 2003
Verification Methodology

o There is a version of the RTC_tester design unit already prepared, that

implements that load functionality. Open the coverage design view of
RTC_tester and switch to the “Tester” process and try to understand
the added functionality.

o In HDL Designer set the coverage design view of

RTC_tester as default view. Do NOT exit
ModelSim, when making the change in HDL
Designer. When the Simulation Flow is started on a
modified design, ModelSim just reloads the modified
design units, restarts the simulation and keeps all the
setup settings.

o In HDL Designer select the RTC_tb design unit and start the
“Simulation flow”. Run the simulation for 60 us.
Now you will see that both design units (address_decoder and
data_out_mux) show no more coverage misses.

• Part 4: Raise coverage by excluding HDL sections that intentionally have

redundant code

o Select the one of the tens counter instances, e.g. the

rtc_tb/i0/registers/i0/tens in the Workspace-Instance window. Use
RMB > View Source to open the HDL Source window.

The coverage misses at lines 47-48 and 52-54 are within the logic that

Designing with FPGA Advantage 12-43

November 2003
Verification Methodology

handles the rollover from 9 to 0 and produces the carry_out signal. But
in the RTC_Clock design none of the tens counters ever encounters a
rollover from 99 to 00. The Registers are forced to rollover at 59, 23
and 6. Therefore the reported coverage misses are a intended feature.
To get true coverage reports it is necessary to exclude these sections
from coverage reporting.

o At the HDL Source window place the

cursor over the “X” at line 48 and use the
popup menu command “Exclude
Coverage Line 48”. The “X” is then
replaced by an “E”, abbreviation for
“Exclude”.

o Repeat this for all other lines that show “X”.

o Why wouldn’t it make sense to use the “Exclude Entire File” command,
since we excluded all reported lines? __________________________

o The coverage report of the tens counter should now show green bars for
Statement and Branch coverage.

• Part 5: Optional. Measure performance impact of Code Coverage.

There is a TCL command available in ModelSim to measure the time which
the execution of the specified command needed. The syntax is:

time {command}

and the output is like:

# 13730000 microseconds per iteration

Caution: The measured time is real time, not processor/kernel time.

Therefore in order to get true repeatable results it is necessary to have no
other processor or file I/O intensive programs running on the machine.

o Restart the simulator.

12-44 Designing with FPGA Advantage

November 2003
Verification Methodology

o Run the simulation for 100 ms and measure the time with Code
Coverage. Type the following at the VSIM command prompt:

time {run 100 ms}

o Simulation time in seconds: ________________

o Save the setup of the waveform window: File > Save Format.

o Exit the simulation by typing the following at the command prompt:

quit -sim

o Resimulate the RTC_tb without Code Coverage:

vsim rtc.rtc_tb

Restore the setup of the waveform window: File > Load Format.

o Run the simulation again for 100 ms:

time {run 100 ms}

o Simulation time in seconds: ________________

o What is the difference in % between both runs? __________

o Quit the simulator.

vsim> quit -f

CONGRATULATIONS
You’ve got it!

Designing with FPGA Advantage 12-45

November 2003
Verification Methodology

12-46 Designing with FPGA Advantage

November 2003
Appendix A
Additional Block Diagram Features

Objectives
This module will cover the following topics:

• Find and Replace Facility

• Hierarchical Net Change
• Make Connections: Bus Ripper
• Make Connections: Bundle
• Reconcile Interface

Designing with FPGA Advantage A-1

November 2003
Additional Block Diagram Features

Find and Replace Facility

♦ The FIND facility can be
used to find and replace
text
♦ Selection can be filtered
by objects
♦ Can use regular
expressions
♦ Find results reported so
that individual changes
can be made or viewed

Notes:

A-2 Designing with FPGA Advantage

November 2003
Additional Block Diagram Features

Hierarchical Net Highlight

Clear Net Highlight

Highlight Net : - in Diagram
- in Hierarchy
1- Select the net

3- Status of what was

highlighted
2- Select the options

Notes:

Designing with FPGA Advantage A-3

November 2003
Additional Block Diagram Features

Hierarchical Net Change

For example I want to rename a signal through the hierarchy

1- Edit the signal properties (double-click)

2- Enter a new name

4- Choose the options

2- Rename the signal

3- Check the scope of the change

5- Check the status carefully !!!

(double-click on the line to get
to the source of the problem)

Eg: If you rename a signal that enters a language block, the interface of the block is
modified but not the HDL. You get a warning that the HDL must be modified accordingly!

Notes:

A-4 Designing with FPGA Advantage

November 2003
Additional Block Diagram Features

Even simpler ...

2- Create a bundle

1- Select a bunch of signals

3- The tool will pick the selected signals

and create the bundle

Notes:

A-8 Designing with FPGA Advantage

November 2003
Additional Block Diagram Features

Make Connections: Bundle (Cont.)

Signals can be ripped from

bundles

Notes:

Designing with FPGA Advantage A-9

November 2003
Additional Block Diagram Features

Reconcile Interface

Reconcile Interface
Interface Discrepancy between the symbol and the block diagram (1)

2- The View interface is no more up-to-date

1- You modify the symbol interface

Diagram → Reconcile Interface...

Notes:

A-10 Designing with FPGA Advantage

November 2003
Additional Block Diagram Features

Reconcile Interface (Cont.)

Interface Discrepancy between the symbol and the block diagram (2)

2- The Symbol interface is no more up-to-date

1- You modify the Block Diagram interface

When you save the inconsistency

in the interface is detected

Notes:

Designing with FPGA Advantage A-11

November 2003
Additional Block Diagram Features

Reconcile Interface (Cont.)

Interface Discrepancy between the child diagram and the Block (1)

Diagram → Reconcile Interface...

1- You modify the child diagram interface

2- The Block interface is out-of-date

Push down

3- You must reconcile the interface

Notes:

A-12 Designing with FPGA Advantage

November 2003
Additional Block Diagram Features

Reconcile Interface (Cont.)

Interface discrepancy between the child diagram and the Block (2)

Diagram → Reconcile Interface...

1- You modify the Block interface
2- The child Block interface is out-of-date

Push down

3- You must reconcile the interface

Notes:

Designing with FPGA Advantage A-13

November 2003
Additional Block Diagram Features

Reconcile Interface (Cont.)

Options → Master Preferences → Block Diagram

The symbol can be updated

automatically if requested

While reconciling you can:

– Make everything consistent
– Disregard the last change

Notes:

A-14 Designing with FPGA Advantage

November 2003
Appendix B
HDL Import / HDL2Graphics

Objectives
This module will cover the following topics:

• HDL Import / HDL2Graphics

• Block Diagram Options
• Routing Options
• Placement Options
• General Options

Designing with FPGA Advantage B-1

November 2003
HDL Import / HDL2Graphics

HDL Import Overview

♦ Import any HDL design into HDL Designer environment
! Automatically recovering structural relationships as hierarchy
! Ability to change imported HDL to graphics or keep as HDL text
! Many options to control the end-results
! Performs HDL checks
– non-strict checks
– detection of syntactic and semantic errors
– multiple declaration detection
– black-box detection
– any behavioral code accepted
♦ HDL Designer pragmas - hds translate_on / hds translate_off
! gives user the control to instruct HDL Designer to ignore chosen
fragments of HDL
– i.e.: instruct HDL Import to ignore specific fragments such as system
functions in Verilog

Notes:

B-2 Designing with FPGA Advantage

November 2003
HDL Import / HDL2Graphics

HDL Import: Step 1 — File selection

HDL → HDL Import

♦ In most of the cases no order is necessary

♦ Recursive search of the files when they are
spread out in several directories
♦ The file list can be saved for later use
♦ Mixed language can be imported

For unrecognized
extensions only

Notes:

Designing with FPGA Advantage B-3

November 2003
HDL Import / HDL2Graphics

HDL Import: Step 2 — Verification

Import only error free code

♦ The files are parsed and analyzed. Eventual warnings or errors can be reported at
that stage.
♦ The user decides which part of the design he’d like to import.

Notes:

B-4 Designing with FPGA Advantage

November 2003
HDL Import / HDL2Graphics

HDL Import: Step 3 — Context Definition

♦ The user defines the target library

♦ Black-boxes are detected. They can be resolved by
pointing to the relevant HDS library (eg: io_lib)
♦ The remaining BB will be marked in the browser

November 2003
HDL Import / HDL2Graphics

Converting HDL Views to Graphical

Views

Converting HDL Views to Graphical Views

♦ Some view types e.g. state machines, structural HDL is easier
to understand when displayed graphically
♦ HDL Designer converts text views into graphical ones

Select design view

Notes:

B-8 Designing with FPGA Advantage

November 2003
HDL Import / HDL2Graphics

Block Diagram Options

♦ Full control of the object visibility of the extracted views at import

ports on components when
this will simplify routing and
allow a more compact layout.

Notes:

B-14 Designing with FPGA Advantage

November 2003
HDL Import / HDL2Graphics

Block Diagram — Symbol Shape Options

♦ If Extract concurrent
assignments is set,
separate embedded
blocks are created for
each concurrent Verilog
assign statement or
VHDL signal
assignment statement
in the source HDL

Notes:

Designing with FPGA Advantage B-15

November 2003
HDL Import / HDL2Graphics

B-16 Designing with FPGA Advantage

November 2003
Appendix C
Version Management Using HDL
Designer

Objectives
This module will cover the following topics:

• Version Management Concepts

• HDL Designer Environment Setup
• Various Version Management Functions
• When to Use Reference

Designing with FPGA Advantage C-1

November 2003
Version Management Using HDL Designer

Version Management Concepts

♦ To track & audit changes made to files

♦ To retrieve previous versions of files

HDL Designer Environment

♦ Easy to use and customize
♦ Supports ClearCase V3 and V4 (Rational), DesignSync (Synchronicity),
VSS (Mainsoft Visual SourceSafe) or SoS (ClioSoft)
♦ Supports repository locations on remote servers
using a CVS pserver, RSH (remote shell) or SSH (secure shell) mechanism
♦ RCS V5.7 and CVS V1.11.1p1 are included in HDL Designer
! Included as part of HDL Designer installation
♦ Compatible with older repositories
! Configuration through Option → Version Management ...
! Support for HDL and downstream data and “Side Objects”
! Available in Browser and all Graphical Editors
! VM commands accessible via tool bar
Change Lock Label
Get Synchronize
Check Out Status
Check In History

Notes:

Designing with FPGA Advantage C-5

November 2003
Version Management Using HDL Designer

Setup

Setup
Options → Version Management...
Choose RCS, CVS, DesignSync,
VSS, SoS or ClearCase

Specify Repository
Directory

Including HDL,
default_view file and
Side Data Directory

Useful if the interface

is not changed

♦ Do not include default_view file can keep your own default view in your workspace

Notes:
You can always choose which design objects will be under version management.
These will always include source design unit views and any associated design side
data but you can optionally include the default_view file when you check in a
design unit or hierarchy of design units. For example, you may choose not to
check in the default view file if different users are working on views of the same
design unit and want to use a different default view in their local workspace. This
option is always ignored when you check in a single design unit.

If Associate symbol with views is set, any version management operation on a

design unit view of a component automatically also includes the symbol for the
design unit. However, you may want to unset this option when you want to check
out a view to make changes which do not modify its interface.

C-6 Designing with FPGA Advantage

November 2003
Version Management Using HDL Designer

Check In

Check In
♦ Check In the selected objects (libraries, design units and design unit
views) to the repository using latest or specified version

Single Level or Hierarchy

Associated packages

Refer to notes

Latest/Specified Version
To transfer an
Optional Label existing label

Description (optional)

To re-use the last

Notes:
You can optionally enable version management for user side data objects by
setting Side Data Directory. When this option is set, any user side data is also
checked in by default when you check in the corresponding design unit view.

Carefully use this option when the side data directory contains large binary files.

Designing with FPGA Advantage C-7

November 2003
Version Management Using HDL Designer

Check In (Cont.)

Before Check-In After Check-In

Notes:

C-8 Designing with FPGA Advantage

November 2003
Version Management Using HDL Designer

Check Out

Check Out
♦ Check Out selected objects from repository using latest/specified
version
! will replace any “read-only” copies which exist in workspace
! cannot check out a file if it is already “editable”

Single Level
Or Hierarchy
Packages

Latest or
Specified Version

A “lock” allows only

this user to make
edits to the checked- Repository Browser dialog
out objects appears if nothing selected!
C-9 • Designing with FPGA Advantage: Version Management Using HDL Designer Copyright © 2003 Mentor Graphics Corporation

Notes:

Designing with FPGA Advantage C-9

November 2003
Version Management Using HDL Designer

Get

Get
♦ Get performs check-out without a “lock”, creating “read-only”
copies
! Check-out the selected objects from the repository using latest or
specified version as read only
! Not available for ClearCase

Single Level Or Hierarchy

Latest or Specified version

Replace “editable” files

with latest/specified version

Notes:

C-10 Designing with FPGA Advantage

November 2003
Version Management Using HDL Designer

Change Lock

Change Lock
♦ “Lock” makes selected objects in workspace “editable”

♦ “Unlock” makes selected objects in workspace “read-only”

Lock or Unlock

Notes:

Designing with FPGA Advantage C-11

November 2003
Version Management Using HDL Designer

Label

Label
♦ Add/Remove/Overwrite a symbolic name for selected objects
! The label is used to identify a set of version controlled design
objects which may have different individual version numbers but
share a common label

Add/Remove/Overwrite a Label
User provides “Label”

Notes:

C-12 Designing with FPGA Advantage

November 2003
Version Management Using HDL Designer

Synchronize

Synchronize
♦ Performs a check-out without a lock,
! existing “read-only” objects are overwritten
! existing “editable” objects ignored
! option to update workspace with
missing files

Add Missed Files

Notes:

Designing with FPGA Advantage C-13

November 2003
Version Management Using HDL Designer

Status

Status
♦ Show the status of selected object

editable or read-only

Labels/Tags

Locker’s Name & Version

Notes:

C-14 Designing with FPGA Advantage

November 2003
Version Management Using HDL Designer

History

History
♦ Show the version history of selected objects

Choose From the List

Summary of Version,
Label, Author, Check-
in Date, Comment

Details

Notes:

Designing with FPGA Advantage C-15

November 2003
Version Management Using HDL Designer

Versioning of the HDL files

♦ The generated HDL files can be versioned manually by the user if the
option is enabled Option → Version Management ...

HDL Directory specified by the mapping

♦ The generated HDL can be out of sync with the graphical source if no
generation has occurred after the last changes

Notes:
If you enable Allow management of generated HDL, the version management
commands can also be used for generated HDL files in the HDL browser. The
repository location for these files (when you are using RCS, CVS, DesignSync or
Visual SourceSafe) is a directory called _hdl which is created directly below the
normal repository location.

C-16 Designing with FPGA Advantage

November 2003
Version Management Using HDL Designer

When to Use Reference

♦ Save the changes in the repository => Check In
! will save the differences comparing with last version
♦ Retrieve latest/specified version for editing => Check Out
♦ Retrieve latest/specified version in read-only mode for information => Get
! give an error message if get a file which is editable in the workspace

– optional 'replace writable files'

! get a library always get the whole of those currently in the repository.

♦ Update workspace using latest/specified version in the repository => Synchronize

! ignore writable files
! synchronize a library get those currently in the workspace
– optional 'add files not currently in my workspace'
! Keep the read-only ones up-to-date with what in the repository

♦ Find the usage information of specified object => Status

♦ Find the version history of selected object => History
♦ Change editing mode of selected object => Change Lock
♦ Define a tag for a group of selected objects for specific actions like simulation or synthesis => Label

Notes:

Designing with FPGA Advantage C-17

November 2003
Version Management Using HDL Designer

C-18 Designing with FPGA Advantage

November 2003
Appendix D
Packages

Objectives
This module will cover the following topics:

• Creating a Package
• External Package Source
• Using a Package

Designing with FPGA Advantage D-1

November 2003
Packages

Creating a Package

Creating a Package
♦ Packages can be created in a HDL Designer library. First
create the package header and then if appropriate the package
body.

The package is identified

Notes:

D-2 Designing with FPGA Advantage

November 2003
Packages

Creating a Package (Cont.)

♦ Type the package header ♦ Type the package body

Notes:

Designing with FPGA Advantage D-3

November 2003
Packages

Using a Package

♦ All the editors have the

menu option:
Diagram > Package
References

♦ To use a particular
package:
! Select the library
! select the package

Notes:

D-4 Designing with FPGA Advantage

November 2003
NOTES:

Designing with FPGA Advantage

November 2003
Part Number: 069875

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