AUTOMATION FOR PRODUCTIVITY

IMPROVEMENT OF AMS AND SOFT IP’S

A
Dissertation
Submitted in partial fulfillment of the requirements for the Award of the
Degree of

BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION

Submitted by
KUSHALDEEP
ECE-4365-2K16

Department of Electronics & Communication Engineering

JC Bose University of Science and Technology, YMCA

Faridabad, Haryana, India – 121006

I
 Date: 19th Dec 2019

TRAINING COMPLETION CERTIFICATE

This is to certify that the project work presented in this report entitled “AUTOMATION
FOR PRODUCTIVITY IMPROVEMENT OF AMS AND SOFT IP’s” submitted by
Kushaldeep in fulfilment of the requirement for the award of degree of Bachelor of
Engineering submitted at Electronics and Communication Engineering, JC Bose
University of Science and Technology, YMCA Faridabad is an authentic record of
work carried out at ST Microelectronics, Greater Noida from June 10, 2019 to
December 20, 2019 under the guidance of Mr. Amit Singh, STMicroelectronics.

Signature of Mentor
AMIT SINGH
Senior Staff Engineer
STMicroelectronics
Greater-Noida

II
 CANDIDATE DECLARATION

I hereby certify that the work which is being presented in this project report
AUTOMATION FOR PRODUCTIVITY IMPROVEMENT OF AMS AND SOFT
IP’s submitted to JC Bose University of Science and Technology, YMCA, Faridabad is
an authentic record of my own work carried out in the company - STMicroelectronics
Pvt. Ltd. Greater Noida. The work contained in this thesis has not been submitted to any
other University or Institute.

Kushaldeep
ECE-4365-2K16
B. Tech ECE
JC Bose University of Science and Technology, YMCA
Faridabad, 121006

III
The following examiners have access the project report and conducted the viva-voce
Examination:

Internal Examiners External Examiners

Name: …………………………… Name: …………………………….
Affiliation: ………………………. Affiliation: ……………………….
……………………………..……. ……………………………..…….
Contact no: ………………..……. Contact no: ………………..…….
E-mail lD: ………………………. E-mail lD: ……………………….
Signature: ………………….……. Signature: ………………….…….

IV
 ACKNOWLEDGEMENT

I wish to express my gratitude to the most helping and kind people who have been the
part of this experience from the beginning. Firstly, my sincere thanks to Digital
Modelling IP Subsystems (DMIPS) team for their help during this training. Their support,
feedback and motivation helped me to make this much progress.
The success of this project is a result of the hard work, team spirit and the motivation put
in us by our Group Manager Mr. Anupam Jain & Mentor Mr. Amit Singh for
providing necessary information regarding the project, guidance, supervision and
invaluable support in all aspects. I would like to thank Ruchi Yadav, Shuchi Singla and
Vaishak K. for helping me to improve my skills in all domains required.
I acknowledge with gratitude my indebtedness to Head of the Department, Ms. Neelam
Turk, Electronics and Communication Engineering Department, JC Bose University of
Science and Technology, YMCA, Faridabad and all the faculty to provide me with this
excellent opportunity to carry out my project work in such a highly renowned and
esteemed organization. I am equally thankful to ST Microelectronics for providing me
the invaluable exposure to the industry and the current market trends.

Kushaldeep
ECE-4365-2K16

V
Table of Contents

CERTIFICATE
DECLARATION
EXAMINER CERTIFICATE
ACKNOWLEDGEMENT
ST AT A GLANCE
INTRODUCTION TO PROJECT
1. INTRODUCTION
1.1 What is a mixed signal circuit?
1.2 What is a chip?
1.3 Need of an I/O
1.4 UNIX
1.4.1 Features of UNIX
1.4.2 Advantages of using UNIX
2. SHELL SCRIPTING
2.1 Shell
2.2 Shell Scripting
2.2.1 Advantages of Shell Scripting
2.2.2 Commonly used commands
2.2.3 Shell built-in functions
2.2.4 Flow Constructs
2.2.5 Example of Script
3. Spice Cent Automation Tool
3.1 Objective
3.2 Files Generated
3.3 Execution and Working
3.3.1 Choice of Techno
3.3.2 Choosing between Generation and Validation
3.3.3 Project Name
3.3.4 Device List
3.3.5 IOSIM Setup Creation Form
3.3.6 Generation
3.3.7 Netlist and Command Files

VI
3.3.8 Validation
3.4 Conclusion
4. Script Device Analysis
4.1 Objective
4.2 Files Generated
4.3 Working
4.4 Execution
4.4.1 Validation with old DK
4.4.2 Model Parameters
4.4.3 Eldo Simulation in DK1
4.4.4 New DK Files
4.4.5 Device Structure
4.4.6 XLS Generation
4.5 Results
REFERENCES
APPENDIX
PERSONAL DETAILS

VII
 ST AT A GLANCE

ST Microelectronics is a global independent semiconductor company and is a leader in

developing and delivering semiconductor solutions across the spectrum of
microelectronics applications. An unrivalled combination of silicon and system expertise,
manufacturing strength, Intellectual Property (IP) portfolio and strategic partners
positions the Company at the forefront of System-on- Chip (SoC) technology and its
products play a key role in enabling today’s convergence trends.

ST is a global semiconductor company with net revenues of US$ 6.97 billion in 2016.
Offering one of the industry’s broadest product portfolios, ST serves customers across
the spectrum of electronics applications with innovative semiconductor solutions for
Smart Driving and the Internet of Things. By getting more from technology to get more
from life, ST stands for life augmented.

 Among the world’s largest semiconductor companies

 A leading Integrated Device Manufacturer serving all electronics segments

 A leading technology innovator (approximately 7,500 people working in R&D,

~16,000 owned patents in ~9,500 patent families and ~500 new patent filings in
2016)

 Delivering solutions that are key to Smart Driving and the Internet of Things.

 Rich and diversified portfolio (discrete and standard commodity components, ASICs,
full custom devices and semi-custom devices, and Application-Specific Standard
Products)

 President and CEO: Jean-Marc Chery

 2017 revenue: $8.35 Billion

 Approximately 43,500 employees

 Over 75 sales & marketing offices in 35 countries

1
Product Portfolio

ST’s products are found everywhere today, and together with their customers, they are
enabling smarter driving and smarter factories, cities and homes, along with the next
generation of mobile and Internet of Things devices.
Smart Driving:
It is estimated that 80% of all innovations in the automotive industry today are directly or
indirectly enabled by electronics, which means a constant increase in the semiconductor
content per car year after year. ST’s Smart Driving products and solutions are making
driving safer, greener and more connected through the fusion of several of our
technologies.

Figure 1: ST Logo for Smart Driving

Driving is safer thanks to their Advanced Driver Assistance Systems (ADAS) products –
vision, radar, imaging, sensors and GNSS positioning technologies, as well as their
Adaptive Lighting Systems and User Display Technologies. Driving is greener with their
energy-management processors (EMU, ECU), Power Electronics at the heart of all
automotive subsystems, Wide Band Gap technologies (SiC and GaN) for electric cars,
Sensors, and more. And vehicles are more connected using their car-to-car and car-to
infrastructure (V2X) connectivity solutions, infotainment system and telematics
processors, Tuners, Amplifiers and Sensors.

The Internet of Things:

Due to the fragmented nature of the Internet of Things, the markets ST serve span the
entire customer base – from our largest customers to the tens of thousands of smaller and
equally important customers who we serve through our distribution partners and mass
market initiatives.

Our daily lives as individuals benefit from the “Smart Things” we carry and use
extensively. ST is a leading supplier of all the key technologies going into the next
generations of personal consumer devices: Sensors, Micro-controllers for low and

2
ultralow power processing, Power and Analog components, and RF & Connectivity
products.

ST addresses the rise of the smart home and smart city systems through their core: energy
consumption and management systems, or the future smart grids and their applications.
Its solutions address the critical functions: from the combo chips inside the smart meters
helping consumers and utilities track and balance the use and billing of electricity and
water or gas to combo chips, to more intelligent street lighting able to sense its
environment and dim or switch off to adjust to lighting conditions and municipal needs
and sensors that can measure traffic flow and potentially re-route around obstructions.

ST provides a range of technologies enabling manufacturing and other industrial sectors

to achieve better efficiency, flexibility, and safety through automation and robotics – this
is what we call smart industry. The current shift, often labeled as the “fourth industrial
revolution” is making industrial systems smarter with the combined application of a
broad range of products, including Micro-controllers, Sensors and Actuators, Motor
Control, Signal Conditioning, Industrial Communication Solutions, Power Supplies,
Protection Devices, Wireless Modules, and Display and LED Controllers.

Figure 2: ST logo for Internet of Things

Research & Development and Manufacturing:

To keep its technology edge, ST has maintained an unwavering commitment to R&D

since its creation. Almost one fifth of our people work in R&D and product design and in
2015 the Company spent about 21% of its revenue in R&D. Among the industry’s most
innovative companies, ST owns and continuously refreshes a substantial patent library
(~15,000 owned patents in ~9,000 patent families and 500 new patent filings).

The Company draws on a rich pool of chip fabrication technologies, including advanced
FDSOI (Fully Depleted Silicon- on -Insulator), CMOS (Complementary Metal Oxide
Semiconductor), Imaging Technologies, RF-SOI (RF Silicon- on -Insulator), Bi CMOS,
BCD (Bipolar, CMOS, DMOS) and MEMS technologies.

3
ST believes in the benefits of owning manufacturing facilities and operating them in
close proximity with its R&D operations.

Figure 3: STMicroelectronics Manufacturing Site

ST has a worldwide network of front-end (wafer fabrication) and back-end (assembly and
test and packaging) plants. ST’s principal wafer fabs are located in Agrate Brianza and
Catania (Italy), Crolles, Rousset, and Tours (France), and in Singapore. These are
complemented by assembly- and-test facilities located in China, Malaysia, Malta,
Morocco, the Philippines, and Singapore.

Group Introduction

The T&DP (Training & Design Platform) is a group in ST which works on intellectual
properties (IPs). Its work is to provide quality Library Solutions and services to divisions,
in the company’s drive in time to market, IP Reuse and Super Integration.

Team Introduction

4
DMIPS- Digital Modelling and IP Subsets. The team

5
 INTRODUCTION TO PROJECT
I/O's are the input/output cells which are providing end to end chip connections in
different SOC’s. IO allows interface between logic inside the chip and external system
environment. I/O’s are placed at the periphery of core logic i.e. on sides of core logic
except on the corners of the cell because it will increase Ldi/dt drop through bond wire.
At corner we place corner cells. If there is free space b/w I/O’s, filler cells must be used
to fill up those empty areas. Any input signal which comes from off-chip environment
into the chip must be checked by I/O as per the requirement of core. The only component
that stands in between the harsh external environment and core is the I/O buffers. I/O
buffers handle buffering, interfacing and translation of external/internal signals to and
from core.
The objective of my project is to build a tool to automate the generation of the files
required for design-to-technology alignment across different technologies. Files such as
flags, lib.spec, reference_model.spec, tool.spec are required for simulation and archiving
of every techno. The process of generation of these files can take a lot of time, if done
manually. Hence, if this process of generation can be automated by taking only specific
inputs from user, a lot of time and manpower can be saved and efficiency will be greatly
improved.
Furthermore, in the process of generating these files, the tool can also use these files to
automatically perform simulation using the netlist and command file provided by the
user. With a view to analyze the problems and suggest relevant solutions to the queries
has also been a major task of the work done.
In my second dimension of work, ‘Script Device Analysis’ of two versions of the same
technology or of different technologies has been done. The values of currents and
voltages of a device/model at all PVTs of both versions are compared and their
percentage difference is calculated.

6
CHAPTER 1

Introduction
1.1 WHAT IS A MIXED SIGNAL CIRCUIT?

A mixed signal circuits, consists of both Analog and Digital circuits on a Single chip.
This integration of all the circuits is, “A mixed signal system on a chip" (AMS-OC). The
design of mixed signal ICs is quite challenging and complicated than only-analog or
only-digital ICs.

1.2 WHAT IS A CHIP?

Chip is a set of tiny electronic circuits and device components fabricated on a piece of
semiconductor. While most of the ICs are fabricated with the digital functions, a few
chips are analog only. Having both analog and digital is mixed signal mode. Digital chips
are aimed for processors use and intend to perform the logic of particular integrated
circuit.

1.3 ASIC

Any IC other than a general purpose IC which contain the functionality of thousands of
gates is usually called an ASIC (Application Specific Integrated Circuit). ASICs are
designed to fit a certain application. An ASIC is a digital or mixed-signal circuit designed
to meet specifications set by a specific project.

1.4 ASIC FLOW

The customer follows a flow in which he can utilize the product delivered. He has the
specifications of his product. Simulations are carried out at the Verilog netlist and
checked if they meet the required specifications. In case there is some discrepancy, it is
brought to the notice of the developing team and the required action is taken. The
customer checks the required specifications are delivered otherwise he requests for the
missing ones. Now, with all the libraries and the Verilog models, synthesis is carried out
and gate level netlist is extracted. Routing is done using the place and route tools. Also,

7
gds is streamed out so that the design rules are verified. Then product is send to
fabrication unit for the preparation of chip. Thus the chip is ready to be launched in the
market.

Figure 1.1 Basic ASIC

1.4.1 STEPS OF FLOW

ASIC Design is based on a flow that uses HDL as the entry level for design, which
applies for both Verilog and VHDL. The following description describes the flow
from specification of design up to tape out, which is the form sent to silicon foundry
for fabrication.

The following are the steps of the flow:

1. Specification- This is the beginning and most important step towards designing a
chip as the features and functionalities of the chip are defined. Speed, size, power
consumption is among the considerations on which the accepted range of values is
specified.

2. RTL Coding- The micro architecture at specification level is then transformed in

RTL code which marks the beginning of the real design phase towards realizing a

8
chip. As a real chip is expected, so the code has to be a synthesizable RTL code.

3. Simulation and Test bench- RTL code and test bench are simulated using HDL
simulators to check on the functionality of the design. Some of the tools available at
CEDEC include: Cadence’s Verilog XL, Synopsys’s VCS, and Mentor Graphics
ModelSim. If the simulation results do not agree with the intended function expected,
the test bench file or the RTL code could be the cause. The simulation has to be
repeated once either one of the two causes, or both, have been corrected. There could
be a possibility of the loop in this process, until the RTL code correctly describes the
required logical behavior of the design.

4. Synthesis-This process is conducted on the RTL code. This is the process whereby
the RTL code is converted into logic gates. The synthesis process however requires
two input files: firstly, the “standard cell technology files” and secondly the
“constraints file”.

5. Pre-Layout timing analysis- When synthesis is completed, the synthesized database

along with timing information from the synthesis process is used to perform a Static
Timing Analysis (STA).

6. APR- This is the Automatic Place and Route process whereby the layout is being
produced. In this process, the synthesized database together with timing information
from synthesis is used to place the logic gates.

7. Back Annotation- This is the process where extraction for RC parasitics made from
the
layout. The path delay is calculated from these RC parasitic. Back annotation is the step
that bridges synthesis and physical layout.

8. Post- Layout timing analysis- This step in ASIC flow allows real timing violations

9
such as hold and setup to be detected. In this step, the net interconnect delay information
is fed into the timing analysis and any setup violation should be fixed by optimizing the
paths that fail while hold violation is fixed by introducing buffers to the path to increase
the delay.

9. Logic Verification- This step acts as the final check to ensure the design is correct
functionally after additional timing information from layout. Changes have to be made
on the RTL code or the post-layout synthesis to correct the logic verification.

10. Tape out-When the design passed the logic verification check, it is now ready for
fabrication. The tape out design is in the form of GDSII file, which will be accepted by
the foundry.

10
 Figure 1.2 ASIC Design Flow
1.5 MODELLING

ASIC design descriptions are written by designers at different levels of abstraction. Most
common hardware description languages used by designers are Verilog and VHDL. Both
these languages are equally capable of providing complex constructs to describe complex
functionality. Behavioral modeling forms highest level of abstraction.

1.5.1 Behavioral Description

At initial stage of design process designer provides a Behavioral description of the

functionality intended. Behavioral model does not care about the structure of the design,
combinational or sequential elements used in the design, clock signal and the timing
constraints involved. It captures the intended behavior of the design. The below given
example describes the behavior of an adder that adds two four digit inputs to return and
output. It is important to note that this description does not capture timing information.

Figure 1.3: Behavioral modelling

1.5.2 RTL description

RTL stands for Register Transfer Level. In this model the entire design is split into
registers with flow of information between these registers at each clock cycle. RTL
description captures the change in design at each clock cycle. All the registers are
updated at the same time in a clock cycle. Typically, an RTL description divides design
into registers and the logic blocks that join those registers together. RTL captures the data
flow but fails to give a good description of control flow.

11
 Figure 2: Register Transfer Level description of a design.

1.5.3 Structural Description

Structural description consists of a network of instances of logic gates and registers

described by a technology library. Technology library is provided by fabrication houses.
Technology library is a description of simple AND, OR, NOT and complicated multiple
functionality cells. The description of a cell includes its geometry, delay and power
characteristics. Structural modelling describes circuit in form of instances of cells and
interconnect between those cells.

Figure 3: Structural Modelling.

12
2.1 UNIX:

UNIX is an operating system which was first developed in the 1960s, and has been under
constant development ever since. By operating system, we mean the suite of programs
which make the computer work. It is a stable, multi-user, multi-tasking system for
servers, desktops and laptops. UNIX systems also have a graphical user interface (GUI)
similar to Microsoft Windows which provides an easy to use environment. However,
knowledge of UNIX is required for operations which aren't covered by a graphical
program, or for when there is no windows interface available, for example, in a telnet
session.

2.1 Features of UNIX:

• UNIX is a time-shared operating system.

• Many computer vendors have their own flavor of UNIX (like Solaris (Sun), AIX
(IBM), ru64 (Compaq) etc.).
• Linux is not UNIX, but its feature are very close to UNIX.
• High-performance computers generally run on UNIX.

2.3 Advantages of using UNIX:

• Data stored on a UNIX file system can easily be shared with colleagues in your
lab and around the world.
• UNIX is more user friendly and reliable than other Operating Systems such as
Windows NT etc.
• It is very light and fast. UNIX kernel needs a very small fraction of the secondary
memory to install and requires small amount of main memory to run. This makes
it possible to install it on the modest of devices, those with little memory.
• UNIX offers dual user interface in GUI and Command Interface, making it very
flexible as well as easy to use.
• Most well written user programs are independent of the underlying hardware,
making them readily portable to new systems.
• It is so powerful that the user has the ability to change permissions of individual
files.

13
Figure 1.2 UNIX Environment

14
15
3.1 Perl:

Perl is an acronym for Practical Extraction and Report Lannguage, which is a pretty good
description of what Perl does particularly well. Extraction for looking at files and pulling
out the important parts (for example, the actual text data from an HTML file, or the user
or hostnames from a networking log file); and report for generating output and, reports
based on the information that was extracted. It’s a practical language because it’s much
easier to write these sorts of programs quickly in Perl than it would be in a language such
as C.

It was designed by Larry Wall as a tool for writing programs in the UNIX environment.
Perl is an Open Source software. It is a general purpose programming language initially
developed for text manipulation. It runs on almost all platforms and does not require any
special editor – Notepad or vi editor is sufficient.

For many years, Perl was the language of choice for Unix system administrators and
other Unix programmers who needed a flexible, quick-to-program language to
accomplish tasks for which a language such as C would be overkill (or take too much
work), or for tasks that were too complex for shell scripting. It was because of its existing
popularity as a Unix language that Perl became popular as a Web language for creating
CGI (Common Gateway Interface) scripts. Nowadays used for a wide range of tasks like
system administration, web development, network programming, GUI development etc.

The Perl slogans:

• There's more than one way to do it (TMTOWTDI)

• Easy things should be easy and hard things should be possible.

3.2 PERL SCRIPTING:

Scripting is a way by which one can alleviate the necessity of typing a particular
sequence of commands used frequently. This is achieved by automating these command
sequences in order to
make one’s life easier and more productive. Scripting is all about making the computer,
the tool, do the work. The user may use command redirection, variables, control
constructs, etc. for writing a script.

Script is defined as just a plain text file with a set of UNIX commands.

3.2.1 ADVANTAGES OF PERL SCRIPTING:

1. Managing multiple associated files for reading/executing

2. Generating a report in .xls format
3. Creating a specific directory structure
4. Managing a file for any change in names
5. Reading a specific content in multiple files
6. Managing command line inputs
7. Automation of VLSI Verification process

3.2.2 COMMONLY USED PERL VARIABLES:

1. Scalar variables - $
2. Array variables - @
3. Hash variables - %

3.2.3 Flow Constructs:

Just like in C-programming, Perl also supports all the loops and flow constructs. Most of
them have slightly different syntaxes. The following commands are most commonly used
for flow constructs:

11
1. If/elseif/else

2. For

3. While

4. Do-While

5. Foreach

6. Unless

7. Untill

3.2.4 EXAMPLE OF SCRIPT :

Following is a script that takes the user input and evaluates it according to the conditions
mentioned in the script.

12
 CHAPTER 3 SHELL
SCRIPTING
3.1 SHELL:

The shell sits between the user and the operating system, acting as a command
interpreter. It reads the terminal input and translates the commands into actions taken
by the system. When user logs into the system, he/she is given a default shell. When
the shell starts up it reads its start-up files and may set environment variables,
command search paths and command aliases, and executes any commands specified
in these files.
The original shell was the Bourne Shell, sh. Every UNIX platform will have either the
Bourne shell, or a Bourne compatible shell available. It has very good features for
controlling the input and output, but is not well suited for an interactive user. To meet
the latter, we use the c shell, csh. It is now found on most of the UNIX systems. It
uses the c-type syntax, the language UNIX is written in, but has a more awkward
input/output implementation.
C-shell has job control, so one can reattach a job running in the background to the
foreground. It also provides a history feature which allows the user to modify and
repeat previously executed commands.
The shells have a number of built-in or native commands. These commands are
executed directly in the shell and don’t have to call another program to be run. These
built-in commands are different for different shells.
The user may work in different shells at the same time. This is done by opening
different terminals and setting different shell environments in each. So while one of

20
the terminals can continue to work on the default shell, the user may select a different
shell for the other. When the user enters a command in the terminal the shell
interprets it and translates the same into action to be taken by the OS. The kernel will
not understand user commands without an interpreter.

3.2 SHELL SCRIPTING:

Scripting is a way by which one can alleviate the necessity of typing a particular
sequence of commands used frequently. This is achieved by automating these
command sequences in order to make one’s life at the shell easier and more
productive. Scripting is all about making the computer, the tool, do the work. The
user may use command redirection, variables, control constructs, etc. for writing a
script.

3.2.1 Advantages of Shell Scripting:

1. Combine lengthy and repetitive sequences.

2. Create new commands from basic ones.
3. Write wrapper scripts.
4. Automation.
5. Writing it is much quicker.
6. Interactive debugging.
7. Absence of a compilation step.

3.2.2 Commonly Used Commands:

Most Commonly used filters are:

1. cat
2. cut
3. grep
4. egrep
5. sed
6. awk
7. head
8. tail
9. more
10. paste

21
 11. sort
12. tr
13. uniq
14. wc

3.2.3 Shell Built-in Functions:

1. eval
2. exec
3. read
4. read-only
5. set/unset
6. test
7. expr

3.2.4 Flow Constructs:

Just like in C-programming, csh also supports all the loops and flow constructs. Most
of them have slightly different syntaxes. The following commands are most commonly
used for flow constructs:
1. If
2. For
3. While
4. Do-While
5. Foreach

3.2.5 Example of Script:

Following is a script that takes the user input and evaluates it according to the
conditions mentioned in the script.

22
Figure 3.1 Example of Shell Scripting

23
4.1 TCL

Tcl (pronounced "tickle") expands to Tool Command Language. It is a high-

level, general-purpose, interpreted, dynamic programming language. It was designed with
the goal of being very simple but powerful. Tcl casts everything into the mold of
a command, even programming constructs like variable assignment and procedure
definition. Tcl supports multiple programming paradigms, including object-
oriented, imperative and functional programming or procedural styles.

Tcl is a radically simple open-source interpreted programming language that provides

common facilities such as variables, procedures, and control structures as well as many
useful features that are not found in any other major language. Tcl runs on almost all
modern operating systems such as Unix, Macintosh, and Windows (including Windows
Mobile).

It is commonly used embedded into C applications, for rapid prototyping, scripted

applications, GUIs, and testing. Tcl interpreters are available for many operating systems,
allowing Tcl code to run on a wide variety of systems. Because Tcl is a very compact
language, it is used on embedded systems platforms, both in its full form and in several
other small-footprint versions.

4.2 TCL SCRIPTING

Tcl is a general purpose multi-paradigm system programming language. It is a scripting

language that aims at providing the ability for applications to communicate with each
other. Tcl was developed initially for Unix. It was then ported to Windows, DOS, OS/2,
and Mac OSX. Tcl is much similar to other unix shell languages like Bourne Shell (Sh),
the C Shell (csh), the Korn Shell (sh), and Perl.

It aims at providing ability for programs to interact with other programs and also for
acting as an embeddable interpreter. Even though, the original aim was to enable
programs to interact, you can find full-fledged applications written in Tcl/Tk.
4.3 TCL FEATURES

The features of Tcl are as follows −

 Reduced development time.
 Powerful and simple user interface kit with integration of TK.
 Write once, run anywhere. It runs on Windows, Mac OS X, and almost on every Unix
platform.
 Quite easy to get started for experienced programmers; since, the language is so
simple that they can learn Tcl in a few hours or days.
 You can easily extend existing applications with Tcl. Also, it is possible to include Tcl
in C, C++, or Java to Tcl or vice versa.
 Have a powerful set of networking functions.
 Finally, it's an open source, free, and can be used for commercial applications
without any limit.

4.4 APPLICATIONS

Tcl is a general-purpose language and you can find Tcl everywhere. It includes,

 Scalable websites that are often backed by databases.

 High performance web servers build with TclHttpd.
 Tcl with CGI based websites.
 Desktop GUI applications.
 Embedded applications.

4.5 BASIC TCL COMMANDS

 gets
 puts
 proc
 set
 unset
 seek

32
  incr
 string
 regexp
 break
 lappend
 flush

3.2.3 Flow Constructs:

Just like in C-programming, TCL also supports all the loops and flow constructs. Most of
them have slightly different syntaxes. The following commands are most commonly used
for flow constructs:

 If/elseif/else

 For

 While

 Switch

 Foreach

3.2.5 Example of Script:

Following is a script that takes the user input and evaluates it according to the conditions
mentioned in the script.

33
34
4.1 MAKEFILE

Make is Unix utility that is designed to start execution of a makefile. A makefile is a

special file, containing shell commands, that you create and name makefile (or Makefile
depending upon the system). While in the directory containing this makefile, you will
type make and the commands in the makefile will be executed. If you create more than
one makefile, be certain you are in the correct directory before typing make.

Make keeps track of the last time files (normally object files) were updated and only
updates those files which are required (ones containing changes) to keep the sourcefile
up-to-date. If you have a large program with many source and/or header files, when you
change a file on which others depend, you must recompile all the dependent files.
Without a makefile, this is an extremely time-consuming task.

As a makefile is a list of shell commands, it must be written for the shell which will
process the makefile. A makefile that works well in one shell may not execute properly in
another shell.

The makefile contains a list of rules. These rules tell the system what commands you
want to be executed. Most times, these rules are commands to compile(or recompile) a
series of files. The rules, which must begin in column 1, are in two parts. The first line is
called a dependency line and the subsequent line(s) are called actions or commands. The
action line(s) must be indented with a tab.

4.2 FORMAT

RULE: DEPENDENCY LINE

[tab]ACTION LINE(S)

The dependency line is made of two parts. The first part (before the colon)
are target files and the second part (after the colon) are called source files. It is

35
called a dependency line because the first part depends on the second part.
Multiple target files must be separated by a space. Multiple source files must
also be separated by a space.

DEPENDENCY LINE: TARGET FILES: SOURCE FILES

After the makefile has been created, a program can be (re)compiled by

typing make in the correct directory. Make then reads the makefile and creates a
dependency tree and takes whatever action is necessary. It will not necessarily
do all the rules in the makefile as all dependencies may not need updated. It
will rebuild target files if they are missing or older than the dependency files.

Unless directed otherwise, make will stop when it encounters an error during
the construction process.

RULE: DEPENDENCY LINE

[tab]ACTION LINE(S)

36
[tab]ACTION LINE(S)

REFERENCES

1. I/O User Manual

2. Eldo User Manual
3. IOSIM User Manual
4. Chris A. Mack’s “Fifty Years of Moore’s Law”, IEEE Transactions on
Semiconductor Manufacturing, Vol. 24, No. 2, pp. 202-207, May 2011.
5. Classic Shell Scripting by Arnold Robbins, Nelson H.F. Beebe, O’Reilly Media
Inc, 16 May 2005.
6. UNIX Shell Programming by Yashvant Kanetkar, BPB Publications, 2003.
7. Learning Perl by Randal L Schwarts, Phoenix & Brian D Foy, O’Reilly Media
Inc, June 2011.

37
 APPENDIX
Commonly used UNIX Commands

1. pwd - print working directory

2. cd - change directory
3. mkdir - make a directory
4. ls - list directory contents
5. cp - copy a file
6. chmod - change file permissions
7. cat - concatenate a file
8. kill - terminate a process
9. grep - search the argument for all occurrences of the search string, and list them.
10. awk - scan for patterns in a file and process the results
11. sed - stream editor for editing files from a script or from the
12. command line
13. diff - compare the two files and display the differences (text
14. files only)
15. find - find files matching a type or pattern
16. cmp - compare two files and list where differences occur (text
17. or binary files)
18. touch - create an empty file, or update the access time of an

38
19. existing file
20. tar - archive files

Student Details
Student Name Kushaldeep
Roll No ECE-4365-2K16
Email Address [email protected] Phone No (M) +91-7015793488

39
Project Details
Project Title Automation for Productivity Improvement of AMS and soft IP’s
Project Duration 6 Months Date of 10th June 2019
reporting
Organization Details
Organization Name ST Microelectronics Pvt. Ltd.
Full postal address Plot No 1, Knowledge Park III, Greater Noida, Noida - 201310
with pin code
Website address www.st.com

Supervisor Details
Supervisor Name Amit Singh
Designation Senior Staff Engineer
Full contact address 2nd Floor, New Design Building, Plot No 1, Knowledge Park III,
Greater
with pin code
Noida, Uttar Pradesh - 201308
Email address [email protected] Phone No (M) +91-9999369445

Internal Guide Details

Faculty Name Shailender

Full contact address Electronics Department, JC Bose University of Science and
with pin code Technology, YMCA , Faridabad 121006

Email address [email protected] Phone No (M) +91-9971350816

40
41