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Vlsi Module

The document contains 30 questions related to the module test on VLSI Technology and Design for 5th semester Electronics and Communication Engineering students. The questions cover a range of topics including VLSI design flow, IC design quality metrics, design complexity reduction approaches, design styles, photoresist types, LOCOS isolation problems, MOS transistor fabrication, CMOS processes, MOS energy band diagrams, MOS transistor modeling, threshold voltage calculation, inverter circuits, delay calculation methods, CMOS implementations of logic gates, latch-up problems in CMOS, voltage bootstrapping, built-in self-test techniques, and pass transistor logic.

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Ashwini kumar
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
77 views

Vlsi Module

The document contains 30 questions related to the module test on VLSI Technology and Design for 5th semester Electronics and Communication Engineering students. The questions cover a range of topics including VLSI design flow, IC design quality metrics, design complexity reduction approaches, design styles, photoresist types, LOCOS isolation problems, MOS transistor fabrication, CMOS processes, MOS energy band diagrams, MOS transistor modeling, threshold voltage calculation, inverter circuits, delay calculation methods, CMOS implementations of logic gates, latch-up problems in CMOS, voltage bootstrapping, built-in self-test techniques, and pass transistor logic.

Uploaded by

Ashwini kumar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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SILVER OAK COLLEGE OF ENGINEERING

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

VLSI TECHONOLOGY & DESIGN

5th EC STUDENTS

MODULE TEST QUESTIONS

Que MODULE QUESTIONS


No. TEST
NO.
1 Explain VLSI Design flow using Y-chart.
2 What are the four general criteria to measure design quality of a
fabricated IC? Briefly explain each of them.
3 Discuss following approaches (with example) used to reduce complexity
1 of IC design.
a) Hierarchy b) Modularity
4 Explain in brief the different VLSI design styles.
5 Discuss comparison between different design styles based on logic cells &
interconnections.
6 Compare different design styles in VLSI design.
7 Define Positive photoresist & negative photoresist. What is the
difference between the two? Which is commonly used in the
manufacturing of high-density integrated circuits?
8 2 What are the problems associated with the LOCOS isolation technique?
Explain each of the fabrication steps involved in LOCOS technique
with suitable diagrams.
9 Explain the fabrication steps of PMOS transistor with necessary figures.
10 Explain the fabrication steps of NMOS transistor with necessary figures.
11 Explain n-well CMOS process (diagram only).
12 Explain twin tub CMOS process (diagram only).
13 Explain the energy band diagram of MOS Structure at surface inversion
and derive the expression for threshold voltage.
14 3 With neat sketch explain gradual channel approximation and derive the
equation for drain current in linear region mode and saturation mode.
15 Discuss the effect of channel length modulation and substrate bias on
drain current of NMOS transistor.
16 Calculate the threshold voltage VTO at VSB = 0 for a polysilicon gate nMOS
16 -3 20 -3
transistor with the following parameters: NA = 10 cm , ND = 2 x 10 cm ,
10 -2 10 -3
tox = 500 Aº, and Nox = 4 x10 cm . Take kT/q = 26 mV, ni= 1.45 x 10 cm ,
-19 -14 -14
q = 1.6 x 10 C, εox = 3.97 x 8.85 x 10 F/cm, εsi= 11.7 x 8.85 x 10 F/cm.
17 Draw the Resistive load inverter circuit. Derive VOL and VOH for resistive
4 load inverter and also draw the voltage transfer characteristics (VTC)
curve for the same.
18 Obtain expression for switching power dissipation for CMOS Inverter
circuit. Assume ideal step as an input to CMOS inverter (draw necessary
diagrams).
19 Consider a resistive load inverter circuit with VDD = 5V, kn’ = 20µA/V2,
VTO = 0.8V, RL = 200KΩ, and W/L = 2. Calculate the critical voltages VOH
and VOL on the VTC.
20 Explain Elmore Delay Calculation method for RC network. Derive the
formula for Elmore delay  DN .
21 Write a short note on CMOS Ring Oscillator (draw necessary diagrams).
22 Define propagation delay and derive the expression for propagation delay
time (only for saturation region)  PHL for CMOS inverter. Assume ideal step
as an input to CMOS inverter (draw necessary diagrams).
23 (a) Implement the Boolean function in CMOS logic:
5 Y= (D+E+A)(B+C)
Determine the equivalent (W/L) ratio of the nMOS and pMOS networks.
Given: (W/L)n =10 and (W/L)p =15
(b) Draw the full CMOS implementation of the following:
(i) XOR gate (ii) 2:1 Multiplexer
(c) Draw the CMOS implementation of SR Latch using NAND gate.
24 Draw the full CMOS implementation of the following using transmission
gate:
(i) XOR gate (ii) BC+AB+ABC
25 Draw the nMOS logic design for the following:
(i) (A.B)+C (ii) CD + DE
Draw the CMOS implementation of SR Latch using NOR gate
26 Define and discuss Latch-up problem in CMOS inverter. Mention causes
for latch-up and guideline for avoiding latch-up.
27 What is the need of voltage bootstrapping? Discuss Voltage bootstrapping
in detail.
28 Discuss Built-in Self-Test (BIST) techniques.
29 Write a short note on Ad Hoc Testable Design.
30 Explain the basic principle of pass transistor circuit. Explain logic ‘1’
transfer and logic ‘0’ transfer.

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