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LEAKAGE POWER REDUCTION IN SRAM CELL USING CIRCUIT LEVEL APPROACH

IN 65nm TECHNOLOGY

Thesis · August 2016

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 LEAKAGE POWER REDUCTION IN SRAM
CELL USING CIRCUIT LEVEL APPROACH IN
65nm TECHNOLOGY

DISSERTATION REPORT

SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE AWARD OF THE DEGREE

OF

MASTER OF TECHNOLOGY
IN

CONTROL AND INSTRUMENTATION SYSTEMS

Submitted By

MANISHA RAJPUROHIT
14MCIS1010

Under the supervision of

Prof. ABDUL QUAIYUM ANSARI

DEPARTMENT OF ELECTRICAL ENGINEERING

FACULTY OF ENGINEERING &TECHNOLOGY
JAMIA MILLIA ISLAMIA
NEW DELHI-110025
2016
 DEPARTMENT OF ELECTRICAL ENGINEERING
FACULTY OF ENGINEERING &TECHNOLOGY
JAMIA MILLIA ISLAMIA

CERTIFICATE

This is to certify that the project titled “LEAKAGE POWER REDUCTION IN SRAM
USING CIRCUIT LEVEL APPROACH IN 65NM TECHNOLOGY” submitted in partial
fulfilment of the requirements of the award of the degree of Master of Technology in Control
and Instrumentation System by “MANISHA RAJPUROHIT (14MCIS1010)” is a bona fide
record of the candidate’s own work carried out by him/her under my supervision and
guidance.
This work has not been submitted earlier in any university or institute for the award of
any degree to the best of my knowledge.

Prof. A. Q. Ansari (Supervisor) Prof. Majid Jamil (HOD)

Department of Electrical Engineering Department of Electrical Engineering
Faculty of Engineering & Technology Faculty of Engineering & Technology
Jamia Millia Islamia Jamia Millia Islamia
New delhi-110025 (India) New delhi-110025 (India)
 ACKNOWLEDGEMENT

It is my proud privilege to express deep sense of gratitude, heartfelt regards, appreciation and
indebtedness to my supervisor Dr. A.Q. Ansari, Department of Electrical Engineering,
Faculty of Engineering & Technology, Jamia Millia Islamia for his invaluable guidance,
deep-rooted interest, inspiration & continuous encouragement throughout the project work.
He gave me the opportunity to work on such an interesting theme and he has essentially
contributed to this work through his guidance and encouragement. I would also like to thank
IIIT Delhi institute for providing me the lab facilities and software.
Words do not come easy and I found myself in difficult position of attempting to express my
deep indebtedness to all Faculty Members of Electrical Engineering Department.

Manisha Rajpurohit
Roll no.14MCIS1010
M. Tech (CIS)
Department of Electrical Engineering
Faculty of Engineering & Technology
Jamia Millia Islamia
New delhi-110025 (India)
 CONTENTS
Particulars Page no.

Chapter 1 1
Introduction

1.1 Motivation……………………………………………………….. 1
1.2 Literature Review………………………………………………… 2
1.3 Objective…………………………………………………………. 8

Chapter 2 9
Theoretical Background

2.1 SRAM memory…………………………………………………... 9

2.1.1 Schematic and working of 6T SRAM cell……………………….. 10
2.1.1.1 Read operation…………………………………………………… 11
2.1.1.2 Write operation……………………………………………........... 11
2.1.2 Schematic and working of 7T SRAM cell……………………….. 12
2.1.2.1 Read and write operation of 7T SRAM cell …………………….. 13
2.1.3 Cell stability ……………………………………………………... 13
2.1.4 Performance parameters of SRAM ……………………………… 14
2.1.5 SRAM memory applications……………………………………... 14

Chapter 3 15
Leakage current components inside an SRAM cell

3.1 Leakage mechanism in CMOS transistor………………………... 15

3.1.1 Junction leakage………………………………………………….. 15
3.1.2 Gate induced drain leakage………………………………………. 16
3.1.3 Gate direct tunnelling leakage …………………………………... 16
3.1.4 Sub threshold leakage…………………………………………… 17
3.2 Leakage mechanism inside an SRAM…………………………… 18
3.2.1 Sub threshold leakage…………………………………………… 19
3.2.2 Gate tunnelling leakage ………………………………………… 20
3.3 Standby leakage reduction techniques…………………………… 21
3.3.1 Leakage reduction by stacking effect……………………………. 21
3.3.2 Leakage reduction by sleep transistor…………………………… 22
3.3.3 Leakage reduction by increasing the threshold voltages ………. 23
 Chapter 4 24
Proposed SRAM Cells For Leakage Reduction

4.1 Sleep approach…………………………………………………… 24

4.1.1 8T SRAM cell……………………………………………………. 25
4.1.2 9T SRAM cell……………………………………………………. 26
4.2 Stack approach…………………………………………………… 27
4.2.1 10T SRAM cell…………………………………………………... 27
4.2.2 11T SRAM cell…………………………………………………... 27
4.3 Sleep and stack approach………………………………………… 28
4.3.1 12T SRAM cell…………………………………………………... 28
4.3.2 13T SRAM cell…………………………………………………... 29

Chapter 5 31
Simulation and result

5.1 Software tool……………………………………………………... 31

5.2 Cell stability……………………………………………………… 31
5.2.1 Calculation of w/l ratio of driver, access and load transistor…….. 32
5.2.1.2 Calculation of Pull-up Ratio (PR)………………………………... 32
5.2.1.1 Calculation of Cell Ratio (CR)…………………………………... 32
5.3 Simulations of 6t and 7T SRAM cells…………………………… 32
5.3.1 Schematic of 6T SRAM cell for read operation…………………. 33
5.3.2 Waveforms of 6T SRAM cell for read operation………………... 33
5.3.3 Schematic of 6T SRAM cell for write operation………………… 34
5.3.4 Waveforms of 6T SRAM cell for write operation……………….. 34
5.3.5 Schematic of 6T SRAM for write static noise margin…………… 35
5.3.6 Waveform of 6T SRAM for write static noise margin…………... 35
5.3.7 Schematic of 6T SRAM for read static noise margin……………. 36
5.3.8 Waveform of 6T SRAM for read static noise margin……………. 36
5.3.9 Schematic of 6T SRAM for hold static noise margin……………. 37
5.3.10 Waveform of 6T SRAM for hold static noise margin…………… 37
5.3.11 Schematic of 7T SRAM cell for read operation………………… 38
5.3.12 Waveform of 7T SRAM cell for read operation………………… 38
5.3.13 Schematic of 7T SRAM cell for write operation………………… 39
5.3.14 Waveforms of 7T SRAM cell for write 1 operation……………... 39
5.3.15 Schematic of 7T SRAM cell for write operation………………... 40
5.3.16 Waveforms of 7T SRAM cell for write operation……………….. 40
5.3.17 Schematic of 7T SRAM cell for read static noise margin……….. 41
5.3.18 Waveform of 7T SRAM for read static noise margin…………… 41
5.3.19 Schematic of 7T SRAM for write static noise margin…………… 42
5.3.20 Waveform of 7T SRAM for write static noise margin………….. 42
5.4 Simulation of leakage control models…………………………… 43
5.4.1 Waveform of leakage current in 8T SRAM cell………………… 44
5.4.2 Waveform of leakage current in 9T SRAM cell………………… 44
5.4.3 Waveform of leakage current in 10T SRAM cell……………….. 45
5.4.4 Waveform of leakage current in 11T SRAM cell……………….. 45
5.4.5 Waveform of leakage current in 12T SRAM cell……………….. 46
5.4.6 Waveform of leakage current in 13T SRAM cell……………….. 46
5.5 Layouts of leakage control SRAM cells………………………… 47
 5.5.1 6T SRAM cell layout…………………………………………….. 47
5.5.2 7T SRAM cell layout…………………………………………….. 48
5.5.3 8T SRAM cell layout…………………………………………….. 48
5.5.4 9T SRAM cell layout…………………………………………… 49
5.5.5 10T SRAM cell layout………………………………………….. 49
5.5.6 11T SRAM cell layout…………………………………………. 50
5.5.7 12T SRAM cell layout…………………………………………… 50
5.5.8 13T SRAM cell layout…………………………………………… 51
5.6 Results……………………………………………………………. 52

Chapter 6 55
Conclusion and future scope

6.1 6.1Conclusion……………………………………………………. 55
6.2 6.2 Future scope………………………………………………….. 55
References………………………………………………………. 56
LIST OF TABLES

Table 1. Comparison of various performance parameters…………………………. 52

Table 2. Leakage power and area for SRAM models……………………………... 53

Table 3. Comparative analysis…………………………………………………….. 54

LIST OF FIGURES

Fig. 2.1 6T SRAM cell…………………………………………………………….. 10

Fig. 2.2 Read operation for 6T SRAM cell………………………………………… 11
Fig 2.3 Write operation for 6T SRAM cell………………………………………... 13
Fig. 2.4 Schematic of proposed 7T SRAM Cell…………………………………… 13
Figure 3.1 Sub Threshold Leakages……………………………………………….. 19
Figure 3.2 Gate Tunnelling Leakage………………………………………………. 20
Fig. 3.3 Stacking approach for leakage reduction…………………………………. 21
Fig. 3.4 Sleep approach for leakage reduction…………………………………….. 22
Figure 3.5 Dual threshold voltage techniques…………………………………….. 23
Figure 3.6 Reverse Body Biasing…………………………………………………. 24
Fig 4.1 schematic of 8T SRAM cell……………………………………………….. 25
Fig 4.2 Schematic of 9T SRAM cell………………………………………………. 26
Fig 4.3 Schematic of 10T SRAM cell……………………………………………… 27
Fig. 4.4 Schematic of 11T SRAM cell…………………………………………….. 28
Fig. 4.5 12T SRAM Cell………………………………………………………….. 29
Fig. 4.6 Schematic of 13T SRAM cell……………………………………………. 30
Fig. 5.1 Schematic of 6T SRAM cell during read operation………………………. 33
Fig. 5.2 Output waveform of 6T SRAM cell during read operation……………….. 33
Fig. 5.3 Schematic of 6T SRAM cell during write operation……………………… 34
Fig. 5.4 Output waveform of 6T SRAM cell during write operation……………… 34
Fig. 5.5 Schematic of 6T SRAM cell for calculation of write static noise margin… 35
Fig. 5.6 Waveform of 6T SRAM cell for calculation of write static noise margin… 35
Fig. 5.7 Schematic of 6T SRAM cell for calculation of read static noise margin…. 36
Fig. 5.8 waveform of 6T SRAM cell for calculation of read static noise margin….. 36
Fig. 5.9 Schematic of 6T SRAM cell for calculation of hold static noise margin…. 37
Fig. 5.10 Waveform of 6T SRAM cell for calculation of hold static noise margin... 37
Fig. 5.11 Schematic of 7T SRAM cell during read operation……………………… 38
Fig. 5.12 Waveform of 7T SRAM cell during read operation……………………... 38
Fig. 5.13 Schematic of 7T SRAM cell during write 1 operation………………....... 39
Fig. 5.14 Waveform of 7T SRAM cell during write 1 operation………………….. 39
Fig. 5.15 Schematic of 7T SRAM cell during write 0 operation………………….. 40
Fig. 5.16 Waveform of 7T SRAM cell during write 0 operation………………….. 40
Fig. 5.17 Schematic of 7T SRAM cell for calculation of read static noise margin... 41
Fig. 5.18 Waveform of 7T SRAM cell for calculation of read static noise margin... 41
Fig. 5.19 Schematic of 7T SRAM cell for calculation of write static noise margin.. 42
Fig. 5.20 Waveform of 7T SRAM cell for calculation of write static noise margin.. 42
Fig. 5.21 Leakage current waveform of 8T SRAM cell…………………………… 43
Fig. 5.22 Leakage current waveform of 9T SRAM cell…………………………... 44
Fig. 5.23 Leakage current waveform of 10T SRAM cell………………………… 44
Fig. 5.24 Leakage current waveform of 11T SRAM cell………………………….. 45
Fig. 5.25 Leakage current waveform of 12T SRAM cell…………………………. 45
Fig. 5.26 Leakage current waveform of 13T SRAM cell………………………….. 46
Fig.5.27 6T SRAM cell layout……………………………………………………. 47
Fig. 5.28 7T SRAM Cell layout………………………………………………….. 48
Fig. 5.29 8T SRAM Cell layout………………………………………………….. 48
Fig. 5.30 9T SRAM Cell layout………………………………………………….. 49
Fig. 5.31 10T SRAM Cell layout……………………………………………….... 49
Fig. 5.32 11T SRAM Cell layout………………………………………………… 50
Fig. 5.33 12T SRAM Cell layout………………………………………………… 50
Fig. 5.34 13T SRAM Cell layout………………………………………………… 51
ABBREVIATIONS

RAM Random Access Memory

SRAM Static Random Access Memory

DRAM Dynamic Random Access Memory

ROM Read Only Memory

EPROM Erasable programmable Read Only Memory

EEPROM Electrically Erasable programmable Read Only Memory

SDRAM Synchronous Dynamic Random Access Memory

MRAM Magneto Resistive Random Access Memory

NMOS n-type MOSFET

PMOS p-type MOSFET

SoC System on Chip

WL Word Line

BL Bit line

BLB Bit Line Bar

SNM Static Noise Margin

VDD Voltage Supply

GND Ground
 ABSTRACT

Power has been a major issue in system-on-chip (SoC) designs with the contemporary sub-
micron technologies. It has thus become very important to control the power and address the
power dissipation throughout the design cycle right from the architectural level. However, for
65nm and below technologies, leakage is the main factor which dominates over the dynamic
power and contributes to almost 40-50% of total power dissipation. In many new high
performance designs, the leakage component of power consumption is comparable to the
dynamic/switching component. According to some authenticated reports, 40% or more of the
total power consumption is due to the leakage of transistors. This percentage is likely to
increase with technology scaling unless effective techniques are introduced to bring leakage
under control. This dissertation report presents various models of SRAM cells to reduce the
static power dissipation. Substantial reduction in the leakage current in standby mode has
been obtained. The leakage current components considered in present work are gate leakage
and sub threshold leakage. In this dissertation report two conventional leakage reduction
techniques have been applied to both 6T and 7T-SRAM cells and results have been
compared. 7T-SRAM cell with stacking and sleep transistor shows 75% decrease in leakage
current with only 11.70% increase in cell area as compared to 6T-SRAM cell with stacking
and sleep transistor. All the simulation work has been carried out by using Analog
environment virtuoso (cadence) simulator for 65nm technology at 25ºC temperature.

0
 CHAPTER 1
INTRODUCTION
1.1 MOTIVATION
High power consumption in portable electronics devices is an issue of serious concern.
Shortening of battery life and additional packaging and cooling requirement are associated
with high power consumption. Static power dissipation due to standby leakage currents is an
important component of total power dissipation. Ubiquitous electronics devices contain
different types of component of which many remain idle during a particular operation. Static
power dissipation occurring in these idle components accounts for a huge percentage of total
power dissipation in the system. Therefore, minimization of this leakage component becomes
crucial for effective power management. As a result of continued scaling of MOS devices, a
dramatic enhancement in the performance of MOS devices has been achieved. This has led to
increase power dissipation due to leakage currents. Till now, the drain to source sub threshold
current has been the dominant leakage component.
The second driving force behind the low power design phenomenon is a growing class of
personal computing devices, such as portable desktops, digital pens, audio and video-based
multimedia products, and wireless communications and imaging systems, such as personal
digital assistants, personal communicators and smart cards. These devices and systems
demand high-speed, high-throughput computations, complex functionalities and often real
time processing capabilities. The performance of these devices is limited by the size, weight
and lifetime of batteries. Serious reliability problems, increased design costs and battery
operated applications prompted the IC design community to look more aggressively for new
approaches and methodologies that produce more power-efficient designs, which means
significant reductions in power consumption for the same level of performance. Memory
circuits form an integral part of every system design as Dynamic RAMs, Static RAMs,
Ferroelectric RAMs, ROMs or Flash Memories, significantly contributing to the system level
power consumption. Reducing the power dissipation in memories can significantly improve
the system power-efficiency, performance, reliability and overall costs. RAMs have
experienced a very rapid development of low-power low-voltage memory design during
recent years due to an increased demand for notebooks, laptops, hand-held communication
devices and IC memory cards.

1
1.2 LITERATURE REVIEW

Chen and Peh, August 2003 [1]: Power will be the key limiter to system scalability as inter
connection networks take up an increasingly significant portion of system power. In this
paper, the authors propose an architectural leakage power modelling methodology that
achieves 95- 98% accuracy against HSPICE estimates. When applied to interconnection
networks, combined with previous proposed dynamic power models, the authors provide
valuable insights on total network power consumption. Their modelling shows router buffers
to be a prime candidate for leakage power optimization. They thus investigate the design
space of power-aware buffer policies, propose a suite of policies, and explore the impact of
various circuit mechanisms on these policies. Simulations show power-aware buffers saving
up to 96:6% of total buffer leakage power.

Andrei et.al., 2004 [2]: In contemporary and future embedded as well as high performance
microprocessors, power consumption is one of the most important design considerations.
Since, in current technologies the dynamic power consumption dominates the static power
consumption. Voltage scaling is an effective technique to reduce the power consumption. The
most common way to reduce the power consumption of multi-processor systems is to
schedule a program to run on as many processors as possible and apply voltage scaling
afterwards. As technology scales to increasingly smaller feature sizes, however, the static
power consumption is expected to grow exponentially. In this paper, the authors first show
for which combinations of leakage current, supply voltage, and clock frequency the static
power consumption dominates the dynamic power dissipation. Based on these results, it is at
a certain point no longer advantageous to use as many processors as possible. They then
present a heuristic to schedule task graphs on a number of processors that is sufficient to meet
the deadline, but at the same time minimizes the power consumption. Their results show that
their scheduling algorithm reduces the total energy consumption by up to 65%, compared to
the strategy that schedules the tasks on the maximum number of processors and then exploits
the remaining slack to lower the supply voltage.

Mutoh et.al., 1995 [3]: For the most recent CMOS feature sizes (e.g., 90nm and 65nm),
leakage power dissipation has become an overriding concern for VLSI circuit designers.
ITRS reports that leakage power dissipation may come to dominate total power consumption.

2
The authors propose a novel approach, named “sleepy keeper,” which reduces leakage
current while saving exact logic state. Sleepy keeper uses traditional sleep transistors plus
two additional transistors – driven by a gate’s already calculated output to save state during
sleep mode. Dual Vth values can be applied to sleepy keeper in order to dramatically reduce
sub threshold leakage current. In short, like the sleepy stack approach, sleepy keeper achieves
leakage power reduction equivalent to the sleep and zigzag approaches but with the
advantage of maintaining exact logic state (instead of destroying the logic state when sleep
mode is entered). Based on experiments with a 4-bit adder circuit, sleepy keeper approach
achieves up to 49% less delay and 49% less area than the sleepy stack approach.
Unfortunately, sleepy keeper causes additional dynamic power consumption, approximately
15% more than the base case (no sleep transistors used at all). However, for applications
spending the vast majority of time in sleep or standby mode while also requiring low area,
high performance and maintenance of exact logic state, the sleepy keeper approach provides
a new weapon in a VLSI designer's arsenal.

Karimi and Alimoradi, 2011[4]: Rapid growth in semiconductor technology has led to
shrinking of feature sizes of transistors using deep submicron (DSM) process. As MOS
transistors enter deep submicron sizes, undesirable consequences regarding power
consumption arise. Until recently, dynamic or switching power component dominated the
total power dissipated by an IC. Voltage scaling is perhaps the most effective method to
decrease dynamic power due to the square law dependency of digital circuit active power on
the supply voltage. As a result, this demands a reduction of threshold voltage to maintain
performance.

Low threshold voltage results in an exponential increase in the sub-threshold leakage current.
On the other hand as technology scales down, shorter channel lengths result in increased sub-
threshold leakage current through an off transistor. Therefore, in DSM process static or
leakage power becomes a considerable proportion of the total power dissipation. For these
reasons, static power consumption, i.e. leakage power dissipation, has become a significant
portion of total power consumption for current and future silicon technologies.

There are several different approaches tackling leakage. Each technique provides an efficient
way to reduce leakage power, but disadvantages of each technique limit the application of
each technique.
3
Previously proposed work can be divided into following techniques:

(1) State-saving techniques: where circuit state (present value) is retained.

(2) State-destructive techniques: where the current Boolean output value of the circuit
might be lost.

MTCMOS power gating is a well-known way to reduce leakage and it continues to be

applied to very-deep submicron CMOS technologies. This can be done by using one PMOS
transistor and one NMOS transistor in series with the transistors of each logic block to create
a virtual ground and a virtual power supply. Notice that in practice only one transistor is
necessary, because of their lower on-resistance, NMOS transistors are usually used.

Amrutur et.al.,2000 [5]: They propose a novel approach that leverages circuit and
architecture level techniques to drastically reduce leakage power dissipation in high
performance caches even when most of the cache cells are actively used. They observe that
the cache resident memory values of ordinary programs exhibit a strong bias towards zero or
one at the bit level. They introduce a family of high-speed dual-Vt SRAM cell designs that
exploit this bit-level bias to reduce leakage power while maintaining low access latency. The
main characteristic of this cell family is asymmetry: Leakage power dissipation depends on
the actual bit value stored. Asymmetry is also a key to maintaining high performance reads
(the main disadvantage of a high-Vt cell).

They propose two asymmetric-cell cache (ACC) designs. The first is statically biased towards
the zero bit value. The other uses run-time selective inversion to increase the number of zero
holding bits. They evaluate their designs using the SPEC2000 benchmarks and for a
commercial 0.13m, 1.2V CMOS technology. They find that for most programs the majority
of memory bits are zero with the actual fraction varying from 52% to 88% for the level one
data cache. They also find that this bias is less evident in the instruction stream (around 60%
on the average). Using selective inversion, it is possible to further increase the fraction of
zero holding bits by another 6% and 11% for the level one data and instruction caches
respectively. Overall, for one cell design, leakage power is reduced by 96% and 94% for the

4
level one data and instruction caches compared to conventional caches. Finally, the novelty
of their proposed method has been established.

Roy et.al., 2003 [6]: High leakage current in deep-sub micrometer regimes is becoming a
significant contributor to power dissipation of CMOS circuits as threshold voltage, channel
length, and gate oxide thickness are reduced. Consequently, the identification and modelling
of different leakage components is very important for estimation and reduction of leakage
power, especially for low-power applications. This paper reviews various transistors intrinsic
leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate leakage,
gate induced drain and gate oxide tunnelling.

Channel engineering techniques including retrograde well and halo doping are explained as
means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the
paper explores different circuit techniques to reduce the leakage power consumption. To
achieve higher density and performance and lower power consumption, CMOS devices have
been scaled for more than 30 years. Transistor delay times decrease by more than 30% per
technology generation, resulting in doubling of microprocessor performance every two years.
Supply voltage has been scaled down in order to keep the power consumption under control.
Hence, the transistor threshold voltage has to be commensurately scaled to maintain a high
drive current and achieve performance improvement. However, the threshold voltage scaling
results in the substantial increase of the sub threshold leakage current.

In this paper, all leakage mechanisms contributing to the off-state current (not just the current
from the drain terminal) have been explored. Other leakage mechanisms are peculiar to the
small geometries themselves. As the drain voltage increases, the drain to channel depletion
region widens, resulting in a significant increase in the drain current. This increase in drain
current is due to channel surface current caused by drain-induced barrier lowering (DIBL) or
due to deep channel punch through currents. Moreover, as the channel width decreases, the
threshold voltage and the off current both get modulated by the width of the transistor, giving
rise to significant narrow-width effect.

All these adverse effects which cause threshold voltage reduction (leakage current increase)
in scaled devices are called short-channel effects (SCE). To maintain a reasonable SCE
immunity while scaling down the channel length, oxide thickness has to be reduced nearly in
5
proportion to the channel length. Decrease in oxide thickness results in increase in the electric
field across the gate oxide. The high electric field and low oxide thickness result in
considerable current flowing through the gate of a transistor. This current destroys the
classical infinite input impedance assumption of MOS transistors and thus affects the circuit
performance severely.

Powell et.al., 2000 [7]: Deep-submicron CMOS designs have resulted in large leakage
energy dissipation in microprocessors. While SRAM cells in on chip cache memories always
contribute to this leakage, there is a large variability in active cell usage both within and
across applications. This paper explores an integrated architectural and circuit level approach
to reducing leakage energy dissipation in instruction caches. They propose, gated-Vdd, a
circuit-level technique to gate the supply voltage and reduce leakage in unused SRAM cells.
Their results indicate that gated-Vdd together with a novel resizable cache architecture
reduces energy-delay by 62% with minimal impact on performance. The ever-increasing
levels of on-chip integration in the recent decade have enabled phenomenal increases in
computer system performance. Unfortunately, the performance improvement has been also
accompanied by an increase in a chip’s power and energy dissipation. Higher power and
energy dissipation require more expensive packaging and cooling technology, increase cost,
decrease product reliability in all segments of computing market, and significantly reduce
battery life in portable systems. Historically, chip designers have relied on scaling down the
transistor supply voltage in subsequent generations to reduce the dynamic energy dissipation
due to a much larger number of on chip transistors. Maintaining high transistor switching
speeds, however, requires a commensurate downscaling of the transistor threshold voltage
giving rise to a significant amount of leakage energy dissipation even when the transistor is
not switching.

Sumita et.al, 2005 [8]: There remains a need to improve sub-1-V CMOS VLSIs with respect
to variation in transistor behaviour. In this paper, to minimize variation in delay and the noise
margin of the circuits in processors, they propose several mixed body bias techniques using
body bias generation circuits. In these circuits, either the saturation region of the current
between source and drain or the threshold voltage of PMOS/NMOS is permanently fixed,
regardless of temperature range or variation in process. A test chip that featured these body
bias generation circuits was fabricated using a 130-nm CMOS process with a triple-well
structure. The mixed body bias techniques which keep the current (drain to source) of the
6
MOS in the decoder and I/O circuits of a register file fixed and maintain the threshold voltage
of MOS in both the memory cell and domino circuits of the register file fixed resulted in
positive temperature dependence of delay from 40 C to 125 C, 85% reduction of the delay
variation compared with normal body bias (NBB) at = 0 8 V. In addition, the results using
these techniques show a 100-mV improvement in lower operating voltage compared with
NBB at -40 degree C on a 4-kb SRAM.

Wei et. al., 1999 [9]: Reduction in leakage power has become an important concern in low
voltage, low-power, and high-performance applications. In this paper the dual-threshold
technique was used to reduce leakage power by assigning a high-threshold voltage to some
transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order
to achieve the best leakage power saving under target performance constraints, an algorithm
is presented for selecting and assigning an optimal high-threshold voltage. A general leakage
current model which has been verified by HSPICE simulations is used to estimate leakage
power. Results show that the dual-threshold technique is good for leakage power reduction
during both standby and active modes. For some ISCAS benchmark circuits, the leakage
power can be reduced by more than 80%. The total active power saving can be around 50%
and 20% at low- and high-switching activities, respectively.

Okuyama et. al., 1988 [10]: A 256K CMOS static RAM (SRAM) which achieves an access
time of 7.5 ns and 50-mA active current at 50 MHZ operation is described. A 32-block
architecture is used to achieve high-speed access and low power dissipation. To achieve
faster access time, a double activated- pulse circuit which generates the word-line-enable
pulse and the sense-amplifier-enable pulse has been developed. The data-output reset circuit
reduces the transition time and the noise generated by the output buffer. A new self-aligned
contact technology reduces the diffused region capacitance. This RAM has been fabricated in
a twin-tub CMOS 0.8 um technology with double-level poly silicon (the first level is
polycide) and double-level metal. The memory cell size is 6* 11 um2 and the chip size is
4.38X9.47 mm².

7
1.3 OBJECTIVE

This dissertation proposes various SRAM cells to reduce the static power dissipation and to
design low power SRAM memory cells of different configurations like 6T and 7T (where T
represents the transistor) and compare their performance parameters like-
 Read and write delay
 Leakage power consumption
 Static noise margins ( during hold, read and write)
As the technology is shrinking, the leakage power is increasing due to reduction in channel
length, threshold voltage and gate oxide thickness. In modern VLSI chips static RAMs are
used extensively as a critical component. SRAMs have large storage density and small access
latency. Therefore SRAMs are widely used as on chip memories where speed is more crucial
than capacity. Successive technology generations results in high chip density and therefore
leakage current is increasing exponentially due to more number of transistors per given area.
Design techniques are developed to reduce static power dissipation when the transistors are in
standby mode. Power gating is one technique where PMOS sleep transistor is added between
ground rail and circuit block and NMOS sleep transistor is added between VDD rail and
circuit block. These sleep transistors are added to cut off VDD rail from the circuit block
when the circuit block is not switching. In another technique two extra NMOS and PMOS
transistors are connected in series called stack approach. In sleep stack approach both the
technologies are combined and results are obtained. In this dissertation these conventional
leakage reduction techniques are applied to both 6T and 7T SRAM cells and results are
compared. The comparative analysis of the results shows that, Leakage reduction techniques
when applied with 7T model (9T, 11T and 13T) shows better performance as compared to
conventional 6T model (8T, 10T and 12T). Hence this dissertation concludes that 7T SRAM
cell with sleep and stacking approach (13T model) is the best leakage reduction technique.

8
 CHAPTER 2
THEORATICAL BACKGROUND

2.1 SRAM MEMORY

SRAM or Static Random Access Memory is a form of semiconductor memory widely used in
electronics, microprocessor and general computing applications. This form of semiconductor
memory gains its name from the fact that data is held in there in a static fashion, and does not
need to be dynamically updated as in the case of DRAM memory. While the data in the
SRAM memory does not need to be refreshed dynamically, it is still volatile, meaning that
when the power is removed from the memory device, the data is not held, and will disappear.
There are two key features to SRAM and these set it out against other types of memory that
are available.

a) The data is held statically: This means that the data is held in the semiconductor
memory without the need to be refreshed as long as the power is applied to the
memory.

b) SRAM is a form of random access memory: A random access memory is one in

which the locations in the semiconductor memory can be written to or read from in
any order, regardless of the last memory location that was accessed.

The circuit for an individual SRAM memory cell comprises typically four transistors
configured as two cross coupled inverters. In this format the circuit has two stable states, and
these equate to the logical "0" and "1" states. In addition to the four transistors in the basic
memory cell and additional two transistors are required to control the access to the memory
cell during the read and write operations. Sometimes further transistors are used to give either
8T or 10T memory cells. These additional transistors are used for functions such as
implementing additional ports in a register file, etc for the SRAM memory.

9
Although any three terminal switch device can be used in an SRAM, MOSFETs and in
particular CMOS technology is normally used to ensure that very low levels of power
consumption are achieved. With semiconductor memories extending to very large
dimensions, each cell must achieve very low levels of power consumption to ensure that the
overall chip does not dissipate too much power.

2.1.1 SCHEMATIC AND WORKING OF 6T SRAM CELL

A SRAM cell needs to be able to read and write data and to hold the data as long as the
power is applied. An ordinary flip-flop could accomplish this requirement, but the size is
quite large. Figure 2.1 shows a standard 6-transistor (6T) SRAM cell that can be an order of
magnitude smaller than a flip-flop. The 6T cell achieves its compactness at the expense of
more complex peripheral circuitry for reading and writing the cells [18].

Fig. 2.1 6T SRAM cell

The 6T SRAM cell contains a pair of weak cross-coupled inverters holding the state and a
pair of access transistors to read or write the state. The positive feedback corrects
disturbances caused by leakage or noise. The cell is written by driving the desired value and
its complement onto the bit lines, BL and BLB, then raising the word line (WL). The new data
overpowers the cross-coupled inverters. It is read by precharging the two bit lines high, then
allowing them to float. When word is raised, BL or BLB pulls down, indicating the data
value. The central challenges in SRAM design are minimizing its size and ensuring that the
circuitry holding the state is weak enough to be overpowered during a write, yet strong
enough not to be disturbed during a read.

10
2.1.1.1 READ OPERATION

Figure 2.2 shows a SRAM cell being read. The bit lines are both initially floating high.
Without loss of generality, assume Q is initially 0 and thus QBAR is initially 1. QBAR and
BLB both should remain 1. When the word line is raised, bit should be pulled down through
driver and access transistor. At the same time bit is being pulled down, node Q tends to rise.
Q is held low by driver, but raised by current flowing in from access transistor. Hence, the
driver must be stronger than the access transistor. Specifically, the ratio of transistors must be
such that node Q remains below the switching threshold of the M4/M3 inverter. This
constraint is called read stability. Waveforms for the read operation are shown in Figure 2.2
as a 0 is read onto bit. Observe that Q momentarily rises, but does not glitch badly enough to
flip the cell.

Fig. 2.2 Read operation for 6T SRAM cell

2.1.1.2 WRITE OPERATION

Figure 2.3 shows the SRAM cell being written. Again, assume Q is initially 0 and that we
wish to write a 1 into the cell. bit is precharged high and left floating. BLB is pulled low by a
write driver. We know on account of the read stability constraint that bit will be unable to
force Q high through access transistor. Hence, the cell must be written by forcing QBAR low
through M6. M4 opposes this operation; thus, M4 must be weaker than M6 so that QBAR can
be pulled low enough. This constraint is called writability. Once QBAR falls low, M1 turns
OFF and M2 turns ON, pulling Q high as desired.

11
 Fig 2.3 Write operation for 6T SRAM cell

2.1.2 SCHEMATIC AND WORKING OF 7T SRAM CELL

Main objective of this new 7T SRAM cell [30] is to have good Read Stability and static
Noise Margins (SNMs). 7T SRAM cell is shown in fig. 2.4. This SRAM cell is made up of
seven transistors, uses single bit-line (BL), a word line (WL), and a read line (RL). Since 7T
SRAM cell uses only one bit line, power required for charging and discharging of one more
bit line will be reduced. Hence usage of only one bit line reduces power required to charge
and discharge the bit lines approximately to half, because only one bit line is charged during
read operation instead of two. The bit line is charged during the write operation about half of
the time instead of every time when a write operation is required, here we are assuming equal
probability of writing 0 and 1. The 7T SRAM cell uses two transistors M6 and M7 with read-
line (RL) for read operation.

12
 Fig. 2.4 Schematic of proposed 7T SRAM Cell

2.1.2.1 READ AND WRITE OPERATION OF 7T SRAM CELL

While writing, the data need to be written will be loaded on bit-line (BL) and then word-line
(WL) will be activated. Strong access transistor M5 allows bit line to overpower the cell, so
that required data will be written into the cell. To write ‘1’ into the cell, the bit-line (BL) is
charged to VDD. If the data need to be written is ‘0’, bit-line should be at logic low, and then
word-line (WL) should be pulled to VDD. In write mode read-line (RL) will be inactive (i.e.
at logic ‘0’). To read data from the cell, initially bit line (BL) is being pre-charged to VDD.
After precharging the bit line read line (RL) is activated. Depending upon whether the bit line
(BL) discharges or holds the held charge, data stored in the 7T SRAM cell can be decided. If
BL discharges after pulling the RL to VDD, it indicates 7T SRAM cell is storing ‘0’ in it. If
bit line holds the held charge then the data stored is ‘1’. In read mode (WL) is inactive (i.e. at
logic ‘0’).

2.1.3 CELL STABILITY

To ensure both read stability and writability, the transistors must satisfy ratio constraints. The
NMOS pull down transistor in the cross-coupled inverters must be strongest. The access
transistors are of intermediate strength, and the PMOS pull up transistors must be weak. To
achieve good layout density, all of the transistors must be relatively small. The SRAM cells

13
must operate correctly at all voltages and temperatures despite process variation. The stability
and writability of the cell are quantified by the hold margin, the read margin, and the write
margin, which are determined by the static noise margin of the cell in its various modes of
operation. A cell should have two stable states during hold and read operation, and only one
stable state during write.

2.1.4 PERFORMANCE PARAMETERS OF SRAM

Read delay: Read delay is the delay involved in allowing the bit lines to discharge by
about 10% of the peak value or the delay between the application of the WL signal and the
response time of the sense amplifier.
Write delay: It is the delay between the applications of the word line WL signal and the
time at which the data is actually written.
Leakage power: The power consumed by a device not related to state changes (also
referred to as static power). Leakage power is actually consumed when a device is both static
and switching, but generally the main concern with leakage power is when the device is in its
inactive state, as all the power consumed in this state is considered “wasted” power.
Static Noise Margin: The static noise margin (SNM) measures how much noise can be
applied to the inputs of the two cross-coupled inverters before a stable state is lost (during
hold or read) or a second stable state is created (during write).

2.1.5 SRAM MEMORY APPLICATIONS

There are many different types of semiconductor memory that are available these days.
Choices need to be made regarding the correct memory type for a given application. Possibly
two of the most widely used types are DRAM and SRAM memory, both of which are used in
processor and computer scenarios. Of these two SRAM is a little more expensive than
DRAM. However SRAM is faster and consumes less power especially when idle. In addition
to this SRAM memory is easier to control than DRAM as the refresh cycles do not need to be
taken into account, and in addition to this the way SRAM can be accessed is more exactly
random access. A further advantage if SRAM is that it is more dense than DRAM. As a result
of these parameters, SRAM memory is used where speed or low power are considerations. Its
higher density and less complicated structure also lend it to use in semiconductor memory
scenarios where high capacity memory is used, as in the case of the working memory within
computers.
14
 CHAPTER 3
LEAKAGE CURRENT COMPONENTS INSIDE AN
SRAM CELL

3.1 LEAKAGE MECHANISM IN CMOS TRANSISTOR

There are four main source of leakage current in a CMOS transistor as shown in figure:
1. Reverse biased junction leakage (I )
2. Gate induced drain leakage (I )
3. Gate direct tunnelling leakage (I )
4. Sub threshold leakage (I )

3.1.1 JUNCTION LEAKAGE

The junction leakage occurs from the source or drain to the substrate through the reverse
biased diodes when a transistor is OFF. A reverse-biased P-N junction leakage has two main
components: one in minority carrier diffusion/drift near the edge of the depletion region, the
other is due the electron-hole pair generation in the depletion region of the reverse biased
junction. For example in the case of inverter with a low input voltage, the NMOS is OFF,
PMOS is ON and the output voltage is high. Subsequently the drain to substrate voltage of
the OFF NMOS transistor is equal to the supply voltage. This results in a leakage current
from the drain to the substrate through the reverse-biased diode. The magnitude of the diode
leakage current depends on the area of the drain diffusion and the leakage current density
which is in turn determined by the doping concentration. If both the n and p regions are
heavily doped, band to band tunnelling (BTBT) dominates the p-n junction leakage. Junction
leakage has a very high dependency on the temperature. However junction reverse leakage
components from the both source drain diodes and the well diodes are generally negligible
with respect to the other three leakage components.

15
3.1.2 GATE INDUCED DRAIN LEAKAGE
The gate induced drain leakage (GIDL) is caused by high field effect in the drain junction of
MOS transistors. For a NMOS transistor with grounded gate and drain potential at VDD, a
significant band bending in the drain allow electron-hole pair generation through avalanche
multiplication and the band to band tunnelling. A deep depletion condition is created since
the holes are rapidly swept out to the substrate. At the same time electrons are collected by
the drain, resulting in GIDL current. This leakage mechanism is made work by high drain to
body voltage and high drain to gate voltage.

Transistor scaling has led to the increasingly steep halo implants, where the substrate doping
at the junction interface is increased, while the channel doping is low. This is done mainly to
control punch-through and drain-induced barrier lowering while having a low impact on the
carrier mobility in the channel. The resulting steep doping profile at the drain edge increases
band to band tunnelling current there, particularly a VDB is increased. Thinner oxide and
higher supply voltage increases GIDL current.

3.1.3 GATE DIRECT TUNNELING LEAKAGE

With scaling of the channel length, maintaining good transistor aspect ratio by the
comparable scaling of the gate oxide thickness, junction depth and depletion depth are
important for ideal MOS transistor behaviour. Unfortunately with the technology scaling,
maintaining good transistor aspect ratio has been a challenge. In other words, reduction of the
vertical dimensions has been harder than that of horizontal dimensions with the silicon oxide
gate thickness approaching scaling limits there is now a rapid increase in gate direct
tunnelling leakage current.
Due to quantum mechanical and poly silicon gate depletion effects, both the gate charge and
inversion layer charge will be located at the finite distance from the oxide channel interface
with the charge location being a strong function of bias applied to the gate. The location of
the inversion layer in the silicon substrate for a transistor with a typical bias when quantum
mechanical effects are taken into account is 1 nm from the oxide channel interface. This
increases the effective oxide thickness by 0.3 nm. Taking charge spread on the both sides of
the interface along with poly depletion charge the 1nm oxide tunnelling limit into an effective
oxide thickness of 1.7 nm.

16
To compact this limit researchers have been exploring several alternatives including the use
high permittivity gate dielectric, metal gate, novel transistor structure and circuit based
techniques. The use of high permittivity gate dielectric will result in thicker and easier to
fabricate dielectric for gate oxide capacitance with potential for significant reduction in gate
leakage. Identification of a proper high permittivity dielectric material that has good interface
state with silicon along with limited gate leakage is in progress. However it has also been
shown that use of high permittivity gate dielectric has limited value.

3.1.4 SUBTHRESHOLD LEAKAGE

The sub threshold leakage is current flowing from drain to source when a transistor operated
in weak inversion region. Unlike the strong inversion region in which the drift-current
dominates, the sub threshold conduction is due to the diffusion current of the minority
carriers in the channel for a MOS device. For instance, in case of an inverter with a low input
voltage, the NMOS is turned off and the output voltage is high. In this case, although VGS is
0V, there is still a current flowing in the channel of the OFF NMOS transistor due to the VDD
potential of the VDS. The magnitude of the sub threshold current is a function of temperature,
supply voltage, device size and the process parameter out of which the threshold voltage
plays a dominant role. For the current CMOS technologies, the sub threshold leakage current,
ISUB is much larger than the other leakage current components. This is much larger than the
other leakage current components. This is mainly because VT is lower in modern device.

I= µ 1− … … … … … … . (1.1)

Equation 1.1 describes sub threshold current in terms of other device parameters
Here W and L denote the transistor width and length, µ denotes the carrier mobility.

= … … . … … … … … . . … (1.2)

Vth is the thermal voltage

is given by

=1+ … … … … … … … … (1.3)

17
Here denotes the gate input capacitance per unit area, C is the sum of depletion region
capacitance and interface trap capacitance.

3.2 LEAKAGE MECHANISM INSIDE AN SRAM

When SRAM cell is in standby mode then static power dissipation occurs due to following
factors:-
 High parasitic capacitance

 Diode leakage current

 Gate leakage current

 Switching action of transistors

 Sub threshold leakage current

An SRAM cell is in the inactive state, when the word line is held low and bit line is charged
to VDD. These inactive states come in between read and write operations. In the inactive
state, different transistors dissipate leakage power depending on the value stored in the cell.
This leakage current primarily owes its origin to two dominant leakage mechanism viz., sub
threshold leakage and gate leakage. Major contributors to the gate leakage current are gate
oxide tunnelling and injection of hot carrier from substrate to the gate oxide. Gate-induced
drain leakage (GIDL) is another significant leakage mechanism, resulting due to the depletion
at the drain surface below the gate-drain overlap region. Due to the substantial increase in the
leakage current, the static power consumption is expected to exceed the switching component
of the power consumption unless effective measures are taken to reduce the leakage power.
Due to adverse SCEs, the channel length cannot be arbitrarily reduced even if allowed by
lithography. For digital applications, the most undesirable SCE is the reduced gate threshold
voltage at which the device turns on, especially at high drain voltages. Therefore, to take the
best advantage of the new high-resolution lithographic techniques, new device designs,
structures, and technologies should be developed to keep SCEs under control at very small
dimensions. In addition to gate oxide thickness and junction scaling, another technique to
improve short-channel characteristics is well engineering. By changing the doping profile in
the channel region, the distribution of the electric field and potential contours can be changed.
The goal is to optimize the channel profile to minimize the off-state leakage while
maximizing the linear and saturated drive currents. Super steep retrograde wells and halo

18
implants have been used as a means to scale the channel length and increase the transistor
drive current without causing an increase in the off-state leakage current.
Till recently, the drain source sub-threshold current had been thought to be the dominant
leakage mechanism. A number of techniques have been proposed in the particular literature
for reducing drain to source sub-threshold leakage when the SRAM is in the inactive state.

3.2.1 SUB THRESHOLD LEAKAGE

Sub threshold leakage is the drain-source current of a transistor when the gate-source voltage
is less than the threshold voltage (Figure 2.2 [22]). More precisely, sub threshold leakage
happens when the transistor is operating in the weak inversion region. The sub threshold
current depends exponentially on threshold voltage, which results in large sub threshold
current in short channel devices. To reduce the sub threshold leakage of an SRAM cell, one
can increase the threshold voltage of all or some of the transistors in the cell. The drawback
of this technique is an increase in read/write delay of the cell. If the threshold voltage of the
pull up PMOS transistors is increased, the write delay increases whereas the effect on the
read delay would be negligible.
On the other hand, if the threshold voltage of the pull down NMOS transistors is increased,
the read delay increases whereas the effect on the write delay would be marginal. By
increasing the threshold voltage of the pass transistors both read and write delays increase.
Due to the delay of sense amplifiers and output buffers in a read path, the write delay of an
SRAM cell tends to be smaller than its read delay. Therefore, one can think of reducing the
sub threshold leakage by increasing the threshold voltage of the PMOS transistors as long as
the write delay is less than the read delay.

Figure 3.1 Sub Threshold Leakage

19
3.2.2 GATE TUNNELING LEAKAGE
Electrons (holes) tunnelling from the bulk silicon through the gate oxide into the gate results
in gate tunnelling current in an NMOS (PMOS) transistor. Gate tunnelling current is
composed of three major components:

 Gate to source and gate to drain overlap current.

 Gate to channel current, part of which goes to source and the rest goes to drain.
 Gate to substrate current.

In bulk CMOS technology, the gate to substrate leakage current is several orders of
magnitude lower than the overlap tunnelling current and gate to channel current [22]. On the
other hand, while the overlap tunnelling current dominates the gate leakage in the OFF state,
gate to channel tunnelling dictates the gate current in the ON condition. Since the gate to
source and gate to drain overlap regions are much smaller than the channel region, the gate
tunnelling current in the OFF state is much smaller than gate tunnelling in the ON state [22].
If SiO2 is used for the gate oxide, PMOS transistors will have about one order of magnitude
smaller gate leakage than NMOS transistors [22, 23]. Therefore, in an SRAM cell, the power
saving achieved by increasing the oxide thickness of the PMOS transistors is marginal. The
sub threshold and gate tunnelling leakage currents of an SRAM cell storing “0” are shown in
Figure 2.3[22].

Figure 3.2 Gate Tunnelling Leakage

20
3.3 STANDBY LEAKAGE REDUCTION TECHNIQUES
3.3.1 LEAKAGE REDUCTION BY STACKING EFFECT

Stacking of series-connected transistors reduces the sub threshold leakage currents when
more than one transistor in the stack is turned off, which is known as stacking effect [19]. It
yields a positive potential at the intermediate node of off-transistors, which has three effects:
1) Gate-to-source voltage of upper transistor becomes negative
2) Reverse biased body-to-source voltage of upper transistor induces larger body effect
3) Reduced drain-to-source voltage

Fig. 3.3 Stacking approach for leakage reduction

As shown in the above figure 2, there is a stack of series connected transistors. If the input is
zero then both the transistors M1 and M2 are in off state. The voltage at node A is higher than
ground due to internal resistance of M2. Due to this small voltage at node A the gate to
source voltage of M2 is negative and therefore sub threshold current reduces. The positive
voltage at node A results in positive body to source potential of M2.Therefore threshold
voltage of M2 increases to further reduce the leakage current. The drain to source potential of
M2 decreases due to positive voltage at node A. Therefore due to Drain Induced Barrier
Lowering (DIBL) affect the threshold voltage of M2 increases. The overall leakage current
reduction takes place due to all these effects. Leakage in a logic gate depends on the applied

21
input vector during standby periods since it determines the number of off-transistors in the
stack. In the following, existing techniques are described in more details.

3.3.2 LEAKAGE REDUCTION BY SLEEP TRANSISTOR

There are many ways to use a sleep transistor, but the basic idea is to increase the resistance
by inserting the extra transistors (sleep transistors) in series between the power supply and
ground, thereby reducing the standby leakage currents. The sleep transistors are turned on
when circuits are in active mode and turned off when circuits are in standby mode. In the
following, existing techniques are described in more details.

Fig. 3.4 Sleep approach for leakage reduction

As shown in above diagram power gating [20][21] technique uses additional transistors,
called sleep transistors, which are inserted in series between the power supply and pull-up
(PMOS) network and between pull-down (NMOS) network and ground to reduce the standby
leakage currents. The sleep transistors are turned “ON” when circuits are in active mode and
turned off when circuits are in standby mode. By disconnecting the logic networks from the

22
power supply and ground using sleep transistors, this technique reduces the leakage power in
standby mode. During standby mode, both sleep transistors are turned off to produce stacking
effect which reduces leakage current by increasing resistance of the path from power supply
to ground.

3.3.3 LEAKAGE REDUCTION BY INCREASING THE THRESHOLD

VOLTAGES

Increasing the threshold voltage is one of the effective ways to reduce the leakage current.
There are several ways to achieve this [24].
 Increase a doping concentration.
 Increase a gate oxide thickness.
 Apply a reverse body bias voltage.
In the following, existing techniques are described in more details.
Multi-threshold voltage CMOS (MTCMOS) [24]-[25] uses high-threshold devices as sleep
transistors while low-threshold devices are used to implement the logic. In practice, one sleep
transistor per gate is used, but larger granularities are also used, which require fewer but
larger sleep transistors. Typically, the NMOS sleep transistor is preferable because the on
resistance of NMOS is smaller than that of PMOS at the same width; hence, NMOS has size
advantage over PMOS. This technique, however, comes with area and performance penalties.

Figure 3.5 Dual threshold voltage techniques

Dual threshold voltage technique [26]-[27] assigned different threshold voltages depending
on whether a gate is on critical or non-critical path as shown in Figure. Low threshold voltage
on the critical path is used to maintain the performance; while high threshold voltage

23
assigned along non-critical path reduces the leakage current.7T SRAM model is designed by
using this technique for leakage reduction.

Figure 3.6 Reverse Body Biasing

Reverse boy biasing (RBB) [28]-[29] is an effective way of reducing the leakage in standby
mode by increasing the threshold voltages of MOS transistors (making the substrate (body)
voltage higher than supply voltage for PMOS transistors and lower than ground for NMOS
transistors); reverse biasing body to source junction of a MOS transistor widens the bulk
depletion region and increases the threshold voltage. Reverse body bias is applied to suppress
the leakage current when circuits are in standby mode, and is removed to restore the nominal
performance of the transistors when circuits are in active mode as shown in Figure 3.6.

24
 CHAPTER 4
PROPOSED SRAM CELLS FOR LEAKAGE
REDUCTION

4.1 SLEEP APPROACH

Solutions for leakage reduction are required at both process technology and circuit levels
[14]. One of the methods at circuit level to reduce the leakage power is by adding two sleep
transistors in 6T SRAM circuit.

4.1.1 8T SRAM CELL

8T SRAM cell is designed by adding NMOS and PMOS sleep transistors to basic 6T SRAM
cell. Sleep transistors are the two extra transistors connected to the SRAM load circuit.

Fig 4.1 schematic of 8T SRAM cell

As shown in above figure 4.1, NMOS M8 sleep transistor is connected between VDD and
pull up network and PMOS M9 sleep transistor is connected between pull down network and
ground. When SRAM cell is in active mode then both sleep transistors remain in on state.
The voltage at source node of sleep NMOS transistor is the difference between the power
supply and threshold voltage of NMOS. The voltage at source node of PMOS sleep transistor

25
is equal to negative of threshold voltage of PMOS. Static power is proportional to applied
voltage, so with the reduced voltage the power reduces.
4.1.2 9T SRAM CELL
9T SRAM cell is designed by adding NMOS and PMOS sleep transistors to 7T SRAM cell
for leakage reduction. As 7T SRAM cell is designed to reduce the leakage current by using
dual threshold technique in which the transistors which are not in critical path are kept at high
threshold voltage as compared to transistors which are in critical path as explained above in
section 3.3.3. Now to further reduce the leakage current we have used sleep approach to this
7T SRAM cell as shown in figure 4.2

Fig 4.2 Schematic of 9T SRAM cell

As shown in figure 4.2, in the active mode of operation, both the sleep transistors NMOS
(M8) and PMOS (M9) are turned on. According to the NMOS and PMOS pass transistors'
property; the voltage at the source node of M8 would be VDD-VTH whereas the voltage at
the source node of M9 would be -Vth. In the stand-by mode of operation both the sleep
transistors M8 and M7 are turned off and these transistors provide very high impedance paths
between VDD to ground and a very small sub-threshold leakage current flows.

26
4.2 STACK APPROACH

By using stacking approach we have designed 10T and 11T SRAM cells. In this method there
are 8 cross coupled transistors in SRAM cell and leakage is drastically reduced in an
exponential manner with the increase of threshold voltage.

4.2.1 10T SRAM CELL

6T SRAM cell with stacking approach is shown in figure 4.3. Here two additional PMOS and
two additional NMOS transistors are connected to conventional circuit block to control the
leakage current. In the pull up network the drain of M5 and M6 is connected to source of M7
and M8 respectively. Similarly in the pull down network the source of M2 and M3 is
connected to drain of M9 and M10 respectively. These leakage control transistors will work
near cut off region. So, the resistances in conducting state will be less than off state
resistances. Therefore little conduction takes place and overall resistance from VDD to
ground path increases due to which leakage current reduces

Fig 4.3 Schematic of 10T SRAM cell

4.2.2 11T SRAM CELL
11T SRAM cell is designed by using the stacking approach with the 7T SRAM cell as shown
in figure 4.4. In Fig. 4.4, eight transistors (M4-M3, M5-M6, M7-M8 and M1-M2) are cross-

27
coupled. The pairs of M4-M8 and M1-M5 are called leakage control transistors. Here two
leakage control transistors NMOS (M1 and M5) and PMOS (M4 and M8) are connected with
two symmetrical invertors.
Here in Fig.4.4 drain terminals of both the transistors (M7 and M3) or, (M2 and M6) are
connected to the nodes Q and QB and produce output voltages, respectively. By the
properties of leakage control transistors (M4-M8) and (M1-M5), they will work near its cut-
off region, so their resistances will be lesser than their OFF resistances, thus allowing a little
conduction [12]. Even though the resistances are not as high as their OFF state resistances,
they increase the resistance from VDD to ground path, controlling the flow of lower leakage
currents, resulting in leakage power reduction [13].

Fig. 4.4 Schematic of 11T SRAM cell

4.3 SLEEP AND STACK APPROACH

In this approach, we have combined both the techniques. By adding stack and sleep
transistors to both 6T and 7T SRAM cell, we designed the 12T and 13T SRAM cell
respectively.

28
4.3.1 12T SRAM CELL
The schematic of 6T SRAM cell with both stacking and sleep transistors is shown in figure
4.5. In this approach, we have combined both stacking and sleep approach. When SRAM cell
is in standby mode then both the sleep transistors are in cut off state and due to stacking of
transistors further reduction in leakage current takes place. There is increase in area due to
extra transistors and wires for sleep signals.

Fig. 4.5 12T SRAM Cell

4.3.2 13T SRAM CELL

13T SRAM cell is designed by applying both stacking and sleep approach to 7T SRAM cell
to further reduce the leakage current. As we have discussed above that power gating is one
technique where PMOS sleep transistor is added between ground rail and circuit block and
NMOS sleep transistor is added between VDD rail and circuit block. These sleep transistors
are added to cut off VDD rail from the circuit block when the circuit block is not switching.
In another technique two extra NMOS and PMOS transistors are connected in series called
stack approach. In sleep stack approach both the technologies are combined and results are
obtained as shown in below figure 4.6

29
Fig. 4.6 Schematic of 13T SRAM cell

30
 CHAPTER 5
SIMULATION AND RESULT

5.1 SOFTWARE TOOL

All the simulation work is done using analog environment virtuoso (cadence) simulator for
circuit design, circuit logic verification and power calculation of the circuit at 65nm
technology. For calculation of area, we have designed the layouts of all SRAM cells using
cadence tool. Layouts are verified by using Mentor’s Calibre DRC (Design rule check) and
LVS (layout v/s schematic). We have used 1.2 V supply voltage VDD.
Cadence tool is electronic design automation (EDA) environment for the design, layout and
verification of analog, mixed signal, RF and MEMS ICs.

5.2 CELL STABILITY

After making a schematic we have to set the W/L ratio of the driver, access and load
transistor that we have used in the basic cell design. In any CMOS circuit design W/L ratio is
important parameter because this is the only parameter in the hand of the design engineer. So
it should be carefully selected in the design of memory cell. There are number of design
criteria must be taken into consideration. The two basic criteria which we have taken are
given below.
I. The data read operation should not be destructive.
II. Static noise margin should be in the acceptable range.
We take the static noise margin (SNM) consideration to calculate the W/L ratio. SNM is
defined as maximum value of noise that can be tolerated by cross coupled inverters before
altering the state SNM is very important parameter to design any of the memory cell because
it indicate the stability of the cell. So the cell sizing is summarized as:

Cell Sizing:
W1/L1 = 230nm / 70nm ………………… (NMOS latch transistor)
W2/L2 = 160nm / 80nm ………………… (Access transistor)
W3/L3 = 160nm / 80nm ………………… (Access transistor)
W4/L4 =135nm / 80nm…………………. (PMOS latch transistor)

31
W5/L5 = 230nm/ 70nm…………………. (NMOS latch transistor)
W6/L6 = 135nm / 80nm ………………… (PMOS latch transistor)

5.2.1 CALCULATION OF W/L RATIO OF DRIVER, ACCESS AND

LOAD TRANSISTOR

.W/L ratio of the PMOS transistor = 1.68

W/L ratio of the Access transistor = 2
W/L ratio of the NMOS transistor = 3.28

5.2.1.1 Calculation of Cell Ratio (CR)

The CR (β) is the cell ratio defined as:

CR= (W1/L1) / (W5/L5) = β = 3.2857/2 = 1.64
(During Read Operation)

5.2.1.2 Calculation of Pull-up Ratio (PR)

The pull-up ratio of the cell, PR, is defined as:

PR = (W4/L4) / (W6/L6) = PR=1.6875/2 = 0.84
(During Write Operation)
• Bit cell ratio (β) should be from1.25 to 2.5.
• The value of PR has to be less than 1.8.

5.3 SIMULATIONS OF 6T AND 7T SRAM CELLS

We have simulated the basic 6T and 7T (where T represents the transistor) SRAM cells using
cadence tool to compare their performance parameters like-
 Read and write delay
 Leakage power consumption
 Static noise margins ( during hold, read and write)

32
5.3.1 SCHEMATIC OF 6T SRAM CELL FOR READ OPERATION

Fig. 5.1 Schematic of 6T SRAM cell during read operation

5.3.2 WAVEFORMS OF 6T SRAM CELL FOR READ OPERATION

Fig. 5.2 Output waveform of 6T SRAM cell during read operation

33
 5.3.3 SCHEMATIC OF 6T SRAM CELL FOR WRITE OPERATION.

Fig. 5.3 Schematic of 6T SRAM cell during write operation

5.3.4 WAVEFORMS OF 6T SRAM CELL FOR WRITE OPERATION

Fig. 5.4 Output waveform of 6T SRAM cell during write operation

34
 5.3.5 SCHEMATIC OF 6T SRAM FOR WRITE STATIC NOISE
MARGIN

Fig. 5.5 Schematic of 6T SRAM cell for calculation of write static noise margin

5.3.6 WAVEFORM OF 6T SRAM FOR WRITE STATIC NOISE

MARGIN

Fig. 5.6 Waveform of 6T SRAM cell for calculation of write static noise margin

35
5.3.7 SCHEMATIC OF 6T SRAM FOR READ STATIC NOISE MARGIN

Fig. 5.7 Schematic of 6T SRAM cell for calculation of read static noise margin

5.3.8 WAVEFORM OF 6T SRAM FOR READ STATIC NOISE MARGIN

Fig. 5.8 waveform of 6T SRAM cell for calculation of read static noise margin

36
5.3.9 SCHEMATIC OF 6T SRAM FOR HOLD STATIC NOISE
MARGIN

Fig. 5.9 Schematic of 6T SRAM cell for calculation of hold static noise margin

5.3.10 WAVEFORM OF 6T SRAM FOR HOLD STATIC NOISE

MARGIN

Fig. 5.10 Waveform of 6T SRAM cell for calculation of hold static noise margin

37
5.3.11 SCHEMATIC OF 7T SRAM CELL FOR READ OPERATION

Fig. 5.11 Schematic of 7T SRAM cell during read operation

5.3.12 WAVEFORM OF 7T SRAM CELL FOR READ OPERATION

Fig. 5.12 Waveform of 7T SRAM cell during read operation

38
5.3.13 SCHEMATIC OF 7T SRAM CELL FOR WRITE OPERATION

Fig. 5.13 Schematic of 7T SRAM cell during write 1 operation

5.3.14 WAVEFORMS OF 7T SRAM CELL FOR WRITE 1 OPERATION

Fig. 5.14 Waveform of 7T SRAM cell during write 1 operation

39
5.3.15 SCHEMATIC OF 7T SRAM CELL FOR WRITE OPERATION

Fig. 5.15 Schematic of 7T SRAM cell during write 0 operation

5.3.16 WAVEFORMS OF 7T SRAM CELL FOR WRITE OPERATION

Fig. 5.16 Waveform of 7T SRAM cell during write 0 operation

40
5.3.17 SCHEMATIC OF 7T SRAM FOR READ STATIC NOISE
MARGIN

Fig. 5.17 Schematic of 7T SRAM cell for calculation of read static noise margin

5.3.18 WAVEFORM OF 7T SRAM FOR READ STATIC NOISE

MARGIN

Fig. 5.18 Waveform of 7T SRAM cell for calculation of read static noise margin

41
5.3.19 SCHEMATIC OF 7T SRAM FOR WRITE STATIC NOISE
MARGIN

Fig. 5.19 Schematic of 7T SRAM cell for calculation of write static noise margin

5.3.20 WAVEFORM OF 7T SRAM FOR WRITE STATIC NOISE

MARGIN

Fig. 5.20 Waveform of 7T SRAM cell for calculation of write static noise margin

42
5.4 SIMULATION OF LEAKAGE CONTROL MODELS

Simulation work of all the leakage control models discussed in chapter 4 is carried out to
calculate the leakage current using cadence tool. When SRAM is idle (word line =0, i.e. no
read and write operation) then current supplied by the voltage source VDD is leakage current.
While calculating the leakage current internal data storage nodes must be initialized by
complementary bits.

5.4.1 WAVEFORM OF LEAKAGE CURRENT IN 8T SRAM CELL

Fig. 5.21 Leakage current waveform of 8T SRAM cell

43
5.4.2 WAVEFORM OF LEAKAGE CURRENT IN 9T SRAM CELL

Fig. 5.22 Leakage current waveform of 9T SRAM cell

5.4.3 WAVEFORM OF LEAKAGE CURRENT IN 10T SRAM CELL

Fig. 5.23 Leakage current waveform of 10T SRAM cell

44
 5.4.4 WAVEFORM OF LEAKAGE CURRENT IN 11T SRAM CELL

Fig. 5.24 Leakage current waveform of 11T SRAM cell

5.4.5 WAVEFORM OF LEAKAGE CURRENT IN 12T SRAM CELL

Fig. 5.25 Leakage current waveform of 12T SRAM cell

45
5.4.6 WAVEFORM OF LEAKAGE CURRENT IN 13T SRAM CELL

Fig. 5.26 Leakage current waveform of 13T SRAM cell

46
5.5 LAYOUTS OF LEAKAGE CONTROL SRAM CELLS

For calculation of area, we have designed the layouts of all SRAM cells using cadence tool.
Layouts are verified by using Mentor’s Calibre DRC (Design rule check) and LVS (layout
versus schematic).

5.5.1 6T SRAM CELL LAYOUT

Fig.5.27 6T SRAM cell layout

47
5.5.2 7T SRAM CELL LAYOUT

Fig. 5.28 7T SRAM Cell layout

5.5.3 8T SRAM CELL LAYOUT

Fig. 5.29 8T SRAM Cell layout

48
5.5.4 9T SRAM CELL LAYOUT

Fig. 5.30 9T SRAM Cell layout

5.5.5 10T SRAM CELL LAYOUT

Fig. 5.31 10T SRAM Cell layout

49
5.5.6 11T SRAM CELL LAYOUT

Fig. 5.32 11T SRAM Cell layout

5.5.7 12T SRAM CELL LAYOUT

Fig. 5.33 12T SRAM Cell layout

50
5.5.8 13T SRAM CELL LAYOUT

Fig. 5.34 13T SRAM Cell layout

51
5.6 RESULTS
We have tabulated the results of the entire research work. Table 1 provides the comparative
analysis between 6T and 7T SRAM cell. Table 2 provides the leakage current in basic SRAM
models and reduction in leakage power after adopting various techniques. From layout of
various SRAM models it also calculates the area. Table 3 compares the percentage increase
in area and percentage decrease in leakage current of all SRAM cells.

TABLE 1 COMPARISION OF VARIOUS PERFORMANCE PARAMETERS

SRAM CELL 6T 7T % ANALYSIS

READ DELAY (ns) 0.161 2.1598 12.41 %

(INCREASE)
WRITE DELAY (ns) 0.3792 0.3695 2.55 %
(DECREASE)
LEAKAGE 334.2682 200.833 39.91 %
CURRENT (pA) (DECREASE)
LEAKAGE POWER 0.4011 0.2410 39.91 %
(pA) (DECREASE)
READ SNM (mV) 195.94 474.62 142.22%
(INCREASE)
WRITE SNM (mV) 488.443 427.135 12.55%
(DECREASE)
HOLD SNM (mV) 426.29 426.29 NO CHANGE

52
 TABLE2. LEAKAGE POWER AND AREA FOR SRAM MODELS

CIRCUIT TOTAL TOTAL LEAKAGE AREA OF CELL

(65 nm LEAKAGE POWER (nW) (µm²)
TECHNOLOGY) CURRENT (pA)

6T SRAM CELL 418.739 0.502 10.9681

7T SRAM CELL 230.1994 0.276 14.6497

8T SRAM CELL 11.6138 0.013 14.7839

9T SRAM CELL 5 .006 16.4138

10T SRAM CELL 32.591 0.039 16.1261

11T SRAM CELL 24.3799 0.02925 18.6956

12T SRAM CELL 8 0.0096 18.6572

13T SRAM CELL 2.05105 0.0024 21.1308

53
 TABLE3. COMPARATIVE ANALYSIS

SRAM MODELS DECREASE IN INCREASE IN AREA

LEAKAGE POWER

BASIC SRAM CELLS (6T 58.96% 25.13%

V/S 7T)

SRAM CELLS WITH 25% 13.74%

SLEEP APPROACH
(8T V/S 9T)
SRAM CELLS WITH 53.84% 9.93%
STACKING APPROACH
(10T V/S 11T)
SRAM CELLS WITH 75% 11.70%
BOTH SLEEP AND
STACKING APPROACH
(12T V/S 13T)

54
 CHAPTER 6
CONCLUSION AND FUTURE SCOPE
6.1 CONCLUSION
The simulation of 6T and 7T SRAM cells has been carried out successfully with the help of
cadence tool on 65nm technology at 25 degree Celsius. The compared parameters are
propagation delay, power consumption and noise margin (during hold, read and write).
The results obtained from the simulation of 6T and 7T cell shows that 7T SRAM cell gives
the low power and better stability as the structure is such modified that it uses the single bit
line for charging and discharging and providing dual port operation also. We can see that by
single bit operation write delay is reduced by 2.55% and by using dual threshold voltage
technique leakage power consumption is also reduced by 39.91%. Read destruction problem
is also cured as read SNM is increased by 142.22%, but write SNM is little reduced which we
can consider acceptable as other parameters are improved.
The comparative analysis of the results shows that, Leakage reduction techniques when
applied with 7T model (9T, 11T and 13T) shows better performance as compared to
conventional 6T model (8T, 10T and 12T). 7T SRAM cell with sleep and stacking approach
(13T model) is the best leakage reduction technique and it yields 75% leakage power
reduction and only 11.70% area increment as compared to 6T SRAM cell with sleep and
stacking approach (12T model). By adding extra transistors there is an increase in delay and
area of SRAM cell. Hence the authors conclude that the proposed SRAM architectures (9T,
11T and 13T) can be used for low power applications and high performance.

6.2 FUTURE SCOPE

 Investigating the effect of transistor adding on circuit delay:

In our research, we focus on reducing leakage power consumption, and did not consider the
effect of transistor adding on circuit delay. So, this should be analyzed and designed in order
to meet the circuit performance value.
 Analyzing the impact of loading effect on leakage current:

The impact of the loading effect on leakage current is considered to further enhance the
accuracy of leakage current analysis in standby leakage reduction methods.

55
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