DSD lab Manuals LAB12

DESIGN AND IMPLEMENTATION OF A REAT TIME CLOCK ON FPGA.

OBJECTIVES

Designing and implementation of a real time clock inVerilog on FPGA using seven
segments and push buttons.

INTRODUCTION

A real time clock shows seconds, minutes and hours on the seven segments
available on the board. The time can be changed by using switches present on the
board .later on calendar for showing date on the seven segments can also be
implemented.

Verilog Code:
modulereal_time_clk_verilog (clk,clear,hour1,hour2,minute1,minute2,second1,
second2, hour_A2, min_A1, sec_A0, load, data_in);
inputclk,clear;
outputreg [6:0]hour1,hour2,minute1,minute2,second1,second2;
input load;
input hour_A2,min_A1,sec_A0;
input [7:0]data_in;
regclk_sec,clk_msec;
reg [7:0]sec,min,hr;
integer timer_count1=0,timer_count2=0;
always@(posedgeclk)
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begin
if(timer_count1==3999)
begin
timer_count1=0;
clk_msec=1'b1;
end
else
begin
timer_count1=timer_count1+1;
clk_msec=1'b0;
end
end

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always@(posedgeclk_msec)
begin
if(timer_count2==999)
begin
timer_count2=0;
clk_sec=1'b1;
end
else
begin
timer_count2=timer_count2+1;
clk_sec=1'b0;
end
end
always@(negedgeclk_sec)
begin
if(~clear)
begin
sec=0;
min=0;
hr=0;
end
else
if(~load)
begin
if(hour_A2)
begin
if(hr[7:4] == 4'b0010)
begin
if(hr[3:0] < 4'b0100)
hr = data_in;
end
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else if(hr[7:4] < 4'b0010)
hr = data_in;
else
hr = 8'b0;
end
if(min_A1)
begin
if(min[7:4] < 4'b0110)
min = data_in;

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DSD lab Manuals LAB12
else
min = 8'b0;
end
if(sec_A0)
begin
if (sec[7:4] < 4'b0110)
sec = data_in;
else
sec = 8'b0;
end
end
else
begin
if(sec[3:0]==4'b1001)
begin
sec[3:0]=4'b0;
if(sec[7:4]==4'b0101)
begin
sec[7:4]=4'b0;
if(min[3:0]==4'b1001)
begin
min[3:0]=4'b0;
if(min[7:4]==4'b0101)
begin
min[7:4]=4'b0;
if(hr==8'b00100011)
hr=0;
else if(hr[3:0]==4'b1001)
begin
hr[3:0]=4'b0;
hr[7:4]=hr[7:4]+1;
end
else
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hr[3:0]=hr[3:0]+1; //hours count completed
end
else
min[7:4]=min[7:4]+1;
end
else
min[3:0]=min[3:0]+1; // minutes count

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DSD lab Manuals LAB12
completed
end
else
sec[7:4]=sec[7:4]+1;
end
else
sec[3:0]=sec[3:0]+1; //seconds count completed
end
end
always@(sec)
begin
case (sec[3:0])
4'b0000: second1=7'b1111110;
4'b0001: second1=7'b0110000;
4'b0010: second1=7'b1101101;
4'b0011: second1=7'b1111001;
4'b0100: second1=7'b0110011;
4'b0101: second1=7'b1011011;
4'b0110: second1=7'b1011111;
4'b0111: second1=7'b1110000;
4'b1000: second1=7'b1111111;
4'b1001: second1=7'b1111011;
default: second1=7'b0;
endcase
end
always@(sec)
begin
case(sec[7:4])
4'b0000: second2=7'b1111110;
4'b0001: second2=7'b0110000;
4'b0010: second2=7'b1101101;
4'b0011: second2=7'b1111001;
4'b0100: second2=7'b0110011;
4'b0101: second2=7'b1011011;
4'b0110: second2=7'b1011111;
4'b0111: second2=7'b1110000;
4'b1000: second2=7'b1111111;
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4'b1001: second2=7'b1111011;
default: second2=7'b0;
endcase

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DSD lab Manuals LAB12
end
always@(min)
begin
case(min[3:0])
4'b0000: minute1=7'b1111110;
4'b0001: minute1=7'b0110000;
4'b0010: minute1=7'b1101101;
4'b0011: minute1=7'b1111001;
4'b0100: minute1=7'b0110011;
4'b0101: minute1=7'b1011011;
4'b0110: minute1=7'b1011111;
4'b0111: minute1=7'b1110000;
4'b1000: minute1=7'b1111111;
4'b1001: minute1=7'b1111011;
default: minute1=7'b0;
endcase
end
always@(min)
begin
case(min[7:4])
4'b0000: minute2=7'b1111110;
4'b0001: minute2=7'b0110000;
4'b0010: minute2=7'b1101101;
4'b0011: minute2=7'b1111001;
4'b0100: minute2=7'b0110011;
4'b0101: minute2=7'b1011011;
4'b0110: minute2=7'b1011111;
4'b0111: minute2=7'b1110000;
4'b1000: minute2=7'b1111111;
4'b1001: minute2=7'b1111011;
default: minute2=7'b0;
endcase
end
always@(hr)
begin
case(hr[3:0])
4'b0000: hour1=7'b1111110;
4'b0001: hour1=7'b0110000;
4'b0010: hour1=7'b1101101;
4'b0011: hour1=7'b1111001;
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DSD lab Manuals LAB12
4'b0100: hour1=7'b0110011;
4'b0101: hour1=7'b1011011;
4'b0110: hour1=7'b1011111;
4'b0111: hour1=7'b1110000;
4'b1000: hour1=7'b1111111;
4'b1001: hour1=7'b1111011;
default: hour1=7'b1111110;
endcase
end
always@(hr)
begin
case(hr[7:4])
4'b0000: hour2=7'b1111110;
4'b0001: hour2=7'b0110000;
4'b0010: hour2=7'b1101101;
default: hour2=7'b1111110;
endcase
end
end module

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DSD lab Manuals LAB12

PROCEDURE:

Software part:

1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC.
2. Write the Verilog code, check syntax, view RTL schematic and note the device
utilization summary by double clicking on the synthesis in the process window.
3. Open a new UCF file and lock the pins of the design with FPGA I/O pins.
4. Implement the design by double clicking on the implementation tool selection.
5. Create programming file (i.e., bit file) for downloading into the device.

Hardware part:

- Connect the power supply cable to the FPGA kit using power supply adapter.
- Connect the FPGA kit to the parallel port of the PC through the cable
provided along with the kit.
- Run the program on the fpga board.

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DSD lab Manuals LAB12
RTL Schematic:

RESULT:

Thus the real time clock was designed using verilog code and its working was
demonstrated in FPGA board.

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DSD lab Manuals LAB12

DESIGN AND TESTING ONBOARD SWITCHES AND LED’S IN FPGA.

OBJECTIVES

To simulate and test onboard switches and LED’s using Verilog code and to
implementthe same in FPGA.

INTRODUCTION

XC3S200 is an array of Configurable Logic Blocks (CLB’s) and is embedded within a

set of horizontal and vertical channels that contain Routing that can be personalized
to interconnect CLB’s. The configuration of interconnect is achieved by turning ON
‘n’ channel pass transistors. The state that determines a given interconnect pattern
is held in the Static RAM cells distributed across the chip close to the controlled
elements. The CLB’s and routing channels are surrounded by a set of
programmable Inputs / Outputs.

Verilog Code:

module buffer(a, y);

input [7:0] a;
output [7:0] y;
reg [7:0]y;
always@(a)
begin
y=a;
end
endmodule

UCF file(User constraint file):

NET "a[0]" LOC = "p83" ;

NET "a[1]" LOC = "p80" ;
NET "a[2]" LOC = "p82" ;
NET "a[3]" LOC = "p78" ;
NET "a[4]" LOC = "p79" ;
NET "a[5]" LOC = "p77" ;
NET "a[6]" LOC = "p76" ;

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DSD lab Manuals LAB12
NET "a[7]" LOC = "p74" ;
NET "y[0]" LOC = "p96" ;
NET "y[1]" LOC = "p92" ;
NET "y[2]" LOC = "p90" ;
NET "y[3]" LOC = "p89" ;
NET "y[4]" LOC = "p87" ;
NET "y[5]" LOC = "p86" ;
NET "y[6]" LOC = "p85" ;
NET "y[7]" LOC = "p84" ;

PROCEDURE:

Software part:

6. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC.
7. Write the Verilog code, check syntax, view RTL schematic and note the device
utilization summary by double clicking on the synthesis in the process window.
8. Open a new UCF file and lock the pins of the design with FPGA I/O pins.
9. Implement the design by double clicking on the implementation tool selection.
10. Create programming file (i.e., bit file) for downloading into the device.

Hardware part:

- Connect the power supply cable to the FPGA kit using power supply adapter.
- Connect the FPGA kit to the parallel port of the PC through the cable
provided along with the kit.
- Run the program on the fpga board.

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DSD lab Manuals LAB12

RTL Schematic:

RESULT:

Thus the onboard switches and LEDs were designed using Verilog HDL and it was
simulated and tested in the FPGA device.

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Observations/Comments/Explanation of Results