DSD lab Manuals Lab11

DESIGN AND IMPLEMENTATION OF LEAP YEAR CALCULATOR ON FPGA.

OBJECTIVES

Designing and implementation of leap year calculator in Verilog on FPGA using

seven segments and push buttons/ PS2 keyboard.

INTRODUCTION

February 29 is a date that usually occurs every four years, and is called leap day.
This day is added to the calendar in leap years as a corrective measure, because
the earth does not orbit around the sun in precisely 365 days.

How to determine whether a year is a leap year:

To determine whether a year is a leap year, follow these steps:

1. If the year is evenly divisible by 4, go to step 2. Otherwise, go to step 5.

2. If the year is evenly divisible by 100, go to step 3. Otherwise, go to step 4.
3. If the year is evenly divisible by 400, go to step 4. Otherwise, go to step 5.
4. The year is a leap year (it has 366 days).
5. The year is not a leap year (it has 365 days).

Algorithm:

if year modulo 4 is 0
then
if year modulo 100 is 0
then
if year modulo 400 is 0
then
is_leap_year
else
not_leap_year
elseis_leap_year
elsenot_leap_year

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Block Diagram Implementation on FPGA Board:

Push Buttons FPGA Seven

or PS2 Verilog Schematic. Segment
keyboard. display

Combinational Logic design:

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Verilog:
- Construct a circuit that determines if the year is divisible by 4.
- Construct a circuit that determines if the year is divisible by 100.
- Construct a circuit that determines if the year is divisible by 400.
- Combine the results of the previous three steps to yield the leap year flag.

The code:

/*
Reference :
Contemporary logic design Randy H. Katz 2nd ed Chapter 5
*/

module leap(/*AUTOARG*/
// Outputs
leap_year_flag,
// Inputs
year
);
input [15:0] year; // years in 4 digit bcd
outputleap_year_flag;

wire div_by_100, div_by_400;

reg div_by4;

/* Divisible-by-4 circuit
Only need to look at low-order two digits of the year
all years ending in 00, 04, 08, 12, 16, 20, etc. are divisible by 4

if tens digit is even, then divisible by 4 if ones digit is 0, 4, or 8

if tens digit is odd, then divisible by 4 if the ones digit is 2 or 6.
Translates into the following Boolean expression
*/
always @(/*AS*/year)
if (year[4]) begin //tens digit is odd
div_by4 = (year[3:0] == 4'h2) | (year[3:0] == 4'h6);
end else begin
div_by4 = (year[3:0] == 4'h0) | (year[3:0] == 4'h4) | (year[3:0] == 4'h8);
end

/*
Divisible-by-100 just requires checking that all bits of two low-order digits are
all 0:
*/
assign div_by_100 = (year[7:4] == 4'h0) & (year[3:0] == 4'h0);

/*
Divisible-by-400 combines the divisible-by-4
(applied to the thousands and hundreds digits)
and divisible-by-100 circuits
*/
assign div_by_400 = div_by_100 & div_by4;

assignleap_year_flag = div_by4 & (~div_by_100) | div_by_400;

endmodule // leap

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DSD lab Manuals Lab11

PS/2 Port
The 6-pin mini-DIN connector can accommodate a PS/2 mouse or keyboard. Most PS/2
devices can operate from a 3.3V supply, but older devices may require a 5VDC supply. A
three-pin jumper on the Nexys2 board immediately adjacent to the PS/2 connector selects
whether regulated 3.3V or the main input power bus voltage (VU) is supplied to the PS/2
connector. To send 5V to the PS/2 connector, set the PS2 power jumper to Vswt (the main
input power bus), and ensure the board is powered from USB or a 5VDC wall-plug supply.
To send 3.3V to the connector, set the jumper to 3.3V.

Keyboard
The keyboard uses open-collector drivers so the keyboard or an attached host device can
drive the two-wire bus (if the host device will not send data to the keyboard, then the host
can use input-only ports).
PS2-style keyboards use scan codes to communicate key press data. Each key is assigned a
code that is sent whenever the key is pressed; if the key is held down, the scan code will be
sent repeatedly about once every 100ms. When a key is released, a “F0” key-up code is
sent, followed by the scan code of the released key. If a key can be “shifted” to produce a
new character (like a capital letter), then a shift character is sent in addition to the scan
code, and the host must determine which ASCII character to use. Some keys, called
extended keys, send an “E0” ahead of the scan code (and they may send more than one
scan code). When an extended key is released, an “E0 F0” key-up code is sent, followed by
the scan code. Scan codes for most keys are shown in the figure. A host device can also

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send data to the keyboard. Below is a short list of some common commands a host might
send.
ED Set Num Lock, Caps Lock, and Scroll Lock LEDs. Keyboard returns “FA” after receiving
“ED”, then host sends a byte to set LED status: Bit 0 sets Scroll Lock; bit 1 sets Num Lock;
and Bit 2 sets Caps lock. Bits 3 to 7 are ignored.
EE Echo (test). Keyboard returns “EE” after receiving “EE”.
F3 Set scan code repeat rate. Keyboard returns “F3” on receiving “FA”, then host sends
second byte to set the repeat rate.
FE Resend. “FE” directs keyboard to re-send most recent scan code.
FF Reset. Resets the keyboard.
The keyboard can send data to the host only when both the data and clock lines are high (or
idle). Since the host is the “bus master”, the keyboard must check to see whether the host
is sending data before driving the bus. To facilitate this, the clock line is used as a “clear to
send” signal. If the host pulls the clock line low, the keyboard must not send any data until
the clock is released. The keyboard sends data to the host in 11-bit words that contain a ‘0’
start bit, followed by 8-bits of scan code (LSB first), followed by an odd parity bit and
terminated with a ‘1’ stop bit. The keyboard generates 11 clock transitions (at around 20 -
30KHz) when the data is sent, and data is valid on the falling edge of the clock.

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Implementation
When the host is only reading (and does not send data), the basic function to accomplish is
to sample the Data line just after each Clock line’s falling edge. This determines a word
made of 11 bits, including in this order a Start bit (=0), the 8-bits code (appearing LSB
first), an Odd parity bit, and a Stop bit (=1).

Communication: General Description

The PS/2 mouse and keyboard implement a bidirectional synchronous serial protocol. The
bus is "idle" when both lines are high (open-collector). This is the only state where the
keyboard/mouse is allowed begin transmitting data. The host has ultimate control over the
bus and may inhibit communication at any time by pulling the Clock line low.

The device always generates the clock signal. If the host wants to send data, it must first
inhibit communication from the device by pulling Clock low. The host then pulls Data low
and releases Clock. This is the "Request-to-Send" state and signals the device to start
generating clock pulses.

Summary: Bus States

Data = high, Clock = high: Idle state.
Data = high, Clock = low: Communication Inhibited.
Data = low, Clock = high: Host Request-to-Send

All data is transmitted one byte at a time and each byte is sent in a frame consisting of 11-
12 bits. These bits are:

• 1 start bit. This is always 0.

• 8 data bits, least significant bit first.
• 1 parity bit (odd parity).
• 1 stop bit. This is always 1.
• 1 acknowledge bit (host-to-device communication only)

The parity bit is set if there is an even number of 1's in the data bits and reset (0) if there is
an odd number of 1's in the data bits. The number of 1's in the data bits plus the parity bit
always add up to an odd number (odd parity.) This is used for error detection. The

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keyboard/mouse must check this bit and if incorrect it should respond as if it had received
an invalid command.

Data sent from the device to the host is read on the falling edge of the clock signal; data
sent from the host to the device is read on the rising edge. The clock frequency must be in
the range 10 - 16.7 kHz. This means clock must be high for 30 - 50 microseconds and low
for 30 - 50 microseconds.

Communication: Device-to-Host

The Data and Clock lines are both open collector. A resistor is connected between each line
and +5V, so the idle state of the bus is high. When the keyboard or mouse wants to send
information, it first checks the Clock line to make sure it's at a high logic level. If it's not,
the host is inhibiting communication and the device must buffer any to-be-sent data until
the host releases Clock. The Clock line must be continuously high for at least 50
microseconds before the device can begin to transmit its data.As I mentioned in the
previous section, the keyboard and mouse use a serial protocol with 11-bit frames. These
bits are:

• 1 start bit. This is always 0.

• 8 data bits, least significant bit first.
• 1 parity bit (odd parity).
• 1 stop bit. This is always 1.

The keyboard/mouse writes a bit on the Data line when Clock is high, and it is read by the
host when Clock is low. Following figures illustrate this.

Figure: Device-to-host communication. The Data line changes state when Clock is high and
that data is valid when Clock is low.

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Figure: Scan code for the "Q" key (15h) being sent from a keyboard to the computer.
Channel A is the Clock signal; channel B is the Data signal.

---The clock frequency is 10-16.7 kHz. The time from the rising edge of a clock pulse to a
Data transition must be at least 5 microseconds. The time from a data transition to the
falling edge of a clock pulse must be at least 5 microseconds and no greater than 25
microseconds.

The host may inhibit communication at any time by pulling the Clock line low for at least
100 microseconds. If a transmission is inhibited before the 11th clock pulse, the device
must abort the current transmission and prepare to retransmit the current "chunk" of data
when host releases Clock. A "chunk" of data could be a make code, break code, device ID,
mouse movement packet, etc. For example, if a keyboard is interrupted while sending the
secondbyte of a two-byte break code, it will need to retransmit both bytes of that break
code, not just the one that was interrupted.

If the host pulls clock low before the first high-to-low clock transition, or after the falling
edge of the last clock pulse, the keyboard/mouse does not need to retransmit any data.
However, if new data is created that needs to be transmitted, it will have to be buffered
until the host releases Clock. Keyboards have a 16-byte buffer for this purpose. If more
than 16 bytes worth of keystrokes occur, further keystrokes will be ignored until there's
room in the buffer.

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Observations/Comments/Explanation of Results