Digital System Design Lab 9

IMPLEMENTATION OF ARITHMETIC LOGIC UNIT

OBJECTIVES

• To write Verilog module for ALU at behavioral level

INTRODUCTION

The arithmetic logic unit (ALU) carries out the logic operations (such as comparisons) and
arithmetic operations (such as add or subtract) required during the program execution.
Generally

an ALU has two data inputs and one data output. Operations performed in the ALU often
affect bits in the status register (bits are set to indicate actions such as whether an overflow
has occurred). The ALU knows which operations to perform because it is controlled by
signals from the control unit.

ALU IN VERILOG HDL

Table below shows pin description for ALU

Signal I/O Number of Bits

op_a; Input 4

op_b; Input 4

Func Input 2

alu_out Output 4

module alu_simp(op_a, op_b, func, alu_out);

input [3:0] op_a;

input [3:0] op_b;

input [1:0] func;

output reg [3:0] alu_out;

Page | 72
Digital System Design Lab 9

always @ (op_a or op_b or func)

begin

case(func)

2'd0: alu_out = op_a + op_b;

2'd1: alu_out = op_a - op_b;

2'd2: alu_out = op_a & op_b;

2'd3: alu_out = op_a | op_b;

endcase

end

endmodule

Page | 73
Digital System Design Lab 9
Task1
Create a project in Xilinx ISE .Add this file to the project .Now simulate this file using ISE
Simulator. Next synthesize this file using XST.

Now Answer following Questions

What is the purpose of func line in above verilog module?

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

Draw results from Test bench for ALU? Indicate Input & Output signals?

Figure 1Test Bench waveform for ALU

Page | 74
Digital System Design Lab 9

Task2

Table below shows pin description for complex ALU

Signal I/O Number of Bits

op_a; Input 4

op_b; Input 4

Func Input 3

alu_out Output 4

Objective of this task is to write a Verilog module for a complex ALU which can add,
subtract, compare and shift and rotate operands.

Before writing module for complex ALU first answer following questions

Write statements in Verilog HDL that can compare two operands each of 4 bits?

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

How you can shift and rotate data at behavioral level?

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

Page | 75
Digital System Design Lab 9

Read verilog module for complex ALU called alu_cmplx .Explain its operation
without using Xilinx ISE?

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

Without using synthesizer tool draw hardware diagram for complex ALU from
module given below?

Complex ALU in Verilog HDL

Page | 76
Digital System Design Lab 9
module alu_cmplx(op_a, op_b, func, alu_out);

input [3:0] op_a;

input [3:0] op_b;

input [2:0] func;

output reg [3:0] alu_out;

always @ (op_a or op_b or func)

begin

casex({func, op_b})

//Logic operations:

//And, Or, Xor, Not

7'b000_xxxx: alu_out = op_a & op_b;

7'b001_xxxx: alu_out = op_a | op_b;

7'b010_xxxx: alu_out = op_a ^ op_b;

7'b011_xxxx: alu_out = ~op_a;

//Aritmetic operations:

//Addition, Subtration, Comparison, Shifting&Rotation

7'b100_xxxx: alu_out = op_a + op_b;

7'b101_xxxx: alu_out = op_a - op_b;

//Comparator

//alu_out[3] = 0, alu_out[2] = G;

//alu_out[1] = E, alu_out[0] = L;

7'b110_xxxx: begin

if (op_a > op_b)

alu_out = 4'b0100;

if (op_a == op_b)

alu_out = 4'b0010;

if (op_a < op_b)

Page | 77
Digital System Design Lab 9
alu_out = 4'b0001;

end

//Shifter Rotator

//cases for shift left

7'b111_0000: alu_out = op_a;

7'b111_0001: alu_out = {op_a[2:0], 1'b0 };

7'b111_0010: alu_out = {op_a[1:0], 2'b00 };

7'b111_0011: alu_out = {op_a[0] , 3'b000};

//cases for shift right

7'b111_0100: alu_out = op_a;

7'b111_0101: alu_out = {1'b0 , op_a[3:1]};

7'b111_0110: alu_out = {2'b00 , op_a[3:2]};

7'b111_0111: alu_out = {3'b000, op_a[3] };

//cases for rotate left

7'b111_1000: alu_out = op_a;

7'b111_1001: alu_out = {op_a[2:0], op_a[3] };

7'b111_1010: alu_out = {op_a[1:0], op_a[3:2]};

7'b111_1011: alu_out = {op_a[0] , op_a[3:1]};

//cases for rotate right

7'b111_1100: alu_out = op_a;

7'b111_1101: alu_out = {op_a[0] , op_a[3:1]};

7'b111_1110: alu_out = {op_a[1:0], op_a[3:2]};

7'b111_1111: alu_out = {op_a[2:0], op_a[3] };

endcase

end

endmodule

Page | 78
Digital System Design Lab 9

Draw results from Test bench for ALU? Indicate Input & Output signals? Verify
that each function of ALU is being performed.

Figure 2 Test Bench waveform for complex ALU

Page | 79
Observations/Comments/Explanation of Results