Digital System Design Lab 8

IMPLEMENTATION OF SEQUENTIAL CIRCUITS

OBJECTIVES

• To write Verilog module for Logic Shifters.

Counters & Shift-Left Registers

Counters and shift registers are two important classes of sequential circuits. In the simplest
terms, a counter is a circuit that counts pulses. As such, it is used in many circuit
applications, such as event counting and sequencing, timing, frequency division, and
control. A basic counter can be enhanced to incorporate functions such as synchronous or
asynchronous parallel loading, synchronous or asynchronous clear, count enable, directional
control, and output decoding.

Task
Create a project in Xilinx ISE .Add this file to the project .Add all of the modules given below
to this project. For each of the module create a test bench .Now simulate this file using ISE
Simulator. Next synthesize this file using XST. Then answer Questions given at the end of
module

8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and Serial Out
The following is the Verilog module for an 8-bit shift-left register with a positive-edge clock,
serial in, and serial out.

module shift (C, SI, SO);

input C,SI;

output SO;

reg [7:0] tmp;

always @(posedge C)

begin

tmp = tmp << 1;

tmp[0] = SI;

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Digital System Design Lab 8
end

assign SO = tmp[7];

endmodule

Draw results from Test bench for above module?

Figure 1Test Bench Results for 8-bit shift-left register with a positive-edge clock, serial in,
and serial out.

8-bit Shift-Left Register with Negative-Edge Clock, Clock Enable, Serial In, and
Serial Out
The following is the Verilog module for an 8-bit shift-left register with a negative-edge clock,
a clock enable, a serial in, and a serial out.

module shift (C, CE, SI, SO);

input C, SI, CE;

output SO;

reg [7:0] tmp;

always @(negedge C)

begin

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Digital System Design Lab 8
if (CE)

begin

tmp = tmp << 1;

tmp[0] = SI;

end

end

assign SO = tmp[7];

endmodule

Draw results from Test bench for above module?

Figure 2Test Bench Results for 8-bit shift-left register with a negative-edge clock, a clock
enable, a serial in, and a serial out

8-bit Shift-Left Register with Positive-Edge Clock, synchronous Clear, Serial In,
and Serial Out
The following is the Verilog module for an 8-bit shift-left register with a positive-edge
clock,asynchronous clear, serial in, and serial out.

module shift (C, CLR, SI, SO);

input C, SI, CLR;

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Digital System Design Lab 8
output SO;

reg [7:0] tmp;

always @(posedge C or posedge CLR)

begin

if (CLR)

tmp = 8’b00000000;

else

begin

tmp = {tmp[6:0], SI};

end

end

assign SO = tmp[7];

endmodule

Draw results from Test bench for above module?

Figure 3 Test Bench Results for for an 8-bit shift-left register with a positive-edge
clock,asynchronous clear, serial in, and serial out

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Digital System Design Lab 8

8-bit Shift-Left Register with Positive-Edge Clock, Synchronous Set, Serial In, and
Serial Out
The following is the Verilog module for an 8-bit shift-left register with a positive-edge clock,
a synchronous set, a serial in, and a serial out.

module shift (C, S, SI, SO);

input C, SI, S;

output SO;

reg [7:0] tmp;

always @(posedge C)

begin

if (S)

tmp = 8’b11111111;

else

begin

tmp = {tmp[6:0], SI};

end

end

assign SO = tmp[7];

endmodule

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Digital System Design Lab 8
Draw results from Test bench for above module?

Figure 4Test Bench Results for an 8-bit shift-left register with a positive-edge clock, a
synchronous set, a serial in, and a serial out

Task:
Write a verilog module for an 8-bit shift-right register with a negative -edge clock,
asynchronous set, a serial in, and a serial out.

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Digital System Design Lab 8
ACCUMULATORS

An accumulator differs from a counter in the nature of the operands of the add and subtract
operation: In a counter, the destination and first operand is a signal or variable and the
other operand is a constant equal to 1: A <= A + 1.

In an accumulator, the destination and first operand is a signal or variable, and the second
operand is either:

• a signal or variable: A <= A + B.

4-bit Up Accumulator
The following is the Verilog module for an Accumulator.

module accum (C, CLR, D, Q);

input C, CLR;

input [3:0] D;

output [3:0] Q;

reg [3:0] tmp;

always @(posedge C or posedge CLR)

begin

if (CLR)

tmp = 4’b0000;

else

tmp = tmp + D;

end

assign Q = tmp;

endmodule

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Digital System Design Lab 8
How you are accumulating data in above module in above verilog module?

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Task

Create a project in Xilinx ISE .Add this file to the project .Now simulate this file using ISE
Simulator. Next synthesize this file using XST

Draw results from Test bench for Accumulator ? Test your module for different
values .What is the maximum value that can be accumulated?

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Digital System Design Lab 8
Draw results from Test bench for above module?

Figure 5Test Bench Results for an accumulator

Counter
4-bit Unsigned Up/Down counter with Asynchronous Clear
module counter (C, CLR, UP_DOWN, Q);

input C, CLR, UP_DOWN;

output [3:0] Q;

reg [3:0] tmp;

always @(posedge C or posedge CLR)

begin

if (CLR)

tmp = 4’b0000;

else

if (UP_DOWN)

tmp = tmp + 1’b1;

else

tmp = tmp - 1’b1;

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Digital System Design Lab 8
end

assign Q = tmp;

endmodule

Explain working of module given above?

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Task

Create a project in Xilinx ISE .Add this file to the project. For this module create a test
bench .Now simulate this file using ISE Simulator. Next synthesize this file using XST. Then
answer Questions given at the end of module

Draw results from Test bench for above module?

Figure 6Test Bench Results for 4-bit Unsigned Up/Down counter with Asynchronous Clear

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Digital System Design Lab 8

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Observations/Comments/Explanation of Results