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Digital System Design: Implementation of Sequential Circuits

This lab document describes implementing sequential circuits and memory devices in Verilog. It includes modules for a single-port RAM with enable, a dual-port RAM with asynchronous read, a dual-port RAM with synchronous read, and a ROM. For each module, students are asked to write a test bench and simulate the design using a simulator to observe the results.

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65 views8 pages

Digital System Design: Implementation of Sequential Circuits

This lab document describes implementing sequential circuits and memory devices in Verilog. It includes modules for a single-port RAM with enable, a dual-port RAM with asynchronous read, a dual-port RAM with synchronous read, and a ROM. For each module, students are asked to write a test bench and simulate the design using a simulator to observe the results.

Uploaded by

AL RIZWAN
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Digital System Design LAB 7

IMPLEMENTATION OF SEQUENTIAL CIRCUITS

OBJECTIVES

• To write Verilog module for Sequential digital circuits at behavioral level


• To write Verilog module for RAM.
• To write Verilog module for ROM.

INTRODUCTION

This lab will introduce a new category of digital circuitry: the sequential circuit. The output
of a sequential circuit is a function both of the present input conditions and the previous
conditions of the inputs and/or outputs. The output depends on the sequence in which the
inputs are applied. These are similar devices, each being used to store a single bit of
information indefinitely. The difference between a latch and a flipflop is the condition under
which the stored bit is allowed to change.

RAM/ROM

Task
Create a project in Xilinx ISE .Add this file to the project .Add all of the modules given below
to this project. For each of the module create a test bench .Now simulate this file using ISE
Simulator. Next synthesize this file using XST. Then answer Questions given at the end of
module.

Single-Port RAM with Enable


Module raminfr (clk, en, we, a, di, do);

Input clk;

Input en;

Input we;

Input [4:0] a;

Input [3:0] di;

output [3:0] do;

reg [3:0] ram [31:0];

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Digital System Design LAB 7
reg [4:0] read_a;

always @(posedge clk) begin

if (en)

begin

if (we)

ram[a] <= di;

read_a <= a;

end

end

assign do = ram[read_a];

endmodule

Draw results from Test bench for above module?

Figure 1Test Bench Results for single port RAM with Enable.

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Digital System Design LAB 7

Dual-Port RAM with Asynchronous Read


Following is the Verilog code for a dual-port RAM with asynchronous read.

module raminfr (clk, we, a, dpra, di, spo, dpo);

input clk;

input we;

input [4:0] a;

input [4:0] dpra;

input [3:0] di;

output [3:0] spo;

output [3:0] dpo;

reg [3:0] ram [31:0];

always @(posedge clk) begin

if (we)

ram[a] <= di;

end

assign spo = ram[a];

assign dpo = ram[dpra];

endmodule

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Digital System Design LAB 7
Draw results from Test bench for above module?

Figure 2Test Bench Results for dual-port RAM with asynchronous read..

Dual-Port RAM with Synchronous Read


module raminfr (clk, we, a, dpra, di, spo, dpo);

input clk;

input we;

input [4:0] a;

input [4:0] dpra;

input [3:0] di;

output [3:0] spo;

output [3:0] dpo;

reg [3:0] ram [31:0];

reg [4:0] read_a;

reg [4:0] read_dpra;

always @(posedge clk) begin

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Digital System Design LAB 7
if (we)

ram[a] <= di;

read_a <= a;

read_dpra <= dpra;

end

assign spo = ram[read_a];

assign dpo = ram[read_dpra];

endmodule

Draw results from Test bench for above module?

Figure 3Test Bench Results for dual port RAM with synchronous read.

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Digital System Design LAB 7
ROM
module rominfr (clk, en, addr, data);

input clk;

input en;

input [4:0] addr;

output [3:0] data;

always @(posedge clk) begin

if (en)

case(addr)

4’b0000: data = 4’b0010;

4’b0001: data = 4’b0010;

4’b0010: data = 4’b1110;

4’b0011: data = 4’b0010;

4’b0100: data = 4’b0100;

4’b0101: data = 4’b1010;

4’b0110: data = 4’b1100;

4’b0111: data = 4’b0000;

4’b1000: data = 4’b1010;

4’b1001: data = 4’b0010;

4’b1010: data = 4’b1110;

4’b1011: data = 4’b0010;

4’b1100: data = 4’b0100;

4’b1101: data = 4’b1010;

4’b1110: data = 4’b1100;

4’b1111: data = 4’b0000;

default: data = 4’bXXXX;

endcase

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Digital System Design LAB 7
end

endmodule

Draw results from Test bench for above module?

Figure 4Test Bench Results for ROM.

Page | 41
Observations/Comments/Explanation of Results

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