Digital System Design LAB 1

INTRODUCTION TO BASIC SYNTAX OF VERILOG AND GATE-LEVEL-MODELING

USING XILINX ISE TOOLS

OBJECTIVES

• Identifying the components of a Verilog module definition

• Understanding how to define the port list for a module and declare it in
Verilog Familiarization with the logic gate primitives provided in Verilog
• Understanding instantiation of gates and construction of a Verilog
description from the logic diagram of the circuit
• Hierarchical Design in Verilog

REFERENCE

Chapter 4 and Chapter 5

BOOK : Verilog HDL by Samir Palnitkar

Chapter 4

BOOK : Advanced Digital Design with the Verilog HDL

PROCEDURE

1. Launch the Xilinx ISE 7.1 software as follows:

Start >> Programs >> Xilinx ISE 7.1 >> Project Navigator

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2. Start a new project as follows:

File >> New Project

3. Give the project name as : Half_Adder

Select the project location as follows:
C:\COMParch\2004_E_XXX
Select the top level module type as : HDL

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4. Click Next.

5. In the next window of ‘Select Device and Design Flow for the Project’:
Select the simulator as : ISE simulator and don’t worry about the rest of the options for the time
being. We shall look at them in greater detail afterwards.

6. Click Next.

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7. In the next window of ‘Create a new source’:

Simply click Next. We shall not use this option for the time being.

8. In the next window of ‘Add Existing Sources’:

Simply click Next. We shall not use this option for the time being.

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9. In the next window, click Finish.

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10. Select Project >> New Source

11. In the ‘New Source’ window:

Select ‘Verilog module’ out of different options available in the
left hand column. Give the file name as: half_adder

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12. In the next window of ‘Define Verilog Source’:

Simply click Next. We shall not use this option for the time being.

13. In the next window, click Finish.

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14. You will see something like this:-

15. Enter the following Verilog Code in half_adder.v file and save the file:

module half_adder(sum , carry, in1, in2);

output sum;
output carry;
input in1;
input in2;

xor x1(sum, in1, in2);

and a1(carry, in1, in2);

endmodule

Follow carefully the instructor’s explanation of the basic syntax of a Verilog

module, port list and Verilog’s gate level statements.

In the ‘Processes Window’, located 2nd from the top on the left hand side, locate the
“Synthesize-XST” process and expand it by clicking on the small box containing + sign
alongside it. Now, in the options available inside the “Synthesize-XST” process, locate
the “Check Syntax” step and click on it.

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16. Make the Gate-level Diagram of the half and full adder. Show proper working and table.

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17. Make sure that your Verilog Code is free of any Syntax errors and the Check Syntax process does not
give any error.( of course we are talking about half-adder you just made. )

18. Moving on to simulating the Verilog module for half adder:

Select Project>> New Source

19. In the New Source Window, select the ‘Test Bench Waveform’ out of different options available in the
left hand column and give the file name as “half_adder_tb”.

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20. Click Next

21. In the next window, you have to associate this testbench waveform with a particular verilog module
of your design to which you want to apply this waveform and check the results. As we have only one
module, half_adder, in our design, select half_adder and then click Next.

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22. In the next ‘New Source Information’ window, simply click Finish.

23. You will see something like this:

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24. In the right hand side portion named ‘Clock Information’, select ‘Combinational (or Internal Clock)’
option.

25. Then, select OK.

26. The screen will take the form as shown below:

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27. In this Waveform window, you can see that outputs are indicated with yellow colour and inputs are
indicated with light green colour.

28. You can click the input signal waveform area to decide what waveform you want to apply to the inputs
of your module and then in the next step, you will be able to simulate and see the results of applying
that particular input in the form of output waveforms.

29. Click the save icon in order to save this TestBenchWaveform file named
half_adder_tb.tbw.

30. In the ‘Sources in the Project’ window on the top left hand side, select the Test Bench
Waveform file named ‘half_adder_tb’. Then, click on the ‘Process View’ tab, located at
the bottom of the 2nd window from the top on the left hand side.

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31.Clicking the ‘Process View’ for half_adder_tb file will result in the screen as shown
below:

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32. Expand the “Xilinx ISE Simulator” options in the Processes Window and double click on
the “Simulate Behavioral Model” option.

33. This will start the simulation process and you will end up with something like this:

34. Out of the four tabs available at the bottom of the main window, select the second from
the right hand side named half_adder_tb_isim. This will show you the results of
simulating the Verilog module half_adder.v by applying it the input waveform mentioned
in the file half_adder_tb.tbw.

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Name:_________________ Section :_________ Roll #:_______________

35. Exercise:
Write down the module statement and port list for the following Block diagram:
(You are not expected to write the whole programme just the first couple of statements)

36. Following the steps indicated as above simulate the full adder . ( I mean the so many
steps you just did , do them again and get used to them . They are your friends!!! )
Gate level code for the full adder module:

module full_adder(sum ,carry_out, in1, in2, carry_in);

output sum;

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output carry_out;
input in1;
input in2;
input carry_in;

wire c, d, e;

xor x1(c,in1,in2);
xor x2(sum, c, carry_in);
and a1(d, in1, in2);
and a2(e, c, carry_in);
or o1(carry_out, d, e);

end module

Note the difference of Verilog code for the full adder and the code of half adder
employed in the last couple of steps . Note the use of “wire c,d,e;” in order to handle
the intermediate connections between the gates.

37.Enter this code and then, simulate it using the steps described above

38.Following is the full adder diagram implemented as a combination of half adders:

39. The use of the smaller blocks to design a larger block is known as “Hierarchical Design”.
This sort of hierarchical design can be implemented in Verilog as well through the
concept of “Instantiating” a smaller module in some larger module .Following is the
Verilog Code for the full adder using this hierarchical approach, by “Instantiating” the
half_adder module.

module full_adder (sum ,carry_out, in1, in2, carry_in);

output sum;
output carry_out;
input in1;
input in2;

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input carry_in;

wire c, d, e;

half_adder h1(s1,c1,in1,in2);
half_adder h2( x2(sum, c2, s1, carry_in);
or o1(carry_out, c1, c2);

endmodule

40. Enter this code and then, simulate it using the steps described above.

41. Previously you had been asked to write the Verilog Code of a 4 bit Ripple Carry Adder
which consisted of 4 full adders that you had previously designed. Now, you will again
write the Verilog Code for this Ripple Carry Adder but this time the inputs and outputs
will be handled differently using the concept of “Vectors” in Verilog.

42. Following is the Diagram for that Ripple Carry Adder using this new approach.

43. Following is the Verilog code for the Ripple Carry Adder defining the inputs and outputs as
Vectors.

module full_adder_4(sum, carry_out, a, b, carry_in);

output [3:0] sum;

output carry_out;
input [3:0] a,b;
input carry_in;

wire c1, c2, c3;

full_adder fa0(sum[0], c1, a[0], b[0], carry_in);

full_adder fa1(sum[1], c2, a[1], b[1], c1);
full_adder fa2(sum[2], c3, a[2], b[2], c2);
full_adder fa3(sum[3], carry_out, a[3], b[3], c3);

endmodule

As it had been mentioned in the first lab that in Verilog we have different levels of
abstraction available to us like:

a. Gate level
b. Dataflow level
c. Behavioral level

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In the first few labs, we have looked at the Gate level coding. Now, we shall take a look at
the Dataflow level Coding:
In the manual techniques of designing any digital logic circuit, we start from the truth
table, generate a separate Boolean Equation for each output column of the truth table,
then these Boolean equations are simplified using different techniques and finally, these
simplified Boolean equations are translated into gate level diagram.
In Gate level coding, we basically translate the gate level diagram of a circuit into
statements. While in Dataflow level coding, we can directly translate the Boolean
equations of a circuit into statements. So, you can easily see that Dataflow level coding
is at a higher level of abstraction as compared to Gate level coding. While describing
Boolean equations in the form of Dataflow statements, we use logical operators like
negation (~), and (&), or(|), xor(^), xnor(^~),etc. Besides describing Boolean
equations at Dataflow level, we can even move on to a higher level of abstraction and
use other type of operators as well like arithmetic operators(+,-) etc.

Write down the Boolean equations for half adder.

44. Use the following dataflow level code.

module half_adder(sum , carry, X, Y);

output sum;
output carry;
input X;
input Y;
assign sum = X ^ Y;
assign carry = X & Y;
end module

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45. See the results of Designed module using ISE Simulator.

46. Write down the Boolean Equations for full adder:

47. Use the following dataflow level code.

module full_adder(sum , carry, X, Y, Z);

output sum;
output carry;
input X,Y,Z;

assign sum = X ^ Y ^ Z;
assign carry = (X & Y) | (Z & (X ^ Y));

endmodule

48. See the results of designed module using ISE Simulator.

Name:_________________ Section :_________ Roll #:_______________

49. Write the code for a 4 bit adder using data flow modelling.

50. See the results of designed module using ISE Simulator.

51. This was the start and end of Gate Level Modelling.

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Observations/Comments/Explanation of Results