IPSJ Transactions on System LSI Design Methodology Vol.10 45–62 (Aug.

2017)
[DOI: 10.2197/ipsjtsldm.10.45]

Invited Paper

Large-Scale 3D Chips: Challenges and Solutions for

Design Automation, Testing, and Trustworthy Integration

Johann Knechtel1,a) Ozgur Sinanoglu1,b) Ibrahim (Abe) M. Elfadel2,c) Jens Lienig3,d)

Cliff C. N. Sze4,e)
Received: March 1, 2017

Abstract: Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia
for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on
performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective
and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed
the mainstream transition from “classical 2D chips” to such large-scale 3D chips. In this paper, we survey all popular
3D integration options available and advocate that using an interposer as system-level integration backbone would
be the most practical for large-scale industrial applications and design reuse. We review major design (automation)
challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options.
Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current
design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer
stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in
general and the prospects for large-scale and trustworthy 3D chips in particular.

Keywords: 3D chips, large-scale integration, system-level integration, heterogeneous integration, design automation,
testing, hardware security, trustworthy integration

1. Introduction
3D chips—multiple vertically (and/or laterally) stacked and in-
terconnected layers of active components (and/or whole chips)—
are often claimed to meet current and future requirements for
electronic devices. By their stacked and densely integrated na-
ture, 3D chips offer shorter interconnects and, thus, reduced de-
lays and power, and increased performance [1], [2], [3]. At the
same time, both digital and heterogeneous components spread
across multiple chips/dies are relatively easy to integrate into one
common 3D stack. Note that such heterogeneous 3D chips, if tai-
lored for small footprints and low power consumption, are also
essential for widely-anticipated applications such as the Inter- Fig. 1 The well-known “More Moore” trend for down-scaling the nodes is
net of Things (IoT). Two prominent design paradigms, namely slowly but surely reaching its limits for CMOS technology. New
“More Moore” (shrinking device nodes and leveraging new ma- technologies and materials are being investigated, but most are not
mature yet for high-volume manufacturing. “More than Moore”,
terials) and “More-than-Moore” (heterogeneous integration), ad- which targets for heterogeneous integration, has been identified as
vocate both for 3D chips in particular [4] (Fig. 1). another important direction. The concept of 3D chips offers the po-
tential to meet both trends at the same time.
Despite the significant benefits projected over 2D chips in
general, and the recent high-volume emergence of 3D mem-
ory stacks (such as High-Bandwidth Memory, HBM [5], [6]) in particular, the overall adoption of 3D chips still lags behind
1 expectations—academic and industry leaders have been promot-
New York University Abu Dhabi, PO Box 129188, Abu Dhabi, UAE
2
Masdar Institute, Khalifa University of Science and Technology, PO Box ing 3D integration for more than one decade now [1], [2], [7], [8].
54224, Abu Dhabi, UAE Successful adoption of 3D chips requires addressing different
3
TU Dresden, 01062 Dresden, Germany
4
Google Inc., Austin, Texas 78705, USA
classical and novel challenges which simultaneously affect the
a)
[email protected] manufacturing processes, design practices and physical design
b)
[email protected] tools [3], [9], [10], [11], [12], [13]. If not properly addressed,
c)
[email protected]
d)
[email protected] these fairly complex challenges (such as adverse coupling ef-
e)
[email protected] fects [14], [15]) may render 3D chips commercially unviable.


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Fig. 2 Implementation options for 3D chips. Originating with traditional and package stacking using
mainly flip-chip and wire bonding, 3D integration has evolved towards interposer stacks (also
known as “2.5D integration”) as well as towards more encapsulated options: through silicon-via
(TSV)-based 3D ICs and monolithic 3D ICs. While the latter two options provide the highest inte-
gration densities and connectivity, the other options, especially modern interposer stacks, facilitate
large-scale, system-level integration and chip-level design reuse.

Physical design automation, among other stages such as testing, flip-chip and wire bonding) allow for reuse of legacy 2D chips,
partially meets these challenges already at present, but further ef- but only with limited integration and interconnectivity rates.
forts are needed to exploit the full potential of 3D chips and to In the following, key aspects of the 3D implementation op-
facilitate their wide-scale commercial breakthrough. tions are reviewed and design challenges are outlined. Further
In this paper, we elaborate on these challenges and review technical details have been reviewed, e.g., by imec’s Eric Beyne
promising solutions. A key observation is that most challenges in Ref. [23], here along with the related 2D and 3D interconnect
can be eased once system-level 3D integration (of 2D chips) is topologies.
pursued. The related concept of interposer-based 3D integra- Traditional and package stacking has been widely adopted in
tion is widely accepted nowadays [8], [16], [17], [18], [19], [20], the past; it is thus not reviewed in detail in our paper*1 .
[21], [22]; it is a practical, flexible, and cost-effective alterna- 1.1.1 TSV-based 3D ICs
tive to the previously more anticipated full-custom and native 3D This option has initially attracted the most attention and re-
integration. search and development efforts; many prototypes and products
Here we initially provide an overview on 3D integration in gen- nowadays are based on TSV technology [2], [5], [6], [18], [28],
eral and its design-automation challenges in particular (in the re- [29], [30], [31]. The key element, the through-silicon vias (TSVs)
mainder of this Section 1). In Sections 2 and 3, we then discuss are metal plugs (typically copper or tungsten) that penetrate
the respective challenges and solutions for design automation of whole stacked dies in order to interconnect those dies. Differ-
interposer in general and heterogeneous interposer in particular. ent options for stacking of the dies are applicable [23], [32]; for
In Section 4, we review the state-of-art for testing of 3D chips and example, face-to-back stacking is where the metal layers (the
we outline open challenges. In Section 5, we address hardware “face”) of one die are bonded to the substrate (the “back”) of
security, an important aspect for modern chip design, especially another die.
for advanced and complex devices such as 3D chips. Finally, we Depending on the TSV process (Fig. 3), different design chal-
summarize and conclude in Section 6. lenges arise: via-first TSVs and via-middle TSVs obstruct the
device layer and result in placement obstacles; via-last TSVs ob-
1.1 Implementation Options for 3D Chips struct the device layer and the metal layers, resulting in place-
3D chips can be classified into four categories (Fig. 2): (i) tra- ment and routing obstacles. Due to their relatively large diameter
ditional and package stacking, (ii) interposer stacks, (iii) through- and intrusive character, TSVs can neither be deployed excessively
silicon via (TSV)-based 3D ICs, and (iv) monolithic 3D ICs. Note nor arbitrarily; they have to be optimized in count and arrange-
that advanced 3D stacks may cross different categories, such as *1 Even though they are not strictly stacking-centric, there are modern pack-
when multiple TSV-based 3D ICs are integrated on an interposer. aging approaches still worth mentioning for large-scale integration. One
Each option has its scope of application, with distinctive bene- such approach is fan-out-wafer-level packaging (FOWLP) [12], and it is
currently widely applied, e.g., in Apple’s iPhone 7 [24], for its higher in-
fits and drawbacks, as well as requirements for design and man- tegration level and a greater number of external contacts than traditional
ufacturing processes. On the one end of the scale, monolithic 3D wafer-level packaging. Another approach is that of the embedded multi-
ICs enable the highest integration density (i.e., transistor-level die interconnect bridge (EMIB) [25], [26]. Here a small chip slice with
metal layers, called “bridge”, is embedded into the package substrate
3D integration), but this requires full-custom design and dedi- such that dies bonded above can be interconnected through it. Similarly
cated manufacturing steps, which both hinders system-level inte- as an interposer, an EMIB enables chip-level and high-bandwidth inter-
connectivity. An EMIB is less costly than an interposer, but it cannot
gration and design reuse. On the other end of the scale, interposer offer a system-level integration platform like an interposer. The Stratix
stacks as well as traditional and package stacking (originated with 10 FPGA [27] is a prominent high-end package using multiple EMIBs.


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tegration and large-scale design reuse as it is possible with the

other 3D options.
1.1.3 Interposer Stacks
Interposer stacks are a widely accepted, cost-efficient alterna-
tive to 3D ICs [8], [16], [17], [18], [19], [20], [21], [22]. Here, ac-
tive dies are arranged in lateral direction on a substrate—possibly
on both of its sides—instead of stacking them strictly vertically.
The interconnects are realized via TSVs and metal layers within
the interposer (see Fig. 2).
Interposer stacks enable a heterogeneous design where
chips/dies encompassing different technologies, e.g., “biochips,”
Fig. 3 The different TSV processes; illustration derived from Ref. [38]. Via-
first TSVs are fabricated before the active layers (front-end-of-line, sensors, MEMS, and memory units, can be relatively easily con-
FEOL). Via-middle TSVs are fabricated after the FEOL but be- nected in one package. As for homogeneous digital integration,
fore the metal layers (back-end-of-line, BEOL). Via-last TSVs are
interposer enable the partitioning of a large monolithic die (with
fabricated after (or during) the BEOL process. According to Eric
Beyne [23], via-middle TSVs are the most popular option for ad- low yield) into smaller dies (with higher yield) [19], [22]. This
vanced 3D ICs as well as for interposer stacks. greatly lowers the overall manufacturing cost and also helps to
improve the power efficiency. Further, interposer allow for better
ment [3], [13], [33], [34], [35], [36]. Note that TSVs do not scale heat dissipation [17], [50]. In short, interposer are considered as
at the same rate as transistors, thus the mismatch between TSV the platform for “new multi-chip modules (MCMs)” [51], [52],
and cell dimensions will remain for future nodes and may even with low cost, high yield, and the combination of heterogeneous
increase [37]. integrated circuits in one package cited as the major advantages.
Overall, TSV-based 3D ICs enable chip-level integration of There exists a wide variety of interposer-based systems which
both homogeneous and heterogeneous dies but still require dedi- can be categorized in different ways:
cated design and manufacturing steps. This limits their scope for • According to the core material: silicon (today), organic (cur-
large-scale and system-level design reuse. Besides, the integra- rently considered), or glass substrates (future) [16], [52],
tion density of TSV-based 3D ICs is lower than that of monolithic [53]
3D ICs (but higher than that of interposer stacks). • According to the interposer type: fully passive, with embed-
1.1.2 Monolithic 3D ICs ded components such as microfluidic channels [54], or with
This option has recently gained more attention [39], [40], [41], active components [8], [20], [21], [55]
mainly thanks to advances of the processing technology [42]. The • According to the mounting approach: one-sided or double-
key feature of monolithic 3D ICs is that active layers are sequen- sided die placement, distributed high-power or low-power
tially manufactured into one chip rather than bonded using sep- die allocation [8]
arate dies. Due to their small vias, comparable to regular metal- • According to the chip design: prefabricated dies stacked
stack vias, monolithic 3D ICs are the only option to enable fine- onto the interposer (such as the AMD Fiji/Fury GPU with
grained transistor-level integration. This is especially sought after stacked HBM chips [56], [57], [58]) or custom dies de-
for high-density and full-custom logic integration [39]. signed for specific applications (such as the Xilinx Virtex-7
As for design challenges, both signal and power routing be- FPGA [59])
come notably more complex due to high congestion [39], [43]. As of today, there are several products with interposer technol-
However, once the area gain inherent in monolithic 3D ICs is ogy available on market, notably the AMD Fiji/Fury GPU [56],
traded-off, routability can become even significantly better than it [57], [58] and the Xilinx Virtex-7 FPGA [59]. In 2016, CEA Leti
is in 2D chips [41]. Besides, thermal properties differ from “clas- demonstrated their second generation 3D-NoC technology [20],
sical” TSV-based 3D ICs: on the one hand, the regular vias are [21], which combines a series of small dies (“chiplets”) fabricated
by far not as effective as TSVs for conducting heat out of the at the FDSOI 28 nm node and co-integrated on a 65 nm CMOS
stack [44], [45]; on the other hand, monolithic chips do not ex- interposer. The active interposer embeds several lower-cost func-
hibit potential “thermal barriers” in the form of bonding layers*2 . tions, such as communication through the NoC and system I/Os,
Hence, the thermal coupling within monolithic stacks is larger power conversion, design-for-testability, and integrated passive
and more uniform than for TSV-based 3D ICs, which calls for components. These products are all good examples leading to
dedicated thermal management [45]. our belief that interposer stacks stand at the right spot in terms of
For placement, routing, and design closure of monolithic 3D the production-scale economy for 3D integration.
ICs, the reuse of commercial 2D physical design tools has The design of interposer stacks is still manual to some degree;
been demonstrated to lower the barrier for industry-wide accep- there is a lack of dedicated and advanced design tools [60]. Rout-
tance [40], [47], [48], [49]. Nevertheless, due to its sequential ing of active interposer and the related design of a large-scale
processing nature, such 3D ICs cannot apply “plug-and-play” in- network-on-chip (NoC), for example, requires further research
efforts [61]. Other challenges such as simulation and verification
*2 For example, the micro-bump bonding in TSV-based 3D ICs may be un-
derfilled with BCB polymer layers. This polymer has an approximately
of signal integrity across an interposer stack have been recently
600 times higher thermal resistivity than silicon [46]. addressed [62], but require further efforts regarding tool integra-


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For large-scale and system-level 3D integration—leveraging an

interposer as “plug-and-play” integration backbone—much of the
outlined design complexity and iteration processes may be kept
under control or even avoided in the first place. That is, individual
components/dies are designed and manufactured separately, and
only then integrated into a 3D chip. Nevertheless, there are still
design challenges (but also promising solutions) associated with
this style, as we elaborate in the next sections.

2. Interposer Stacks: On Solutions and Future

Prospects for Classical Design Automation
The physical design of interposer-based 3D-ICs is hampered
by a multitude of design challenges that are similar to the ones
encountered when designing other systems, such as system-on-a-
package (SOP) or MCMs. Besides complexity, these are mainly
issues of thermal, mechanical, and routability management. Test-
ing issues also need special consideration (see Section 4); how-
ever, due to better access to individual dies, testing of interposer
Fig. 4 Full workflow for custom design of 3D chips. Pathfinding and
physical-design prototyping link system-level design and layout- stacks is more manageable than it is for stacked 3D designs.
level design; this link eases the design closure for the complex and
highly iterative process. Modeling and simulation as well as chip- 2.1 Floorplanning and Placement
package co-design interact with most design stages. All stages re-
quire feedback loops to enable, among others, thermal management As mentioned before, (technology-heterogeneous) chips are
and stack-wide variation-aware design closure (not illustrated). often designed independently and then placed on a silicon inter-
poser. Hence, placement algorithms should arrange a small num-
tion [63]. Still, interposer stacks are the most promising option ber (usually 2–10) of mostly bare dies on the interposer with the
for large-scale and system-level 3D integration. shortest external connections between them, in a manner analo-
gous to classical floorplanning.
1.2 On High-Level Challenges for the Design of 3D Chips Today’s (academic) tools for die placement on interposer are
To select and explore the most suitable 3D integration option often based on randomized algorithms such as simulated anneal-
for any particular design is much more complex than handling ing, e.g., as proposed in Refs. [65], [66]. The authors of Ref. [67]
similar decisions for classical 2D chips. A team of 3D designers apply an enumerative search to identify optimal die positions be-
has to consider the following aspects, among others: fore using a pin assignment routine. This method, however, does
• How to reuse intellectual property (IP) blocks or pre- not scale beyond six dies. The authors of Ref. [68] claim to ef-
designed modules effectively in the 3D chip in order to meet fectively place the multiple FPGA dies of an interposer-based
time-to-market and cost constraints? system. Based on force-directed placement and the B*-tree rep-
• How are heterogeneous components designed and properly resentation, their approach allows to optimize the die positions
integrated along with digital modules? according to signal delay within the overall FPGA framework.
• How can the final 3D chip be secured and made trustworthy?
• Into how many dies/layers should the overall design be split 2.2 Data Structures and Solution Space
up, and how does the design perform after being spread across Design optimization is performed in the realm of the data struc-
multiple dies/layers? How can a classical 2D implementation ture’s solution space by applying some optimization algorithms.
be leveraged as baseline for the 3D implementation [64]? The algorithms require a solution space with minimum redun-
• What are the bandwidth, power, and signal integrity require- dancy, excluding invalid solutions and including the best solu-
ments for all the interconnects? What is an appropriate system- tions. In addition, an efficient implementation of a data structure
level interconnect fabric? must allow for a fast execution of various operations. Examples
• How to test components/dies individually and the overall are the exchange of components within and across multiple dies,
stack both partially and fully? the transformation from the abstract representation to the real 3D
It is important to note that most of these aspects are interacting; chip geometry, and the consideration of layout constraints.
consequently, any respective decision does impact the overall de- The above requirements are notably harder to achieve for the
sign process as well the final performance, reliability, and cost 3D solution space than it has been in the case for “classical” 2D
of the 3D chip. Solving such a complex set of intertwined chal- design automation [69], [70]. Still, efficient data structures ini-
lenges requires sophisticated design know-how, EDA capabilities tially developed for the physical design of 2D ICs (notably the
and well-defined project structures. Given the plethora of avail- Slicing Tree, the O-Tree or the Sequence Pair) have been suc-
able (2D) and upcoming (3D) tools, various design practices and cessfully extended towards 3D integration. These extensions and
design know-how, all distributed among multiple design parties, other 3D data structures are reviewed in detail in Ref. [70].
the introduction of a unified workflow is essential (Fig. 4).


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2.3 Routability and Routing

Assuming that the dies to be integrated on the interposer are
prefabricated, connecting (routing) them can be done with con-
ventional routing tools. Hence, published work on routing con-
centrates on various interposer-specific constraints which are of-
ten technology-related. For an active interposer, however, the de-
sign of a large-scale and possibly hierarchical network-on-chip
(NoC) requires further research efforts [61].
A global routing algorithm for SOPs is presented in Ref. [71];
it can also be applied to interposer systems for routing or routabil-
ity estimation purposes. The authors of Ref. [72] studied the im-
pact of IR-drop while routing the interposer and redistribution
layers (RDL) of each die, along with simultaneous planning of
micro-bumps and signal assignment. Their approach initially de-
termines the number of micro-bumps required for each die, as-
signs I/O buffers, and finally routes the RDLs and the interposer.
The minimization of the interposer’s metal layers was sought af-
ter by the authors of Ref. [73]. Their approach is based on a Fig. 5 Selected challenges for the design automation of interposer-based 3D
chips: (top) holistic and package-wide thermal simulation, which
routability estimation which then derives the minimum number
shall also be fast, efficient, and accurate; (left) efficient and opti-
of required metal layers. mal die placement while considering/solving pin assignment; (right)
chip-interposer co-design, exploring the technological and physical-
design space of various interposer configurations.
2.4 Pin and TSV Assignment
During the aforementioned placement procedure, dies may
change their relative positions and orientations which affect the 2.6 Outlook: Novel Challenges for Design Automation
individual and overall wirelength, due to non-optimal bump While interposer-based 3D chips are successfully designed and
and/or pin assignment. Therefore, placement algorithms often built using conventional but adapted design tools, there is still an
include techniques for pin assignment. For example, the authors urgent need for physical design methodologies that are tailored
of Ref. [67] use a network-flow algorithm to establish the con- for the specific needs of interposer systems. Some of these chal-
nections between I/O buffers and micro-bumps with the goal of lenges are outlined next (see also Fig. 5).
minimizing the external wirelength. The approach in Ref. [66] Multi-objective optimization during early design stages
applies an integer-linear program (ILP) formulation for the same Applying physical simulations or additional optimization goals
purpose. Bipartite matching is leveraged in Ref. [65]. during the early stages of physical design should enable the iden-
Alternatively, pin assignment can also be combined with the tification of the best-available solutions with state-of-the-art place
routing of dies. The authors of Ref. [72], for example, assign and route algorithms. Specifically, routability estimation and
the I/O buffers (to the pre-placed bumps) prior to routing of the thermo-mechanical simulations should be accounted for during
RDL and interposer layers. Their pin assignment is based on the the floorplanning and/or placement stages.
optimization of network flows while also honoring IR-drop con- Chip-interposer co-design
straints. The ultimate goal could be a simultaneous design of dies and
interposer, that is, the design of the entire system within one flow
2.5 Thermal Management (Fig. 4). This would enable the optimization of global key param-
When compared to solely stacked 3D chips, interposer-based eters like wirelength (external and internal), timing, routability
3D chips also offer more flexible means for thermal manage- and thermo-mechanical stability. However, such a system-level
ment. Excessive thermal energy can dissipate more efficiently optimization might conflict with the aforementioned advantages
from the dies to the interposer (i.e., using the multiple heat paths of relatively easy heterogeneous integration, so its application has
via bumps), and it can also spread laterally and vertically to the to be carefully calibrated considering all constraints.
outside/boundaries, where (multiple) heat sinks can be placed. Efficient and optimal die placement
While a multitude of thermal-aware placement or floorplan- The placement of dies has a significant effect on key interposer
ning algorithms for stacked 3D designs have been published, characteristics, such as performance. Since the number of dies
there is a lack of similar solutions for interposer systems. Nev- is (so far) rather limited, it can be solved effectively or even op-
ertheless, several thermal models and optimization flows are pre- timally using tailored algorithms, even with pin assignment ac-
sented in Refs. [50], [74]. However, in order to facilitate a suc- counted for. However, most previous work applies probabilistic
cessful adoption for realistic interposer solutions, they need to be optimization [65], [66], which falls short of this prospect.
adapted and integrated into the early stages of the design flow, Fast thermal simulation
such as die placement or the floorplanning stage of the interposer The inherently effective thermal management is one of the key
circuit. advantages of interposer-based 3D design. To support this, fast
thermal simulation should be integrated in the design flow for


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holistic estimation of thermal behavior during early design stages. lenges are compounded with additional complexities pertaining
Data structures for large and heterogeneous 3D chips to the multi-physics nature of the heterogeneous case.
Recall that data structures have been proposed for 3D physical-
design automation. However, the heterogeneous structure of 3.2 MEMS Integration
interposer-based 3D chips requires new and efficient data struc- One possible way of dealing with these additional complexi-
tures which take the special properties of interposer designs into ties is to “package them away” within the die itself, and to subse-
account. Specifically, data structures that are capable of consid- quently incorporate (on the interposer) an accordingly packaged
ering a multitude of constraints, such as inter-die thermal rela- die that has only electrical ports. This approach can be taken,
tionships, are needed. The concept of an assembly design kit e.g., for MEMS sensors where the electromechanical interface is
(ADK) [75], which is analogous to the well-known PDK but tai- encapsulated in the packaged die itself using wafer-scale, mono-
lored for 3D chips, is an interesting option towards this end. lithic integration processes. Such MEMS processes are described
in Refs. [84] and [77] for motion sensing, in Refs. [85] and [86]
3. Heterogeneous Interposer Stacks: Practical
for ultrasound sensing, and in Ref. [87] for piezoelectric energy
Solutions for Advanced Design Automation harvesting. Taking the latter process as a representative exam-
One major benefit of the interposer architecture is that it ple, it is comprised of three bonded wafers with the middle one
enables a low-cost approach to heterogeneous integration with containing the mechanical element and the other two wafers con-
the possibility of placing photonics [76], MEMS [77], integrated stituting capping structures, bonded to the device wafer, with
power sources [78], imaging sensors [79] or acoustic transduc- etched cavities to allow the mechanical element unconstrained
ers [80] on the same substrate as the IC dies. Furthermore, the movement.
interposer architecture enables novel ways for system integration In such MEMS devices where only their electrical pads are
based on vertical interconnect technologies that are not necessar- exposed to the interposer (e.g., capacitive accelerometers and
ily exclusively electrical [81], [82]. gyroscopes, ultrasound transducers, piezoresistive pressure sen-
sors, and piezoelectric energy harvesters), a physical and logi-
3.1 CAD Requirements cal CAD methodology similar to the one advocated in Ref. [83]
The major challenge in such heterogeneous system integration can be used. However, even under these favourable conditions,
is that, by its very nature, it spans multiple physical domains. As such a methodology will have to be adopted to the specific case
a result, the design, analysis and verification of the heterogeneous of interposer-based MEMS integration, considering the following
system require that we augment the traditional VLSI CAD envi- two caveats:
ronment with several physics-aware features, including: ( 1 ) The mechanical integrity of the MEMS devices in the pres-
( 1 ) Cross-domain design capabilities in general, with seamless ence of an interposer must be verified. Indeed, residual
interfaces between the various signal domains, be they elec- stresses induced by interposer bonding are bound to impact
trical, mechanical, optical, acoustic, or fluidic. the mechanical figures of merit of the MEMS devices. In
( 2 ) A rigorous methodology for signal-port definition and place- the case of resonant structures such as gyroscopes or magne-
ment, capable of addressing each of the physical subsystems, tometers, both the resonant frequency and the Q factor can
to enable consistent interlocking between the state spaces of be impacted. In the case of an accelerometer, the maximum
the various physical domains. g acceleration rating of the device can be affected.
( 3 ) A unified system-level language for describing the connec- ( 2 ) In a bulk-machined, multi-wafer MEMS process, the MEMS
tivity between various multi-port components belonging to devices are typically packaged and hermetically sealed un-
different physical domains. der vacuum. The interposer-device assembly must be tested
( 4 ) A physics-aware verification framework enabling domain- to verify that the MEMS device continues to meet design
aware design-rule checking and post-layout validation. specifications post-bonding and that the device is still her-
While the above features are needed even for 2D heteroge- metically sealed.
neous integration, the technological variety provided by the in- Obviously, CMOS foundries have preference for MEMS pro-
terposer architecture makes their incorporation in related CAD cesses that are CMOS-compatible, and the PDKs released for
frameworks even more pressing. The interposer itself has addi- such processes are necessarily CMOS-centric. Due to the signif-
tional requirements of its own that can be summarized as follows: icant market opportunity of the Internet of Things (IoT), a con-
( 1 ) Domain-aware planning and placement of vertical TSVs, be sistent effort is being made by foundries and CAD vendors alike
they electrical, optical, acoustic, or fluidic. to provide the designers with comprehensive PDKs that include
( 2 ) Domain-aware design-rule checking of vertical intercon- parameterized libraries for both IC and MEMS elements. Fur-
nects, including keep-out zones, critical dimensions, and thermore, the MEMS library elements are made visible to the IC
mechanical integrity rules. design interface so that system-level co-simulations of the MEMS
( 3 ) Domain-aware compact models of vertical interconnects to device and its interface ICs (i.e., the driver and readout) are en-
enable system-level performance evaluation. abled. This is for instance the case of the MEMS compact mod-
An up-to-date account of the challenges faced in existing EDA els produced by the Coventor MEMS+ tool, which can be co-
environments in interposer-based, electronic integration is given simulated with their respective ICs using Cadence Spectre within
in Ref. [83]. When such integration is heterogeneous, these chal- the Virtuoso analog design environment [88].


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tronic/Photonic Design Automation. Here also, Cadence’s Vir-

tuoso can play the role of a heterogeneous design cockpit both
on the front-end for system-level simulation (using, for instance,
the INTERCONNECT tool from Lumerical Solutions) and on the
back-end for physical design (using, for instance, PhotoDesigner
from PhoeniX Software) [94]. The Pyxis custom design environ-
ment from Mentor Graphics can play a similar role. An emerging
CAD feature, already implemented in PhotoDesigner, is auto-
matic waveguide routing in the photonic domain. The extension
of this feature to automatic routing in the presence of photonic
TSVs is still an open problem.

3.4 CMOS Image Sensors

While photonic devices require that the interposer supports
Fig. 6 An organic interposer supporting optoelectronic chips and embedded passive elements to couple the photonic signals to the package,
waveguides. Illustration derived from Ref. [8].
CMOS imagers will require that the interposer supports the pixel
array with active elements such as photodetectors to transform the
3.3 Photonics Integration incident photon energy into electrical signals. In an Si interposer,
Unfortunately, in other interposer-based heterogeneous inte- for example, a Si-Ge process to implement the photodetectors
gration cases such as with photonics or micro-fluidics, the inter- will be required. In fact, this process is similar to the one used in
poser will be presented with die ports that are not solely electrical. the CMOS-compatible Si photonics processes mentioned above.
For instance, a Si photonic transceiver for fiber-optic data center Another possible imager architecture is a passive interposer with
communications will have optical ports as well as electrical ports. electrical TSVs, connecting the pixel array through its access cir-
Coupling the optical ports to the interposer will necessitate pas- cuits to the analog and signal-processing back-ends, which will
sive photonics elements such as couplers and waveguides on the be placed on the other side of the interposer.
interposer itself. To enable such elements, the silicon interposer One motivation for moving CMOS imagers from a 3D TSV-
will have to include SOI cross sections similar to the ones sup- based solution [95], [96] to an interposer solution is to integrate
ported by the 2D Si photonics platforms of IBM [89], STMicro- advanced imaging solutions such as stereo vision, surround view
electronics [90], or IME [91]. cameras, and embedded 3D imaging. The challenge to the in-
Although these integration processes are fundamentally 2D, terposer solution is certainly the TSV foundry momentum in this
they can conceivably be adapted to a 3D stacking solution. A particular market segment. Indeed, according to Ref. [97], the
case in point is the 3D stacking of IC drivers on photonics com- market for CMOS imaging sensors will account for 63% of the
ponents using a copper micro-pillar technology as in the STMi- TSV market in 2019, very much ahead of the second market
croelectronics process described in Ref. [92]. It is to be noted that segment, namely, 3D stacked DRAM, which will account for
this photonic-electronic integration is happening at the electrical only 17%.
interconnect level and, unlike the interposer solution of Ref. [81], Given the importance of the CMOS imaging market in the 3D
no photonic TSVs are used. Conceivably, an electrical TSV can integration landscape, a CAD tool for evaluating and comparing
replace the micro pillar used in Ref. [92] if an interposer solu- the various 3D CMOS imager solutions according to the metrics
tion to IC-photonics 3D integration is adopted. But such TSV of power, pixel-array area, resolution, sensitivity and cost would
has the disadvantage that it will present a higher capacitance to be highly desirable.
the driver circuit, thus increasing the power consumption of the
photonic transceiver. At the same time, the interposer can act as a 3.5 Outlook
heat spreader and alleviate the Joule heating due to the electronic We expect that the market opportunity of the IoT will drive in-
driver. It is well known that photonic paths are extremely sensi- novation in the area of interposer integration for heterogeneous
tive to thermal effects, and so the interposer solution in combi- systems. The key reason is that the interposer occupies the sweet
nation with an athermal photonic path design [93] will minimize spot at the intersection of low cost and small footprint.
the negative thermal impact. Another example is that of an or- Our main concern is the business model of heterogeneous inte-
ganic interposer supporting optoelectronic chip communications gration, namely, who will own the heterogeneous interposer? Is it
using embedded mirrors and polymer waveguides as illustrated in the Si foundry or the packaging house? The IoT supply chain will
Fig. 6. As in the MEMS case, CMOS foundries are in preference decide this important question in due time. Until then, the CAD
for such a monolithic CMOS-photonics integration. framework for 2.5D or 3D heterogeneous integration will con-
From a CAD viewpoint, the heterogeneous design environ- tinue to be CMOS-centric as this is where the industry is most
ment will be IC-centric with the reference design flows for the heavily invested.
CMOS-photonics processes supporting passive and active pho-
tonic library elements. This has given rise to a new acronym
in the EDA industry, namely, EPDA, which stands for Elec-


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affect the overall cost of the product. At the same time, detecting
4. Design-for-Test and Testing in 3D Chips
a defective die/interposer early on helps save the excessive cost
In this section, we elaborate on the challenges in testing 3D of good dies stacked/connected with bad ones. An interposer, for
chips and the recent efforts in tackling these challenges. Nat- example, is typically cheaper than dies, which necessitates the
urally, the research developments in 3D chip testing have been identification of a defective interposer to prevent it from being
mostly in the form of adopting 2D chip testing methods, while connected to good and valuable dies. Pre-bond and final testing
there are particular aspects unique to 3D chips that have necessi- are almost considered standard practice for 3D chips; mid-bond
tated the development of novel solutions. and post-bond tests are optional. Detailed test cost modeling and
optimization techniques have been proposed in Ref. [102].
4.1 From 2D to 3D Chip Testing
Regardless of the underlying chip architecture, testing is fun- 4.3 Pre-Bond Testing
damentally an access problem. The parts of a circuit that are most To ensure the stacking/connection of known-good dies, pre-
challenging to test are typically those that are buried deep inside bond testing is necessary. One key challenge thereby is probing
the circuit. For 2D chips, Design-for-Testability (DfT) structures the micro-bumps; they are difficult to access using the probing
such as test points, scan cells, and wrapper cells have been used technology available today. Another challenge is the handling of
to improve access, and thus, testability. These structures help wafers at intermediate stages.
to (i) control nets that are otherwise difficult to reach from the Various techniques have been proposed for the pre-bond testing
primary inputs and (ii) observe nets that are otherwise difficult of interposer. The use of e-fuses inside interposer has been pro-
to monitor through the primary outputs. This way, deeply em- posed in Ref. [103] to connect/disconnect functional paths; test
bedded logic can be “isolated” from its environment. Yet phys- paths are then created to test the interposer through a small num-
ical structures are further needed to effect the connection be- ber of added test pads that can be probed. Other approaches
tween this logic and the primary inputs/outputs. For this purpose, include the use of additional dummy metal layers to create test
scan chains, Test Access Ports (TAPs) and Test Access Mecha- loops [104] or contactless testing using thermal images [105].
nisms (TAMs) have been used in 2D chips. These solutions have These techniques aim at testing the vertical and horizontal inter-
also been standardized via IEEE Std 1149.1 [98] and IEEE Std connects within the interposer. Vertical interconnects may have
1500 [99]. Through these structures, 2D chips have been tested break, void and pin-hole faults [106], while horizontal intercon-
by applying test stimuli and observing the responses. The test nects may have open, inter-bridge and inner-bridge faults [107].
stimuli is obtained via automated test pattern generation (ATPG) The pre-bond testing of TSVs can be performed contactless via
tools, which target for faults representing physical defects. ring oscillators [108]. This way, the potential TSV defects, such
Development of the test techniques in the context of 3D chips as micro-voids and pin-holes, can be tested for.
has necessitated an understanding of what is the same and what The pre-bond testing of dies, in order to detect the defects in-
is different for 3D chips with respect to 2D chips. Only then side a die, is similarly hampered by the challenge of probing
can the structures or techniques from 2D chips be adopted for micro-bumps. Solutions include contactless test [109] or insert-
3D chips and novel ones be developed as needed. For example, ing additional probing pads to non-bottom dies at the cost of in-
isolation and access for 3D chips can be effected by adopting so- creased area [110]. Another concern is whether to perform the
lutions from IEEE Std 1149.1 [98] and IEEE Std 1500 [99], albeit test before or after wafer thinning [111]. Running tests before
with slight modifications. Tester probe access for wafers is sig- wafer thinning excludes defects due to thinning. Also, TSVs are
nificantly more challenging in 3D chips than in 2D chips due to still buried inside the substrate, and thus, cannot be tested easily.
structures such as micro-bumps, which are too small, too dense Testing after thinning, however, necessitates delicate probing.
and too numerous. New defects emerge for 3D chips due to pro-
cessing steps that did not exist in 2D chips, e.g., wafer thinning, 4.4 Mid-Bond, Post-Bond, and Final Testing
alignment and bonding [100]. Micro-bumps in 3D chips are sus- During mid-bond and post-bond tests, mainly the TSV-based
ceptible to open/bridging defects [101]. New decisions specific to interconnects are targeted. Final testing, on the other hand, is the
3D chips also complicate the test flow; there are multiple points at last quality screening step prior to shipping the product to cus-
which 3D chips may have to be tested. These are pre-bond, mid- tomers; any part of the 3D chip should remain testable here [111].
bond (partial stack), post-bond (pre-packaging) and final tests TSV-based interconnects can be tested via dedicated test
(post-packaging; final product), each with its own challenges. pattern generator structures to cover transition faults and
shorts [112]. Though the number of interconnects is large, a
4.2 Test Flow few patterns can potentially test for all these faults. Direct face-
In large-scale 3D chips, known-good dies are stacked together to-face BEOL bonding, another bonding option implemented
or are connected through an interposer. A single defective die in without TSVs [23], can be tested via dedicated built-in-self-test
the stack or a defective interposer results in an unusable 3D chip. (BIST) transceivers [113]. These transceivers help to sense high-
It is therefore crucial to determine the points in which test needs resistive interconnects, which indicate bonding failures [113].
to be conducted, preventing the stacking/connection of good dies Dies and the interposer can be tested only if die isolation and
on top of defective dies/interposer. As each test incurs cost, the access mechanisms are in place. External test access is obtained
decisions as to at what point and how much testing is conducted via probing, typically at wafer-level, for pre-bond, mid-bond and


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post-bond tests, and via package pins in final test. Further on-chip test features, such as IEEE Std 1149.1 [98], to limit the cost and
structures are needed to isolate and access the interposer and the need for novel tools when testing 3D chips [107], [114]. An in-
dies from the external I/Os. This access is defined by IEEE Std teresting consideration is whether these efforts allow to stream-
P1838 [114], which is reviewed next. line the test of heterogeneous 3D interposer. That is, how to first
standardize and then implement access mechanisms for dies with
4.5 Test Access: IEEE Std P1838 [114] diverse analog, photonics, MEMS or other components, and how
IEEE Std P1838 is a standard under development that aims at to synchronize these mechanisms with those on the logic dies—
providing a standardized 3D-DfT, to ensure the inter-operability these are all open challenges.
of dies possibly obtained from different vendors. The standard Another challenge yet to be addressed is the potential for se-
has been largely developed by adopting structures from IEEE Std curity breaches via the test infrastructure. That is, a malicious
1149.1 [98] and IEEE Std 1500 [99]. Figure 7 illustrates the test tester or end-user may try to misuse that infrastructure, seeking
access mechanisms in 3D and 2.5D/interposer chips. access to sensitive on-chip assets such as hard-coded software IP
All dies are assumed to have wrappers around them similar to or security tokens [115]. Such potential misuse of the test infras-
the wrapping of cores in IEEE Std 1500. The wrappers support tructure is only one security concern among others; in the next
INTEST operations where the internal die is tested, and EXTEST section we elaborate on the related challenges and opportunities
operations where the die interconnects (i.e., micro-bumps, TSVs, for 3D chips in more detail.
interposer connections) are tested while bypassing the dies. To
5. Towards Trustworthy 3D Integration
do so, the wrappers support shift, capture, and apply operations.
Every die is assumed to have its TAP controller as in IEEE Std Hardware is at the base of any information processing and,
1149.1; this serial control mechanism connects the dies along the thus, hardware is per se the root of trust (Fig. 8). Among other
stack (or through the interposer), providing them a one-bit band- considerations, this suggests that any chip can only be considered
width for testing as well. Bypass registers inside the dies allow trustworthy if all the individual hardware components as well as
the quick access of other dies or interconnects. The standard also the whole (2D/3D) chip have been thoroughly evaluated in terms
supports a flexible n-bit parallel port to provide an optional par- of their actual, implemented functionality versus their intended,
allel n-bit access to dies, enabling a high-bandwidth test as well. specified functionality [116], [117], [118], [119]*3 . One crucial
concern here is the economics-driven trend to increasingly out-
4.6 Summary and Outlook source various steps of the manufacturing flow, e.g., to outsourced
Testing of 3D (and 2D) chips is essentially characterized by semiconductor assembly and test (OSAT) parties [122]. We ex-
the quest for speedy, comprehensive, yet low-cost access to all pect this trend to further intensify for the complex and diverse
the internal circuitry. In contrast to 2D chips, 3D chips contain 3D integration landscape, thereby increasing the risk exposure
more components to be tested both individually and for the whole for 3D chips. To address and manage this challenge of verifi-
stack, rendering the test procedures more complex, costly, and it- cation and other security-centric challenges, the notions of “se-
erative in nature. Furthermore, novel 3D interconnects (mainly cure by design” and “design-for-trust” have been promoted for
the TSVs) introduce new types of faults. System-level integration some years now for “regular” 2D chips [116], [117], [118], [119],
on an interposer notably eases testing since individual dies, which [123], [124], [125], [126], [127], [128]. Similar studies are re-
are typically fully functional legacy dies, can be easily tested be- cently focusing on 3D chips as well [129], [130], [131], [132],
fore bonding them onto the interposer. Besides, probing an inter- [133], [134], [135], [136], [137], [138]. Note that early stud-
poser may be facilitated by dedicated test pads; highly-integrated,
small-footprint 3D ICs are harder to probe in comparison.
Most testing efforts leverage and extend well-established 2D

Fig. 8 Pyramid of security stages for modern (2D/3D) chips. Trustworthy

information processing relies on all stages, and physical and func-
tional dependencies are built up inherently from the root to the top.
For example, the notion of secure hardware as root of trust—which
also provides security features to enable secure processing further up
Fig. 7 Test access mechanisms as proposed in IEEE Std P1838 [114] for (a) the pyramid—relies itself on trustworthy design and manufacturing
stacked 3D ICs and (b) interposer-based chips. For both configura- steps. “Design-for-trust” seeks to induce that essential trust in those
tions, IEEE Std P1838 utilizes IEEE Std 1149.1 [98] for access con- very steps via a multitude of measures, such as split manufacturing.
trol and IEEE Std 1500 [99] for the wrapper. The mechanisms rely on
the following signals: TDI/TDO (test data input/output), TMS (test *3 Physical and functional verification traditionally has been (and still is) a
mode select), TCK (test clock), TRSTn (test reset not) [114]. major challenge for modern chip design itself [120], [121].


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ies and whitepapers on 3D integration indicate the potential for

trustworthy 3D chips as well [139], [140].
Here we review challenges and promising solutions towards
trustworthy chips, both for 2D and 3D integration. Note that most
solutions devised for 2D chips can be applied for 3D stacks as
well, as long as the latter reuse some 2D components/dies (i.e.,
such 2D security solutions are not directly applicable for mono-
lithic or full-custom 3D stacks). Additionally, we also highlight Fig. 9 Abstract scheme of Refs. [129], [130]. Each security feature re-
quires an introspective interface (TSVs, in red) between the con-
distinct aspects arising for 3D integration.
troller/security die and the untrusted commodity die, along with
some additional transistors for the latter (not illustrated). The ar-
5.1 Securing the Test Infrastructure and Test Procedure rows in the TSVs indicate the signal flow, and the function of each
feature is explained next (along with TSV references): (a) signal tap-
Recall that the test infrastructure may be misused by ma- ping, with on/off (left) and the actual signal (right); (b) re-routing,
licious testers/end-users [115]. Note that 3D chips may offer with on/off (left), the re-routed signal (middle), and off/on for the
even new avenues for such attacks. For example, testing chan- original signal (right); (c) overriding, with on/off (left), new signal
on/off (middle), and the actual new signal (right); and (d) disabling,
nels implemented by dedicated TSVs may leak data to other with on/off.
nearby, regular TSVs (or wires) via cross-coupling effects. More
concerning, these effects may also be exploited to inject mali- nents are outsourced due to time-to-market constraints, it may
cious data into the testing-channel TSVs via nearby “aggressor” become practically infeasible to verify the full 2D/3D chip. At
TSVs. Cross-coupling effects have been generally accounted the same time, one faulty/prone component may compromise the
for [141], [142]; the outlined leakage/injection in TSVs can also trustworthiness of the whole chip, necessitating that all compo-
be mitigated [133], albeit with considerable cost and effort. Still, nents be monitored during runtime, as discussed next.
only few studies explored such test-specific aspects for the se-
curity assessment of 3D chips so far; other risks may have been 5.3 Runtime Attacks and Hardware Monitors
overlooked until now. Malicious software or malicious end-user may seek to retrieve
At the same time, 3D integration can help to secure the system- critical information from on-chip assets, either with or without
level test procedure, thanks to the die wrappers proposed in IEEE the help of hardware Trojans. In the latter case, such attacks typ-
Std P1838 [114]. That is because any sensitive information about ically exploit some side-channel information, which reflects the
the die’s assets (required for ATPG) can be concealed from an various physical interactions that any electronic device experi-
untrusted OSAT party, assuming that the designers provide the ences. For example, demonstrated attacks successfully leverage
test patterns along with the dies. Besides die wrappers, such a the spatio-temporal thermal patterns [146], [147] or the measur-
secure testing procedure would still require features like crypto- able timing behaviour [144] of modern chips. It is understand-
graphic primitives for protected and controlled access to the test ably hard—if possible at all—to anticipate all potential attacks
infrastructure [143]. on modern, large-scale, and more and more heterogeneous elec-
tronic devices. This implies a practical challenge: how to detect
5.2 Verification of Outsourced Components advanced and possibly yet unknown attacks at runtime?
It is straightforward that the more outsourced components a With that challenge in mind, one particularly aspiring solu-
2D/3D chip contains, the higher the risk that some of them are tion towards trustworthy chips are hardware monitors or wrap-
faulty and/or prone to attacks. Components can be rendered pers for the continuous and pervasive control of untrusted and/or
unintentionally faulty/prone, via design or implementation bugs security-critical components [129], [130], [139], [148], [149],
(e.g., Rowhammer [144]), but they can also be made intentionally [150], [151]. The moment such monitors/wrappers observe
and inherently faulty/prone (e.g., via hardware Trojans [145], see some malicious behaviour, i.e., any behavioural anomaly with
Section 5.4). respect to well-defined, “normal” patterns (which may also be
Recent work on structural and functional verification targets re-programmed if need arises), the related components are over-
the security analysis of outsourced components [116], [117], ridden or isolated. In order to compensate for the resulting “loss
[118], [119]. In general, for any 2D/3D chip, the efforts for veri- in processing capacity,” redundant components may be provi-
fication scale with: sioned for.
( 1 ) the number of outsourced components; The notion of monitors is especially attractive in the context of
( 2 ) the structural and functional complexity of the outsourced 3D integration; untrustworthy components in one die may be con-
components; trolled in a precise and localized manner with the help of monitor-
( 3 ) the “permission for introspection” of outsourced compo- ing components implemented in another die [129], [130], [139].
nents: soft IP components typically offer detailed insights For example, Valamehr et al. [129], [130] propose powerful se-
and access into their implementation, whereas hard IP com- curity features acting on the gate- and transistor-level, based on
ponents tend to obfuscate such details; and introspective TSV interfaces (Fig. 9). These features allow for
( 4 ) the system-level connectivity of outsourced components in- tapping, overriding, re-routing, and disabling of internal signals
tertwined with custom-designed components. at will.
For large-scale 2D/3D integration, where typically most compo-


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5.4 Detection of Hardware Trojans that any split of FEOL/BEOL parts across the 3D stack shall
Hardware Trojans are another major concern for reliable and maintain the testability of individual dies; this is an open
trustworthy chips; they are hardware modifications inserted by challenge. As of now, classical known-good die testing lim-
an untrustworthy third party in order to alter the chip’s function- its 3D SM towards 2D SM and possibly easy to resolve lay-
ality, leak critical information, or degrade the chip’s reliability outs, which is contradicting the original promise of 3D SM.
and/or performance [145]. The detection of hardware Trojans, • There is an inherent trade-off between security and cost im-
both at design and runtime, has recently gained more interest, posed by 2D/3D SM. When FEOL and BEOL parts are split
and promising techniques have been proposed [116], [117], [118], across large distances among multiple dies and/or an inter-
[119], [145], [148], [152], [153]. For example, simulation-based poser, the impact on power, performance, and area will be
Trojan detection cannot guarantee full coverage within polyno- more exaggerated than for 2D SM. Previous work on 3D SM
mial runtime, but Wei et al. [153] demonstrate full coverage for either oversimplified this challenge [158] or explored only
industrial circuits within minutes by combining reverse engineer- the scope of secure-but-excessive-overhead solutions [155].
ing and formal verification. Still, advanced Trojans will be ex- • For up-and-coming monolithic 3D chips, manufacturing is
tremely hard to detect; they may, for example, exhibit no distin- typically conducted in a single high-end fab, precluding 3D
guishable patterns at all during functional analysis [127]. SM altogether. Similarly, for 3D SM with advanced TSV-
Note that hardware monitors (Section 5.3) may also be used based 3D chips, the requirements on high-precision align-
for the runtime detection of Trojans. As indicated, this is espe- ment, bonding, and stacking may be met only by a few, po-
cially attractive for 3D chips where such monitors can be imple- tentially untrustworthy OSAT parties.
mented in trustworthy dies, separated from the potentially Trojan- In essence, 3D SM may not be superior to “classical” 2D SM, at
infected legacy chips [127], [129], [130], [139]. Nevertheless, least not unless it is performed holistically, considering the trade-
some Trojans may be crafted specifically for 3D integration and offs for cost and security as well as the prospects for splitting at
end up being “buried somewhere in the midst of the 3D chip”; the chip- and/or the system-level of 3D stacks.
they are harder to detect during runtime [134], and may also ex-
ploit distinct trigger mechanisms such as increased internal heat- 5.6 Summary and Outlook
ing [154]. Notwithstanding the claims made in prior work regarding se-
curity (by allegedly providing a proper root of trust), most work
5.5 Split Manufacturing relies on naive, overly optimistic assumptions regarding their de-
Another recent approach towards trustworthy chips is split sign and implementation. For example, it is easy to see that
manufacturing [124], [135], [140], [155], [156], [157], [158], hardware monitors/wrappers (Section 5.3) are particularly prone
[159], [160], [161], [162]. It seeks to prevent the insertion of to Trojan-based attacks. The moment third parties are involved
Trojans and/or the theft of IP in the first place. in the design and/or manufacturing process of chips containing
More specifically, the key idea is to split the manufacturing such monitors/wrappers, these parties must be trustworthy. Oth-
process into several parts, typically as follows: (i) the advanced erwise, the implementation and functionality of the security fea-
and high-end FEOL parts, which are costly to manufacture and tures themselves cannot be trusted in the first place.
are thus typically outsourced; and (ii) the “modest” BEOL parts, Remarkably, this concern also applies to 3D integration
which are relatively cheap to manufacture in low-end but trusted where untrustworthy commodity components and trusted moni-
fabs. To the untrusted FEOL party, the outsourced design parts tor/supervisor components can be easily manufactured in differ-
merely appear as a “sea of gates,” where the missing intercon- ent dies (or across an interposer) for security reasons [129], [130],
nects may prevent one from (i) inferring any of the actual func- [135], [139]. In order to monitor an untrusted die (without lever-
tionality and/or (ii) localizing particular circuitry prone or fruitful aging side-channel information), the separate supervisor die has
for Trojan attacks. How exactly such splitting can be rendered to rely on the proper physical and functional implementation of
truly secure yet practical (in terms of reasonably low manufactur- some introspective interfaces built within the commodity die. For
ing and layout-level cost) is currently still under broad and vivid example, recall that Valamehr et al. [129], [130] propose several
investigation [155], [156], [157], [159], [160], [161]. security features which all rely on such interfaces (Fig. 9). These
Note that split manufacturing for 3D chips (3D SM) is more features may easily fail or be mislead with false data/signals in
flexible and, thus, potentially more secure than for 2D chips, at case the interfaces are manipulated by untrusted third parties in-
least in theory [162]. That is because 3D integration allows to volved for the design and manufacturing of the commodity dies.
split a design into multiple 2D dies, which then represent inde- In essence, it is arguably difficult yet essential to avoid insecure
pendent FEOL/BEOL parts. Some or all of the BEOL parts may physical and functional dependencies where security features rely
also be manufactured only by the trusted party [124], [140]. Espe- on untrusted components and/or third parties to perform their in-
cially interposer-based 3D SM is hence promising, since it allows tended security functions. If this key requirement fails, the whole
to keep some BEOL parts confidential for the final stacking pro- root of trust is inevitably undermined (Fig. 8).
cess in the trusted fab [135], [155], [158]. In practice, however, System-level 3D integration appears promising towards this
there are some constraints for 3D SM: end. Here, any untrustworthy component/die shall depend on a
• Test and diagnosis of 3D chips (Section 4) typically man- trustworthy system platform (e.g., an actively secured interposer,
dates that individual dies be pre-bond tested. This implies see Fig. 10) for its system-level applicability, and not vice versa.


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designs, the stages of system-level design, design prototyping,

and detailed physical design are all intertwined and furthermore
require advanced capabilities, e.g., for chip-package co-design.
While more and more 3D design-automation solutions are be-
coming available (also with 2D tools being extended), there is
still a need for dedicated tools to design particular applications
such as CMOS imaging sensors.
Testing: Both the test of individual components/dies as well as
the test of the full 3D chip is required; the former is to ensure inte-
gration of known-good dies while the latter is to ensure the proper
Fig. 10 A large-scale and trustworthy, interposer-based 3D chip. The active 3D interconnectivity and the overall functionality. On the one
interposer with the secure network-on-chip (NoC) is the backbone,
i.e., the root of trust. Any internal communication is to remain
hand, existing probing technology falls short in providing physi-
within the untrustworthy dies to limit the load on the interposer cal access to dies/interposer through micro-bumps, complicating
NoC; system-wide and external communication has to be routed the test of 3D chips. On the other hand, well-established 2D test-
through the secure NoC. In case malicious traffic coming from an
untrustworthy die is detected by the secure NoC, the respective die ing standards are currently being extended towards 3D testing,
is isolated, i.e., decoupled from the NoC. Isolating only the mali- streamlining the efforts for testing. Besides, standardized access
cious component(s) instead of the whole die is not practical—we
mechanisms for not purely digital but heterogeneous 3D stacks
cannot rely on any control features implemented in that die to begin
with, as the malicious component(s) may undermine them as well. are currently also still lacking.
Trustworthy integration: Secure hardware is at the heart of
As this approach is implementing a thorough root of trust along any trustworthy information processing, also in up-and-coming
with a correct dependency scheme, it becomes relatively easy to 3D chips. While recent advances for “classical 2D hardware se-
detect and properly isolate malicious components from the trust- curity” can be leveraged for 3D chips to some degree, 3D chips
worthy 3D system if need arises. Note that isolating malicious present unique challenges as well as opportunities. For example,
dies implies no compromise for the system’s overall security, but security measures such as split manufacturing may benefit from
“only” a loss of functionality. The latter can be provisioned for, the additional third dimension but also need to comply with prac-
at least to some degree, by integrating functionally redundant yet tical constraints, e.g., testability and performance of split dies.
physically different commodity dies (from different vendors). Another important consideration is that TSVs experience cross-
coupling effects which may be exploited to leak on-chip assets
6. Summary and Conclusion and/or tamper with the data at runtime. Finally, system-level 3D
In this paper, we discuss the state-of-art for 3D integration, integration on an active interposer can, arguably for the first time,
with particular focus on design automation, testing, and trustwor- enable truly trustworthy integration of untrusted components.
thy system integration. We review the most relevant challenges, Conclusion: 3D integration has been advocated and explored
we outline existing and promising solutions, and we point out by industry and academia for many years now. While there is still
needs for further research and development. In the following we a multitude of challenges for various aspects of 3D integration,
summarize the key points of this paper. there is also notable progress, and different products (memory-
3D implementation options: The sequentially manufactured centric 3D ICs, large-scale 3D FPGAs, NoC interposer, etc.) are
monolithic 3D ICs enable the highest integration density (i.e., already in high volumes in the market. Besides the TSV-based
transistor-level 3D integration) but require full-custom design 3D ICs, which have been highly anticipated early on, the more
which largely hinders design reuse. Furthermore, monolithic 3D practical, cost-effective and flexible interposer stacks may even-
ICs are so far demonstrated only for the digital domain. TSV- tually dominate the 3D landspace. Aside from the easy heteroge-
based 3D ICs enable chip-level integration of both homogeneous neous integration using interposer, this is also because interposer
and heterogeneous components but still require a unified 3D de- can serve as a “unifying integration backbone” for both classical,
sign flow and dedicated manufacturing steps. Interposer stacks legacy 2D chips as well as novel, fully customized 3D ICs.
allow for “plug-and-play” reuse of legacy 2D chips and are thus Acknowledgments The authors thank Sergii Osmolovskyi
the most promising option for large-scale 3D integration; inter- (TU Dresden) for his input on interposer integration (Section 2).
poser have been widely accepted and applied in the industry by
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Validated Against Full-Wave FEM Simulations and RF Measure-
ments, Proc. Elec. Compon. Tech. Conf., pp.966–971 (online), DOI:
10.1109/ECTC.2016.227 (2016). Johann Knechtel received his M.Sc.
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anisms, VLSI Test Symp., pp.100–104 (online), DOI: 10.1109/VTS.
2011.5783765 (2011). (Dipl.-Ing.) in 2010 and Ph.D. in Com-
[144] van der Veen, V., Fratantonio, Y., Lindorfer, M., et al.: Dram- puter Engineering (Dr.-Ing.) in 2014,
mer: Deterministic Rowhammer Attacks on Mobile Platforms,
Proc. Comp. Comm. Sec., pp.1675–1689 (online), DOI: 10.1145/ both from TU Dresden, Germany. He is
2976749.2978406 (2016). a Postdoctoral Associate with the Design
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Learned After One Decade of Research, Trans. Des. Autom. Elec.
for Excellence Lab, in the Department
Sys., Vol.22, No.1, pp.6:1–6:23 (online), DOI: 10.1145/2906147 of Electrical and Computer Engineering,
(2016).
at the New York University Abu Dhabi (NYUAD), UAE. Dr.
[146] Hutter, M. and Schmidt, J.-M.: The Temperature Side Channel and
Heating Fault Attacks, Smart Card Research and Advanced Applica- Knechtel was a Postdoctoral Researcher in 2015–2016 at the
tions, Lect. Notes Comp. Sci., Vol.8419, Springer, pp.219–235 (on- Masdar Institute of Science and Technology, Abu Dhabi. From
line), DOI: 10.1007/978-3-319-08302-5 15 (2014).
[147] Masti, R.J., Rai, D., Ranganathan, A., et al.: Thermal Covert Chan- 2010 to 2014, he was a Research Associate and Scholar with
nels on Multi-core Platforms, Proc. USENIX Sec. Symp., pp.865– the DFG Graduate School on “Nano- and Biotechnologies for
880 (online), available from https://www.usenix.org/conference/
usenixsecurity15/technical-sessions/presentation/masti (2015). Packaging of Electronic Systems” and the Institute of Electrome-
[148] Kim, L.W. and Villasenor, J.D.: A System-On-Chip Bus Architec- chanical and Electronic Design, both hosted at the TU Dresden.
ture for Thwarting Integrated Circuit Trojan Horses, Trans. VLSI
Syst., Vol.19, No.10, pp.1921–1926 (online), DOI: 10.1109/TVLSI. In 2012, he was a Research Assistant with the Department of
2010.2060375 (2011). Computer Science and Engineering, Chinese University of Hong
[149] Bhunia, S., Abramovici, M., Agrawal, D., et al.: Protection
Against Hardware Trojan Attacks: Towards a Comprehensive So- Kong, China. In 2010, he was a Visiting Research Student with
lution, J. Des. Test, Vol.30, No.3, pp.6–17 (online), DOI: 10.1109/ the Department of Electrical Engineering and Computer Science,
MDT.2012.2196252 (2013).
[150] Sepúlveda, J., Flórez, D. and Gogniat, G.: Reconfigurable se- University of Michigan, USA. His research interests cover VLSI
curity architecture for disrupted protection zones in NoC-based Physical Design Automation, with particular focus on 3D Inte-
MPSoCs, Proc. ReCoSoc, pp.1–8 (online), DOI: 10.1109/ReCoSoC.
2015.7238098 (2015). gration and Hardware Security. In addition to various conference
[151] Chandrasekharan, A., Schmitz, K., Kuhne, U., et al.: Ensuring safety papers, he has authored 8 journal papers, invited papers and
and reliability of IP-based system design – A container approach,
Proc. Int. Symp. Rapid System Prototyping, pp.76–82 (online), DOI:
book chapters on these topics. Dr. Knechtel is an active member
10.1109/RSP.2015.7416550 (2015). of the community, serving as reviewer for Elsevier Integration,
[152] Chen, X., Wang, L., Wang, Y., et al.: A General Framework for Hard- the VLSI journal, IEEE Transactions on Computers (TC), IEEE
ware Trojan Detection in Digital Circuits by Statistical Learning Al-
gorithms, Trans. Comp.-Aided Des. Integ. Circ. Sys., Vol.PP, No.99, Transactions on Computer-Aided Design of Integrated Circuits
p.1 (online), DOI: 10.1109/TCAD.2016.2638442 (2017). and Systems (TCAD), ACM Transactions on Design Automation
[153] Wei, X., Diao, Y. and Wu, Y.L.: To Detect, Locate, and Mask Hard-
ware Trojans in digital circuits by reverse engineering and functional of Electronic Systems (TODAES), IEEE Transactions on Very
ECO, Proc. Asia South Pac. Des. Autom. Conf., pp.623–630 (online), Large Scale Integration Systems (TVLSI), as well as for various
DOI: 10.1109/ASPDAC.2016.7428081 (2016).
[154] Hasan, S.R., Mossa, S.F., Elkeelany, O.S.A., et al.: Tenacious hard- conferences: ASPDAC, DAC, DATE, GLSVLSI, ICCAD, ISPD,
ware trojans due to high temperature in middle tiers of 3-D ICs, Proc. MWSCAS, SLIP, and IOLTS. He is a member of IEEE and
Midwest Symp. Circ. Sys., pp.1–4 (online), DOI: 10.1109/MWSCAS.
2015.7282148 (2015). ACM.
[155] Imeson, F., Emtenan, A., Garg, S., et al.: Securing Computer
Hardware Using 3D Integrated Circuit (IC) Technology and Split
Manufacturing for Obfuscation, Proc. USENIX Sec. Symp., pp.495–


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Ozgur Sinanoglu is an Associate Profes- Ibrahim (Abe) M. Elfadel is a Professor

sor of Electrical and Computer Engineer- of Electrical and Computer Engineering at
ing at New York University Abu Dhabi. the Masdar Institute, Khalifa University
He earned his B.S. degrees, one in Elec- of Science and Technology, Abu Dhabi,
trical and Electronics Engineering and UAE. Since May 2013, he has been the
one in Computer Engineering, both from founding co-director of the Abu Dhabi
Bogazici University, Turkey in 1999. He Center of Excellence on Energy-Efficient
obtained his M.S. and Ph.D. in Computer Electronic Systems (ACE4 S), and since
Science and Engineering from University of California San Diego May 2014, he has been the Program Manager of TwinLab
in 2001 and 2004, respectively. He has industry experience at MEMS, a joint collaboration with GLOBALFOUNDRIES and
TI, IBM and Qualcomm, and has been with NYU Abu Dhabi the Singapore Institute of Microelectronics on microelectrome-
since 2010. During his Ph.D., he won the IBM Ph.D. Fellow- chanical systems. Between November 2012 and October 2015,
ship Award twice. He is also the recipient of the Best Paper he was the founding co-director of Mubadala’s TwinLab 3DSC,
Awards at IEEE VLSI Test Symposium 2011 and ACM Confer- a joint research center on 3D integrated circuits with the Techni-
ence on Computer and Communication Security 2013. Profes- cal University of Dresden, Germany. He also headed the Mas-
sor Sinanoglu’s research interests include design-for-test, design- dar Institute Center for Microsystems (iMicro) from November
for-security and design-for-trust for VLSI circuits, where he has 2013 until March 2016. Between 1996 and 2010, he was with
around 160 conference and journal papers, and 20 issued and the corporate CAD organizations at IBM Research and the IBM
pending US Patents. Sinanoglu has given more than a dozen tuto- Systems and Technology Group, Yorktown Heights, NY, where
rials on hardware security and trust in leading CAD and test con- he was involved in the research, development, and deployment of
ferences, such as DAC, DATE, ITC, VTS, ETS, ICCD, ISQED, CAD tools and methodologies for IBM’s high-end microproces-
etc. He is serving as track/topic chair or technical program com- sors. In addition to 3D integrated circuits, his current research
mittee member in about 15 conferences, and as (guest) associate interests include integrated photonics; power and thermal man-
editor for IEEE TIFS, IEEE TCAD, ACM JETC, IEEE TETC, El- agement of multi-core processors; energy-efficient cloud com-
sevier MEJ, JETTA, and IET CDT journals. Professor Sinanoglu puting; low-power, embedded digital-signal processing; energy-
is the director of the Design-for-Excellence Lab at NYU Abu efficient IoT communications; and modeling and integration of
Dhabi. His recent research in hardware security and trust is be- micro power sources. He is currently leading Design Enablement
ing funded by US National Science Foundation, US Department at the Masdar Institute Center of Excellence on Integrated Pho-
of Defense, Semiconductor Research Corporation, and Mubadala tonics (CEIPh) in collaboration with the Semiconductor Research
Technology. Corporation and GLOBALFOUNDRIES. Dr. Elfadel is the recip-
ient of six Invention Achievement Awards, one Outstanding Tech-
nical Achievement Award and one Research Division Award, all
from IBM, for his contributions in the area of VLSI CAD. He is
the inventor or co-inventor of 50 issued US patent. In 2014, he
was the co-recipient of the D. O. Pederson Best Paper Award from
the IEEE Transactions on Computer-Aided Design Automation
for Integrated Circuits and Systems. He is also the co-editor (with
Professor Gerhard Fettweis) of “3D Stacked Chips: From Emerg-
ing Processes to Heterogeneous Systems,” Springer, 2016. Be-
tween 2009 and 2013, Dr. Elfadel served as an Associate Editor
of the IEEE Transactions on Computer-Aided Design. He is cur-
rently serving as Associate Editor of the IEEE Transactions on
VLSI Systems and on the Editorial Board of the Microelectron-
ics Journal (Elsevier). Dr. Elfadel has also served on the Tech-
nical Program Committees of several top conferences, including
DAC, ICCAD, ASPDAC, DATE, ICCD, ICECS, and MWSCAS.
He will be the General Co-chair of the IFIP/IEEE 25th Interna-
tional Conference on Very Large Scale Integration (VLSI-SoC
2017), Abu Dhabi, UAE, October 23-25, 2017. He received his
Ph.D. from MIT in 1993.


c 2017 Information Processing Society of Japan 61
IPSJ Transactions on System LSI Design Methodology Vol.10 45–62 (Aug. 2017)

Jens Lienig received his M.Sc.

(diploma), Ph.D. (Dr.-Ing.) and Habili-
tation degrees in Electrical Engineering
from Dresden University of Technology,
Dresden, Germany, in 1988, 1991 and
1996, respectively. He is currently a Full
Professor of Electrical Engineering at
Dresden University of Technology (TU
Dresden) where he is also Director of the Institute of Electrome-
chanical and Electronic Design (IFTE). From 1999 to 2002, he
worked as Tool Manager at Robert Bosch GmbH in Reutlingen,
Germany, and from 1996 to 1999, he was with Tanner Research
Inc. in Pasadena, CA. From 1994 to 1996, he was a Visiting
Assistant Professor with the Department of Computer Science,
University of Virginia, Charlottesville, VA, and from 1991 to
1994, a Postdoctoral Fellow at Concordia University in Montréal,
QC, Canada. His current research interests are in physical design
automation, with a special emphasis on electromigration avoid-
ance, 3D design, and constraint-driven design methodologies of
analog circuits. Professor Lienig has served on the Technical
Program Committees of the DATE, SLIP and ISPD conferences.
He is a Senior Member of IEEE.

Cliff C. N. Sze is currently a software en-

gineer at Google. Previously, he was a re-
search staff member at the IBM T. J. Wat-
son Research Center and the Austin Re-
search Laboratory. Dr. Sze filed more than
90 patent applications and was granted
over 50 patents. His research interests
include the design and analysis of algo-
rithms in order to solve a wide range of practical problems such as
e-commerce, healthcare analytics, cancer radiation therapy, and
electronic design automation. He received his bachelor and mas-
ter degrees from the Department of Computer Science and Engi-
neering at the Chinese University of Hong Kong, and his Ph.D.
degree in computer engineering from the Department of Electri-
cal Engineering at Texas A&M University. As the senior mem-
bers of IEEE and ACM, Dr. Cliff Sze has been actively serving
the academic/research community, for example, serving as the
general chair and technical program committee chair of Interna-
tional Symposium on Physical Design, and being appointed as
an associate editor for ACM Transactions on Design Automation
of Electronic Systems (TODAES). He is a recipient of the ACM
Special Interest Group on Design Automation (SIGDA) technical
leadership award.

(Invited by Editor-in-Chief: Masanori Hashimoto)


c 2017 Information Processing Society of Japan 62