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Federal University of Technology Akure

This report describes the design of a 6:1 multiplexer circuit. It includes the aim, apparatus used, problem analysis, truth table, circuit diagram, and VHDL code. The report discusses constructing the truth table and deriving the Boolean expression. It then shows how three 2:1 multiplexers can realize the circuit. The VHDL code defines the entity with inputs and output, and uses a process with if/else statements to implement the multiplexer logic. In conclusion, a 6:1 multiplexer was successfully implemented on an FPGA board using VHDL and schematic design.

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100 views9 pages

Federal University of Technology Akure

This report describes the design of a 6:1 multiplexer circuit. It includes the aim, apparatus used, problem analysis, truth table, circuit diagram, and VHDL code. The report discusses constructing the truth table and deriving the Boolean expression. It then shows how three 2:1 multiplexers can realize the circuit. The VHDL code defines the entity with inputs and output, and uses a process with if/else statements to implement the multiplexer logic. In conclusion, a 6:1 multiplexer was successfully implemented on an FPGA board using VHDL and schematic design.

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FEDERAL UNIVERSITY OF TECHNOLOGY AKURE

REPORT ON

6:1 MULTIPLEXER

SUBMITTED TO

THE COMPUTER ENGINEERING DEPARTMENT

MARCH 2021
NAMES MATRIC. NO.

ADELEKE ANUOLUWAPO JOSHUA CPE/17/3090

ADEWOLE ABRAHAM ADEGBOYEGA CPE/17/3094

AGBOOLA STEPHEN ADEBAYO CPE/17/3096

DARAMOLA PONMILE KOLAWOLE CPE/17/3108

EMMANUEL VICTOR OJIMAOJO CPE/17/3111

HAMMED TAOFEEK ADEBAYO CPE/17/3117

IDOWU JERIMIAH TOLUWANI CPE/17/3118

IGE EBENIZER OLUWATOBI CPE/17/3119

LAWAL OLUWASEUN BERNARD CPE/17/3122

MUOGHO ENDURANCE EDINRIN CPE/17/3123

MUSEFIU OJO AMOS CPE/17/3124

ODUFISAN OLUWASEUN ISAAC CPE/17/3125

OLADIPUPO PEACE AYOMIDE CPE/17/3129

OLUGBENGA FAVOUR ENIOLA CPE/17/3134

OLUSHINA AYOMIDE ISREAL CPE/17/3136

OMOOBA EMMANUEL PRECIOUS CPE/17/3138

OYEMAJA PRAISE OLUWAFEMI CPE/17/3145

ORE-EWI EMMANUEL OLUWAFEMI CPE/17/3141

ADELOYE ADENIYI CPE/17/3091

MOSES PRINCE SAMMUEL CPE/18/6675

OLAOLUWA MARVELLOUS SAMMUEL CPE/18/6675

ADBDULWAHAB MUQODIN OLAWALE CPE/17/3085

TORVENDER TERVER STEPHEN CPE/17/3148


TITLE: BUILDING COMBINATIONAL CIRCUIT

AIM AND OBJECTIVES:


➢ To design 6:1 multiplexer circuit
➢ To show the truth table for the design
➢ To show VHDL code of the design

APPARATUS / EQUIPMENTS:

1. Intel Cyclone IV FPGA development board


2. 830561 Programmable Logic Device
3. Altera Quartus II (CAD tool)
4. Laptop computer
PROBLEM ANALYSIS

Building a 6 to 1 multiplexer requires the combination of three 2:1 multiplexer and some two others 2:1
multiplexer to realize the circuit. The truth table will have three select lines and outputs. The 6:1 multiplexer
will have six data inputs A, B, C, D E and F, three selection lines and one output Z. The input will be connected
to the output based on combination of inputs present at these selection lines. The logic expression is derived
and the VHDL code is implemented. The entity of the code will show the inputs and output variables and their
data types while the architecture of the code will show the implementation of the internal view of these inputs
and outputs.

C OUTPUT
6:1 MUX
D

S0 S1 S2

FIG-1.0: 6:1 MUX

PROCEDURE
1) Construct the truth table of the 6:1 multiplexer showing selection lines and the outputs.
2) From the truth table derive the Boolean expression/function for the output.
3) Implement the Boolean function using three 2:1 multiplexers to take in the inputs and some other two 2:1
multiplexers to realize the final circuit.
4) Draw the circuit diagram for the 6:1 multiplexer.
5) Write the VHDL code for the 6:1 multiplexer.
ALGORITHM
FOR TRUTH TABLE:
1) Fill in the inputs.
2) Fill in the logic values of the inputs and also the outputs.

FOR VHDL CODE:


1) Import the Library IEEE.
2) Declare the entity using the right identifiers for the entity name.
3) Assign ABCDEF and S0 S1 S2 inputs of standard logic.
4) Assign Z to the output as standard logic.
5) Write the architecture of the 6:1 multiplexer using process and then-if else statement.
6) End the process and the architecture.
7) Compile the code and run.
FIG1.2: TRUTH TABLE FOR 6:1 MULTIPLEXER
S2 S1 S0 OUTPUT

0 0 0 A

0 0 1 B

0 1 0 C

0 1 1 D

1 0 0 E

1 0 1 F

FIG1.3: 830561 Programmable Logic Device


FIG1.4: CIRCUIT DIAGRAM FOR 6:1 MUX

FIG1.5: Altera Quartus II Development Environment


VHDL CODE FOR 6:1 MULTIPLEXER
--CPE301 GROUP 3 PROJECT
--SUBMITTED ON 19/03/2021
--vhdl code to implement 6:1 multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY mux_6t1 is
port( Data_in : in STD_LOGIC_VECTOR ( 5 downto 0);
SEL : in STD_LOGIC_VECTOR (2 downto 0);
F_CTRL : out STD_LOGIC);
END mux_6t1;
--architecture behaviour of multiplexer
architecture mux_6t1_arch of mux_6t1 is
my_mux: process(Data_in, SEL)
begin
constant clock_period : time:= 10ns;
if (SEL = "101") then F_CTRL <= Data_in(5);
elsif (SEL = "100") then F_CTRL <= Data_in(4);
elsif (SEL = "011") then F_CTRL <= Data_in(3);
elsif (SEL = "010") then F_CTRL <= Data_in(2);
elsif (SEL = "001") then F_CTRL <= Data_in(1);
elsif (SEL = "000") then F_CTRL <= Data_in(0);
else F_CTRL <= '0';
--clock process definition
clock_process : process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end if;
end process my_mux;
END mux_6t1;
END mux_6t1_arch;

CONCLUSION
In this project, we were able to implement a 6:1 multiplexer in Altera quartus prime DE on Intel Cyclone IV FPGA board
using VHDL and schematic implementation. The methodology, truth table, circuit diagram and VHDL code used can be
found in this document.

REFERENCES
Quatus II handbook version 10.0, volume I(Design and Synthesis), Chapter9.

Renesas Electronics Corporation, 83056 Data sheet.

CPE301 LAB manual by Mr Tony

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