❖ Objectives

● Design a complete minimal combinational logic system from specification to

implementation.
● Minimize combinational logic circuits using Karnaugh maps.
● Learn various numerical representation systems.
● Implement circuits using 1st and 2nd canonical minimal forms.

❖ Apparatus

● Trainer Board
● 1 x IC 7411 Triple 3-input AND gates
● 1 x IC 7432 Quadruple 2-input OR gates
● 1 x IC 7404 Hex Inverters (NOT gates)
● IC 7400 Quadruple 2-input NAND gates

❖ Theory

● Analysis of combinational logic design minterms and maxterms canonical forms

universal gates al- bubble pushing.De Morgan’s theorem.

1.​Analysis of combinational logic design:

Combinational logic circuits are made up from basic logic NAND,NOR or NOT gates
that are “combined” or connected together to produce more complicated switching
circuits.These logic Gates are the building blocks of combinational logic circuits
Combinational logic circuits can be very simple or very complicated and any
combinational Circuit can be implemented with only NAND and NOR gates as these are
classed as “universal” gates. ​The three main ways of specifying the function of a
combinational logic circuit are:

a.​Boolean Algebra: This forms the algebraic expression showing the operation of the
logic circuit for each input variable either True or False that results in a logic “1” output.

b. Truth Table : A truth table defines the function of a logic gate by providing a concise
list that shows all the output states in tabular form for each possible combination of input
variable that the gate could encounter.
c. Logic Diagram :​This is a graphical representation of a logic circuit that shows the
wiring and connections of each individual logic gate, represented by a specific graphical
symbol, that implements the logic circuit.

2.Minterm: A minterm is a product term in boolean function in which every element is

present is either in normal or in complemented form.

3.Maxterm: ​A maxterm is a sum term in boolean function in which every element is

present is either in normal or in complemented form.

4.Canonical Form : ​In Boolean algebra,Boolean function can be expressed as Canonical

Disjunctive Normal Form known as minterm and some are expressed as Canonical
Conjunctive Normal Form known as maxterm .

Standard Form - ​A Boolean variable can be expressed in either true form or

complemented form. In standard form Boolean function will contain all the variables in

either true form or complemented form while in canonical number of variables depends

on the output of SOP or POS forming a :

○ minterm for each combination of the variables that produces a 1 in the function
and then taking the OR of all those terms.
○ maxterm for each combination of the variables that produces a 0 in the function
and then taking the AND of all those terms.
5.Universal logic gates:
A universal logic gate is a logic gate that can be used to construct all other logic gates.
There are many articles about how NAND and NOR are universal gates, but many of
these articles omit other gates that are also universal gates. This article covers two input
logic gates, demonstrates that the NAND gate is a universal gate, and demonstrates how
other gates are universal gates that can be used to construct any logic gate.

6.DeMorgan’s law:

A mathematician named DeMorgan developed a pair of important rules regarding

group complementation in Boolean algebra. By ​group complementation, I’m referring
to the complement of a group of terms, represented by a long bar over more than one
variable.
You should recall from the chapter on logic gates that inverting all inputs to a gate
reverses that gate’s essential function from AND to OR, or vice versa, and also inverts
the output. So, an OR gate with all inputs inverted (a Negative-OR gate) behaves the
same as a NAND gate, and an AND gate with all inputs inverted (a Negative-AND
gate) behaves the same as a NOR gate. DeMorgan’s theorems state the same
equivalence in “backward” form: that inverting the output of any gate results in the
same function as the opposite type of gate (AND vs. OR) with inverted inputs.
❖ Circuit Diagram
● Experiment 1:
○ 1st canonical Form

○ 2nd Canonical Form

● Experiment 2:
○ Step 1:

○ Step 2:

❖ Working Procedure

● Experiment 1:
○ First we wrote down all the minterms and maxterms of three inputs ABC in the
table C.1 (from lab manual) .
○ The we wrote the function F in 1st and 2nd canonical forms in table C.2( from lab
manual).
○ Then we drew the circuits along with indicating the pin numbers corresponding to
the relevant ICs.
○ Finally we constructed the 1st canonical form of the circuit and tested it with the
truth table. We connected and tested one minterm at a time and after testing all of
them we OR-ed the minterms for function output.
● Experiment 2:
○ At first we completed the truth table for the circuit of figure 0.1 in table 0.1(from
lab manual).
○ Then we used the space provided below to convert the circuit of figure 0.1 to a
universal NAND gate circuit and converted the inverter to a NAND equivalent as
well.
○ Then we labeled the pin numbers of the appropriate ICs.
○ Then we constructed the universal gate circuit in figure 0.2(from lab manual),
checking the output of each NAND gate independently before connecting the
entire circuit together.
○ Finally we validated the universal gate circuit using table 0.1.

❖ Data and Table

● Experiment 1:

Input Reference ABC F Min term Max term

0 000 0 A’B’C’ A+B+C

1 001 1 A’B’C A+B+C’

2 010 1 A’BC’ A+B’+C

3 011 0 A’BC A+B’+C’

4 100 0 AB’C’ A’+B+C

5 101 0 AB’C A’+B+C’

6 110 1 ABC’ A’+B’+C

7 111 0 ABC A’+B’+C’

Shorthand Notation Function

1st Canonical F=∑(1,2,6) F=A’B’C+A’BC’+ABC’

Form

2nd Canonical F=𝚷(0,3,4,5,7) F=(A+B+C)(A+B’+C’)(A’+B+C)(A’+B+C’)(A’+B’

Form +C’)
● Experiment 2:

XYZ I​1​=AC I​1​=BC’ F

000 0 0 0

001 0 0 0

010 0 1 1

011 0 0 0

100 0 0 0

101 1 0 1

110 0 1 1

111 1 0 1
❖ Simulation Result
● Experiment 1:
○ 1st Canonical Form

○ 2nd Canonical Form

● Experiment 2:
○ Step 1

○ Step 2 (Using Nand Gates)

❖ Discussion

● Experiment 1:
In this experiment for the 1st canonical form we used a IC-7411 3-input and gates, a
IC-7432 Quadruple 2-input OR gates and a IC-7404 Hex Inverters (NOT gates) ,which
were placed on a trainer board. Then we constructed the circuits one by one and used
inverters where needed.

First we formed 3 AND gates with 3 inputs with an inverter. Then the 1st 2 AND gates
were connected with an OR gate and finally the 3rd AND gate and the OR gate were
connected or given as the final input for an OR gate and we got the final output. Now to
verify the outputs we used a truth table and with the help of LED lights on trainer board
we chalked down cross-checked the outputs. For 0 the light would be off and for 1 the
light would be on.
 And for the 2nd canonical form , we used the same equipments but here the circuit design
is different from the 1st canonical form circuit design. Here we constructed 5 OR gates
with an inverter. Here also 3 inputs were given and for this IC 3-input OR gate was used
i.e. an extra equipment was used. Then the 1st 3 OR gates were given input for the AND
gate. And finally with the output of the AND gate and other 2-OR gates the final
3-outputs were used to form an AND gate which gave the final output which was exactly
verified as the 1st canonical form.
The circuit design figures are drawn above and also the truth table with the final
equations. Also the pin numbers corresponding to the relevant ICs are indicated above in
the figures.

● Experiment 2:
Here in this experiment we used equipments like a trainer board and an IC-7400
Quadruple 2-input NAND gates. Here a design of a combinational circuit was given
which we converted it to an universal NAND gate logic circuit.

Firstly, we replaced the AND gates of the given combinational circuit by NAND gates.
The AND gate was replaced by a NAND gate with its output complemented by a NAND
gate inverter. The same was done with the OR gate in that given circuit.

Then we constructed the universal NAND gate and got the final output which was
verified with the help of a truth-table. We chalked down the output by trying different
inputs on the trainer board. And through the LED lights on the trainer board we
cross-checked the outputs. O indicates the lights are on and 1 indicates off.

The given combinational circuit design and also the converted universal NAND gate
circuits are drawn above with the truth-table and the final equation. Also the pin numbers
corresponding to the relevant ICs are indicated above in the figure of converted universal
NAND gate circuit.