-

REVIEW ON FPGA IMPLEMENTATION OF IMAGE ENCRYPTION AND

DECRYPTION USING AES ALGORITHM ALONG WITH KEY
ENCRYPTION

Parul Rajoriya1 Nilesh Mohota2

Department of E&TC Department of E&TC
J.D. College of Engineering and Management J.D. College of Engineering and Management

Abstract— The importance of cryptography applied to security in analysis prior to the selection of the best algorithm for the AES.
electronic data transactions has acquired an essential relevance during Finally, on October 2, 2000, NIST announced that the Rijndael
the last few years. A proposed FPGA-based implementation of the algorithm was the winner.
Advanced Encryption Standard(AES) algorithm along with key Field Programmable Gate Arrays (FPGAs) are hardware devices
encryption for images is presented in this paper. An efficient image whose function is not fixed which can be programmed in system. The
encryption scheme based on FPGA using AES algorithm integrated potential advantage of encryption algorithm implemented in FPGAs
with RC4 encryption standard is proposed. The use of RC4 algorithm includes:
imparts additional level of security to the encryption. The design Algorithm agility- This term refers to the switching of cryptographic
converts the original image into its hex values using Matlab and then algorithm during operation. Algorithm upload- It is perceivable that
give it as input to the proposed AES. The key input given to AES is fielded devices upgraded with new encryption algorithm which did
further encrypted using RC4 encryption algorithm. The encrypted not exist at design time.
image is decrypted using AES decryption algorithm. The encrypted Algorithm modification- There are applications which require
key is decrypted using RC4 decryption algorithm so as to give it as modification of a standardized algorithm. Architecture efficiency-
input to the AES decryption algorithm. The encrypted and decrypted With FPGAs it is possible to design and optimize architecture for
image can be analysed in Matlab. The design uses an iterative specific parameter set.
looping approach with block and key size of 128 bits, lookup table Throughput- Although typically slower than ASIC implementation,
implementation of S-box. This gives low complexity architecture and FPGA have potential of running substantially faster than software
easily achieves low latency as well as high throughput. implementations.
Cost efficiency- Time and cost for developing an FPGA
Keywords— AES algorithm, RC4 algorithm, image encryption, key implementation of a given algorithm are much lower than for an
encryption, image decryption, key decryption ASIC implementation.
As shown in Fig. 1 the cryptographic primitives are classified into
I. INTRODUCTION three main categories; not using key, symmetric key and asymmetric
Each day millions of users generate and interchange large volumes of key [1]. Symmetric key ciphers are also known as secret key or single
information in various fields, such as financial and legal files, key ciphers. Secret key ciphers are further classified as block ciphers
medical reports, and bank services via Internet. These and other and stream ciphers. In block ciphers, a block of bits/bytes is
examples of applications deserve a special treatment from the processed at a time. DES, IDEA, RC5, AES, BLOWFISH,
security point of view, not only in the transport of such information TWOFISH are the different available block ciphers. Whereas in
but also in its storage. In this sense cryptography techniques are stream ciphers one bit or a byte of data is processed at a time. Stream
especially applicable. ciphers are further classified as synchronous and self-synchronous
For a long time, the Data Encryption Standard (DES) was considered stream ciphers.Different synchronous stream ciphers available in the
as a standard for the symmetric key encryption. DES has a key length literature are RC4, E0 (a stream cipher used in Bluetooth), A5/1 and
of 56 bits. However, this key length is currently considered small and A5/2 (stream ciphers used in GSM), SNOW 3G, ZUC (4G stream
can easily be broken. For this reason, the National Institute of ciphers), Rabbit, FISH, and HC-256 etc. [2-7].
Standards and Technology (NIST) opened a formal call for A keystream is produced in stream ciphers which is a pseudorandom
algorithms in September 1997. A group of fifteen AES candidate sequence of bits. A plaintext (a sequence of bits/bytes) is converted
algorithms were announced in August 1998. Next, algorithms were into ciphertext (again a sequence of bits/bytes of same length as that
subject to assessment process performed by various groups of of plaintext) by hiding the plaintext with a generated keystream,
cryptographic researchers all over the world. In August 2000, NIST using a simple XOR operation. The strength of stream ciphers is a
selected five algorithms: Mars, RC6, Rijndael, Serpent and Twofish random keystream which ensures the computational security of the
as the final competitors. These algorithms were subject to further cipher.

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In cryptography, the AES is also known as Rijndael. AES has a fixed The image encryption and decryption is carried out using AES
block size of 128 bits and a key size of 128, 192 or 256 bits. This algorithm and key encryption and decryption is carried out using RC4
paper deals with an FPGA implementation of an AES algorithm.
encryptor/decryptor using an iterative looping approach with block A. AES ENCRYPTION AND DECRYPTION
and key size of 128 bits along with key encryption and decryption The AES algorithm is a symmetric block cipher that can encrypt and
using RC4 algorithm . This method imparts additional level of decrypt information. Encryption converts data to an unintelligible
security. form called cipher-text. Ecryption of the cipher-text converts the data
back into its original form, which is called plain-text.
II. PREVIOUS WORK
In paper [8] Mazen El Maraghy et. Used AES-128 bit algorithm for a. AES Encryption
optimization of area and speed. They have used 128 data bits as well The AES algorithm operates on a 128-bit block of data and executed
as 128 bit cipher key. The implemented hardware design is evaluated Nr - 1 loop times. The key length is 128, 192 or 256 bits in length
in real time. M.Sambasiva Reddy et. [9] used the same AES-128 bit respectively. The first and last rounds differ from other rounds in that
algorithm for speed, power consumption and area. They have there is an additional AddRoundKey transformation at the beginning
implemented the AES algorithm using EDK. Hoang Trang et.[10] of the first round and no MixCoulmns transformation is performed in
the last round. In this paper, we use the key length of 128 bits (AES-
128) as a model for general explanation. An outline of AES
encryption is given in Fig. 3a)

This gives low complexity architecture and easily achieves low

latency as well as high throughput. The design used an iterative
looping approach with block and key size of 128 bit, lookup table
implementation of S-box.Kamali S.H et. [11] used the modified
advanced encryption algorithm to reflect a high level security and
better image encryption.The modification is done by adjusting the
ShiftRow Transformation.The author have compared the results of
the previous AES algorithm and modified AES algorithm.
Fig 3. AES Encryption and Decryption process
III. PROPOSED WORK
SubBytes Transformation:
The SubBytes transformation is a non-linear byte substitution,
operating on each of the state bytes independently. The SubBytes
transformation is done using a once-precalculated substitution table
called S-box. That S-box table contains 256 numbers (from 0 to 255)
and their corresponding resulting values. This approach has the
significant advantage of performing the S-box computation in a
single clock cycle, thus reducing the latency and avoids complexity
of hardware implementation.
ShiftRows Transformation:
In ShiftRows transformation, the rows of the state are cyclically left
shifted over different offsets. Row 0 is not shifted; row 1 is shifted
one byte to the left; row 2 is shifted two bytes to the left and row 3 is
shifted three bytes to the left.
MixColumns Transformation:
In MixColumns transformation, the columns of the state are
considered as polynomials over GF (28) and multiplied by modulo x4
Fig 2. Proposed architecture + 1 with a fixed polynomial c(x), given by: c(x)={03}x3 + {01}x2 +
{01}x + {02}.
The figure 2 gives the proposed architecture in which image AddRoundKey Transformation:
encryption and decryption is carried out using blend of AES In the AddRoundKey transformation, a Round Key is added to the
algorithm and RC4 algorithm to provide additional level of security. State - resulted from the operation of the MixColumns transformation

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- by a simple bitwise XOR operation. The RoundKey of each round
is derived from the main key using the KeyExpansion algorithm. The
encryption/ decryption algorithm needs eleven 128-bit RoundKey,
which are denoted RoundKey(0) RoundKey(10).

b. AES Decryption
Decryption is a reverse of encryption which inverse round
transformations to computes out the original plaintext of an encrypted
cipher-text in reverse order shown in fig.3.b). The round
transformation of decryption uses the functions AddRoundKey,
InvMixColumns, InvShiftRows, and InvSubBytes successively.
AddRoundKey:
AddRoundKey is its own inverse function because the XOR function
is its own inverse. The round keys have to be selected in reverse
order.
InvShiftRows Transformation:
InvShiftRows exactly functions the same as ShiftRows, only in the
opposite direction. The first row is not shifted, while the second, third Fig 5.RC4 Stream Cipher
and fourth rows are shifted right by one, two and three bytes
respectively.
InvSubBytes transformation: C. DESIGN STEPS
The InvSubBytes transformation is done using a onceprecalculated The data block is processed as follows:
substitution table called InvS-box. That InvS-box table contains 256 i. The AES encryption routine begins by copying the
numbers (from 0 to 255) and their corresponding values. 16-byte input array into a 4×4 byte matrix.
InvMixColumns Transformation: ii. Input Image block is XOR ed with the first 128-bits
The InvMixColumns transformation is done using polynomials of of the cipher key which is the output of the RC4
degree less than 4 over GF(28), which coefficients are the elements in encryption algorithm.
the columns of the state, are multiplied modulo (x4 + 1) by a fixed iii. Then the resulting matrix is serially passed through 10
polynomial d(x) = {0B}x3 + {0D}x2 + {09}x + {0E}, where {0B}, rounds.
{0D}; {09}, {0E} denote hexadecimal values. iv. The result of the last round is encrypted image.

B. RC4 ENCRYPTION AND DECRYPTION REFERENCES

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[10] Hoang Trang and Nguyen Van Loi, ―An Efficient FPGA
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