Chapter 4

Sequential Circuits

LEARNING OBJECTIVES

 Sequential circuit  Asynchronous counter design

 Basic storage elements  Synchronous counter design
 Latches (SR Latch, D Latch, JK Latch)  Registers
 Flip-flops (JK flip-flop, T flip-flop, D flip-flop)  Various types of registers
 Counters  Application of shift register

seQuentiaL circuits Sequential circuits are of two types:

In sequential circuits the output depends on the input as well as on 1. Clocked or synchronous
the previous history of output, i.e., they contain memory elements. 2. Unclocked or asynchronous
Outputs In synchronous sequential circuits the logic circuits action is allowed to
Inputs X
Combinational Z = F(X, Y ) occur in synchronization with the input clock pulse from a system clock.
States Y circuit In asynchronous sequential circuits the logic sequential action
is allowed to occur at any time.

Memory Basic Storage Elements

Clk pulses elements
Latches and flip-flops
Clk pulses A storage element in digital circuit can maintain a binary state
Figure 1 Block diagram of sequential circuit indefinitely until directed by an input signal to switch states.
Storage elements that operate with signal levels (i.e., level trigger-
Table 1 Comparison between combinational and sequential circuits ing of signal inputs) are referred to as latches. Those controlled by
Combinational Circuits Sequential Circuits a clock transition (i.e., edge triggering) are fl ip-fl ops.
1. Output at any time depends Output depends on the present input Latches and fi lp-fl ops are related because latches are basic cir-
on the combine set of input as well as on the previous history of cuits from which all fl ip-fl ops are constructed. Latches are useful
applied to it simultaneously at output
for storing binary information and for the design of asynchronous
that instant of time
sequential circuits. But latches are not practical for use in synchro-
2. Contains no memory element Contains at least one memory element
nous sequential circuits, so we use fl ip-fl ops.
3. Easy to design due to absence Difficult to design
of memory
4. Totally described by the set of Its performance is totally described Flip-flops
output values by the set of subsequent values as They are also known as bistable multivibrators. This is a basic
well as set of output values
memory element to store 1-bit of information 0 or 1 and is used in
5. Faster in speed because all Slower in speed because secondary storage circuits, counters, shift register, and many other computer
inputs are primary inputs and inputs are also needed which are
applied simultaneously applied after delay
applications. It has two stable states: 1 and 0. The high state is
6. It need more hardware for Less hardware required
called set state and zero as reset.
realization It has two outputs one being the complement of the other usu-
7. Expensive in cost Cheap in cost ally designated by Q and Q.
 Chapter 4  •  Sequential Circuits  |  1.57

Q R
Q
i/p F.F
Q

Clk Q′
S
There are different types of flip-flops S-R flip-flop, D-flip- Figure 2  Logic diagram for SR latch
flop, T-flip-flop, J-K flip–flops, etc.

S R Qn+1 ′
Qn+1
Latches   
0 0 Qn Qn′ (no change)
(i) S-R Latch: The simplest latch is called S-R latch. S-R
0 1 0 1    (Reset)
means Set-Reset. It has two outputs Q and Q and two
inputs S and R, which represent set or reset signal. 1 0 1 0    (set)
1 1 0 0    (invalid)

S G1
G3 Q R
Q

G4 Q
R G2 Q′
S

Figure 3  S R Latch
Above figure shows two cross coupled gates G3 and
G4 and inverters G1 and G2. Here output of G3 is con-
nected to the input of G4 and output of G4 is applied to S R Qn+1 Qn +1
the input of G3. S = 1, R = 0 output of G1 = 0 and G2 =
0 0 1 1    (Invalid)
1. Since one of the input of G3 is 0, so its output will be
0 1 1 0    (Set)
certainly 1 and consequently both input of G4 will be 1
and the output Q = 0. 1 0 0 1    (Reset)
For S = 1, R = 0, Q = 1, Q = 0. S = 0, R = 1 the 1 1 Qn Qn′     (No change)
output will be Q = 0 and Q = 1. The first of the input
condition S = 1 and R = 0 makes Q = 1 which referred
S R latch is active low SR latch
as the set state and the second condition S = 0 and R = (iii) SR latch with control input: The working of gated
1 makes Q = 0 which is referred as reset state. SR latch is exactly the same as SR latch when the EN
For S = 0 and R = 0 output of both G1 and G2 will be pulse is present. When the EN pulse is not present (EN
one and hence there will be no change in Q and Q. pulse = 0) the gates G1 and G2 are inhibited and will not
For S = R = 1, both the outputs Q and Q will try respond to the input.
to become one, which produces invalid results and
should not be used for the above latch. S
Q
Input Output
State EN
S R Q Q
1 0 1 0 Set
Q
0 1 0 1 Reset
R
0 0 0 0 No change
1 1 ? ? Invalid Characteristic table of SR latch shows the operation
of latch in tabular form. Qt stands as the binary state
(ii) SR latch by using NAND/NOR gates: The SR latch of the latch before the application of latch pulse and
is a circuit with two cross-coupled NOR gates or two referred to as the present state. The S and R columns
cross-coupled NAND gates. Two inputs labelled S for give the possible values of the inputs and Qt+1 is the
set and R for reset. Latch will have two outputs: state of the latch after the application of a single pulse,
•• Q: output state in normal form and referred to as next stage. EN input is not included in
•• Q′: output state in complemented form. the characteristic table.
1.58 | Unit 1  •  Digital Logic

Characteristic
table for SR latch is given below: Pr

Qt S R Qt+1
0 0 0 0 S Q
0 0 1 0
SR
0 1 0 1 EN
Latch
0 1 1 X
R Q
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 X Clr

Characteristic equation of the latch is derived from the

(v) D latch (Transparent latch): One way to eliminate
K-map. the invalid condition of SR latch (when S = R = 1) is
SR
00 01 11 10
to ensure that inputs S and R are never equal to 1 at the
Qt
same time.
0 × 1
By connecting a NOT gate between S and R inputs.
1 1 × 1
i.e, complement of S will be given to R, we can form D
latch as shown in block diagram.
∴ Qt +1 = S + RQt
This equation specifies the value of the state as a func-
D S Q
tion of the present state and the inputs. D
(iv) Preset and clear inputs: For the latch/flip-flop, when the Latch
power is switched ON, the state of the circuit is uncertain. R EN Q
It can be either Q = 0 (reset) or Q = 1 (set) state.
In many applications it is desired to set or reset the
circuit, so that initial state of the circuit will be known. Figure 5  Block diagram for D latch
This is accomplished by using the asynchronous,
inputs referred to as preset (Pr) and clear (Clr), inputs. Pr
These inputs can be applied any time, and are not D
synchronized with EN input/Clr input.

Present (Pr) EN

S Q

EN Clr

Figure 6  Logic diagram for D latch

R Q

EN D Qn+1
Clear (Clr)
0 X Qn – No change (Disabled)
Figure 4  SR latch with Pr and Clr inputs 1 0 0 – Reset state
If Pr = Clr = 1, the circuits operates as of S–R latch 1 1 1 – Set state
explained previously.
If Pr = 0, Clr = 1, the output Q will become 1, which in When EN = 0, the circuit will be disabled and input D
turn changes Q = 0. will not have only effect on output, and output will be
If Pr = 1, Clr = 0 the output Q will become 1, which in same as previous state.
turn changes Q = 0. When EN = 1, D = 0, i.e., S = 0, R = 1 which makes

If Pr = Clr = 0, both Q and Q will become 1, which is output Q = 0 and Q = 1 (Reset state).
invalid case, so Pr = Clr = 0 condition must not be used. When EN = 1, D = 1, i.e., S = 1, R = 0 which makes
output Q = 1, and Q = 0 (Set state).
Pr Clr Qn+1
1 1 Q – No change (vi) JK latch: The function of JK latch is identical to
0 1 1 – Set that of SR latch except that it has no invalid state
1 0 0 – Reset as that of SR latch where S = R = 1. In this case the
0 0 X – Invalid
state of the output is changed as complement of pre-
vious state.
 Chapter 4  •  Sequential Circuits  |  1.59

Preset (A) 10, 01, 10 or 01 (B) 11, 00, 10

(C) 01, 00, 10 or 01 (D) 10, 11, 10 or 01
J
G1 G3 Q Solution:  (C)
Given circuit is RS latch with NOR gates.
EN By comparing with RS latch A = R, B = S, and X = Q,
Y = Q, so from truth table of RS latch
G2 G4 Q
K Q/X
S/B R/A Q /Y
0 1 0 1 Reset (Invalid)
Clr
1 1 0 0
EN J K Qt+
0 0 1 0 (Same as previous state)
1 0 0 Qt No change
0 1
1 0 1 0 Reset
1 1 0 1 Set After invalid case S = 1, R = 1, i.e., A = B = 1,
1 1 1 Qt Toggle The output= Q 0= , Q 0, i.e., X= Y= 0
0 x x No change
By applying A = 0, B = 0
Qt
The output X becomes (0 + 0) = 1and which in turn changes

JK latch by using SR latch: The uncertainty of SR flip-flop Y = ( B + X ) = (0 + 1) = 0

(when S = 1, R = 1) can be eliminated by converting it into
JK latch. A=0
X=0
The data inputs J and K, which are ANDed with Q and Q 0
respectively, to obtain S and R inputs.
S = J ⋅ Q,   R = K ⋅ Q 0
Y=0
B=0

J S Q
(or) the output Y becomes (0 + 0) = 1and which in turn
EN SR latch changes X = (Y + A) = (0 + 1) = 0. So, output (X, Y) cannot
be predicted after the invalid condition. So, X = 0, Y = 1 or
K R Q X = 1, Y = 0
Example 2:  Refer to the NAND and NOR latches shown
Figure 7  JK latch by using SR latch in the figure the inputs (P, Q) for both the latches are first
made (1, 0) and then after a few seconds, made (0, 0). The
J K S R Qn+1 Qn+1 corresponding stable outputs (X, Y ) are
0 0 0 0 Qn Qn -No change P P
X X
0 1 0 Qn 0 1-Reset

1 0 Qn 0 1 0-Set

1 1 Qn Qn Qn Qn-Toggle Y Y
Q Q

Example 1:  The following binary values were applied to A (A) NAND: first (0, 1) then (0, 1); NOR: first (1, 0) then (1, 0)
and B inputs of NOR gate latch shown in the figure, in the (B) NAND: first (0, 1) then (1, 1); NOR: First (0, 1) then
sequence indicated below. A = 1, B = 0; A = 1, B = 1; A = 0, (0, 1)
B = 0. The corresponding stable X, Y outputs will be (C) NAND: first (1, 0) then (0, 0); NOR: first (1, 0) then (1, 0)
(D) NAND: first (1, 0), then (1, 0); NOR: first (1, 0) then
A
X (1, 1)
Solution:  (B)
From the truth table of SR latch and S R latch SR latch with
NOR gates:
Y
B For (P, Q) = (1, 0) = (R, S) output (=
X , Y ) (=
Q, Q ) (0, 1)
1.60 | Unit 1  •  Digital Logic

Then (P, Q) are made (0, 0), i.e., (R, S) = (0, 0), which G1m
J
results in no change at output. So, (=X , Y ) (=
Q, Q ) (0,1) Qm
SR latch with NAND gates: Q
For (P, Q) = (1, 0) = (S, R) output (X, Y) = (Q, Q ) = (0,1). Clk
Then (P, Q) are made (0, 0), i.e., (S, R) = (0, 0) which is G 2m Qm Q
K
invalid conditions for S R latch. So, (=
X , Y ) (=
Q, Q ) (1,1)
(vii) Race around condition: The difficulties of both the
inputs (S = R = 1) being not allowed in an SR latch is
eliminated in JK latch by using the feedback connec- Figure 8  Logic diagram of JK flip-flop
tion from the output to the input of the gate G1 and G2. Positive clock pulse is applied to the first latch and
In a normal JK latch if J = K = 1 and Q = 0 and enable the clock pulse will be inverted before its arrival at
signal is applied without RC differentiator, after a the second latch. When Clk = 1, the first latch is ena-
time interval ∆t (the propagation delay through two bled and the outputs Qm and Qm responds to the inputs
NAND gate in series) the output will change to Q = 1. J and K, according to the truth table of JK latch. At
Now we have J = K = 1 and Q = 1 and after another this time the 2nd latch is inhibited because its clock
time interval of ∆t the output will change back to Q = is low (Clk = 0). When the clock goes low (Clk = 0),
0. Hence for the duration of (tp) of the enable signal the first latch is inhibited and the second is enabled.
the output will oscillates back and forth between 0 and Therefore, the outputs Q and Q follow the outputs
1. At the end of the enable signal the values of Q is Qm and Qm , respectively. Since the second latch sim-
uncertain. This situation is referred to as race around ply follows the first one, it is referred to as slave and
condition. the first one as the master. Hence this configuration is
The race around condition can be avoided if enable known as master-slave JK flip-flop. In this circuit, the
time period tp < ∆t but it may be difficult to satisfy this input to the gate G1m and G2m do not change, during
condition, because of very small propagation delays the clock pulse levels.
in ICs. To solve this problem the enable signals are
converted to narrows spike using RC differentiator   The race around condition does not exist.
circuit having a short time constant. Its output will be
Table 2  State/characteristic Table
high during the high transmission time of the enable.
Another method to avoid this problem is master-slave Clk J K Qt Qt+1
JK flip-flop. ↓
↓
0
0
0
0
0
1
0
1
}Q1

Flip-flops ↓ 1 0 0 1
}1
↓ 1 0 1 1
(i) Master-slave JK flip-flop: This is a cascade of 2 SR
latches with feedback from the output of the second SR
latch to the inputs of the first as shown in the figure below.
↓
↓
0
0
1
1
0
1
0
}
0 0

↓
↓
1
1
1
1
0
1
1
}
0 Qt

J S
Q S Q JK
Clk Q 00 01 11 10
Q R Q
K R 0 1 1
1 1 1

Qt +1 = J Qt + Qt K

(ii) Flip-flop switching time: In designing circuits with

flip-flop the following parameters are important:
1. Set-up time: The minimum amount of time
Pr required for the data input to be present before the
J Q
clock arrived.
Clk
2. Hold time: The minimum amount of time that the
K data input to be present after the clock trigger
Clr Q
arrived.
3. Propagation delay: The amount of time it takes for
the output to change states after an input trigger.
 Chapter 4  •  Sequential Circuits  |  1.61

1 flip-flop can be realized using a SR/JK as show in the

Input figure below.
t t hold
0
Set-
up
Clock D S/J Q
i/p
Clk
R/K Q
Output Propagation
tp delay

t1 t2 t3 t4 Table 3  Truth Table

For example, t setup = 50 m sec and t hold = 5 m sec,

clk D Qt+1
the data bit has to be the input at least 50 m sec before ↑ X Qt
the clock bit arrives and hold at least 5 m sec after the ↑ 0 0
clock edge. ↑ 1 1

(iii) Triggering of flip-flop: The flip-flop can be triggered There is no raising problem with D flip-flop. High or
to set or reset either at one of the edges of the clock 1 state will set the flip-flop and a low or 0 state will
pulse. There are three types of triggering as described reset the flip-flop. The presence of inverter at the input
below: ensure that S/J and R/K inputs will always be in the
1. Positive edge triggering flip-flop: These set or opposite state.
reset at the positive (rising or leading) edge of the Table 4  Characteristic Table of D Flip-flop
clock pulse depending upon the state of i/p signal
and o/p remain steady for 1 clock period. Positive Qt D Qt+1
edge triggering is indicated by an arrow head at the 0 0 0
clock terminal of the flip-flop. 0 1 1
1 0 0
S Q
1 1 1

D
R Q Q 0 1
0 1
2. Negative edge triggered flip-flop: There are flip- 1 1
flops those in which state transmissions take Q t +1=D
place only at the negative edge (falling or trailing)
From the characteristic table of D.flip-flop, the next
of the clock signal. Negative edge triggering is
state of the flip-flop is independent of the present state
indicated by arrow head with bubble at the clock
since Qt+1 = D, whether Qt = 0 or 1.
terminal.
(v) T flip-flop: In a JK flip-flop J = K = 1 and the resulting
S Q
flip-flop is referred to as a T flip-flop.
Pr

R Q

T J Q
3. Level triggering: Level triggering means the
Clk FF
specified action occurs based on the steady state
value of the input. That is, when a certain level is K Q
reached (0 or 1) the output will change states level
triggering will be used in latches. Table 5  Truth Table
(iv) D flip-flop: It receives the designation from its ability Clk T Qn+1
to hold data into its internal storage. An SR/JK flip-
↑ 0 Qn
flop has two inputs. It requires two inputs S/J and R/K
to store 1 bit. This is a serious disadvantage in many ↑ 1 Qn
application to overcome the difficulty D flip-flop has ↑ x Qn
been developed which has only one input line. A D
1.62 | Unit 1  •  Digital Logic

If T = 1, it acts as a toggle switch for every Clk pulse 10

with high input, the Q changes to its opposite state.
0× 0 1 ×0
Table 6  Characteristic Table
01
Qt T Qt+1
0 0 0 Figure 9  State diagram of SR flip-flop
0 1 1
1×
1 0 1
1 1 0 0× 0 1 ×0

1 0 1
×1
T 0 1 Figure 10  State diagram of JK flip-flop
Q
0 1
1
1 1
0 0 1 0
Qt +1 = TQt + Qt T
1
(vi) Excitation table of flip-flops: The truth table of flip- Figure 11  State diagram of T flip-flop
flop is also referred to as the characteristic table, which
specifies the operational characteristic of flip-flop. 1
Sometimes we come across situations in which pre-
0 0 1 1
sent state and the next state of the circuit are known
and we have to find the input conditions that must pre- 0
vail to cause the desired transition of the state.
Consider initially JK flip-flop output Qn = 1, Q n Figure 12  State diagram of D flip-flop

= 0, after clock pulse it changed to Qn +1 = 0, Q n + 1 = 1, ( viii)  Conversion of one flip-flop to other flip-flop
The input conditions, which made this transition,  Conversion of T flip-flop to JK flip-flop
can be 1. Write the characteristic table of required flip-flop
Toggle – for J = 1, K = 1, Qn +1 = Q n (here JK).
or 2. Write the excitation table of available or given
Reset – for J = 0, K = 1, Qn +1 = 0, Q n +1 = 1 Flip-flop (here T).
From the above conditions we can conclude that for 3. Solve for inputs of given flip-flop in terms of
transition Qn = 1 to Qn+1 = 0 occurs when J = 0 (or) 1 required flip-flop inputs and output.
(don’t care) and K = 1.
Table 8  JK flip-flop characteristic and T flip-flop excitation table
Similarly, input conditions can be found out for all
possible situations. JK Flip-flop
Characteristic Table T Flip-flop Excitation Table
Table 7  Excitation table of flip-flop.
J K Qn Qn+1 T
Present Next SR JK T D 0 0 0 0 0
State State Flip-flop Flip-flop Flip-flop Flip-flop
0 0 1 1 0
Qn Qn+1 S R J K T D
0 1 0 0 0
0 0 0 × 0 × 0 0
0 1 1 0 1
0 1 1 0 1 × 1 1
1 0 0 1 1
1 0 0 1 × 1 1 0
1 0 1 1 0
1 1 × 0 × 0 0 1
1 1 0 1 1
These excitation tables are useful in the design of syn- 1 1 1 0 1
chronous circuits.
KQ n
(vii) State diagrams of flip-flops: State diagram is a directed J 00 01 11 10
graph with nodes connected with directed arcs. State of 0 1
the circuit is represented by the node, the directed arcs 1 1 1 1
represent the state transitions, from present state (node)
to next state (node) at the occurrence of clock pulse. T = J Q n + KQn
 Chapter 4  •  Sequential Circuits  |  1.63

The circuit is
J
(A) SR flip-flop with inputs A = S, B = R
T Q Q (B) SR flip-flop with inputs= A R= ,B S
K T (C) JK flip-flop with inputs A = J, B = K
Clk Q Q (D) JK flip-flop with inputs=A K=
,B J
Solution:  (C)
Figure 13  D Flip-flop by using other flip-flops
The characteristic equation of D flip-flop is

D S Q D J Q
Qn+1 = D

Clk Here input D = AQ n + BQn

R Q K Q So, output Qn +1 = AQ n + BQn
By comparing this equation with characteristic equation of JK
Clk

Qn +1 = J Q n + KQn
T Q
D If A = J, B = K, then this circuit works like JK flip-flop.
Clk Q Example 4:  The input Clk frequency for the flip-flop given
is 10 kHz, then the frequency of Q will be
Figure 14  T flip-flop by using other flip-flops

S Q Q
S Q
Clk
T R Q

R Q

(A) 10 kHz (B) 5 kHz

Clk
(C) 20 kHz (D) 2.5 kHz

T J Q Solution:  (B)
=
Form circuit we can say S Q=
n, R Qn .
If initially (Qn , Q n ) = (0, 1), then inputs (S, R) = (1, 0), by
K Q
applying clk pulse (Qn +1 Q n +1 ) becomes (1, 0) . . .
Clr
Clk Qn Qn S R Qn+1 Q n+1

D Q 1 0 1 1 0 1 0
T
2 1 0 0 1 0 1
Clk Q 3 0 1 1 0 1 0
4 1 0 0 1 0 1
Example 3:  A sequential circuit using D flip-flop and logic
gates is shown in the figure, where A and B are inputs and The output Qn+1 toggles for every clock pulse.
Q is output.
t
Clk

A
Q
D Q Q 2t
B
Clk Q Q 1 f 10
=
So frequency of Q = = = 5 kHz
2t 2 2
1.64 | Unit 1  •  Digital Logic

Examples 5:  For the D flip-flop shown, if initially Qn is set are not clocked simultaneously. Each flip-flop is trig-
then what is the output state Qn+1 for X = 0, and for X = 1? gered by the previous flip-flop.

(ii)
Asynchronous counters (ripple counters):
D Q Q
X Asynchronous counters do not have a common clock
that controls all the flip-flop stages. The control clock
Clk Q is input to the first stage. The clock for each stage
subsequent is obtained from the flip-flop of the prior
(A) 0, 0 (B) 0, 1 stages. Let us analyze the 3-bit counter and its corre-
(C) 1, 0 (D) 1, 1 sponding wave form diagram shown below.
Solution:  (B)
QA QB
The characteristic equation of D is Qn+1 = D
Here D = X ⊕ Qn 1 JA QA 1 JB QB 1 JC QC
So Qn +1 = X ⊕ Qn Clk
We have Qn = 1 (Qn is set) for X = 0
1 KA 1 KB 1 KC
Qn+1 = 0 ⊕ 0 = 0
We have Qn = 1 (Qn is set), for X = 1 0 1 2 3 4 5 6 7
Clk
Qn+1 = 1 ⊕ 0 = 1
QA
Applications of flip-flops:
QB
1. Data storage: A group of flip-flops connected in
series/parallel is called a register, to store a data of QC
N-bits, N-flip-flops are required. Data can be stored
in parallel or serial order. Similarly, serial to parallel
Figure 15  Timing diagrams
conversion and parallel to serial conversion can be
done by using registers.
•• The counter has three flip-flops and three output bits,
2. Counting: A number of flip-flops can be connected in
therefore it is a three stage counter.
a particular fashion to count the pulses applied (Clk)
•• The input clock does not trigger the three flip-flops,
electronically. One flip-flop can count 2 Clk pulses,
therefore it is an asynchronous counter.
two flip-flops can count up to 22 = 4 pulses, similarly
•• The J and K inputs are tied together as kept high. So
n flip-flops can count up to 2n pulses. Flip-flops may
they are considered to be toggle flip-flops.
be used to count up/down.
•• The flip-flops are negative edge triggered.
3. Frequency division: Flip-flops may be used to divide
•• The wave form analysis reveals that QA is the LSB
input signal frequency by any number. A single flip-
1
flop may be used to divide the input frequency by 2. and that its frequency is the input clock frequency.
Similarly n flip-flops may be used to divide the input 2
1
frequency by 2n. Output of a MOD-n counter (i.e., Further more, Qc is the MSB and its frequency is the
which counts n states) will divide input frequency by n. 8
input clock frequency.
•• The count sequence is 000, 001, 010, 011, 100, 101,
Counters 110, 111 where the LSB is QA. Thus it is MOD-8
Digital counters consist of a number of flip-flops. Their binary up counter.
function is to count the number of clock pulses arriving at •• Asynchronous counters are also known as ripple
its clock input. counters because the effect of the input clock ripples
through the counter until it reaches the final stage.
(i) Counter classification: Counters are classified accord-
ing to their operational characteristic. Some of these Asynchronous Counter Design
characteristics include: Step I:  Write the counting sequence.
1.  Counter triggering techniques Step II:  Tabulate the values of reset signals. R for various
2.  Frequency division characteristic state of counter.
3.  Counter modulus Step III: Obtain the minimal expression for R and R using
4.  Asynchronous or synchronous K-map or any other method.
In a synchronous counter all flip-flops are clocked Step IV:  Provide a feedback such that R or R resets all the
simultaneously. In asynchronous counter the flip-flops flip-flops after the desired count.
 Chapter 4  •  Sequential Circuits  |  1.65

Table 9  Identification of up/down Counters

After Pulses States Q3, Q2, Q1 Reset R
Clock Triggering Q Type 0 000 0
+ve edge Up 1 001 0
Q
2 010 0
+ve edge Q Down
3 011 0
-ve edge Down
Q 4 100 0
-ve edge Q Up 5 101 0
6 110 1

Clock is negative triggering pulse and Q is connected to 7 ↓↓↓

next level clock, it is acting like a up counter. 000 0
111 X

Table 10  Identification of GATE to Clear the Flip-flops From the Truth table R = Q3 Q2
For active Low R is used.
Input to the Gate Output of the Gate Type of Gate
∴ R = 0 for 000 to 101
OR
Q
Clr
R = 1 for 110
R = X for 111
Clr NOR
Q ∴ K-map is
Q2Q3
Q NAND Q1 00 01 11 10
Clr
0 1
Q Clr AND
1 ×

∴ R = Q2 Q3
Example:
Logic diagram is
1 1 1
(i) Clr
Q T2 Q2
T1 Q1 T3 Q3

Clk
Q1 Q2 Q3
(ii) Q Clr Clr Clr
Clr

Asynchronous Decode Counter

Example 6:  Design and Implement a MOD-6 asynchronous A ripple counter is an asynchronous sequential circuit,
counter using T flip-flops. clock is applying only for LSB side. Decade ripple counter
Solution:  Counting sequence is 00, 001, 010, 011, 100, it counts from 0 to 9 for up counter.
101 MOD-10 counter it counts starting from 0000 to 1001. If
the NAND gate output is logic ‘0’ at that instant the counter
reset to initial state.

Q3
Q2
Clr
Q1
Q0

J0 Q0 J1 Q1 J2 Q2 J3 Q3

Clock

K0 K1 K2 K3
1 Clr Q 0 1 Clr Q 1 1 Clr Q 2 1 Clr Q 3

Figure 16  MOD-10 or decade counter

1.66 | Unit 1  •  Digital Logic

To design a MOD-N counter minimum number of flip-flops

required is 1 T0 Q0 T1 Q1 T2 Q2
N ≤ 2n
Clock
where N → MOD
n → No. of flip-flops Q0 Q1 Q2

Example: Figure 17  3-bit series carry counter

MOD-5 counter
5 ≤ 2n
1
∴n=3 f Clk ≤
t pd + ( n − 2)t pd AND
Operating Clock Frequency
(i) Synchronous counter: where
tpd → Propagation delay of each flip-flop.
1 tpd AND → Propagation delay of AND gate.
f Clk ≤
t pd n → Number of flip-flops.
In this, Qo toggles for every clock pulse.
(ii) Asynchronous counter: Q1 toggles when Qo is 1.
Q2 toggles when o/p of AND gate is logic 1.
1
f Clk ≤ Note:  To design a synchronous series carry down counter.
nt pd
Connect Qo to the next flip-flop input.
Output frequency of the MOD-N counter is
Design of Synchronous Counter
f Clk Step I:   Determine the required number of flip-flop.
⇒ fo = . Step II:    Draw the state diagram showing all possible states.
N
Step III: Select the type of flip-flop to be used and write the
(iii) Synchronous counter: When counter is clocked excitation table.
such that each flip-flop in the counter is triggered at Step IV: Obtain the minimal expressions for the excitations
the same time, the counter is called as synchronous of the FFs using the K-maps.
counter. Step V:  Draw a logic diagram based on the minimal expres-
•• Synchronous counters have the advantage of high sion. Let us employ these techniques to design a
speed and less severe decoding problems. MOD-8 counter to count in the following.
•• Disadvantage is having more circuiting than that of
Example 7:  Sequence: 0, 1, 2, 3, 4, 5, 6, and 7. Design a
asynchronous counter.
synchronous counter by using JK flip-flops.

Synchronous Series Carry Counters Solution:

Step I: Determine the required number of flip-flops. The
For normal ring counters to count N sequence total N flip-
sequence shows a 3-bit up counter that requires 3
flops are required.
flip-flops.
Unused states in ring counter = 2N – N. Step II: Draw the state diagram.
Unused states in Johnson ring counter = 2N – 2N.
111
Asynchronous counters are slower than the synchronous
counters. By using synchronous series carry adders we can
000
design MOD-N counter with n Flip-flops-only.
110
For non-binary counters N ≤ 2n
001
3-bit series carry up counter
It counts from initial state 000 to 111. 100
∴ MOD = 2n = 8 states 010
011
∴ MOD-8
 Chapter 4  •  Sequential Circuits  |  1.67

Step III: Select the type of flip-flop to be used and write the 1

excitation table.
JK flip-flop is selected and excitation table of a 3-bit up J1 Q1 J2 Q1 J3
counter is FF1 FF2 FF3

PS NS Required Excitation J2 Q1 K2 Q K3

Q3 Q2 Q1 Q3 Q2 Q1 J3 K3 J2 K2 J1 K1
Clk
0  0   0 0  0  1 0  x  0  x  1  x
0  0  1 0  1  0 0  x  1  x  x  1
0  1  0 0  1  1 0  x  x  0  1  x
Table 11  Comparison between asynchronous counter and
0  1  1 1  0  0 1  x   x   1  x  1 synchronous counter
1  0 0 1  0  1 x  0  0  x  1  x
Asynchronous Counter Synchronous Counter
1  0  1 1  1  0 x  0  1  x  x  1
1. In this type of counter, In this type there is no con-
1  1  0 1  1  1 x  0  x  0  1  x flip-flops are connected nection between output of first
1  1  1 0  0  0 x  1  x  1  x  1 in such a way that output flip-flop and clock input of the
of first flip-flop drives the next flip-flop
clock for the next flip-flop
Step IV:  Obtain the minimal expression using K-map.
2. All the flip-flops are not All the flip-flops are clocked
Q 2Q 1 clocked simultaneously simultaneously
Q 3 00 01 11 10 3. Logic circuit is very simple Design involves complex logic
0 1 even for more number of circuits as number of state
states increases
1 × × × ×
J 3 = Q 2Q 1 4. Main draw back of these As clock is simultaneously
counters is their low speed given to all flip-flops, there is no
Q 2Q 1 as the clock is propagated problem of propagation delay.
Q 3 00 01 11 10 through number of flip- Hence they are preferred when
flops before it reaches last number of flip-flops increases in
0 × × × ×
flip-flop the given design.
1 1
K 3 = Q 2Q 1
The main drawback of ripple counters is their high
Q 2Q 1 delays, if propagation delay of each flip-flop is
Q 3 00 01 11 10 assumed as x, then to get output of the first flip-flop
0 1 × × it takes x, i.e., after x seconds the second flip-flop
1 1 × × will get its clock pulse from previous stage, and out-
J2 = Q1 put of second flip-flop will be out after another x
seconds, similarly the final output of last flip-flop
Q 2Q 1
Q 3 00 01 11 10 will be after nx seconds, where n is the number of
0 × 1 × flip-flops. So the propagation delay of ripple counter
1 × 1 ×
is nx, which is directly proportionate to the number
of flip-flops.
K 3 = Q1
The maximum frequency of operation of ripple
Q 2Q 1 1
Q3 00 01 11 10 counter is inverse of delay, f max =
nx
0 1 × × 1 Maximum operating frequency is the highest fre-
1 1 × × 1 quency at which a sequential circuit can be reliably
triggered. If the clock frequency is above this maxi-
J1 = 1
mum frequency the flip-flops in the circuit cannot
Q 2Q 1 respond quickly and the operation will be unreliable.
Q3 00 01 11 10 In case of synchronous counters (synchronous
0 × 1 1 × circuits) as clock is applied simultaneously to all the
1 × 1 1 × flip-flops, the output of all the flip-flops change by x
seconds (delay of one flip-flop) and this delay is inde-
K1 = 1
pendent of number of flip-flops used in circuit.
Step V: Draw the logic diagram based on the minimal The maximum frequency of operation of synchro-
expression. 1
nous counter is inverse of delay f max =
x
1.68 | Unit 1  •  Digital Logic

Example 8: The maximum operation frequency of

a MOD-64 ripple counter is 33.33 kHz, the same flip- Serial data Serial data
input output
flops are used to design a MOD-32 synchronous counter,
and then the maximum operating frequency of the new
Serial-in–serial-out right-shift register
counter is
(A) 400 kHz (B) 200 kHz
(C) 40 kHz (D) 500 kHz (ii) Serial-in–parallel-out:

1 Serial data
Solution:  For ripple counter f max = , given is a MOD-64
nx input
ripple counter, i.e., 26 states, so n = 6 flip-flops are required.
1
x= = 5µ S
33.33K × 6
Parallel data output
For synchronous counter
(iii) Parallel-in–parallel-out:
1 1
f max = = = 0.2 MHz = 200 kHz Parallel data input
x 5 µS
When multiple counters are connected in cascade, then the
total number of states of the new counter is A × B × C, i.e.,
it will work as MOD-A × B × C counter.

MOD-A MOD-B MOD-C

counter counter counter

For example, decade counter counts from 0 to 9, 10 states –

Parallel data output
If two such decade counters are connected in cascade, then
the total counting states will be 10 × 10 = 100, it will work
as MOD-100 counter, which counts from 00 to 99. (iv) Parallel-in–serial-out:
Parallel data input
Registers
A number of flip-flops connected together such that data
may be shifted into and shifted out of them is called a shift
register. There are four basic types of shift register: Serial
data
1. Serial-in–serial-out output
2. Serial-in–parallel-out
3. Parallel-in–serial-out
4. Parallel-in–serial-out Serial input and serial output register: This type of
shift register accepts data serially, i.e., one bit at a
(i) Serial-in–serial-out:
time and also outputs data serially. The logic diagram
Serial data Serial data
of 4-bit serial input, serial output, shift-right, shift
output input register is shown in the following figure. With four D
flip-flops the register can store up to four bits of data.

Q3 Q2 Q1 Q0
SET SET SET SET
Serial input D Q D Q D Q D Q Serial output

Clr Q Clr Q Clr Q Clr Q

Clk

Figure 18  Serial input and serial output register

 Chapter 4  •  Sequential Circuits  |  1.69

If initially, all flip-flops are reset, then by apply-

Clk Q2 Q1 Q0
ing serial input 1101, the flip-flop states will change as
shown in below table. 0 1 0 0

Clk S.I Q3 Q2 Q1 Q0
1 0 1 0

0 1 0 0 0 0 2 0 0 1

1 0 1 0 0 0 3 1 0 0

4 0 1 0
2 1 0 1 0 0

3 1 1 0 1 0 100

4 1 1 0 1
001 010
The first data bit 1 will appear at serial output after 4
clock pulses. A ring counter with N flip-flops can count up to N states,
i.e., MOD-N counter, whereas, N-bit asynchronous counter
Application of Shift Registers can count up to 2N states. So, ring counter is uneconomi-
1. Delay line: Serial input and serial output shift register cal compared to a ripple counter, but has the advantage of
can be used to introduce delay in digital signals. requiring no decoder. Since it is entirely synchronous oper-
1 ation and requires no gates for flip-flop inputs, it has further
Delay = no.of flip-flops × = No. of
Clk frequency advantage of being very fast.
flip-flops × time period of clock pulse Twisted ring counter (Johnson counter): This counter is
2. Serial to parallel, parallel to serial converter: SIPO, obtained from a SISO shift register by connecting the comple-
PISO registers used for data conversion. ment of serial output to serial input as shown in below figure.
3. Sequence generator: A circuit, which generates a Q2 Q1 Q0
prescribed sequence of bits, with clock pulses is D
SET Q
D
SET
Q D SET Q
called as sequence generator
The minimum number of flip-flops ‘n’ required to gen-
erate a sequence of length ‘S’ bits is given by S ≤ 2n - 1
Clr Q Clr Q Clr Q
Shift register counters Clk
One of the applications of the shift register is that they
Figure 20  Twisted Ring Counter
can be arranged to work as ring counters. Ring counters
are constructed by modifying the serial-in, serial-out, shift Let initially all the FFs be reset, after each clock pulse
registers. There are two types of ring counters—basic ring the complement of last bit will appear as at MSB, and other
counter and twisted ring counter (Johnson counter). The bits shift right side by 1-bit. After 6 clock pulses the register
basic ring counter is obtained from SISO shift register by will come to initial state 000. Similarly, the 3-bit Johnson
connecting serial output to serial input. counter will oscillate between the states 101, 010.
Q2 Q1 Q0 Clk Q2 Q1 Q0
SET Q SET D SET Q
D D Q
0 0 0 0

1 1 0 0

Clr Q Clr Q Clr Q 2 1 1 0

Clk
3 1 1 1
Figure 19  Ring counter
In most instances, only a single 1 or single 0 is in the 4 0 1 1
register and is made to circulate around the register as long
as the clock pulses are applied. Consider initially first flip- 5 0 0 1
flop is set, and others are reset. After 3 clock pulses, again 6 0 0 0
we will get initial state of 100. So this is a MOD-3 counter.
1.70 | Unit 1  •  Digital Logic

1
000 Solution:  N ≤
f max ⋅ t pd

001
fmax = 10 MHz  N ≤ 8
100
tpd = 12 ns

1
N≤
10 × 106 × 12 × 10 −9
011 110
MOD counter is = 2N = 28 = 256
111 Example 6: An AB flip-flop is constructed from an SR
flip-flop as shown below. The expression for next state Q+ is
A
An n-bit Johnson counter can have 2n unique states and S Q
can count up to 2n pulses, so it is a MOD-2n counter. It is
Clk
more economical than basic ring counter but less economi-
cal than ripple counter. B R

Solution:
Solved Examples
A B Q S R Q+
Example 1:  Assume that 4-bit counter is holding the count
0101. What will be the count after 27 clock pulses? 0 0 0 1 0 1
0 0 1 1 0 1
Solution:  Total clock pulses: 27 = 16 + 11
0 1 0 0 1 0
0101 + 1011 = 0000
0 1 1 0 1 0
Example 2:  A MOD-2 counter followed by MOD-5 1 0 0 0 0 0
counter is
1 0 1 0 0 1
Solution:  A decade counter, counts 10 states (5 × 2). 1 1 0 1 1 ×

Example 3:  A 4-bit binary ripple counter uses flip-flops 1 1 1 1 1 ×

with propagation delay time of 25 msec each. The maximum
possible time required for change of state will be ∴ Q + = AB + AQ = AB + BQ
Solution:  The maximum time = 4 × 25 ms = 100 ms
Example 7:  In the circuit shown below, the output y1 and y2
Example 4:  Consider the circuit, the next state Q+ is for the given initial condition y1 = y2 = 1 and after four input
pulses will be
Y1
S
Q J Q J Q Y2
Clk

P Clk Clk
R
K Q K Q
Solution 
P Q S R Q+
0 0 0 1 0 Solution:
0 1 1 0 1 After 1st pulse y1 = 0, y2 = 1
1 0 1 0 1 After 2nd pulse y1 =0, y2 = 0
After 3rd pulse y1 =1, y2 = 0
1 1 0 1 0
After 4th pulse y1 = 1, y2 = 1
So, Q+ = P ⊕ Q Example 8:  A ripple counter is to operate at a frequency
Example 5:  A certain JK FF has tpd = 12 n sec what is the of 10 MHz. If the propagation delay time of each flip-flop
largest MOD counter, that can be constructed from these FF in the counter is 10 ns and the storbing time is 50 ns, how
and still operate up to 10 MHz? many maximum stages can the counter have?
 Chapter 4  •  Sequential Circuits  |  1.71

1 b7 b6 b5 b4 b3 b2 b1 b0
Solution:  nt pd + t s ≤
f
where, n = number of stages
D Q
tpd = propagation delay time
Clk
ts = strobing time Q1
f = frequency of operation = 10 × 10– 9n + 50 × 10– 9
1
≤ Solution:  The output of XOR gate is Z = bi + 1 ⊕ bi and this
10 × 106
output shift the register to left. Initially, Z = 0
(or) 10n + 50 ≤ 100
After 2nd clock Z = b7 ⊕ 0 = b7
(or) 10n ≤ 50
For max stages n = 50 After 2nd clock Z = b7 ⊕ b6
=5 3rd clock Z = b6 ⊕ b5
10
Example 9:  In the circuit assuming initially Q0 = Q1 = 0. 4th clock Z = b5 ⊕ b4
Then the states of Q0 and Q1 immediately after the 33rd It is a binary to gray code converter.
pulse are
Example 12: A 4-bit MOD-16 ripple counter uses JK
Q0 flip-flops. If the propagation delay of each flip-flop is 50
J0 Q0 J1 Q1 ns sec, the maximum clock frequency that can be used is
equal to
1 K0 Q1 K1 Q2
1
Solution:  Max = clock frequency = = 5 MHz
Clk 4 × 50 × 10 −9
Solution:
Example 13:  What is the state diagram for the sequential
J0 K0 J1 K1 Q0 Q1 Count circuit shown?
1 1 0 1 0 0 Initial
1 1 1 0 1 0 1st pulse
0 1 0 1 0 1 2nd
J Q
1 1 0 1 0 0 3rd X
1 1 1 0 1 0 4th Clk
0 1 0 1 0 1 5th pulse
Q1
After 4th pulse, output is same as after 1st one, so, sequence K
gets repeated. So output after 33rd pulse would be same as
after 3rd pulse. i.e., (00).
Example 10:  The frequency of the pulse at z in the network X=1
shown in figure is
w
(A) X = 0 0 1 X=0
10-bit 4-bit Parallel
Ring counter counter X=1
160 kHz
X=1
y
Mod-25 4-bit Jhonson
z
(B) X=0 0 1 X=0
x Ripple counter counter
X=0
Solution:  10-bit ring counter is a MOD-10. So, it divides
X=1
the 160 kHz input by 10. Therefore, w = 16 kHz. The 4-bit
parallel counter is a MOD-16. Thus, the frequency at x = 1 (C) X=0 0 1 X=0
kHz. The MOD-25 ripple counter produces a frequency at y
= 40 Hz (1 kHz/25 = 40 Hz). The 4-bit Johnson counter is X=1
a MOD-8. The frequency at Z = 5Hz. X=1
Example 11:  The 8-bit shift left shift register, and D flip- (D) X = 0 0 1 X=0
flop shown in the figure is synchronized with the same
clock. The D flip-flop is initially cleared. The circuit acts as X=0
1.72 | Unit 1  •  Digital Logic

Solution:  (D) X=1

State diagram of a sequential circuit will have states (output)
X=0 0 1 X=1
of all the flip-flops.
X=0
Present state Next state  Qn+1
Qn For x = 0 For x = 1
0 0 1
1 0 1

Exercises
Practice Problems 1 (A) 001 (B) 010
Directions for questions 1 to 22:  Select the correct alterna- (C) 100 (D) 101
tive from the given choices. 6. 12 MHz clock frequency is applied to a cascaded coun-
1. How many flip-flops are needed for MOD-16 ring coun- ter of MOD-3 counter, MOD-4 counter and MOD-5
ter and MOD-16 Johnson counter? counter. The lowest output frequency is
(A) 16, 16 (B) 16, 8 (A) 200 kHz (B) 1 MHz
(C) 4, 3 (D) 4, 4 (C) 3 MHz (D) 4 MHz
2. A 2-bit synchronous counter uses flip-flops with propa- 7. In the modulo-6 ripple counter shown in the figure
gation delay time of 25 n sec, each. The maximum pos- below, the output of the 2-input gate is used to clear the
sible time required for change of state will be JK flip-flops. The 2-input gate is
1
(A) 25 n sec (B) 50 n sec
(C) 75 n sec D) 100 n sec
C J0 B J1 A J2
3. For given MOD-16 counter with a 10 kHz clock input Clk
determine the frequency at Q3 C K0 B K A K

CP 1
10 kHz 2 input Reset
CP 0 MOD-16 gate

(A) a NAND gate (B) a NOR gate

(C) an OR gate (D) an AND gate
Q 3Q 2Q 1Q 0
8. In figure, J and K inputs of all the 4 flip-flops are made
high, the frequency of the signal at output y is
(A) 625 Hz (B) 10 kHz
(C) 2.5 kHz (D) 0 Hz J Q J Q J Q J Q
4. A 4-bit ripple counter and a 4-bit synchronous counter
are made using flip-flops having a propagation delay of K Clr
K Clr K Clr K Clr
10 n sec each. If the worst case delay in the ripple coun-
ter and the synchronous counter be R and S, respec- F = 10 kHz
tively, then
(A) R = 10 ns, S = 40 ns (B) R = 40 ns, S = 10 ns
(C) R = 10 ns, S = 30 ns (D) R = 30 ns, S = 10 ns
(A) 0.833 kHz (B) 1.0 kHz
5. The counter shown in the figure has initially Q2Q1Q0 =
(C) 0.91 kHz (D) 0.77 kHz
000. The status of Q2Q1Q0 after the first pulse is
9. In a number system a counter has to recycle to 0 at the
sixth count. Which of the connections indicated below
will realize this resetting? (a logic ‘0’ at the R inputs
resets the counters)
J2 Q2 J1 Q1 J0 Q0
x y z
Q Q2 Q
K2 Clk Clk Clk
Q2 K1 Q1 K0 Q0 Q Q Q

Clk Rx Ry Rz
 Chapter 4  •  Sequential Circuits  |  1.73

x (A) Qn Qn+1 A B (B)

Qn Qn+1 A B
(A)
y
Rx, Ry
0 0 0 x 0 0 1 x
y 0 1 1 x 0 1 0 x
(B) Rx, Ry, Rz
z
1 0 x 1 1 0 x 0
x 1 1 x 0 1 1 x 1
(C) y Rx, Ry, Rz
z
(C) Qn Qn+1 A B (D)
Qn Qn+1 A B
x
(D) Rx, Rz
z 0 0 x 0 0 0 x 0
0 1 x 1 0 1 1 x
10. Two D flip-flops, as shown below, are to be connected
1 0 x x 1 0 x 1
as a synchronous counter that goes through the follow-
ing Q1Q0 sequence 00 → 01 → 11 → 10 → 00. The 1 1 0 x 1 1 0 x
inputs D0 and D1 respectively should be connected as
15. A shift register that shift the bits 1 position to the right
at each clock pulse is initialized to 1100 (Q0, Q1, Q2,
D0 Q0 D1 Q1
LSB MSB Q3). The outputs are combined using an XOR gate cir-
Clk Q 0 Clk Q 1 cuit and fed to the D input. After which clock pulse,
will the initial pattern reappear at the output?
Clk

(A)
Q 0 and Q1 (B)
Q 0 and Q1
Serial input Q1 Q2 Q3
(C)
Q1 Q 0 and Q1Q0 (D)
Q1Q0 and Q1Q0 D
Q0

11. N flip-flops can be used to divide the input clock fre-

quency by
(A) N (B) 2N (A) 6th (B) 5th
(C) 2N (D) 2N-1 (C) 4th (D) 7th
12. For a shift register as shown, x = 1011, with initially FF 16. If we need to design a synchronous counter that goes
cleared, ABC will have value of after 3 clock pulses through the states 00 → 01 → 11 → 10 → 00 using D
FF, what should be the input to the FF?
A B C
D0 Q0 D1 Q1
Q1 MSB
X J Q J Q J Q Clk Q0 Clk

K Q K Q K

(A) 101 (B) 011 (A) D0 = Q0, D1 = Q1

(C) 001 (D) 111
(B) D0 = Q1 , D1 = Q0
13. If a FF is connected as shown what will be the output? (C) D0 = Q1 ⋅ Q0 , D1 = Q1Q0
(initially Q = 0)
(D) D0 = Q0 , D1 = Q1

17. Find the counter state sequence (Assume Q0 as MSB).

T Q
Clk
Q

(A) 11111 (B) 0000 D2

D0 Q0 D1 Q1
(C) 1010 (D) 0101
Q2
14. The excitation table for a FF whose output conditions
are if AB = 00, no change of state occurs
AB = 01, FF becomes 1 with next clock pulse
AB = 10, FF becomes 0 with next clock pulse (A) 4, 6, 7, 3, 1, 0, 4 (B) 4, 6, 5, 3, 1, 0, 4
AB = 11, FF changes its state (C) 4, 5, 6, 7, 0, 4, 5 (D) 4, 6, 7, 1, 0, 4
1.74 | Unit 1  •  Digital Logic

18. If the propagation delay of each FF is 50 ns, and for the (A) MOD-2 counter
AND gate to be 20 ns. What will be the fmax for MOD- (B) MOD-4 counter
32 ripple and synchronous counters? (C) MOD-3 counter
(A) 14.3 MHz, 4 MHz (B) 14.3 MHz, 5 MHz (D) MOD-2 generate 00, 10, 00
(C) 5 MHz, 14.3 MHz (D) 3.7 MHz, 14.3 MHz 21. The MOD number of asynchronous counter shown
19. For a given counter identify its behavior All J = K = 1
(1) (1) T Q J Q0 J J J J
T P
Clk
Clk P K Clr K Clr K Clr K Clr K Clr
Q

The output is taken from PQ.

(A) MOD-4 up counter
(B) MOD-2 down counter (A) 24 (B) 48
(C) MOD-4 down counter (C) 29 (D) 28
(D) MOD-2 up counter
22. For the oscillator, find the fundamental frequency if
20. A circuit using T FF is given. Identify the circuit. propagation delay of each inverter is 1000 psec.

T Q T Q
A B (A) 100 MHz (B) 10 MHz
Clk Q Clk Q
(C) 1 GHz (D) 10 GHz

Practice Problems 2 4. Figure below shown as ripple counter using positive edge
Directions for questions 1 to 30:  Select the correct alterna- triggered flip-flops. If the present state of the counters is
tive from the given choices. Q2 Q1 Q0 = 011, then its next state (Q2Q1Q0) will be
1. Match List 1 (operation) with List 2 (associated device) 1 1 1
and select the correct answer using the codes given T0 Q0 T1 Q1 T2 Q2
below:
List 1 List 2 Clk Q0 Q1 Q2
(a)  Frequency Ddivision (1) ROM
(b) Decoding (2) Multiplexer (A) 010 (B) 100
(c)  Data selection (3) Demultiplexer (C) 111 (D) 101
(d)  Code conversion (4) Counter
5. A synchronous sequential circuit is designed to detect
a bit sequence 0101 (overlapping sequence include).
(A) a–3, b–4, c–2, d–1
Every time, this sequence is detected, the circuit pro-
(B) a–3, b–4, c–1, d–2
duces output of 1. What is the minimum number of
(C) a–4, b–3, c–1, d–2
states the circuit must have?
(D) a–4, b–3, c–2, d–1
(A) 4 (B) 5
2. A MOD-5 synchronous counter is designed by using (C) 6 (D) 7
JK flip-flop, the number of counts skipped by it will be
6. What is represented by digital circuit given below?
(A) 2 (B) 3
(C) 5 (D) 0
3. A counter starts off in the 0000 state, then clock D Q
pulses are applied. Some time later the clock pulses A
are removed and the counter flip-flops read 0011. How
B
many clock pulses have occurred?
Q
(A) 3 (B) 35
(C) 51 (D) Any of these
 Chapter 4  •  Sequential Circuits  |  1.75

(A) An SR flip-flop with A = S and B = R (C) S Qn

D
(B) A JK flip-flop with A = K and B = J Clk
(C) A JK flip-flop with A = J and B = K Qn
R
(D) An SR flip-flop with A = R and B = S
7. In a ripple counter, the state whose output has a fre-
1 (D) S
quency equal to th that of clock signal applied to the D Qn
8
1 R Clk Qn
first stage, also has an output periodically equal to th
8
that of the output signal obtained form the last stage.
The counter is
(A) MOD-8 (B) MOD-6
(C) MOD-64 (D) MOD-16 12. Which of the circuit is being represented by the figure?
8. A flip-flop is popularly known as t1 t1
C
(A) Astable multivibrator •
(B) Bistable multivibrator t1 Q
G1 R G2
(C) Monostable multivibrator
(D) None of these
9. Which of the following represents the truth table for JK (A) NAND gate
flip-flop? (B) Monostable multivibrator
(C) Astable multivibrator
(A) J K Output (B)
J K Output (D) Schmitt trigger
0 0 Q0 0 0 Q0 1 3. Hold time is
(A) time for which output is held constant.
0 1 0 0 1 0
(B) time for which clock is to be held constant on
1 0 1 1 0 1
­applying input.
1 1 Q0 1 1 Q0 (C) time for which input should be maintained con-
stant after the triggering edge of clock pulse.
(D) time for which input should be maintained con-
(C) J K Output (D)
J K Output stant prior to the arrival of triggering edge of
0 0 Q0 0 0 1 clock pulse.
0 1 0 0 1 0 14. Shift registers are made up of
1 0 1 1 0 1 (A) MOS inverters (B) FF
1 1 Invalid 1 1 0 (C) Latches (D) None of these
15. Data from a satellite is received in serial form. If the
10. One disadvantage of master-slave FF is data is coming at 8 MHz rate, how long will it take to
(A) setup time becomes longer. serially load a word in 40-bit shift register?
(B) it requires input to be held constant before clock (A) 1.6 µs (B) 5 µs
­transition. (C) 6.4 µs (D) 12.8 µs
(C) unpredictable output even if input held constant.
16. A JK FF can be converted into T FF by connecting
(D) hold time becomes longer.
11. Which of the following converts D FF to SR FF? (A) Q to 0
(B) 0 to Q
(A) S (C) 0 to Q
D Qn
(D) by connecting both J and K inputs to T
R
Clk Qn 17. The flip-flop that is not affected by race around
condition
(A) T FF (B) JK FF
(B) S (C) SR FF (D) None of these
D Qn
R 18. The characteristic equation of JK FF is
Clk Qn (A) J′Q(t) + KQ′(t) (B) J′Q(t) + KQ(t)
(C) JQ′(t) + K′Q(t) (D) None of these
1.76 | Unit 1  •  Digital Logic

19. For a D.FF input, the s Q is connected. What would be 25. A divide by 50 counter can be realized by using
the output sequence? (A) 5 no. of MOD-10 counter
(A) 0000 (B) 1111 (B) 10 no. of MOD-5 counter
(C) 010101 (D) 101010 (C) One MOD-5 counter followed by one MOD-10
counter
20. In order to implement a MOD-6 synchronous counter (D) 10 no. of MOD-10 counter
we have 3 FF and a combination of 2 input gate(s).
26. The following latch is
Identify the combination circuit.
(A) One AND gate
(B) One OR gate X S Q
(C) One AND and one OR gate
Clk
(D) Two AND gates
21. Given a MOD-5 counter. The valid states for the coun- R Q
ter are (0, 1, 2, 3, 4). The propagation delay of each FF
is TF and that of AND gate is tA. The maximum rate at
which counter will operate satisfactorily (A) D latch (B) T latch
(C) JK latch (D) RS latch
2 7. Which of the following represent a 3-bit ripple counter
J0 Q0 J1 Q1 J2 Q2 using D FF?
1 K0 Q0 K1 Q1 1 K2 Q2 (A)
D1 Q1 D2 Q2 D3 Q3

Clk Clk Q1 Q2 Q3
1 1
(A) (B) (B)
tF + t A 3t F
D1 Q1 D1 Q2 D3 Q3
1 1 Clk
(C) (D) Q1 Q2 Q3
2t F + t A 3t F − t A
(C) Both (A) and (B)
22. For a NOR latch as shown up A and B are made first (D) None of these
(0, 1) and after a few seconds it is made (1, 1). The cor-
responding output (Q1, Q2) are 2 8. For the Johnson counter with initial Q2, Q1, Q0 as 101,
the frequency of the output is (Q2, Q1, Q0)
A Q1

J2 Q 2 J 1 Q1 J0 Q0

K2 Q2 K1 Q1 K0 Q0
B Q2

(A) first (1, 0) then (0, 0) fc fc

(B) first (1, 0) then (1, 0) (A) (B)
8 6
(C) first (1, 0) then (1, 1)
f fc
(D) first (1, 0) then (0, 1) (C) c (D)
2 4
23. In order to design a pulse generator to generate the
wave form using a shift register, what is the number of 29. For the given circuit the contents of register (b7 - b0)
FF required? are 10010101, what will be the register contents after
8 clock pulses?
1 0 1 1 1 0 1
b7 b6 b5 b4 b3 b2 b1 b0
(A) 3 (B) 4
(C) 5 (D) 6
D Q
24. For what minimum value of propagation delay in each
Clk
FF will a 10-bit ripple counter skip a count when it is
clocked at 5 MHz?
(A) 10 ns (B) 20 ns
(C) 25 ns (D) 15 ns
 Chapter 4  •  Sequential Circuits  |  1.77

(A) 10010101 (B) 01101010 1 0 0 1

(C) 11011111 (D) 01101011 1 0 1 1
30. A latch is to be build with A and B as input. From the 1 1 0 1
table find the expression for the next state Q+ 1 1 1 1
A B Q Q+
(A) A
0 0 0 0 (B) B
0 0 1 0 (C) A + B
0 1 0 0
(D) AB + AB
0 1 1 0

Previous Years’ Questions

1. Consider the following circuit. (D) f D D Q
Q
Q0 D1
D0 Q1
Clk
Q 1′
Q 0′
3. Consider the circuit in the diagram. The ⊕ operator
represents Ex-OR. The D flip-flops are initialized to
zeros (cleared).  [2006]
Clk

The flip-flops are positive edge triggered D FFs. Each

Q D Q D Q D Data
state is designated as a 2-bit string Q0Q1. Let the initial q2 q1 q0
Clk Clk Clk
state be 00. The state transition sequence is [2005]
Clock
00
(A) 11 01

The following data: 100110000 is supplied to the data

(B)
00 11 terminal in 9 clock cycles. After that the values of
q2q1q0 are
00 11 01 11 (A) 000 (B) 001
(C)
(C) 010 (D) 101
00
(D) 11 01 10 4. The control signal functions of a 4-bit binary counter
are given below (where X is ‘don’t care’):
Clear Clock Load Count Function
2. You are given a free running clock with a duty cycle 1 X X X Clear to 0
of 50% and a digital waveform f which changes only
0 X 0 0 No change
at the negative edge of the clock. Which one of the
0 ↑ 1 X Load input
following circuits (using clocked D flip-flops) will
delay the phase of f by 180°? [2006] 0 ↑ 0 1 Count next

The counter is connected as follows:

(A) f D D Q
Q
A4 A3 A2 A1

Clk
(B) f D Q D Q
Clk Count = 1
4-bit counter Load = 0
Clear Clock

(C) f D Q D Q Inputs
Clk
0 0 1 1
1.78 | Unit 1  •  Digital Logic

Assume that the counter and gate delays are negligi- (A) 000 (B) 001
ble. If the counter starts at 0, then it cycles through the (C) 010 (D) 011
following sequence: [2007]
(A) 0, 3, 4 (B) 0, 3, 4, 5 9. Let K = 2n. A circuit is built by giving the output of an
(C) 0, 1, 2, 3, 4 (D) 0, 1, 2, 3, 4, 5 n-bit binary counter as input to an n-to-2n-bit decoder.
This circuit is equivalent to a  [2014)
5. In the sequential circuit shown below, if the initial (A) K-bit binary up counter
value of the output Q1Q0 is 00, what are the next four (B) K-bit binary down counter
values of Q1Q0? [2010] (C) K-bit ring counter
(D) K-bit Johnson counter

10.
1 T Q T Q

Clock
J Q2 J Q1 J Q0
C C C
K Q2 K Q1 K Q0

Q0 Q1

(A) 11, 10, 01, 00 (B) 10, 11, 01, 00 The above synchronous sequential circuit built using
(C) 10, 00, 01, 11 (D) 11, 10, 00, 01 JK flip-flops is initialized with Q2Q1Q0 = 000. The
state sequence for this circuit for the next 3 clock
6. The minimum number of D flip-flops needed to
cycles is [2014]
design a MOD-258 counter is [2011]
(A) 001, 010, 011 (B) 111, 110, 101
(A) 9 (B) 8
(C) 100, 110,111 (D) 100, 011, 001
(C) 512 (D) 258
11. Consider a 4-bit Johnson counter with an initial value
Common Data for Questions 7 and 8: Consider the fol-
of 0000. The counting sequence of this counter is
lowing circuit involving three D-type flip-flops used in a
[2015]
certain type of counter configuration.
(A) 0, 1, 3, 7, 15, 14, 12, 8, 0
(B) 0, 1, 3, 5, 7, 9, 11, 13, 15, 0
(C) 0, 2, 4, 6, 8, 10, 12, 14, 0
P
D Q (D) 0, 8, 12, 14, 15, 7, 3, 1, 0
Clock Q 12. A positive edge-triggered D–flip-flop is connected
to a positive edge-triggered JK flip-flop as follows.
Q
The Q output of the D flip-flop is connected to both
D Q the J and K inputs of the JK flip-flop, while the Q
output of the JK flip-flop is connected to the input
Clock Q
of the D flip-flop. Initially, the output of the D flip-
flop is set to logic one and the output of the JK flip-
R flop is cleared. Which one of the following is the bit
D Q
sequence (including the initial state) generated at the
Clock Q Q output of the JK flip-flop when the flip-flops are
connected to a free-running common clock? Assume
that J = K = 1 is the toggle mode and J = K = 0 is the
7. If all the flip-flops were reset to 0 at power on, what state-holding mode of the JK flip-flop. Both the flip-
is the total number of distinct outputs (states) repre- flops have non-zero propagation delays.[2015]
sented by PQR generated by the counter?[2011] (A) 0110110… (B) 0100100…
(A) 3 (B) 4 (C) 011101110… (D) 011001100…
(C) 5 (D) 6
13. The minimum number of JK flip-flops required to
8. If at some instance prior to the occurrence of the clock construct a synchronous counter with the count
edge, P, Q, and R have a value 0, 1, and 0, respec- sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0, …) is ______
tively, what shall be the value of PQR after the clock [2015]
edge?[2011]
 Chapter 4  •  Sequential Circuits  |  1.79

14. We want to design a synchronous counter that counts 16. The next state table of a 2-bit saturating up-counter is
the sequence 0-1-0-2-0-3 and then repeats. The mini- given below.
mum number of J-K flip-flops required to implement
this counteris _____ . [2016] Q1 Q0 Q1+ Q0+
0 0 0 1
15. Consider a combination of T and D flip-flops con-
nected as shown below. The output of the D flip-flop 0 1 1 0
is connected to the input of the T flip-flop and the out- 1 0 1 1
put of the T flip-flop is connected to the input of the D 1 1 1 1
flip-flop.
The counter is built as a synchronous sequential cir-
cuit using T flip-flops. The expressions for T1 and
T0are  [2017]
Q1 Q0 T1 = Q1Q0,
(A) T0 = Q1 Q 0
T
D
Filp-
Filp-
Flop
Flop T1 = Q1Q0,
(B) T0 = Q1 + Q 0

T1 = Q1 + Q0,
(C) T0 = Q1 + Q 0

(D) T1 = Q1Q0, T0 = Q1 + Q0
Clock
17. Consider the sequential circuit shown in the figure,
Initially, both Q0 and Q1 are set to 1 (before the 1st where both flip-flops used are positive edge-triggered
clock cycle). The outputs [2017] D flip-flops.
(A) Q1 Q0 after the 3rd cycle are 11 and after the 4th
cycle are 00 respectively
(B) Q1 Q0 after the 3rd cycle are 11 and after the 4th in out
cycle are 01 respectively
D Q D Q
(C) Q1 Q0 after the 3rd cycle are 00 and after the 4th Clock
cycle are 11 respectively
(D) Q1 Q0 after the 3rd cycle are 01 and after the 4th
cycle are 01 respectively The number of states in the state transition diagram of
this circuit that have a transition back to the same state
on some value of “in” is ______. [2018]

Answer Keys
Exercises
Practice Problems 1
1. B 2. A 3. A 4. B 5. C 6. A 7. C 8. A 9. B 10. A
11. C 12. B 13. B 14. C 15. D 16. B 17. A 18. D 19. A 20. C
21. D 22. A

Practice Problems 2
1. D 2. B 3. D 4. B 5. A 6. C 7. C 8. B 9. A 10. B
11. C 12. B 13. C 14. B 15. B 16. D 17. C 18. C 19. C 20. D
21. C 22. A 23. D 24. B 25. C 26. A 27. A 28. C 29. C 30. A

Previous Years’ Questions

1. D 2. C 3. C 4. C 5. A 6. A 7. B 8. D 9. C 10. C
11. D 12. A 13.  3(8 = 23) 14. 3 15. B 16. B 17. 2