• If s1=0 and s0=0, then the output f is equal to w0
• If s1=0 and s0=1, then the output f is equal to w1 • If s1=1 and s0=0, then the output f is equal to w2 • If s1=1 and s0=1, then the output f is equal to w3 Graphical Symbol and Truth Table
[ Figure 4.2a-b from the textbook ]
The long-form truth table The long-form truth table
f = s 1 s0 w0 + s1 s0 w1 + s1 s0 w2 + s1 s0 w3 [ Figure 4.2c from the textbook ] Analysis of the 4-1 Multiplexer ( s1=0 and s0=0 ) 0
0 Analysis of the 4-1 Multiplexer ( s1=0 and s0=0 ) 0 1 0 1
0 1
1 0
0 0 Analysis of the 4-1 Multiplexer ( s1=0 and s0=0 ) 0 1 w0 0 1
0 0 1
1 0 0
0 0 0 Analysis of the 4-1 Multiplexer ( s1=0 and s0=0 ) 0 1 w0 0 1
0 0 1 w0
1 0 0
0 0 0 Analysis of the 4-1 Multiplexer ( s1=0 and s0=1 ) 1 0 0 0 1
1 w1 1 w1
0 0 0
1 0 0 Analysis of the 4-1 Multiplexer ( s1=1 and s0=0 ) 0 1 0 1 0
0 0 0 w2
1 w2 1
0 0 1 Analysis of the 4-1 Multiplexer ( s1=1 and s0=1 ) 1 0 0 1 0
1 0 0 w3
0 0 1
1 w3 1 Analysis of the 4-1 Multiplexer ( s1=0 and s0=0 ) 0 0
w0 Analysis of the 4-1 Multiplexer ( s1=0 and s0=1 ) 1 0
w1 Analysis of the 4-1 Multiplexer ( s1=1 and s0=0 ) 0 1
w2 Analysis of the 4-1 Multiplexer ( s1=1 and s0=1 ) 1 1
w3 Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer
s1 s0
w0 0 w1 1
0 f 1
w2 0 w3 1
[ Figure 4.3 from the textbook ]
Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer w0
w1 s1 f s0 w2
w3 That is different from the SOP form of the 4-1 multiplexer shown below, which uses less gates Analysis of the Hierarchical Implementation ( s1=0 and s0=0 ) 0 0
0 w0
[ Figure 4.3 from the textbook ]
Analysis of the Hierarchical Implementation ( s1=0 and s0=1 ) 0 1
0 w1
[ Figure 4.3 from the textbook ]
Analysis of the Hierarchical Implementation ( s1=1 and s0=0 ) 1 0
1 w2
[ Figure 4.3 from the textbook ]
Analysis of the Hierarchical Implementation ( s1=1 and s0=1 ) 1 1
1 w3
[ Figure 4.3 from the textbook ]
16-1 Multiplexer s0 s1
w0
w3
w4 s2 s3 w7
f w8
w11
w12
w15 [ Figure 4.4 from the textbook ] Multiplexers Are Special The Three Basic Logic Gates
x1 x1 x x x1 x 2 x1 + x2 x2 x2
NOT gate AND gate OR gate
[ Figure 2.8 from the textbook ]
Truth Table for NOT
x x x x 0 1 1 0 Truth Table for AND
x1 x1 x2 x2 Truth Table for OR
x1 x1 + x2 x2 Building an AND Gate with 4-to-1 Mux Building an AND Gate with 4-to-1 Mux
These two are the same.
Building an AND Gate with 4-to-1 Mux
These two are the same.
And so are these two. Building an OR Gate with 4-to-1 Mux Building an OR Gate with 4-to-1 Mux
These two are the same.
Building an OR Gate with 4-to-1 Mux
These two are the same.
And so are these two. Building a NOT Gate with 4-to-1 Mux
x x
x x 0 1 1 0 Building a NOT Gate with 4-to-1 Mux
x x
x y f 0 0 1 0 1 1 1 0 0 1 1 0
Introduce a dummy variable y.
Building a NOT Gate with 4-to-1 Mux
x x
x y f 0 0 1 0 1 1 1 0 0 1 1 0 Building a NOT Gate with 4-to-1 Mux
x x
x y f 0 0 1 0 1 1 1 0 0 1 1 0
Now set y to either 0 or 1 (both will work). Why?
Building a NOT Gate with 4-to-1 Mux
x x
x x 0 1 1 0
Two alternative solutions.
Implications
Any Boolean function can be implemented
using only 4-to-1 multiplexers! Building an AND Gate with 2-to-1 Mux Building an AND Gate with 2-to-1 Mux Building an AND Gate with 2-to-1 Mux
x2 Building an OR Gate with 2-to-1 Mux Building an OR Gate with 2-to-1 Mux Building an OR Gate with 2-to-1 Mux
x2
1 Building a NOT Gate with 2-to-1 Mux
x x
x x 0 1 1 0 Building a NOT Gate with 2-to-1 Mux
x x
x x 0 1 1 0 Implications
Any Boolean function can be implemented
using only 2-to-1 multiplexers! Synthesis of Logic Circuits Using Multiplexers 2 x 2 Crossbar switch
x1 y1 x2 y2
[ Figure 4.5a from the textbook ]
2 x 2 Crossbar switch s=0
x1 y1 x2 y2
s=1
x1 y1 x2 y2 Implementation of a 2 x 2 crossbar switch with multiplexers
x1 0 y1 1
x2 0 y2 1
[ Figure 4.5b from the textbook ]
Implementation of a 2 x 2 crossbar switch with multiplexers Implementation of a 2 x 2 crossbar switch with multiplexers
x1
y1
x2
y2 Implementation of a logic function with a 4x1 multiplexer
w2 w1 w2 f w1 0 0 0 0 0 1 1 1 1 f 1 0 1 1 1 0 0
[ Figure 4.6a from the textbook ]
Implementation of the same logic function with a 2x1 multiplexer
w1 w2 f w1 f w1 0 0 0 w2 0 0 1 1 1 w2 w2 1 0 1 f 1 1 0
(b) Modified truth table (c) Circuit
[ Figure 4.6b-c from the textbook ]
The XOR Logic Gate
[ Figure 2.11 from the textbook ]
The XOR Logic Gate
[ Figure 2.11 from the textbook ]
Implementation of the XOR Logic Gate with a 2-to-1 multiplexer and one NOT
f Implementation of the XOR Logic Gate with a 2-to-1 multiplexer and one NOT
f y Implementation of the XOR Logic Gate with a 2-to-1 multiplexer and one NOT
f y
These two circuits are equivalent
(the wires of the bottom AND gate are flipped) In other words, all four of these are equivalent!
x y f x f y
w2 w1
0 x 1 f y f 1 0 Implementation of another logic function
(w1 + w1) Shannon’s Expansion Theorem (In terms of more than one variable)
This form is suitable for implementation with a 4x1 multiplexer.
Another Example Factor and implement the following function with a 2x1 multiplexer Factor and implement the following function with a 2x1 multiplexer Factor and implement the following function with a 2x1 multiplexer
[ Figure 4.11a from the textbook ]
Factor and implement the following function with a 4x1 multiplexer Factor and implement the following function with a 4x1 multiplexer Factor and implement the following function with a 4x1 multiplexer
[ Figure 4.11b from the textbook ]
Yet Another Example Factor and implement the following function using only 2x1 multiplexers Factor and implement the following function using only 2x1 multiplexers Factor and implement the following function using only 2x1 multiplexers Factor and implement the following function using only 2x1 multiplexers w1
g f h Factor and implement the following function using only 2x1 multiplexers Factor and implement the following function using only 2x1 multiplexers Factor and implement the following function using only 2x1 multiplexers
w2 w2
0 w3 g h w3 1 Finally, we are ready to draw the circuit w2
0 w1 g w3 g f w2 h
w3 h 1 Finally, we are ready to draw the circuit w2
