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    Lenovo Thinkpad E485 - LCFC Ee485 Ee585 Nm-b531 r1.0

    Uploaded by

    Yetawa Guaviare
    This document is the schematic for an AMD Raven Ridge FP5 processor with DDR4 memory. It contains confidential information about the processor design including the processor chip, memory interfaces, display outputs, storage interfaces, and USB connections. The schematic shows the processor chip and its connections to DDR4 memory channels, PCIe interfaces, display outputs, storage interfaces, USB ports and more. It is marked as confidential and for internal use only by the company.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Lenovo Thinkpad E485 - LCFC Ee485 Ee585 Nm-b531 r1.0

    Uploaded by

    Yetawa Guaviare
    932 views65 pages
    This document is the schematic for an AMD Raven Ridge FP5 processor with DDR4 memory. It contains confidential information about the processor design including the processor chip, memory interfaces, display outputs, storage interfaces, and USB connections. The schematic shows the processor chip and its connections to DDR4 memory channels, PCIe interfaces, display outputs, storage interfaces, USB ports and more. It is marked as confidential and for internal use only by the company.

    Original Title

    Lenovo Thinkpad e485 - Lcfc Ee485 Ee585 Nm-b531 r1.0

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    © © All Rights Reserved

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    This document is the schematic for an AMD Raven Ridge FP5 processor with DDR4 memory. It contains confidential information about the processor design including the processor chip, memory interfaces, display outputs, storage interfaces, and USB connections. The schematic shows the processor chip and its connections to DDR4 memory channels, PCIe interfaces, display outputs, storage interfaces, USB ports and more. It is marked as confidential and for internal use only by the company.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    932 views65 pages

    Lenovo Thinkpad E485 - LCFC Ee485 Ee585 Nm-b531 r1.0

    Uploaded by

    Yetawa Guaviare
    This document is the schematic for an AMD Raven Ridge FP5 processor with DDR4 memory. It contains confidential information about the processor design including the processor chip, memory interfaces, display outputs, storage interfaces, and USB connections. The schematic shows the processor chip and its connections to DDR4 memory channels, PCIe interfaces, display outputs, storage interfaces, USB ports and more. It is marked as confidential and for internal use only by the company.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 65

    A B C D E

    1 1

    2
    LCFC Confidential 2

    RAVEN EX85 Rev1.0 Schematic


    AMD Raven Ridge FP5 Processor with DDR4

    3 3

    2018-04-10 Rev1.0

    4 4

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 COVER PAGE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 1 of 65
    A B C D E
    A B C D E

    AMD Raven Ridge FP5

    DDR4 Channel A DDR4-SO-DIMM X1


    PCI-Express x4 Gen3 BANK 0, 1
    1 1.2V 2400 MT/s 1
    SSD
    UP TO 16G Page 14~15
    AMD
    Page 25
    Raven Ridge DDR4-SO-DIMM X1
    DDR4 Channel B BANK 0, 1
    eDP Conn.
    DP0 x2Lane Processor 1.2V 2400 MT/s
    UP TO 16G
    Page 14~15

    Page 26
    FP5 BGA 1140P
    25mm * 35mm
    DDI PCIe x1 Gen1
    HDMI Conn. NGFF WLAN Card
    Page 28
    USB 2.0 x1
    BT Page 37
    USB2.0 x1

    Repeator USB C(DP1.2/USB3.0)


    TI
    TUSB544 Page 33
    JUSB-C Conn.
    2 2
    PD
    USB3.0 x1
    CC PD Controller
    Page 33 RTS5457 Page 31 USB Left Front
    USB2.0 x1
    Page 35

    SATA_redriver SATA Gen3 USB charger


    USB2.0 x1 (AOU) Page 35
    SATA 10pin CONN
    Page 30
    Parade PS8527C
    Page 29
    TPS2546RTER USB Left Behind
    USB 3.0 x1 Page 35
    PCIE x1 Gen1(1000M LAN)
    SUB/B CONN

    PCIE x1 Gen1(Cardreader)
    USB2.0 x1

    Page 36 USB2.0 x1
    Int. camera
    SPI ROM Page 5~12 Page 26
    3
    64M SPI BUS 3

    1.8V
    W25Q64FWSSIQ
    Page 9

    TPM HD Audio
    SLB9670VQ1P2
    Page 44
    LPC BUS
    3.3V 33MHz

    PWR Sub Board


    Button
    EC Codec SP_OUTR/L
    CX11852-11Z SPK Conn.
    IT8996E-256/DX Page 39
    Page 38
    Page 42
    RJ45 Conn. Realtek PCIe
    HP_R/L_JACK
    RTL8111GUS
    MIC_CLK/MIC_DATA

    4 4
    G-Sensor Touch Pad Int.KBD Thermal Sensor Int. MIC Conn. Ext. HP/MIC
    BAYHUB Track Point
    JCARD Conn. OZ711LV1LN PCIe BMA255 F75303M (JLCD Conn.) Combo Jack
    SD/MMC Page 50 Page 46 Page 46 Page 49 Page 26 Page 40

    Security Classification LC Future Center Secret Data Title

    JUSB4 Conn. USB2.0 Issued Date 2017/02/16 Deciphered Date 2018/06/01 BLOCK DIAGRAM
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 2 of 65
    A B C D E
    5 4 3 2 1

    Voltage Rails ( O --> Means ON , X --> Means OFF )


    SIGNAL
    +5VS STATE SLP_A# SLP_S3# SLP_S5# EC_ON SUSP#
    +3VS
    S0 HIGH HIGH HIGH ON ON
    Power Plane +1.5VS
    +3VALW +0.9VS_VDDP S3 (Suspend to RAM) LOW LOW HIGH ON OFF
    +1.2V +0.6VS
    S4 (Suspend to Disk) LOW LOW HIGH ON OFF
    D
    +5VALW +VDDCR_SOC
    D
    +VDDC_VDD S5 (Soft OFF) LOW LOW LOW ON OFF

    B9+ +1.8VALW +2.5V +VGA_CORE


    +3.3VGS
    +0.9VALW_VDDP +1.8VGS
    +1.35VGS
    State +0.95VGS

    USB2 Port USB3 Port PCIE Port SATA Port

    Port Device Port Device Port Device Port Device


    S0 O O O O
    0 USBC 0 USB Type-C GPP0 LAN 1 HDD
    1 USB3 port1 1 USB3 port1 GPP1 CardReader 2 X
    S3 O O O X 2 USB3 port2 2 GPP2 X
    3 USB2 port1 3 USB3 port2 GPP3 X
    4 USB2(BT) X GPP4 WLAN
    C
    S5 S4/AC Only O O X X 5 Int. Camera 4 X GPP5 X C
    GFX0 M.2 SSD
    GFX1 M.2 SSD
    S5 S4
    Battery only O X X X GFX2 M.2 SSD
    GFX3 M.2 SSD
    GFX4~7 X
    S5 S4
    AC & Battery X X X X SMBUS Control Table
    don't exist
    Main WLAN Thermal CP
    SOURCE VGA BATT SODIMM WiMAX Sensor APU Module Charge PD G-Sensor PMIC

    EC_SMB_CK1 IT8996E-256-DX
    X V X X X X X V X X
    EC_SMB_DA1 +3VL +3VL +3VL X
    EC_SMB_CK2 IT8996E-256-DX
    X X X X X X X X V X
    EC_SMB_DA2 +3VALW +3VALW X
    B B

    EC_SMB_CK3 IT8996E-256-DX
    EC_SMB_DA3 +3VS
    V X X X V V X X X V
    +3VS_VGA +3VS +3VS +3VS X
    EC_SMB_CK4 IT8996E-256-DX
    X X X X X X V
    EC_SMB_DA4 +3VL X X X X

    APU I2C

    APU Port Net Device

    I2C2_SCL/SDA APU_SMB0CLK/SDA DIMM1/DIMM2

    I2C3_SCL/SDA APU_SMB1_CLK/SDA TOUCHPAD


    SIC/SID EC_SMB_CK3/DA3 Conn EC
    USBC_I2C_SCL
    ZZZ2 PCB@ EC_SMB_CK2/DA2 PD
    A

    APPLY PCB PN /SDA A

    NM-A861
    DA800010W0

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 3 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    BOM Structure Table


    BOM Structure NOTE

    HDT@ For HDT AMD debug port

    LPC@ For LPC AMD debug port

    C C

    TPM@ Trusted Platform Module(TPM)


    UMA@ UMA SKU ID
    CD@ COST DOWN
    EMC_NS@ EMC Reserves
    ME@ ME Connector
    RF@ For RF function

    EMC@ For EMI function


    B B
    RF_NS@ reserves RF component
    RF_PXNS@ VGA reserves RF component

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 SMBus Block
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 4 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    UC1B
    0814: Add SSD PCIE BUS PCIE
    0814: Add SSD PCIE BUS

    PCIE0_SSD_CRX_DTX_P P8 N1 PCIE0_SSD_CTX_DRX_P CC107 2 1 0.22U_0402_10V6-K PCIE0_SSD_CTX_DRX_P_C


    25 PCIE0_SSD_CRX_DTX_P P_GFX_RXP0 P_GFX_TXP0 PCIE0_SSD_CTX_DRX_P_C 25
    PCIE0_SSD_CRX_DTX_N P9 N3 PCIE0_SSD_CTX_DRX_N CC108 2 1 0.22U_0402_10V6-K PCIE0_SSD_CTX_DRX_N_C
    25 PCIE0_SSD_CRX_DTX_N P_GFX_RXN0 P_GFX_TXN0 PCIE0_SSD_CTX_DRX_N_C 25
    PCIE1_SSD_CRX_DTX_P N6 M2 PCIE1_SSD_CTX_DRX_P CC109 2 1 0.22U_0402_10V6-K PCIE1_SSD_CTX_DRX_P_C
    25 PCIE1_SSD_CRX_DTX_P P_GFX_RXP1 P_GFX_TXP1 PCIE1_SSD_CTX_DRX_P_C 25
    PCIE1_SSD_CRX_DTX_N N7 M4 PCIE1_SSD_CTX_DRX_N CC110 2 1 0.22U_0402_10V6-K PCIE1_SSD_CTX_DRX_N_C
    25 PCIE1_SSD_CRX_DTX_N P_GFX_RXN1 P_GFX_TXN1 PCIE1_SSD_CTX_DRX_N_C 25
    PCIE2_SSD_CRX_DTX_P M8 L2 PCIE2_SSD_CTX_DRX_P CC111 2 1 0.22U_0402_10V6-K PCIE2_SSD_CTX_DRX_P_C
    25 PCIE2_SSD_CRX_DTX_P P_GFX_RXP2 P_GFX_TXP2 PCIE2_SSD_CTX_DRX_P_C 25
    PCIE2_SSD_CRX_DTX_N M9 L4 PCIE2_SSD_CTX_DRX_N CC112 2 1 0.22U_0402_10V6-K PCIE2_SSD_CTX_DRX_N_C
    25 PCIE2_SSD_CRX_DTX_N P_GFX_RXN2 P_GFX_TXN2 PCIE2_SSD_CTX_DRX_N_C 25
    PCIE3_SSD_CRX_DTX_P L6 L1 PCIE3_SSD_CTX_DRX_P CC113 2 1 0.22U_0402_10V6-K PCIE3_SSD_CTX_DRX_P_C
    25 PCIE3_SSD_CRX_DTX_P P_GFX_RXP3 P_GFX_TXP3 PCIE3_SSD_CTX_DRX_P_C 25
    PCIE3_SSD_CRX_DTX_N L7 L3 PCIE3_SSD_CTX_DRX_N CC114 2 1 0.22U_0402_10V6-K PCIE3_SSD_CTX_DRX_N_C
    25 PCIE3_SSD_CRX_DTX_N P_GFX_RXN3 P_GFX_TXN3 PCIE3_SSD_CTX_DRX_N_C 25
    K11 K2
    J11 P_GFX_RXP4 P_GFX_TXP4 K4
    P_GFX_RXN4 P_GFX_TXN4
    C H6 J2 C
    H7 P_GFX_RXP5 P_GFX_TXP5 J4
    P_GFX_RXN5 P_GFX_TXN5
    G6 H1
    F7 P_GFX_RXP6 P_GFX_TXP6 H3
    P_GFX_RXN6 P_GFX_TXN6
    G8 H2
    F8 P_GFX_RXP7 P_GFX_TXP7 H4
    P_GFX_RXN7 P_GFX_TXN7
    AC CAP Close to TX output
    PCIE1_CRX_DTX_P N10 N2 PCIE1_CTX_DRX_P CC1 1 2 0.1U_0402_10V7-K PCIE1_CTX_C_DRX_P
    LAN 36 PCIE1_CRX_DTX_P PCIE1_CRX_DTX_N P_GPP_RXP0 P_GPP_TXP0 PCIE1_CTX_DRX_N PCIE1_CTX_C_DRX_N PCIE1_CTX_C_DRX_P 36
    36 PCIE1_CRX_DTX_N N9 P3 CC2 1 2 0.1U_0402_10V7-K LAN
    P_GPP_RXN0 P_GPP_TXN0 PCIE1_CTX_C_DRX_N 36
    PCIE2_CRX_DTX_P L10 P4 PCIE2_CTX_DRX_P CC3 1 2 0.1U_0402_10V7-K PCIE2_CTX_C_DRX_P
    36 PCIE2_CRX_DTX_P PCIE2_CRX_DTX_N P_GPP_RXP1 P_GPP_TXP1 PCIE2_CTX_DRX_N PCIE2_CTX_C_DRX_N PCIE2_CTX_C_DRX_P 36
    CardReader 36 PCIE2_CRX_DTX_N L9 P2 CC4 1 2 0.1U_0402_10V7-K CardReader
    P_GPP_RXN1 P_GPP_TXN1 PCIE2_CTX_C_DRX_N 36
    L12 R3
    M11 P_GPP_RXP2 P_GPP_TXP2 R1
    P_GPP_RXN2 P_GPP_TXN2
    P12 T4
    P11 P_GPP_RXP3 P_GPP_TXP3 T2
    P_GPP_RXN3 P_GPP_TXN3

    PCIE5_CRX_DTX_P V6 W2 PCIE5_CTX_DRX_P CC5 1 2 0.1U_0402_10V7-K PCIE5_CTX_C_DRX_P


    37 PCIE5_CRX_DTX_P PCIE5_CRX_DTX_N V7 P_GPP_RXP4 P_GPP_TXP4 W4 PCIE5_CTX_DRX_N 1 2 PCIE5_CTX_C_DRX_N PCIE5_CTX_C_DRX_P 37 WLAN
    WLAN 37 PCIE5_CRX_DTX_N CC6 0.1U_0402_10V7-K
    P_GPP_RXN4 P_GPP_TXN4 PCIE5_CTX_C_DRX_N 37
    T8 W3
    T9 P_GPP_RXP5 P_GPP_TXP5 V2
    P_GPP_RXN5 P_GPP_TXN5
    SATA_CRX_DTX_P0 R6 V1 SATA_CTX_DRX_P0
    29 SATA_CRX_DTX_P0 SATA_CRX_DTX_N0 P_GPP_RXP6/SATA_RXP0 P_GPP_TXP6/SATA_TXP0 SATA_CTX_DRX_N0 SATA_CTX_DRX_P0 29 HDD
    HDD 29 SATA_CRX_DTX_N0 R7 V3
    P_GPP_RXN6/SATA_RXN0 P_GPP_TXN6/SATA_TXN0 SATA_CTX_DRX_N0 29
    R9 U2
    R10 P_GPP_RXP7/SATA_RXP1 P_GPP_TXP7/SATA_TXP1 U4
    P_GPP_RXN7/SATA_RXN1 P_GPP_TXN7/SATA_TXN1

    B B
    FP5 REV 0.90
    PART 2 OF 13
    CO-LAY RV1 TV2
    AMD-RAVEN-FP5_BGA1140

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 BLANK page
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 5 of 65
    5 4 3 2 1
    5 4 3 2 1

    DDRA_MB_DM[0..7] 15
    DDRA_MA_DM[0..7] 14
    D DDR_B_DQS#[0..7] 15 D
    DDR_A_DQS#[0..7] 14
    DDR_B_DQS[0..7] 15
    DDR_A_DQS[0..7] 14
    DDR_B_D[0..63] 15
    DDR_A_D[0..63] 14
    DDR_B_MA[0..13] 15
    DDR_A_MA[0..13] 14

    UC1A

    MEMORY A UC1I
    MEMORY B
    DDR_A_MA0 AF25
    DDR_A_MA1 AE23 MA_ADD0/MAB_CS0 J21 DDR_A_D0 DDR_B_MA0 AG30
    DDR_A_MA2 AD27 MA_ADD1/RSVD MA_DATA0/MAA_DATA8 H21 DDR_A_D1 DDR_B_MA1 AC32 MB_ADD0/MBB_CS0 B21 DDR_B_D0
    DDR_A_MA3 AE21 MA_ADD2/RSVD MA_DATA1/MAA_DATA9 F23 DDR_A_D2 DDR_B_MA2 AC30 MB_ADD1/RSVD MB_DATA0/MBA_DATA8 D21 DDR_B_D1
    DDR_A_MA4 AC24 MA_ADD3/RSVD MA_DATA2/MAA_DATA13 H23 DDR_A_D3 DDR_B_MA3 AB29 MB_ADD2/RSVD MB_DATA1/MBA_DATA9 B23 DDR_B_D2
    DDR_A_MA5 AC26 MA_ADD4/RSVD MA_DATA3/MAA_DATA12 G20 DDR_A_D4 DDR_B_MA4 AB31 MB_ADD3/RSVD MB_DATA2/MBA_DATA13 D23 DDR_B_D3
    DDR_A_MA6 AD21 MA_ADD5/RSVD MA_DATA4/MAA_DATA11 F20 DDR_A_D5 DDR_B_MA5 AA30 MB_ADD4/RSVD MB_DATA3/MBA_DATA12 A20 DDR_B_D4
    DDR_A_MA7 AC27 MA_ADD6/RSVD MA_DATA5/MAA_DATA10 J22 DDR_A_D6 DDR_B_MA6 AA29 MB_ADD5/RSVD MB_DATA4/MBA_DATA11 C20 DDR_B_D5
    DDR_A_MA8 AD22 MA_ADD7/MAA_CA3 MA_DATA6/MAA_DATA15 J23 DDR_A_D7 DDR_B_MA7 Y30 MB_ADD6/RSVD MB_DATA5/MBA_DATA10 A22 DDR_B_D6
    DDR_A_MA9 AC21 MA_ADD8/MAA_CA4 MA_DATA7/MAA_DATA14 DDR_B_MA8 AA31 MB_ADD7/MBA_CA3 MB_DATA6/MBA_DATA15 C22 DDR_B_D7
    DDR_A_MA10 AF22 MA_ADD9/MAA_CKE1 G25 DDR_A_D8 DDR_B_MA9 W29 MB_ADD8/MBA_CA4 MB_DATA7/MBA_DATA14
    DDR_A_MA11 AA24 MA_ADD10/MAB_CKE0 MA_DATA8/MAA_DATA0 F26 DDR_A_D9 DDR_B_MA10 AH29 MB_ADD9/MBA_CKE1 D24 DDR_B_D8
    DDR_A_MA12 AC23 MA_ADD11/MAA_CA5 MA_DATA9/MAA_DATA1 L24 DDR_A_D10 DDR_B_MA11 Y32 MB_ADD10/MBB_CKE0 MB_DATA8/MBA_DATA0 A25 DDR_B_D9
    DDR_A_MA13 AJ25 MA_ADD12/MAA_CA2 MA_DATA10/MAA_DATA5 L26 DDR_A_D11 DDR_B_MA12 W31 MB_ADD11/MBA_CA5 MB_DATA9/MBA_DATA1 D27 DDR_B_D10
    DDR_A_WE# AG27 MA_ADD13_BANK2/RSVD MA_DATA11/MAA_DATA4 L23 DDR_A_D12 DDR_B_MA13 AL30 MB_ADD12/MBA_CA2 MB_DATA10/MBA_DATA5 C27 DDR_B_D11
    14 DDR_A_WE# DDR_A_CAS# MA_WE_L_ADD14/MAB_CA2 MA_DATA12/MAA_DATA7 DDR_A_D13 DDR_B_WE# MB_ADD13_BANK2/RSVD MB_DATA11/MBA_DATA4 DDR_B_D12
    AG23 F25 AK30 C23
    14 DDR_A_CAS# DDR_A_RAS# MA_CAS_L_ADD15/MAB_CA4 MA_DATA13/MAA_DATA6 DDR_A_D14 15 DDR_B_WE# DDR_B_CAS# MB_WE_L_ADD14/MBB_CA2 MB_DATA12/MBA_DATA7 DDR_B_D13
    AG26 K25 AK32 B24
    14 DDR_A_RAS# MA_RAS_L_ADD16/MAB_CA3 MA_DATA14/MAA_DATA2 DDR_A_D15 15 DDR_B_CAS# DDR_B_RAS# MB_CAS_L_ADD15/MBB_CA4 MB_DATA13/MBA_DATA6 DDR_B_D14
    K27 AJ30 C26
    MA_DATA15/MAA_DATA3 15 DDR_B_RAS# MB_RAS_L_ADD16/MBB_CA3 MB_DATA14/MBA_DATA2 DDR_B_D15
    B27
    DDR_A_BA0 AF21 M25 DDR_A_D16 MB_DATA15/MBA_DATA3
    C C
    14 DDR_A_BA0 DDR_A_BA1 MA_BANK0/MAB_CS1 MA_DATA16/MAA_DATA17 DDR_A_D17 DDR_B_BA0 DDR_B_D16
    AF27 M27 AH31 C30
    14 DDR_A_BA1 MA_BANK1/MAB_CA0 MA_DATA17/MAA_DATA16 DDR_A_D18 15 DDR_B_BA0 DDR_B_BA1 MB_BANK0/MBB_CS1 MB_DATA16/MBA_DATA19 DDR_B_D17
    P27 AG32 E29
    DDR_A_BG0 MA_DATA18/MAA_DATA23 DDR_A_D19 15 DDR_B_BA1 MB_BANK1/MBB_CA0 MB_DATA17/MBA_DATA18 DDR_B_D18
    AA21 R24 H29
    14 DDR_A_BG0 DDR_A_BG1 MA_BG0/MAA_CS1 MA_DATA19/MAA_DATA20 DDR_A_D20 DDR_B_BG0 MB_DATA18/MBA_DATA22 DDR_B_D19
    AA27 L27 V31 H31
    14 DDR_A_BG1 MA_BG1/MAA_CKE0 MA_DATA20/MAA_DATA19 DDR_A_D21 15 DDR_B_BG0 DDR_B_BG1 MB_BG0/MBA_CS1 MB_DATA19/MBA_DATA23 DDR_B_D20
    M24 V29 A28
    DDR_A_ACT_N MA_DATA21/MAA_DATA18 DDR_A_D22 15 DDR_B_BG1 MB_BG1/MBA_CKE0 MB_DATA20/MBA_DATA20 DDR_B_D21
    AA22 P24 D28
    14 DDR_A_ACT_N MA_ACT_L/MAA_CS0 MA_DATA22/MAA_DATA21 DDR_A_D23 DDR_B_ACT_N MB_DATA21/MBA_DATA21 DDR_B_D22
    P25 V30 F31
    DDRA_MA_DM0 MA_DATA23/MAA_DATA22 15 DDR_B_ACT_N MB_ACT_L/MBA_CS0 MB_DATA22/MBA_DATA17 DDR_B_D23
    F21 G30
    DDRA_MA_DM1 G27 MA_DM0/MAA_DM1 M22 DDR_A_D24 DDRA_MB_DM0 C21 MB_DATA23/MBA_DATA16
    DDRA_MA_DM2 N24 MA_DM1/MAA_DM0 MA_DATA24/MAA_DATA30 N21 DDR_A_D25 DDRA_MB_DM1 C25 MB_DM0/MBA_DM1 J29 DDR_B_D24
    DDRA_MA_DM3 N23 MA_DM2/MAA_DM2 MA_DATA25/MAA_DATA31 T22 DDR_A_D26 DDRA_MB_DM2 E32 MB_DM1/MBA_DM0 MB_DATA24/MBA_DATA30 J31 DDR_B_D25
    DDRA_MA_DM4 AL24 MA_DM3/MAA_DM3 MA_DATA26/MAA_DATA26 V21 DDR_A_D27 DDRA_MB_DM3 K30 MB_DM2/MBA_DM2 MB_DATA25/MBA_DATA31 L29 DDR_B_D26
    DDRA_MA_DM5 AN27 MA_DM4/MAB_DM2 MA_DATA27/MAA_DATA27 L21 DDR_A_D28 DDRA_MB_DM4 AP30 MB_DM3/MBA_DM3 MB_DATA26/MBA_DATA26 L31 DDR_B_D27
    DDRA_MA_DM6 AW25 MA_DM5/MAB_DM3 MA_DATA28/MAA_DATA28 M20 DDR_A_D29 DDRA_MB_DM5 AW31 MB_DM4/MBB_DM2 MB_DATA27/MBA_DATA27 H30 DDR_B_D28
    DDRA_MA_DM7 AT21 MA_DM6/MAB_DM1 MA_DATA29/MAA_DATA29 R23 DDR_A_D30 DDRA_MB_DM6 BB26 MB_DM5/MBB_DM3 MB_DATA28/MBA_DATA28 H32 DDR_B_D29
    T27 MA_DM7/MAB_DM0 MA_DATA30/MAA_DATA24 T21 DDR_A_D31 DDRA_MB_DM7 BD22 MB_DM6/MBB_DM1 MB_DATA29/MBA_DATA29 L30 DDR_B_D30
    RSVD_36 MA_DATA31/MAA_DATA25 N32 MB_DM7/MBB_DM0 MB_DATA30/MBA_DATA25 L32 DDR_B_D31
    DDR_A_DQS0 F22 AL27 DDR_A_D32 RSVD_21 MB_DATA31/MBA_DATA24
    DDR_A_DQS#0 G22 MA_DQS_H0/MAA_DQS_H1 MA_DATA32/MAB_DATA16 AL25 DDR_A_D33 DDR_B_DQS0 D22 AP29 DDR_B_D32
    DDR_A_DQS1 H27 MA_DQS_L0/MAA_DQS_L1 MA_DATA33/MAB_DATA17 AP26 DDR_A_D34 DDR_B_DQS#0 B22 MB_DQS_H0/MBA_DQS_H1 MB_DATA32/MBB_DATA16 AP32 DDR_B_D33
    DDR_A_DQS#1 H26 MA_DQS_H1/MAA_DQS_H0 MA_DATA34/MAB_DATA22 AR27 DDR_A_D35 DDR_B_DQS1 D25 MB_DQS_L0/MBA_DQS_L1 MB_DATA33/MBB_DATA17 AT29 DDR_B_D34
    DDR_A_DQS2 N27 MA_DQS_L1/MAA_DQS_L0 MA_DATA35/MAB_DATA20 AK26 DDR_A_D36 DDR_B_DQS#1 B25 MB_DQS_H1/MBA_DQS_H0 MB_DATA34/MBB_DATA21 AU32 DDR_B_D35
    DDR_A_DQS#2 N26 MA_DQS_H2/MAA_DQS_H2 MA_DATA36/MAB_DATA19 AK24 DDR_A_D37 DDR_B_DQS2 F29 MB_DQS_L1/MBA_DQS_L0 MB_DATA35/MBB_DATA20 AN30 DDR_B_D36
    DDR_A_DQS3 R21 MA_DQS_L2/MAA_DQS_L2 MA_DATA37/MAB_DATA18 AM24 DDR_A_D38 DDR_B_DQS#2 F30 MB_DQS_H2/MBA_DQS_H2 MB_DATA36/MBB_DATA19 AP31 DDR_B_D37
    DDR_A_DQS#3 P21 MA_DQS_H3/MAA_DQS_H3 MA_DATA38/MAB_DATA23 AP27 DDR_A_D39 DDR_B_DQS3 K31 MB_DQS_L2/MBA_DQS_L2 MB_DATA37/MBB_DATA18 AR30 DDR_B_D38
    DDR_A_DQS4 AM26 MA_DQS_L3/MAA_DQS_L3 MA_DATA39/MAB_DATA21 DDR_B_DQS#3 K29 MB_DQS_H3/MBA_DQS_H3 MB_DATA38/MBB_DATA23 AT31 DDR_B_D39
    DDR_A_DQS#4 AM27 MA_DQS_H4/MAB_DQS_H2 AM23 DDR_A_D40 DDR_B_DQS4 AR29 MB_DQS_L3/MBA_DQS_L3 MB_DATA39/MBB_DATA22
    DDR_A_DQS5 AN24 MA_DQS_L4/MAB_DQS_L2 MA_DATA40/MAB_DATA30 AM21 DDR_A_D41 DDR_B_DQS#4 AR31 MB_DQS_H4/MBB_DQS_H2 AU29 DDR_B_D40
    DDR_A_DQS#5 AN25 MA_DQS_H5/MAB_DQS_H3 MA_DATA41/MAB_DATA31 AR25 DDR_A_D42 DDR_B_DQS5 AW30 MB_DQS_L4/MBB_DQS_L2 MB_DATA40/MBB_DATA24 AV30 DDR_B_D41
    DDR_A_DQS6 AU23 MA_DQS_L5/MAB_DQS_L3 MA_DATA42/MAB_DATA26 AU27 DDR_A_D43 DDR_B_DQS#5 AW29 MB_DQS_H5/MBB_DQS_H3 MB_DATA41/MBB_DATA25 BB30 DDR_B_D42
    DDR_A_DQS#6 AT23 MA_DQS_H6/MAB_DQS_H1 MA_DATA43/MAB_DATA27 AL22 DDR_A_D44 DDR_B_DQS6 BC25 MB_DQS_L5/MBB_DQS_L3 MB_DATA42/MBB_DATA29 BA28 DDR_B_D43
    DDR_A_DQS7 AV20 MA_DQS_L6/MAB_DQS_L1 MA_DATA44/MAB_DATA28 AL21 DDR_A_D45 DDR_B_DQS#6 BA25 MB_DQS_H6/MBB_DQS_H1 MB_DATA43/MBB_DATA28 AU30 DDR_B_D44
    DDR_A_DQS#7 AW20 MA_DQS_H7/MAB_DQS_H0 MA_DATA45/MAB_DATA29 AP24 DDR_A_D46 DDR_B_DQS7 BC22 MB_DQS_L6/MBB_DQS_L1 MB_DATA44/MBB_DATA31 AU31 DDR_B_D45
    V24 MA_DQS_L7/MAB_DQS_L0 MA_DATA46/MAB_DATA24 AP23 DDR_A_D47 DDR_B_DQS#7 BA22 MB_DQS_H7/MBB_DQS_H0 MB_DATA45/MBB_DATA30 AY32 DDR_B_D46
    V23 RSVD_41 MA_DATA47/MAB_DATA25 N31 MB_DQS_L7/MBB_DQS_L0 MB_DATA46/MBB_DATA26 AY29 DDR_B_D47
    RSVD_40 AW26 DDR_A_D48 N29 RSVD_20 MB_DATA47/MBB_DATA27
    SA_CLK_DDR0 AD25 MA_DATA48/MAB_DATA11 AV25 DDR_A_D49 RSVD_18 BA27 DDR_B_D48
    B 14 SA_CLK_DDR0 SA_CLK_DDR#0 MA_CLK_H0/MAA_CKT MA_DATA49/MAB_DATA10 DDR_A_D50 SB_CLK_DDR0 MB_DATA48/MBB_DATA11 DDR_B_D49 B
    AD24 AV22 AC31 BC27
    14 SA_CLK_DDR#0 SA_CLK_DDR1 MA_CLK_L0/MAA_CKC MA_DATA50/MAB_DATA15 DDR_A_D51 15 SB_CLK_DDR0 SB_CLK_DDR#0 MB_CLK_H0/MBA_CKT MB_DATA49/MBB_DATA10 DDR_B_D50
    AE26 AW22 AD30 BA24
    14 SA_CLK_DDR1 SA_CLK_DDR#1 MA_CLK_H1/MAB_CKT MA_DATA51/MAB_DATA14 DDR_A_D52 15 SB_CLK_DDR#0 SB_CLK_DDR1 MB_CLK_L0/MBA_CKC MB_DATA50/MBB_DATA14 DDR_B_D51
    AE27 AU26 AD29 BC24
    14 SA_CLK_DDR#1 MA_CLK_L1/MAB_CKC MA_DATA52/MAB_DATA12 DDR_A_D53 15 SB_CLK_DDR1 SB_CLK_DDR#1 MB_CLK_H1/MBB_CKT MB_DATA51/MBB_DATA15 DDR_B_D52
    AV27 AD31 BD28
    MA_DATA53/MAB_DATA13 DDR_A_D54 15 SB_CLK_DDR#1 MB_CLK_L1/MBB_CKC MB_DATA52/MBB_DATA12 DDR_B_D53
    AW23 AE30 BB27
    MA_DATA54/MAB_DATA9 AT22 DDR_A_D55 AE32 RSVD_89 MB_DATA53/MBB_DATA13 BB25 DDR_B_D54
    MA_DATA55/MAB_DATA8 AF29 RSVD_90 MB_DATA54/MBB_DATA9 BD25 DDR_B_D55
    AW21 DDR_A_D56 AF31 RSVD_91 MB_DATA55/MBB_DATA8
    DDR_A_CS0# AG21 MA_DATA56/MAB_DATA5 AU21 DDR_A_D57 RSVD_92 BC23 DDR_B_D56
    14 DDR_A_CS0# DDR_A_CS1# MA_CS_L0/MAB_CKE1 MA_DATA57/MAB_DATA6 DDR_A_D58 DDR_B_CS0# MB_DATA56/MBB_DATA6 DDR_B_D57
    AJ27 AP21 AJ31 BB22
    14 DDR_A_CS1# MA_CS_L1/RSVD MA_DATA58/MAB_DATA2 DDR_A_D59 15 DDR_B_CS0# DDR_B_CS1# MB_CS_L0/MBB_CKE1 MB_DATA57/MBB_DATA7 DDR_B_D58
    AN20 AM31 BC21
    MA_DATA59/MAB_DATA3 DDR_A_D60 15 DDR_B_CS1# MB_CS_L1/RSVD MB_DATA58/MBB_DATA2 DDR_B_D59
    AR22 AJ29 BD20
    MA_DATA60/MAB_DATA7 AN22 DDR_A_D61 AM29 RSVD_95 MB_DATA59/MBB_DATA3 BB23 DDR_B_D60
    MA_DATA61/MAB_DATA4 AT20 DDR_A_D62 RSVD_97 MB_DATA60/MBB_DATA4 BA23 DDR_B_D61
    MA_DATA62/MAB_DATA1 AR20 DDR_A_D63 MB_DATA61/MBB_DATA5 BB21 DDR_B_D62
    DDR_A_CKE0 Y23 MA_DATA63/MAB_DATA0 MB_DATA62/MBB_DATA1 BA21 DDR_B_D63
    14 DDR_A_CKE0 DDR_A_CKE1 MA_CKE0/MAA_CA0 DDR_B_CKE0 MB_DATA63/MBB_DATA0
    Y26 T24 U29
    14 DDR_A_CKE1 MA_CKE1/MAA_CA1 RSVD_34 15 DDR_B_CKE0 DDR_B_CKE1 MB_CKE0/MBA_CA0
    T25 T30 M31
    RSVD_35 15 DDR_B_CKE1 MB_CKE1/MBA_CA1 RSVD_17
    W25 V32 N30
    RSVD_51 W27 U31 RSVD_93 RSVD_19 P31
    DDR_A_ODT0 AG24 RSVD_52 R26 RSVD_94 RSVD_26 R32
    14 DDR_A_ODT0 DDR_A_ODT1 MA_ODT0/MAB_CA5 RSVD_27 DDR_B_ODT0 RSVD_29
    AJ22 R27 AL31 M30
    14 DDR_A_ODT1 MA_ODT1/RSVD RSVD_28 15 DDR_B_ODT0 DDR_B_ODT1 MB_ODT0/MBB_CA5 RSVD_16
    V27 AM32 M29
    RSVD_43 15 DDR_B_ODT1 MB_ODT1/RSVD RSVD_15
    V26 AL29 P30
    RSVD_42 AM30 RSVD_96 RSVD_25 P29
    DDR_A_ALERT_N AA25 RSVD_98 RSVD_24
    14 DDR_A_ALERT_N MA_ALERT_L/MA_TEST DDR_A_PARITY DDR_B_ALERT_N
    AF24 DDR_A_PARITY 14 15 DDR_B_ALERT_N W30
    DDR_A_EVENT# AE24 MA_PAROUT/MAB_CA1 MB_ALERT_L/MB_TEST AG31 DDR_B_PARITY
    14 DDR_A_EVENT# DDR4_A_DRAMRST# Y24 MA_EVENT_L DDR_B_EVENT# MB_PAROUT/MBB_CA1 DDR_B_PARITY 15
    14 DDR4_A_DRAMRST# AG29
    MA_RESET_L 15 DDR_B_EVENT# DDR4_B_DRAMRST# MB_EVENT_L
    FP5 REV 0.90 T31
    15 DDR4_B_DRAMRST# MB_RESET_L
    PART 1 OF 13 FP5 REV 0.90
    PART 9 OF 13

    AMD-RAVEN-FP5_BGA1140

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 Switch
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 6 of 65

    5 4 3 2 1
    5 4 3 2 1

    TPC19 1 Test_Point_12MIL PM_SLP_S3#

    0814: Follow 720S &DG add 10U Cap TPC20 1 Test_Point_12MIL PM_SLP_S5#
    +1.8VALW
    TPC21 1 Test_Point_12MIL RSMRST#

    1
    PLT_RST#_R_G 25 TPC22 1 Test_Point_12MIL PBTN_OUT#
    RC129 1 @ 2 0_0402_5% RC28
    22K_0402_5%
    1

    2
    DC1 CC115 +3VALW
    RB751V-40_SOD323-2 10U_0603_25V6-K
    1 2 RSMRST# 2 +3VALW
    42 EC_RSMRST#

    1
    SCS00008K00 1 RC154 +1.8VS
    1 @
    D @ 10K_0402_5% D
    CC103 CC105
    0.1U_0402_10V7-K 0.1U_0402_10V7-K @

    2
    2 2

    5
    RC157 UC7 RPC12
    1 2 PLT_RST#_R_G 1
    Implement IO connect side PSA_I2C_SDA 1 4

    P
    +3VALW B 4 PLT_RST# 36,37,42 PSA_I2C_SCL 2 3
    2 Y
    2

    G
    33_0402_5% A 4.7K_0404_4P2R_5%
    @ CC106 MC74VHC1G09DFT2G_SC70-5 @

    3
    RC133 2 1 10K_0402_5% AC_PRESENT 150P_0201_25V9-J
    1 @

    RC155 1 @ 2 0_0402_5%
    UC1D

    ACPI/AUDIO/I2C/GPIO/MISC

    +3VALW AW12
    EGPIO41/SFI_S5_EGPIO41 AU12 APU_SMB0CLK RC32 1 @ 2 0_0402_5% APU_SMB_CK0
    AGPIO39/SFI_S5_AGPIO39 APU_SMB_CK0 9,14,15
    Strap
    PLT_RST#_R BD5
    1 TPC24 PCIE_RST1_L/EGPIO27 BB6 PCIE_RST0_L/EGPIO26 AR13 EGPIO151 APU_SMB0DATA RC33 1 @ 2 0_0402_5% APU_SMB_DA0 DIMM1, DIMM2
    PCIE_RST1_L/EGPIO27 I2C0_SCL/SFI0_I2C_SCL/EGPIO151 APU_SMB_DA0 9,14,15
    RPC5 Test_Point_20MIL RSMRST# AT16 AT13 EGPIO152
    SYS_RESET# RSMRST_L I2C0_SDA/SFI0_I2C_SDA/EGPIO152 APU_SMB1CLK RC149 @ 0_0402_5% APU_SMB1_CLK
    1 8 1 2
    PBTN_OUT# PBTN_OUT# APU_SMB1_CLK 46
    2 7 AR15 AN8 EGPIO149
    3
    4
    6
    5
    EC_WAKE#
    BATLOW#
    42
    42 PBTN_OUT#
    PWR_GOOD
    PWR_GOOD
    SYS_RESET#
    AV6
    AP10
    PWR_BTN_L/AGPIO0
    PWR_GOOD
    I2C1_SCL/SFI1_I2C_SCL/EGPIO149
    I2C1_SDA/SFI1_I2C_SDA/EGPIO150
    AN9 EGPIO150 APU_SMB1DATA 1
    RC150
    2
    0_0402_5% APU_SMB1_DATA
    APU_SMB1_DATA 46
    TOUCHPAD
    EC_WAKE# AV11 SYS_RESET_L/AGPIO1 BC20 APU_SMB0CLK @
    42 EC_WAKE# WAKE_L/AGPIO2 I2C2_SCL/EGPIO113/SCL0 APU_SMB0DATA
    10K_0804_8P4R_5% BA20
    PM_SLP_S3# AV13 I2C2_SDA/EGPIO114/SDA0
    42 PM_SLP_S3# PM_SLP_S5# AT14 SLP_S3_L AM9 APU_SMB1CLK
    9,42 PM_SLP_S5# SLP_S5_L I2C3_SCL/AGPIO19/SCL1 AM10 APU_SMB1DATA
    PWR_GOOD BOARD_ID1 AR8 I2C3_SDA/AGPIO20/SDA1
    PLT_RST#_R_G S0A3_GPIO/AGPIO10 L16 PSA_I2C_SCL
    AC_PRESENT AT10 PSA_I2C_SCL M16 PSA_I2C_SDA
    42 AC_PRESENT
    1

    BATLOW# AN6 AC_PRES/AGPIO23 PSA_I2C_SDA


    1

    RC109 LLB_L/AGPIO12 RPC6 +3VS


    C RC146 100K_0402_5% AT15 C
    AW8 AGPIO3 AW10 APU_SMB1_CLK 1 8
    10K_0402_5% EGPIO42 AGPIO4/SATAE_IFDET APU_SMB1_DATA 2 7
    2

    AP9 HDD_DEVSLP APU_SMB0CLK 3 6


    2

    AGPIO5/DEVSLP0 AU10 SSD_DEVSLP HDD_DEVSLP 30 APU_SMB0DATA 4 5


    AGPIO6/DEVSLP1 AV15 SSD_DEVSLP 25
    SATA_ACT_L/AGPIO130 2.2K_0804_8P4R_5%
    AU7
    AGPIO9 AU6 APU_SSD_RST#
    AGPIO40 APU_SSD_RST# 25
    RC134 AW13
    1 2 33_0402_5% AZ_BITCLK AGPIO69 AW15 EC_SMI#
    38 APU_AZ_BITCLK AZ_BITCLK AR2 AGPIO86 EC_SMI# 42
    EMC@ AZ_BITCLK/TDM_BCLK_MIC
    APU_AZ_SDIN0 AP7
    1 38 APU_AZ_SDIN0 AZ_SDIN0/CODEC_GPI
    CC14 APU_AZ_SDIN1 AP1 AU14 TPC31 1 Test_Point_20MIL
    10P_0402_50V8-J EMC@ APU_AZ_SDIN2 AP4 AZ_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK INTRUDER_ALERT AU16 APU_SPKR +3VS
    AZ_RST# AZ_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK SPKR/AGPIO91 APU_SPKR 39 RC9 Implement KB connect side
    AP3 AV8
    2 AZ_SYNC AR4 AZ_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC BLINK/AGPIO11
    RPC9
    AZ_SDOUT AR3 AZ_SYNC/TDM_FRM_MIC AW16 NUMLOCK_LED# NUMLOCK_LED# 1 4
    AZ_SDOUT/TDM_FRM_PLAYBACK GENINT1_L/AGPIO89 F1_LED# NUMLOCK_LED# 46 F1_LED#
    BD15 2 3
    AT2 GENINT2_L/AGPIO90 F1_LED# 46
    AT4 SW_MCLK/TDM_BCLK_BT 10K_0404_4P2R_5%
    AR6 SW_DATA0/TDM_DOUT_BT AR18 RF_OFF#
    AGPIO7/FCH_ACP_I2S_SDIN_BT FANIN0/AGPIO84 RF_OFF# 37 @
    BOARD_ID0 AP6 AT18 BT_ON
    RPC7 AGPIO8/FCH_ACP_I2S_LRCLK_BT FANOUT0/AGPIO85 BT_ON 37
    FP5 REV 0.90
    1 8 PART 4 OF 13
    2 7 AZ_RST#
    38 APU_AZ_RST# 3 6 AZ_SYNC
    38 APU_AZ_SYNC AZ_SDOUT AMD-RAVEN-FP5_BGA1140 APU_SSD_RST#
    4 5 RC1672 1 10K_0402_5%
    38 APU_AZ_SDOUT
    33_0804_8P4R_5%
    EC_SMI# RC1532 12.2K_0402_5%
    EMC@

    @
    RF_OFF# RC36 2 1 10K_0402_5%

    RC37 @
    BT_ON 2 1 10K_0402_5%
    @
    10K_0402_5% 2 1 RC117 PCIE_RST1_L/EGPIO27
    B B
    SW Can't pull down change to stuff 4/25
    RPC10
    1 4 APU_AZ_SDIN2
    2 3 APU_AZ_SDIN1
    RC31 2 1 10K_0402_5% EGPIO149
    10K_0404_4P2R_5%
    @
    +3VS
    TP SMB port
    RC110 2 1 10K_0402_5% EGPIO150

    Vgs(th) Max >=2.0V RC111 2 1 10K_0402_5% EGPIO151


    2
    G

    +3VALW
    RC113 2 1 10K_0402_5% EGPIO152

    APU_SMB1CLK 6 1 APU_SMB1_CLK
    S
    D

    QC9A
    2N7002KDWH_SOT363-6
    1

    TOUCHPAD
    G

    @ RC41 RC42 @
    2K_0402_1% 2K_0402_1%
    2

    APU_SMB1DATA APU_SMB1_DATA
    2

    3 4
    S
    D

    BOARD_ID0
    QC9B +3VALW
    BOARD_ID1 2N7002KDWH_SOT363-6

    RC151
    APU_SMB1CLK 2.2K_0402_5% 2 1
    1

    A A
    1

    RC43 RC44 @ RC152


    APU_SMB1DATA 2.2K_0402_5% 2 1
    2K_0402_1% 2K_0402_1%
    2
    2

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 Switch
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 7 of 65
    5 4 3 2 1
    1 2 3 4 5

    UC1C +3VS
    DISPLAY/SVI2/JTAG/TEST
    CPU_EDP_TX0+ C8 G15 APU_ENBKL_R
    26 CPU_EDP_TX0+ DP0_TXP0 DP_BLON

    1
    CPU_EDP_TX0- A8 F15 APU_ENVDD
    DP0-EDP 26 CPU_EDP_TX0- DP0_TXN0 DP_DIGON L14 APU_EDP_PWM_R APU_ENVDD 26 +3VALW RC1
    CPU_EDP_TX1+ D8 DP_VARY_BL 4.7K_0402_5%
    26 CPU_EDP_TX1+ CPU_EDP_TX1- DP0_TXP1 CPU_EDP_AUX
    B8 D9
    26 CPU_EDP_TX1- DP0_TXN1 DP0_AUXP CPU_EDP_AUX 26

    2
    B9 CPU_EDP_AUX#
    CPU_EDP_AUX# 26 eDP

    2
    B6 DP0_AUXN C10 CPU_EDP_HPD RC136
    DP0_TXP2 DP0_HPD CPU_EDP_HPD 26 @
    C7 10K_0402_5% ENBKL ENBKL 42
    DP0_TXN2 G11 HDMI_CLK
    DP1_AUXP HDMI_CLK 28

    1
    C6 F11 HDMI_DAT
    HDMI_DAT 28 HDMI

    1
    D6 DP0_TXP3 DP1_AUXN G13 HDMI_HPD RC148
    DP0_TXN3 DP1_HPD HDMI_HPD 28 @

    3
    A D 100K_0402_5% A
    H_HDMI_TX2+ E6 J12 5 QC2B
    28 H_HDMI_TX2+ H_HDMI_TX2- DP1_TXP0 DP2_AUXP
    28 H_HDMI_TX2- D5 H12 G DMN5L06DWK-7 2N SOT363-6

    2
    DP1_TXN0 DP2_AUXN K13
    H_HDMI_TX1+ E1 DP2_HPD S
    HDMI 28 H_HDMI_TX1+ Typec0

    4
    DP1_TXP1

    6
    H_HDMI_TX1- C1 J10 APU_DP3_AUXP D
    28 H_HDMI_TX1- DP1_TXN1 DP3_AUXP APU_DP3_AUXN APU_DP3_AUXP 33 APU_ENBKL_R @
    H10 APU_DP3_AUXN 33 2 QC2A
    H_HDMI_TX0+ F3 DP3_AUXN K8 DDIP3_HPD G
    28 H_HDMI_TX0+ DP1_TXP2 DP3_HPD DDIP3_HPD 31,33 DMN5L06DWK-7 2N SOT363-6
    H_HDMI_TX0- E4
    28 H_HDMI_TX0- DP1_TXN2

    1
    K15 DP_STEREOSYNC S

    1
    H_HDMI_TXC+ F4 DP_STEREOSYNC 100K_0402_5% RC5
    28 H_HDMI_TXC+ H_HDMI_TXC- DP1_TXP3 APU_TEST4 @
    28 H_HDMI_TXC- F2 F14 TPC1 1 Test_Point_20MIL
    DP1_TXN3 RSVD_4 F12 APU_TEST3 TPC2 1 Test_Point_20MIL @
    RSVD_3

    2
    F10 APU_TEST2 TPC46 1 Test_Point_20MIL @
    RSVD_2 RC3 1 2 0_0402_5%

    +1.8VS

    RC6 1 2 300_0402_5% APU_RESET#


    0814:Change EDP lever shift follow 720S dual MOS solution
    1 2 APU_PWROK AP14 TEST4 TPC3 1 Test_Point_20MIL +3VS
    RC8 300_0402_5% TEST4 AN14 TEST5 TPC4 1 Test_Point_20MIL
    TEST5

    1
    F13 TEST6 TPC5 1 Test_Point_20MIL
    TEST6 +3VALW RC7
    G18 APU_TEST14 TPC6 1 Test_Point_20MIL 4.7K_0402_5%
    TEST14 H19 APU_TEST15 TPC7 1 Test_Point_20MIL
    TEST15

    2
    F18 APU_TEST16 TPC8 1 Test_Point_20MIL

    2
    TEST16 F19 APU_TEST17 TPC9 1 Test_Point_20MIL RC9
    TEST17
    10K_0402_5% PANEL_BKLT_CTRL 26
    W24 APU_TEST31 TPC10 1 Test_Point_20MIL
    TEST31/RSVD

    1
    B B

    3
    APU_RESET# APU_PWROK AR11 APU_TEST41 TPC11 1 Test_Point_20MIL D
    TEST41 5 QC8B
    APU_TDI_H HDT@ 1 RC158 2 0_0402_5%APU_TDI AU2 AJ21 APU_TEST470 TPC12 1 Test_Point_20MIL G DMN5L06DWK-7 2N SOT363-6
    APU_TDO_H HDT@ 1 RC159 2 0_0402_5%APU_TDO AU4 TDI TEST470 AK21 APU_TEST471 TPC13 1 Test_Point_20MIL
    1 1 TDO TEST471
    APU_TCK_H HDT@ 1 RC160 20_0402_5% APU_TCK AU1 S

    4
    TCK

    6
    CC7 @ CC8 APU_TMS_H HDT@ 1 RC161 20_0402_5% APU_TMS AU3 D
    @ TMS
    56P_0402_50V8-J 56P_0402_50V8-J APU_TRST#_H 1 @ 2 0_0402_5% APU_TRST# AV3 APU_EDP_PWM_R 2 QC8A
    2 2 RC162 APU_DBREQ# AW3 TRST_L G
    DBREQ_L DMN5L06DWK-7 2N SOT363-6

    1
    S

    1
    APU_RESET#_H HDT@ 1 RC163 2 0_0402_5% APU_RESET# AW4 V4 P_ZVDDP 196_0402_0.5% 1 2 RC12 100K_0402_5% RC11
    APU_PWROK RESET_L SMU_ZVDD +0.9VS_VDDP
    AW2
    59 APU_PWROK PWROK
    APU_PWROK_H APU_SIC RC13 @ 10K_0402_5% RC135
    HDT@ 1 RC164 2 0_0402_5% H14 AW11 CORETYPE 1 2 +3VALW_APU

    2
    APU_SID J14 SIC CORETYPE 1 1 2
    TPC14 Test_Point_20MIL TPC15 Test_Point_20MIL
    APU_ALERT# J15 SID 1 TPC16
    APU_THERMTRIP# AP16 ALERT_L AN11 VDDP_SENSE Test_Point_20MIL

    1
    42 APU_THERMTRIP# H_PROCHOT# THERMTRIP_L VDDP_SENSE 0_0402_5%
    42 H_PROCHOT#
    RC14 1 @ 2 APU_PROCHOT# L19 J19 VDDCR_SOC_VCC_SENSE VDDCR_SOC_VCC_SENSE 59
    0_0402_5% PROCHOT_L VDDCR_SOC_SENSE K18 VDDCR_VCC_SENSE @
    VDDCR_SENSE VDDCR_VCC_SENSE 59
    APU_SVC RC15 1 @ 2 0_0402_5% SVC_RA
    F16 1 TPC17
    59 APU_SVC SVC0 Test_Point_20MIL
    APU_SVD RC16 1 @ 2 0_0402_5% SVD_RA
    H16 J18 VDDCR_VSS_SENSE
    59 APU_SVD APU_SVT SVT_RA SVD0 VSS_SENSE_A VSS_SENSE_B VDDCR_VSS_SENSE 59
    RC17 1 @ 2 0_0402_5% J16 FP5 REV 0.90 AM11 1
    59 APU_SVT SVT0 VSS_SENSE_B Test_Point_20MIL +1.8VS
    PART 3 OF 13 TPC18

    AMD-RAVEN-FP5_BGA1140 RPC3
    APU_TEST14 1 8
    1 APU_TEST16 2 7
    1 CC10 APU_TEST15 3 6
    CC9 APU_TEST17 4 5
    1000P_0402_50V7-K +1.8VALW
    2
    2 @ JHDT1 10K_0804_8P4R_5%
    1 2 APU_TCK_H
    1000P_0402_50V7-K 1 2 @
    C C
    @ 3 4 APU_TMS_H
    3 4
    HDT@
    5 6 RC20 1 2 APU_TDI_H
    +1.8VALW 5 6 +1.8VALW +1.8VS
    RPC1 0_0402_5% For AMD suggest HDMI driver check HDMI port enable ,change DP_STEREOSYNC from
    7 8 APU_TDO_H 1k pull down to 1K pull high
    APU_TDI_H RC21 7 8
    1 8

    1
    2 7 APU_TMS_H APU_TRST#_H 1 2 9 10 APU_PWROK_BUF
    3 6 APU_TCK_H 33_0402_5% 9 10 RC22
    APU_TRST#_H HDT@ APU_RST#_BUF
    4 5 1 11 12 HDT@ 1K_0402_1%

    2
    CC11 11 12
    1K_0804_8P4R_5% HDT@ Cap close to JHDT.9 13 14
    RC24

    2
    0.01U_0201_25V7-K 13 14 RC23
    HDT@ 2 15 16 1 2 APU_DBREQ# 1K_0402_1%
    15 16 33_0402_5%

    1
    17 18 Cap close to JHDT.16 DP_STEREOSYNC
    17 18 HDT@ 1
    CC12
    RPC2 19 20
    +3VS 1 8 19 20 HDT@ 0.01U_0201_25V7-K
    2 7 2
    3 6

    2
    1K_0402_5% 1 RC127 2 APU_PROCHOT# 4 5 ME@
    SAMTE_ASP-136446-07-B
    @ RC25
    1K_0402_5% 1 RC128 2 APU_ALERT# 10K_0804_8P4R_5% 1K_0402_1%

    1
    HDT@
    +3VS
    AMD check can change R value to 2.2K
    +1.8VALW +1.8VALW
    RPC11 RC26
    1 4 APU_SIC
    2 3 APU_SID APU_SIC 1 @ 2 0_0402_5% EC_SMB_CK3
    1 EC_SMB_CK3 42,50
    2

    2.2K_0404_4P2R_5% CC100 HDT@ RC107 RC108


    D 0.1U_0201_6.3V6-K D
    HDT@ 300_0402_5% 300_0402_5%
    2
    HDT@ Check again 3/30 RC27
    1K_0402_1% RC126
    1

    1 2 APU_THERMTRIP# UC6 APU_SID 1 @ 2 0_0402_5% EC_SMB_DA3


    EC_SMB_DA3 42,50
    APU_PWROK_H 3 4 APU_PWROK_BUF
    2A 2Y
    2 5
    GND VCC
    APU_RESET#_H 1 6 APU_RST#_BUF Security Classification LC Future Center Secret Data Title
    1A 1Y
    HDT@ SN74LVC2G07YZPR_WCSP6 Issued Date 2017/02/16 Deciphered Date 2018/06/01 Switch
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 8 of 65
    1 2 3 4 5
    5 4 3 2 1

    UC1E
    +3VS
    CLK/LPC/EMMC/SD/SPI/eSPI/UART
    EGPIO120 Reserves for SSD detect 8/4

    If no use need SW internal PU PD CLKREQ_PCIE1_LAN# AV18


    36 CLKREQ_PCIE1_LAN# CLKREQ_PCIE2_CR# AN19 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92
    36 CLKREQ_PCIE2_CR# AP19 CLK_REQ1_L/AGPIO115
    FN_LED# RC1702 1 10K_0402_5%
    D_J_CTL AT19 CLK_REQ2_L/AGPIO116
    26 D_J_CTL CLKREQ_PCIE3_WLAN# AU19 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131
    37 CLKREQ_PCIE3_WLAN# SSD_SATA_PCIE_DET# CLK_REQ4_L/OSCIN/EGPIO132 @
    AW18 @
    25 SSD_SATA_PCIE_DET# CLKREQ_PCIE7_SSD# AW19 CLK_REQ5_L/EGPIO120 RC169 1 2 0_0402_5%
    25 CLKREQ_PCIE7_SSD# LPCPD#
    CLK_REQ6_L/EGPIO121
    BD13
    +3VS EGPIO70/SD_CLK BB14 AGPIO21 RC168 1 @ 2 0_0402_5% FN_LED#
    CLK_PCIE_LAN RC48 1 @ 2 0_0402_5% CLK_PCIE_LAN_R AK1 LPC_PD_L/SD_CMD/AGPIO21 BB12 LPC_AD0_R 2 10_0402_5% FN_LED#
    LPC_AD0 46
    RC45 1 LPC_AD0 42
    RPC8 36 CLK_PCIE_LAN CLK_PCIE_LAN# RC46 1 @ 2 0_0402_5% CLK_PCIE_LAN#_R AK3 GPP_CLK0P LAD0/SD_DATA0/EGPIO104 BC11 LPC_AD1_R RC49 1 2 10_0402_5% LPC_AD1 CLK_PCI_EC
    36 CLK_PCIE_LAN# GPP_CLK0N LAD1/SD_DATA1/EGPIO105 LPC_AD2_R LPC_AD2 LPC_AD1 42 1
    BB15 RC50 1 2 10_0402_5%
    CLKREQ_PCIE1_LAN# CLK_PCIE_CR CLK_PCIE_CR_R LAD2/SD_DATA2/EGPIO106 LPC_AD3_R LPC_AD3 LPC_AD2 42
    1 8 RC47 1 @ 2 0_0402_5% AM2 BC15 RC51 1 2 10_0402_5% CC102
    2 7 CLKREQ_PCIE2_CR# 36 CLK_PCIE_CR CLK_PCIE_CR# RC52 1 @ 2 0_0402_5% CLK_PCIE_CR_R# AM4 GPP_CLK1P LAD3/SD_DATA3/EGPIO107 BA15 LPC_CLK0 RC53 1 2 CLK_PCI_EC LPC_AD3 42 Close to APU EMC_NS@
    10P_0402_50V8-J
    D 3 6 CLKREQ_PCIE3_WLAN# 36 CLK_PCIE_CR# GPP_CLK1N LPCCLK0/EGPIO74 BC13 LPC_CLKRUN# CLK_PCI_EC 42 2 D
    EMC@ 22_0402_5%
    4 5 CLKREQ_PCIE7_SSD# AM1 LPC_CLKRUN_L/AGPIO88 BB13 LPC_CLK1
    AM3 GPP_CLK2P LPCCLK1/EGPIO75 BC12 SERIRQ
    GPP_CLK2N SERIRQ/AGPIO87 LPC_FRAME# SERIRQ 42
    10K_0804_8P4R_5% BA12
    AL2 LFRAME_L/EGPIO109 LPC_FRAME# 42
    AL4 GPP_CLK3P BD11 LPC_RST#_R RC561 2 33_0402_5% LPC_RST#
    Delete CLKREQ_PCIE_VGA# GPP_CLK3N LPC_RST_L/SD_WP_L/AGPIO32 BA11 LPC_RST# 42
    change to RPC8 PIN4,PIN5 for CLKREQ_PCIE7_SSD 8/4 CLK_PCIE_WLAN RC54 1 @ 2 0_0402_5% CLK_PCIE_WLAN_R AN2 AGPIO68/SD_CD BA13 EC_SCI#
    37 CLK_PCIE_WLAN CLK_PCIE_WLAN# CLK_PCIE_WLAN#_R AN4 GPP_CLK4P LPC_PME_L/SD_PWR_CTRL/AGPIO22 EC_SCI# 42
    RC55 1 @ 2 0_0402_5%
    37 CLK_PCIE_WLAN# GPP_CLK4N
    AN3
    AP2 GPP_CLK5P BC8
    GPP_CLK5N SPI_ROM_REQ/EGPIO67 BB8
    CLK_PCIE_SSD RC58 1 @ 2 0_0402_5% CLK_PCIE_SSD_R AJ2 SPI_ROM_GNT/AGPIO76
    25 CLK_PCIE_SSD CLK_PCIE_SSD# CLK_PCIE_SSD#_R GPP_CLK6P
    RC59 1 @ 2 0_0402_5% AJ4 BB11 KBRST#
    25 CLK_PCIE_SSD# GPP_CLK6N ESPI_RESET_L/KBRST_L/AGPIO129 BC6 KBRST# 42
    LDRQ0#
    Test_Point_20MIL 1 TPC37X48M_OSC AJ3 ESPI_ALERT_L/LDRQ0_L/EGPIO108
    X48M_OSC BB7SPI_CLK_C RC60 1 SPI_CLK
    2 10_0402_5%
    SPI_CLK/ESPI_CLK SPI_SO SPI_CLK 44
    BA9
    X48M_X1 SPI_DI/ESPI_DAT1 SPI_SI SPI_SO 44
    BB3 BB10
    X48M_X1 SPI_DO/ESPI_DAT0 SPI_IO2 SPI_SI 44
    BA10
    SPI_WP_L/ESPI_DAT2 SPI_IO3 RC62
    BC10 LPCPD# 1 @ 2 10K_0402_5%
    SPI_HOLD_L/ESPI_DAT3 BC9 SPI_CS1#
    X48M_X2 SPI_CS1_L/EGPIO118 SPI_CS2# LPC_CLK1 RC115
    BA5 BA8 1 @ 2 10K_0402_5%
    X48M_X2 SPI_CS2_L/ESPI_CS_L/AGPIO30 BA6 SPI_CS3#
    SPI_CS3_L/AGPIO31 BD8 SPI_CS2#_TPM
    SPI_TPM_CS_L/AGPIO29 SPI_CS2#_TPM 44
    Test_Point_20MIL 1 TPC47
    AF8
    Test_Point_20MIL 1 TPC48
    AF9 RSVD_76 BA16 UART0_RXD_C
    RSVD_77 UART0_RXD/EGPIO136 BB18 UART0_TXD_C
    UART0_TXD/EGPIO138 BC17 UART0_RTS#
    UART0_RTS_L/UART2_RXD/EGPIO137 BA18 UART0_CTS#
    RC64 1 @ 2 0_0402_5% AW14
    RTCCLK UART0_CTS_L/UART2_TXD/EGPIO135 BD18 UART0_INTR
    25,37 RTCCLK_R RTCCLK UART0_INTR/AGPIO139

    X32K_X1 AY1 BC18


    X32K_X1 EGPIO141/UART1_RXD BA17
    EGPIO143/UART1_TXD BC16 F4_LED#
    RC65 EGPIO142/UART1_RTS_L/UART3_RXD BB19 F4_LED# 46 LPC_RST# CC15 1 2 150P_0402_50V8-J
    1 2 X32K_X2 AY4 EGPIO140/UART1_CTS_L/UART3_TXD BB16
    X32K_X2 AGPIO144/UART1_INTR

    20M_0402_5%
    FP5 REV 0.90
    YC1 PART 5 OF 13

    Follow 720S 1 2
    AMD-RAVEN-FP5_BGA1140
    32.768KHZ_12.5PF_202740-PG14

    1 1
    C CC16 CC17 C
    10P_0402_50V8-J 10P_0402_50V8-J
    2 2

    change YC2 PN change to SJ10000MQ00,manual modify PN to SJ10000MQ00


    +1.8V_SPI
    UC8M1 +1.8VALW

    SPI_CS1# +1.8V_SPI 0.085 A


    1 8 RC69 1 @ 2 0_0402_5%
    /CS VCC 0814:Change F4_LED# GPIO control
    SPI_SO 2 7 SPI_IO3 +3VS
    DO(IO1)/HOLD or/RESET(IO3) 1
    CC18
    SPI_IO2 3 6 SPI_CLK @
    /WP(IO2) CLK 0.1U_0201_16V6-K
    SPI_SI 2 F4_LED# RC166
    4 5 1 2 10K_0402_5%
    GND DI(IO0)

    8MB(64Mb) W25Q128FWSIQ_SO8 RC139


    LPC_FRAME# 1 @ 2 10K_0402_5%
    +1.8V_SPI
    For layout change RPC9 1024：Change SA000077F00 8M to SA00008E400 W25Q128FWSIQ 16M for TPM update RC67
    KBRST# 1 2 10K_0402_5%

    RC122 1 2 10K_0402_5% SPI_CS3# X48M_X1

    RC123 1 2 10K_0402_5% SPI_CS1#


    RC75
    RC124 1 2 10K_0402_5% SPI_IO2 1 2 X48M_X2 +1.8VS
    1M_0402_5%
    RC125 1 2 10K_0402_5% SPI_IO3
    YC2
    SPI_CS1# EC_SPI_CS1# UART0_RXD_C @
    RC76 1 @ 2 22_0402_5% RC73 1 2 1K_0402_5%
    0814: For AMD suggestion , pull 10k to S5 SPI_SI EC_SPI_SI EC_SPI_CS1# 42
    1 4 RC77 1 @ 2 22_0402_5% @
    OSC1 NC2 SPI_SO EC_SPI_SO EC_SPI_SI 42 UART0_TXD_C
    RC78 1 @ 2 22_0402_5% RC74 1 2 1K_0402_5%
    RC132 SPI_SO SPI_CLK EC_SPI_CLK EC_SPI_SO 42
    1 2 10K_0402_5% 2 3 RC79 1 @ 2 22_0402_5% @
    NC1 OSC2 EC_SPI_CLK 42 UART0_RTS# RC71 1 2 1K_0402_5%
    1 @
    1

    UART0_CTS# RC72 1 2 1K_0402_5%


    +1.8VALW CC19 48MHZ_10PF_7V48000017 CC20
    UART0_INTR @
    8.2P_0402_50V8-C 10P_0402_50V8-J RC1161 2 1K_0402_5%
    2

    @ 2
    RC81
    1 2 10K_0402_5% SPI_CS2#
    1023: For vendor test request : Change CC19 from 10p to 8.2p
    RC82 0814 Mirror function change to offline burn
    1 2 10K_0402_5% SPI_CS2#_TPM

    SPI_CLK_C RC83
    B 1 2 10K_0402_5% B

    Strap

    LPC ROM EMULATOR HEADER

    +3VALW +3VS_APU

    PIN4 should be removed as a Key


    2

    RC85 RC86
    0_0402_5% 0_0402_5%
    DAISY CHAIN ROUTING FOR LPC SIGNALS
    LPC@ LPC@
    1

    2 0_0402_5% PM_SLP_S5#
    UNNAMED_16_CON20_I130_P6

    IT10 @1 RC88 1 @
    LPC_FRAME# 1@ IT11 PM_SLP_S5# 7,42
    LPC_RST# RC87 1 2 0_0402_5% LPC_RST#_H 1@ IT12
    LPC@ APU_SMB1_DATA_LPC LPC@ 2
    IT21 @1 RC90 1 0_0402_5%
    1@ IT14 APU_SMB_DA0 7,14,15
    LPCRUNPWR IT22 @1 SERIRQ
    APU_SMB_CK0 RC89 1 2 0_0402_5% APU_SMB_CK0_LPC 1@ IT16 IT24 @1 LDRQ0#
    7,14,15 APU_SMB_CK0 1@ IT17
    LPC@

    1 1
    CC22 CC23
    0.1U_0402_10V7-K 0.1U_0402_10V7-K
    LPC@ 2 2
    LPC@

    RC3152 RC3153 should be put on APU side to reduce stub when MP

    +3VS_APU
    A LPC@ A
    RC91 1 2 10K_0402_5% LPCPD#

    RC92 1 @ 2 10K_0402_5% LPC_CLKRUN#

    LPC@
    RC931 2 100K_0402_5% LPC_RST#

    CC24 1 2
    150P_0402_50V8-J
    @

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 Switch
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 9 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    UC1L

    RSVD
    T11 AA9
    RSVD_32 RSVD_62 AA8
    AC7 RSVD_61 AC6
    RSVD_66 RSVD_65

    Y9
    Y10 RSVD_55 AD11
    RSVD_56 RSVD_72
    W11 AC9
    W12 RSVD_47 RSVD_67 AA11
    RSVD_48 RSVD_63
    V9 T12
    V10 RSVD_38 RSVD_33 AD12
    RSVD_39 RSVD_73
    Y6
    RSVD_53 Y7
    RSVD_54
    AA12 W8
    AC10 RSVD_64 RSVD_45 W9
    RSVD_68 RSVD_46

    FP5 REV 0.90


    PART 12 OF 13

    AMD-RAVEN-FP5_BGA1140

    UC1J

    USB
    USBC0_A2/USB_0_TXP0/DP3_TXP[2]1
    +1.8VALW USBC0 For Full typec USB20_P0 AE7 AD2 USBC0_0_TXP0 USBC0_A3/USB_0_TXN0/DP3_TXN[2]1 O-IOVP-D USB Super Speed Port Transmit
    33 USB20_P0 USB20_N0 USB_0_DP0 USBC0_A2/USB_0_TXP0/DP3_TXP2 USBC0_0_TXN0 USBC0_0_TXP0 33 USBC0_B11/USB_0_RXP0/DP3_TXP[3]1
    USB P0 AE6 AD4
    33 USB20_N0 USB_0_DM0 USBC0_A3/USB_0_TXN0/DP3_TXN2 USBC0_0_TXN0 33 USB Typec 0
    USBC0_B10/USB_0_RXN0/DP3_TXN[3]1 B-IOVP-D USB Super Speed Port Receive
    USB20_P1 USBC0_0_RXP0 USBC1_A11/DP2_TXP[0]1
    C
    35 USB20_P1 AG10 AC2 USBC0_0_RXP0 33 USBC1_A10/DP2_TXN[0]1 B-IOVP-D USB Super Speed Port Receive C
    1 RC94 2 USBC_I2C_SCL USB3.0 Port1 USB20_N1 AG9 USB_0_DP1 USBC0_B11/USB_0_RXP0/DP3_TXP3 AC4 USBC0_0_RXN0 USBC1_B2/DP2_TXP[1]1
    USB P1 35 USB20_N1 USB_0_DM1 USBC0_B10/USB_0_RXN0/DP3_TXN3 USBC0_0_RXN0 33 USB Typec integrated USBC SWITCH with DP USBC1_B3/DP2_TXN[1]1 O-IOVP-D USB Super Speed Port Transmit
    4.7K_0402_5% USB20_P2 USBC0_1_TXP0 USBC1_A2/USB_0_TXP3/DP2_TXP[2]1
    AF12 AF4 USBC1_A3/USB_0_TXN3/DP2_TXN[2]1 O-IOVP-D USB Super Speed Port Transmit
    USBC_I2C_SDA 35 USB20_P2 USB20_N2 USB_0_DP2 USBC0_B2/DP3_TXP1 USBC0_1_TXN0 USBC0_1_TXP0 33
    1 RC95 2 USB3.0 port2 AF11 AF2 USBC1_B11/USB_0_RXP3/DP2_TXP[3]1
    USB P2
    35 USB20_N2 USB_0_DM2 USBC0_B3/DP3_TXN1 USBC0_1_TXN0 33
    B-IOVP-D USB Super Speed Port Receive
    4.7K_0402_5% USB20_P3 USBC0_1_RXP0
    AE10 AE3 USBC0_1_RXP0 33
    36 USB20_P3 USB20_N3 USB_0_DP3 USBC0_A11/DP3_TXP0 USBC0_1_RXN0
    IO BOARD AE9 AE1
    36 USB20_N3 USB_0_DM3 USBC0_A10/DP3_TXN0 USBC0_1_RXN0 33
    USB20_P_WLAN AJ12 AG3 USB3P1_TXP
    37 USB20_P_WLAN USB20_N_WLAN AJ11 USB_1_DP0 USB_0_TXP1 USB3P1_TXN USB3P1_TXP 35
    USB3.0 AG1
    USB P4 37 USB20_N_WLAN USB_1_DM0 USB_0_TXN1 USB3P1_TXN 35 USB3.0 Port1
    USB20_P5_CAMERA
    AD9 AJ9 USB3P1_RXP
    26 USB20_P5_CAMERA USB20_N5_CAMERA USB_1_DP1 USB_0_RXP1 USB3P1_RXN USB3P1_RXP 35
    CAMERA AD8 AJ8 USBC0_A11/DP3_TXP[0]1
    USB P5 26 USB20_N5_CAMERA USB_1_DM1 USB_0_RXN1 USB3P1_RXN 35
    USBC0_A10/DP3_TXN[0]1 B-IOVP-D USB Super Speed Port Receive
    AG4 USB3P2_TXP USBC0_B2/DP3_TXP[1]1
    USB_0_TXP2 USB3P2_TXN USB3P2_TXP 35 USBC0_B3/DP3_TXN[1]1 O-IOVP-D USB Super Speed Port Transmit
    AG2
    USB_0_TXN2 USB3P2_TXN 35
    USB3P2_RXP USB3.0 port2
    AG7 USB3P2_RXP 35
    USBC_I2C_SCL AM6 USB_0_RXP2 AG6 USB3P2_RXN
    USBC_I2C_SCL USB_0_RXN2 USB3P2_RXN 35
    USBC_I2C_SDA AM7 AA2
    USBC_I2C_SDA USBC1_A2/USB_0_TXP3/DP2_TXP2 AA4
    USBC1_A3/USB_0_TXN3/DP2_TXN2
    Y1
    USBC1_B11/USB_0_RXP3/DP2_TXP3 Y3
    USBC1_B10/USB_0_RXN3/DP2_TXN3
    AC1
    USBC1_B2/DP2_TXP1 AC3
    INT#_TYPEC_CPU
    AK10 USBC1_B3/DP2_TXN1
    31 INT#_TYPEC_CPU USB_OC0# USB_OC0_L/AGPIO16
    AK9 AB2
    35 USB_OC0# USB_OC1# USB_OC1_L/AGPIO17 USBC1_A11/DP2_TXP0
    AL9 AB4
    35 USB_OC1# USB_OC2# USB_OC2_L/AGPIO18 USBC1_A10/DP2_TXN0
    AL8
    36 USB_OC2# USB_OC3_L/AGPIO24
    AW7 AH4
    AGPIO13 AT12 AGPIO14/USB_OC4_L USB_1_TXP0 AH2
    AGPIO13/USB_OC5_L USB_1_TXN0
    AK7
    +3VALW USB_1_RXP0 AK6
    USB_1_RXN0
    FP5 REV 0.90
    PART 10 OF 13

    AMD-RAVEN-FP5_BGA1140

    RPC13
    1 4 USB_OC1#
    2 3 USB_OC0#

    10K_0404_4P2R_5%

    B B

    RC99 USB_OC2#
    1 2
    10K_0402_5% Vgs(th) max= 1V
    0814: Change MOS to Dual MOS
    AGPIO13 +1.8VALW
    PD I2C port
    2

    RC118
    @ 10K_0402_5%
    1

    2
    G

    USBC_I2C_SCL 1 6 REPETER_SCL
    S

    REPETER_SCL 31,33
    D

    QC4A
    DMN5L06DWK-7 2N SOT363-6
    5
    G

    USBC_I2C_SDA 4 3 REPETER_SDA
    S

    REPETER_SDA 31,33
    D

    QC4B
    DMN5L06DWK-7 2N SOT363-6

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 Switch
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 10 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    UC1M

    CAMERAS

    A18 B15
    C18 CAM0_CSI2_CLOCKP CAM0_CLK
    CAM0_CSI2_CLOCKN D15
    A15 CAM0_I2C_SCL C14
    C15 CAM0_CSI2_DATAP0 CAM0_I2C_SDA
    CAM0_CSI2_DATAN0 B13
    B16 CAM0_SHUTDOWN
    C16 CAM0_CSI2_DATAP1
    CAM0_CSI2_DATAN1
    C19
    B18 CAM0_CSI2_DATAP2
    CAM0_CSI2_DATAN2
    B17
    D17 CAM0_CSI2_DATAP3
    CAM0_CSI2_DATAN3
    D12 B10
    B12 CAM1_CSI2_CLOCKP CAM1_CLK
    CAM1_CSI2_CLOCKN A11
    C13 CAM1_I2C_SCL C11
    A13 CAM1_CSI2_DATAP0 CAM1_I2C_SDA
    CAM1_CSI2_DATAN0 D11
    C B11 CAM1_SHUTDOWN C
    C12 CAM1_CSI2_DATAP1 D13
    CAM1_CSI2_DATAN1 CAM_PRIV_LED D10
    J13 CAM_IR_ILLU
    FP5 REV 0.90
    RSVD_6 PART 13 OF 13

    AMD-RAVEN-FP5_BGA1140

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 Switch
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 11 of 65

    5 4 3 2 1
    5 4 3 2 1

    D D
    Delete 22U 0603 and place PWR portion under SOC
    All BU(on bottom side under SOC)

    Need discuss if space enough ,reserves others component

    +VDDC_VDD

    +3VS +3VS_APU +VDDC_VDD


    +VDDCR_SOC UC1F
    @
    J2 1
    1 2
    2 JUMP_43X39 35A 1
    10A CC44

    180P_0402_50V8-J
    POW ER
    +3VALW +3VALW_APU M15 G7
    @ M18 VDDCR_SOC_1 VDDCR_1 G10
    J3 1 2 JUMP_43X39 M19 VDDCR_SOC_2 VDDCR_2 G12 2
    1 2 N16 VDDCR_SOC_3 VDDCR_3 G14
    N18 VDDCR_SOC_4 VDDCR_4 H8
    N20 VDDCR_SOC_5 VDDCR_5 H11
    P17 VDDCR_SOC_6 VDDCR_6 H15
    VDDCR_SOC_7 VDDCR_7 All BU(on bottom side under SOC)
    +1.8VS P19 K7
    R18 VDDCR_SOC_8 VDDCR_8 K12
    R20 VDDCR_SOC_9 VDDCR_9 K14
    T19 VDDCR_SOC_10 VDDCR_10 L8
    U18 VDDCR_SOC_11 VDDCR_11 M7
    +1.8VS U20 VDDCR_SOC_12 VDDCR_12 M10

    2
    V19 VDDCR_SOC_13 VDDCR_13 N14
    +3VS_APU RC156 +1.2V W18 VDDCR_SOC_14 VDDCR_14 P7
    @ W20 VDDCR_SOC_15 VDDCR_15 P10 +VDDCR_SOC
    0_0603_5% VDDCR_SOC_16 VDDCR_16
    +1.5VS Y19 P13
    CC38 CC39 VDDCR_SOC_17 VDDCR_17 P15

    1
    CC41 T32 VDDCR_18 R8
    1 VDDIO_MEM_S3_1 VDDCR_19
    1 1 1 BU1 BO 1 V28 R14
    BU BO 1U_0402_6.3V7-K VDDIO_MEM_S3_2 VDDCR_20
    CC47
    CC46 CC40 W28 R16
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    BO
    BO 1 2 RC100 +VDDIO_AZ W32 VDDIO_MEM_S3_3 VDDCR_21 T7
    1U_0201_6.3V6-M

    VDDIO_MEM_S3_4 VDDCR_22 1 1
    2 0_0603_5% Y22 T10 CC58
    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    180P_0402_50V8-J
    1 1 VDDIO_MEM_S3_5 VDDCR_23
    2 2 2 2 2 Y25 T13 CC57

    22U_0603_6.3V6-M
    @ CC55
    BU CC56 Y28 VDDIO_MEM_S3_6 VDDCR_24 T15 1U_0402_6.3V6-K
    BO VDDIO_MEM_S3_7 VDDCR_25
    1U_0402_6.3V6-K AA20 T17 2 2
    2 2 AA23 VDDIO_MEM_S3_8 VDDCR_26 U14
    CD@ AA26 VDDIO_MEM_S3_9 VDDCR_27 U16
    AA28 VDDIO_MEM_S3_10 VDDCR_28 V13
    AA32 VDDIO_MEM_S3_11 VDDCR_29 V15 All BU(on bottom side under SOC)
    C CD@ AC20 VDDIO_MEM_S3_12 VDDCR_30 V17 C
    AC22 VDDIO_MEM_S3_13 VDDCR_31 W7
    AC25 VDDIO_MEM_S3_14 VDDCR_32 W10
    AC28 VDDIO_MEM_S3_15 VDDCR_33 W14
    AD23 VDDIO_MEM_S3_16 VDDCR_34 W16
    0823： Chaneg from 1.5V to 1.8V HDA for codec AD26 VDDIO_MEM_S3_17 VDDCR_35 Y8
    AD28 VDDIO_MEM_S3_18 VDDCR_36 Y13 +1.2V
    AD32 VDDIO_MEM_S3_19 VDDCR_37 Y15
    AE20 VDDIO_MEM_S3_20 VDDCR_38 Y17
    AE22 VDDIO_MEM_S3_21 VDDCR_39 AA7
    AE25 VDDIO_MEM_S3_22 VDDCR_40 AA10
    AE28 VDDIO_MEM_S3_23 VDDCR_41 AA14
    VDDIO_MEM_S3_24 VDDCR_42 1 1 1 1 1 1 1 1 1 1 1 1
    AF23 AA16

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    CC59 CC60 CC61 CC62 CC63 CC64 CC65 CC66 CC67 CC70

    22U_0603_6.3V6-M

    180P_0402_50V8-J
    +3VS_APU AF26 VDDIO_MEM_S3_25 VDDCR_43 AA18 CC68 CC69

    1U_0402_6.3V6-K
    +1.8VALW AF28 VDDIO_MEM_S3_26 VDDCR_44 AB13
    +3VALW_APU AF32 VDDIO_MEM_S3_27 VDDCR_45 AB15 2 2 2 2 2 2 2 2 2 1U_0402_6.3V6-K2 2 2
    AG20 VDDIO_MEM_S3_28 VDDCR_46 AB17
    AG22 VDDIO_MEM_S3_29 VDDCR_47 AB19
    AG25 VDDIO_MEM_S3_30 VDDCR_48 AC14
    AG28 VDDIO_MEM_S3_31 VDDCR_49 AC16 CD@ CD@ CD@
    CC72 CC73 CC75 CC76 AJ20 VDDIO_MEM_S3_32 VDDCR_50 AC18
    AJ23 VDDIO_MEM_S3_33 VDDCR_51 AD7 All BU(on bottom side under SOC)
    1 BU1 BO 1
    VDDIO_MEM_S3_34 VDDCR_52
    CC74 AJ26 AD10
    22U_0603_6.3V6-M

    1 1
    BU BO 1 BO VDDIO_MEM_S3_35 VDDCR_53
    CC71 AJ28 AD13
    22U_0603_6.3V6-M

    BO
    AJ32 VDDIO_MEM_S3_36 VDDCR_54 AD15 COST DOWN 4 PIECES
    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    2 2 2 AK28 VDDIO_MEM_S3_37 VDDCR_55 AD17


    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    2 2 2 AL28 VDDIO_MEM_S3_38 VDDCR_56 AD19


    AL32 VDDIO_MEM_S3_39 VDDCR_57 AE8
    VDDIO_MEM_S3_40 VDDCR_58 AE14
    +1.8VS +VDDIO_AZ AP12 VDDCR_59 AE16 +1.2V
    VDDIO_AUDIO VDDCR_60 AE18
    0.25A AL18 VDDCR_61 AF7 DECOUPLING BETWEEN PROCESSOR AND DIMMs
    CD@ AM17 VDD_33_1 VDDCR_62 AF10 ACROSS VDDIO AND VSS SPLIT
    CD@ +1.8VALW VDD_33_2 VDDCR_63 AF13
    2A AL20
    VDD_18_1
    VDDCR_64
    VDDCR_65
    AF15
    AM19 AF17

    0.22U_0402_10V6-K

    0.22U_0402_10V6-K

    0.22U_0402_10V6-K

    0.22U_0402_10V6-K
    VDD_18_2 VDDCR_66 AF19
    +3VALW_APU 0.5A AL19 VDDCR_67 AG14
    1 1 1 1
    CC81
    1 1
    CC82

    180P_0402_50V8-J
    VDD_18_S5_1 VDDCR_68

    CC77

    CC78

    CC79

    CC80
    AM18 AG16
    +0.9VALW_VDDP VDD_18_S5_2 VDDCR_69 AG18
    +0.9VALW_VDDP
    0.25A AL17 VDDCR_70 AH13 2 2 2 2 2 2
    AM16 VDD_33_S5_1 VDDCR_71 AH15 CD@

    180P_0201_25V7-K
    VDD_33_S5_2 VDDCR_72 AH17 EMC@ EMC@
    1A AL14 VDDCR_73 AH19
    AL15 VDDP_S5_1 VDDCR_74 AJ7
    VDDP_S5_2 VDDCR_75
    CC84 CC85 CC86 +0.9VS_VDDP AM14
    VDDP_S5_3 VDDCR_76
    AJ10
    AJ14
    1
    CC83 BU BU BO 4A AL13 VDDCR_77 AJ16
    All BU(on bottom side under SOC)
    22U_0603_6.3V6-M

    BO 1 1 1 VDDP_1 VDDCR_78
    AM12 AJ18 4x0.22UF (0402)+2x180PF(0402)
    AM13 VDDP_2 VDDCR_79 AK13
    2 VDDP_3 VDDCR_80
    B
    +RTC_LDO AN12 AK15 B
    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    2 2 2 AN13 VDDP_4 VDDCR_81 AK17


    VDDP_5 VDDCR_82 AK19
    1K_0402_5% 1 RC101 2 +VDDBT_RTC 0.1A AT11 VDDCR_83
    VDDBT_RTC_G
    FP5 REV 0.90
    PART 6 OF 13
    0.22U_0402_10V6-K

    1 1 AMD-RAVEN-FP5_BGA1140
    CD@
    CC87
    CC88

    1U_0402_6.3V6-K2 2

    +0.9VS_VDDP 0815：Change for 0201 for layout


    +RTC_LDO
    +RTC_LDO
    BO
    1

    CC91 CC92 CC93 CC94 CC95 CC96 CC97 CC98


    1 1 1 1 1 1 1 1 1 1 BU
    R395
    BO BU BU BU BO BO BO @ 470_0603_5%
    BO BU 1
    CC99
    CC89 CC90
    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    2
    1

    2 2 2 2 2 2 2 2 2 2 D QC7
    2 180P_0201_25V7-K 2 EC_RTCRST#_ON
    G EC_RTCRST#_ON 42
    1

    S 2N7002KW_SOT323-3 RC145
    3

    @ @ 100K_0402_5%
    CD@
    2

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 Switch
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 12 of 65

    5 4 3 2 1
    5 4 3 2 1

    D D

    UC1G
    UC1K
    GND
    N12 K32 GND/RSVD
    VSS_316 VSS_62 UC1H
    A3 L5 AR5 BD16
    A5 VSS_1 VSS_63 L13 AR7 VSS_248 VSS_310 BD19
    A7 VSS_2 VSS_64 L15 AR12 VSS_249 VSS_311 BD21 GND
    A10 VSS_3 VSS_65 L18 AR14 VSS_250 VSS_312 BD23 V8 AG8
    A12 VSS_4 VSS_66 L20 AR16 VSS_251 VSS_313 BD26 V11 VSS_124 VSS_186 AG11
    A14 VSS_5 VSS_67 L25 AR19 VSS_252 VSS_314 BD30 V12 VSS_125 VSS_187 AG12
    A16 VSS_6 VSS_68 L28 AR21 VSS_253 VSS_315 V14 VSS_126 VSS_188 AG13
    A19 VSS_7 VSS_69 M1 AR26 VSS_254 V16 VSS_127 VSS_189 AG15
    A21 VSS_8 VSS_70 M5 AR28 VSS_255 V18 VSS_128 VSS_190 AG17
    A23 VSS_9 VSS_71 M12 AR32 VSS_256 V20 VSS_129 VSS_191 AG19
    A26 VSS_10 VSS_72 M21 AU5 VSS_257 V22 VSS_130 VSS_192 AH14
    A30 VSS_11 VSS_73 M23 AU8 VSS_258 V25 VSS_131 VSS_193 AH16
    C3 VSS_12 VSS_74 M26 AU11 VSS_259 W1 VSS_132 VSS_194 AH18
    C32 VSS_13 VSS_75 M28 AU13 VSS_260 W5 VSS_133 VSS_195 AH20
    D16 VSS_14 VSS_76 M32 AU15 VSS_261 W13 VSS_134 VSS_196 AJ1
    D18 VSS_15 VSS_77 N4 AU18 VSS_262 W15 VSS_135 VSS_197 AJ5
    D20 VSS_16 VSS_78 N5 AU20 VSS_263 W17 VSS_136 VSS_198 AJ13
    E7 VSS_17 VSS_79 N8 AU22 VSS_264 W19 VSS_137 VSS_199 AJ15
    E8 VSS_18 VSS_80 N11 AU25 VSS_265 B20 W23 VSS_138 VSS_200 AJ17
    E10 VSS_19 VSS_81 N13 AU28 VSS_266 RSVD_1 G3 W26 VSS_139 VSS_201 AJ19
    E11 VSS_20 VSS_82 N15 AV1 VSS_267 RSVD_5 J20 Y5 VSS_140 VSS_202 AK5
    E12 VSS_21 VSS_83 N17 AV5 VSS_268 RSVD_7 K3 Y11 VSS_141 VSS_203 AK8
    E13 VSS_22 VSS_84 N19 AV7 VSS_269 RSVD_8 K6 Y12 VSS_142 VSS_204 AK11
    E14 VSS_23 VSS_85 N22 AV10 VSS_270 RSVD_9 K20 Y14 VSS_143 VSS_205 AK12
    E15 VSS_24 VSS_86 N25 AV12 VSS_271 RSVD_10 M3 Y16 VSS_144 VSS_206 AK14
    E16 VSS_25 VSS_87 N28 AV14 VSS_272 RSVD_11 M6 Y18 VSS_145 VSS_207 AK16
    C E18 VSS_26 VSS_88 P1 AV16 VSS_273 RSVD_12 M13 Y20 VSS_146 VSS_208 AK18 C
    E19 VSS_27 VSS_89 P5 AV19 VSS_274 RSVD_13 P6 AA1 VSS_147 VSS_209 AK20
    E20 VSS_28 VSS_90 P14 AV21 VSS_275 RSVD_22 P22 AA5 VSS_148 VSS_210 AK22
    E21 VSS_29 VSS_91 P16 AV23 VSS_276 RSVD_23 T3 AA13 VSS_149 VSS_211 AK25
    E22 VSS_30 VSS_92 P18 AV26 VSS_277 RSVD_30 T6 AA15 VSS_150 VSS_212 AL1
    E23 VSS_31 VSS_93 P20 AV28 VSS_278 RSVD_31 T29 AA17 VSS_151 VSS_213 AL5
    E25 VSS_32 VSS_94 P23 AV32 VSS_279 RSVD_37 W6 AA19 VSS_152 VSS_214 AL7
    E26 VSS_33 VSS_95 P26 AW5 VSS_280 RSVD_44 W21 AB14 VSS_153 VSS_215 AL10
    E27 VSS_34 VSS_96 P28 AW28 VSS_281 RSVD_49 W22 AB16 VSS_154 VSS_216 AL12
    F5 VSS_35 VSS_97 P32 AY6 VSS_282 RSVD_50 Y21 AB18 VSS_155 VSS_217 AL16
    F28 VSS_36 VSS_98 R5 AY7 VSS_283 RSVD_57 Y27 AB20 VSS_156 VSS_218 AL23
    G1 VSS_37 VSS_99 R11 AY8 VSS_284 RSVD_58 AA3 AC5 VSS_157 VSS_219 AL26
    G5 VSS_38 VSS_100 R12 AY10 VSS_285 RSVD_59 AA6 AC8 VSS_158 VSS_220 AM5
    G16 VSS_39 VSS_101 R13 AY11 VSS_286 RSVD_60 AC29 AC11 VSS_159 VSS_221 AM8
    G19 VSS_40 VSS_102 R15 AY12 VSS_287 RSVD_69 AD3 AC12 VSS_160 VSS_222 AM15
    G21 VSS_41 VSS_103 R17 AY13 VSS_288 RSVD_70 AD6 AC13 VSS_161 VSS_223 AM20
    G23 VSS_42 VSS_104 R19 AY14 VSS_289 RSVD_71 AF3 AC15 VSS_162 VSS_224 AM22
    G26 VSS_43 VSS_105 R22 AY15 VSS_290 RSVD_74 AF6 AC17 VSS_163 VSS_225 AM25
    G28 VSS_44 VSS_106 R25 AY16 VSS_291 RSVD_75 AF30 AC19 VSS_164 VSS_226 AM28
    G32 VSS_45 VSS_107 R28 AY18 VSS_292 RSVD_78 AJ6 AD1 VSS_165 VSS_227 AN1
    H5 VSS_46 VSS_108 R30 AY19 VSS_293 RSVD_79 AJ24 AD5 VSS_166 VSS_228 AN5
    H13 VSS_47 VSS_109 T1 AY20 VSS_294 RSVD_80 AK23 AD14 VSS_167 VSS_229 AN7
    H18 VSS_48 VSS_110 T5 AY21 VSS_295 RSVD_81 AK27 AD16 VSS_168 VSS_230 AN10
    H20 VSS_49 VSS_111 T14 AY22 VSS_296 RSVD_82 AL3 AD18 VSS_169 VSS_231 AN15
    H22 VSS_50 VSS_112 T16 AY23 VSS_297 RSVD_83 AN29 AD20 VSS_170 VSS_232 AN18
    H25 VSS_51 VSS_113 T18 AY25 VSS_298 RSVD_87 AN31 AE5 VSS_171 VSS_233 AN21
    H28 VSS_52 VSS_114 T20 AY26 VSS_299 RSVD_88 AE11 VSS_172 VSS_234 AN23
    K1 VSS_53 VSS_115 T23 AY27 VSS_300 AE12 VSS_173 VSS_235 AN26
    K5 VSS_54 VSS_116 T26 BB1 VSS_301 AE13 VSS_174 VSS_236 AN28
    K16 VSS_55 VSS_117 T28 BB20 VSS_302 AE15 VSS_175 VSS_237 AN32
    K19 VSS_56 VSS_118 U13 BB32 VSS_303 M14 AE17 VSS_176 VSS_238 AP5
    K21 VSS_57 VSS_119 U15 BD3 VSS_304 RSVD_14 AL6 AE19 VSS_177 VSS_239 AP8
    K22 VSS_58 VSS_120 U17 BD7 VSS_305 RSVD_84 AL11 AF1 VSS_178 VSS_240 AP13
    K26 VSS_59 VSS_121 U19 BD10 VSS_306 RSVD_85 AN16 AF5 VSS_179 VSS_241 AP15
    K28 VSS_60 VSS_122 V5 BD12 VSS_307 RSVD_86 AF14 VSS_180 VSS_242 AP18
    VSS_61 VSS_123 BD14 VSS_308 AF16 VSS_181 VSS_243 AP20
    FP5 REV 0.90
    PART 7 OF 13 VSS_309 AF18 VSS_182 VSS_244 AP25
    FP5 REV 0.90
    PART 11 OF 13 AF20 VSS_183 VSS_245 AP28
    AMD-RAVEN-FP5_BGA1140 VSS_184 VSS_246
    AG5 AR1
    AMD-RAVEN-FP5_BGA1140 VSS_185 VSS_247
    FP5 REV 0.90
    PART 8 OF 13

    AMD-RAVEN-FP5_BGA1140

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 Switch
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 13 of 65
    5 4 3 2 1
    5 4 3 2 1

    +2.5V

    1 1 1
    +1.2V CD9 CD10 CD11 CD66
    +1.2V CD@ CD@

    0.1U_0402_10V7-K

    0.1U_0402_10V7-K
    2 2 2

    180P_0402_50V8-J
    1U_0402_6.3V6-K
    1 1 1 1 1 1 1 1
    CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8

    1
    RD1 CD@ 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M
    2 2 2 2 2 2 2 2
    1K_0402_1%

    2
    D D
    M_VREF_CA_DIMMA +0.6VS

    +1.2V
    EMC@
    EMC@ 1 1

    1
    1 CD25 CD23 CD24
    RD2 CD13 2 2 2 2 2 2 2 2 1 CD74 1
    CD14 CD15 CD16 CD17 CD18 CD19 CD20 CD21CD75 @ 100U_1206_6.3V6M

    0.1U_0402_10V7-K
    1K_0402_1% 0.1U_0402_10V7-K @ 2 2

    1U_0402_6.3V6-K

    4.7U_0402_6.3V6-M
    2 @
    0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 100U_1206_6.3V6M

    2
    1 1 1 1 1 1 1 1 2 2

    DDRA_MA_DM[0..7] 6

    DDR_A_D[0..63] 6

    DDR_A_MA[0..13] 6

    DDR_A_DQS#[0..7] 6

    DDR_A_DQS[0..7] 6
    +1.2V

    +1.2V +1.2V

    1
    +2.5V +1.2V +1.2V +0.6VS RD3
    JDIMM1B
    1K_0402_1%
    JDIMM1A

    2
    DDR_A_MA3 131 132 DDR_A_MA2
    DDR_A_MA1 133 A3 A2 134
    A1 EVENT_n/NF DDR_A_EVENT# 6
    1 2 135 136
    DDR_A_D5 3 VSS_1 VSS_2 4 DDR_A_D4 SA_CLK_DDR0 137 VDD_9 VDD_10 138 SA_CLK_DDR1
    DQ5 DQ4 6 SA_CLK_DDR0 SA_CLK_DDR#0 CK0_t CK1_t/NF SA_CLK_DDR#1 SA_CLK_DDR1 6
    5 6 139 140
    DDR_A_D1 VSS_3 VSS_4 DDR_A_D0 6 SA_CLK_DDR#0 CK0_c CK1_c/NF SA_CLK_DDR#1 6
    7 8 141 142
    C
    9 DQ1 DQ0 10 DDR_A_PARITY 143 VDD_11 VDD_12 144 DDR_A_MA0 C
    DDR_A_DQS#0 VSS_5 VSS_6 DDRA_MA_DM0 6 DDR_A_PARITY Parity A0
    11 12
    DDR_A_DQS0 13 DQS0_C DM0_n/DBl0_n 14
    15 DQS0_t VSS_7 16 DDR_A_D6 DDR_A_BA1 145 146 DDR_A_MA10
    DDR_A_D7 VSS_8 DQ6 6 DDR_A_BA1 BA1 A10/AP
    17 18 147 148
    19 DQ7 VSS_9 20 DDR_A_D2 DDR_A_CS0# 149 VDD_13 VDD_14 150 DDR_A_BA0
    DDR_A_D3 VSS_10 DQ2 6 DDR_A_CS0# DDR_A_WE# CS0_n BA0 DDR_A_RAS# DDR_A_BA0 6
    21 22 6 DDR_A_WE# 151 152 DDR_A_RAS# 6
    23 DQ3 VSS_11 24 DDR_A_D12 153 A14/WE_n A16/RAS_n 154
    DDR_A_D10 25 VSS_12 DQ12 26 DDR_A_ODT0 155 VDD_15 VDD_16 156 DDR_A_CAS#
    DQ13 VSS_13 DDR_A_D8 6 DDR_A_ODT0 DDR_A_CS1# ODT0 A15/CAS_n DDR_A_MA13 DDR_A_CAS# 6
    27 28 157 158
    DDR_A_D13 VSS_14 DQ8 6 DDR_A_CS1# CS1_n A13
    29 30 159 160
    31 DQ9 VSS_15 32 DDR_A_DQS#1 DDR_A_ODT1 161 VDD_17 VDD_18 162
    DDRA_MA_DM1 VSS_16 DQS1_c DDR_A_DQS1 6 DDR_A_ODT1 ODT1 C0/CS2_n/NC M_VREF_CA_DIMMA
    33 34 163 164
    35 DM1_n/DBl_n DQS1_t 36 165 VDD_19 VREFCA 166 SA2_CHA_P
    DDR_A_D15 37 VSS_17 VSS_18 38 DDR_A_D9 167 C1/CS3_n/NC SA2 168
    DQ15 DQ14 DDR_A_D37 VSS_53 VSS_54 DDR_A_D36 1 1
    39 40 169 170 CD26 CD27
    DDR_A_D14 41 VSS_19 VSS_20 42 DDR_A_D11 171 DQ37 DQ36 172
    43 DQ10 DQ11 44 +3VS +3VS +3VS DDR_A_D33 173 VSS_55 VSS_56 174 DDR_A_D32 1000P_0402_50V7-K 0.1U_0402_10V7-K
    DDR_A_D21 45 VSS_21 VSS_22 46 DDR_A_D20 175 DQ33 DQ32 176 2 2
    47 DQ21 DQ20 48 DDR_A_DQS#4 177 VSS_57 VSS_58 178 DDRA_MA_DM4
    VSS_23 VSS_24 DQS4_c DM4_n/DBl4_n
    1

    1
    DDR_A_D17 49 50 DDR_A_D16 DDR_A_DQS4 179 180
    51 DQ17 DQ16 52 RD4 RD5 RD6 181 DQS4_t VSS_59 182 DDR_A_D39
    DDR_A_DQS#2 53 VSS_25 VSS_26 54 DDRA_MA_DM2 @ @ @ DDR_A_D38 183 VSS_60 DQ39 184
    DDR_A_DQS2 55 DQS2_c DM2_n/DBl2_n 56 10K_0402_5% 10K_0402_5% 10K_0402_5% 185 DQ38 VSS_61 186 DDR_A_D35
    57 DQS2_t VSS_27 58 DDR_A_D22 DDR_A_D34 187 VSS_62 DQ35 188
    2

    2
    DDR_A_D23 59 VSS_28 DQ22 60 189 DQ34 VSS_63 190 DDR_A_D45
    61 DQ23 VSS_29 62 DDR_A_D18 SA0_CHA_P SA1_CHA_P SA2_CHA_P DDR_A_D44 191 VSS_64 DQ45 192
    DDR_A_D19 63 VSS_30 DQ18 64 193 DQ44 VSS_65 194 DDR_A_D41
    65 DQ19 VSS_31 66 DDR_A_D28 DDR_A_D40 195 VSS_66 DQ41 196
    VSS_32 DQ28 DQ40 VSS_67
    2

    2
    DDR_A_D29 67 68 197 198 DDR_A_DQS#5
    69 DQ29 VSS_33 70 DDR_A_D24 DDRA_MA_DM5 199 VSS_68 DQS5_c 200 DDR_A_DQS5
    DDR_A_D25 71 VSS_34 DQ24 72 0_0402_5% 0_0402_5% 0_0402_5% 201 DM5_n/DBl5_n DQS5_t 202
    73 DQ25 VSS_35 74 DDR_A_DQS#3 R1 RD7 RD8 DDR_A_D46 203 VSS_69 VSS_70 204 DDR_A_D47
    DDRA_MA_DM3 75 VSS_36 DQS3_c 76 DDR_A_DQS3 205 DQ46 DQ47 206
    1

    1
    77 DM3_n/DBl3_n DQS3_t 78 DDR_A_D42 207 VSS_71 VSS_72 208 DDR_A_D43
    DDR_A_D30 79 VSS_37 VSS_38 80 DDR_A_D31 209 DQ42 DQ43 210
    81 DQ30 DQ31 82 DDR_A_D52 211 VSS_73 VSS_74 212 DDR_A_D53
    DDR_A_D26 83 VSS_39 VSS_40 84 DDR_A_D27 213 DQ52 DQ53 214
    85 DQ26 DQ27 86 1023: change 0 ohm to R SHORT DDR_A_D49 215 VSS_75 VSS_76 216 DDR_A_D48
    87 VSS_41 VSS_42 88 +1.2V 217 DQ49 DQ48 218
    89 CB5/NC CB4/NC 90 DDR_A_DQS#6 219 VSS_77 VSS_78 220 DDRA_MA_DM6
    91 VSS_43 VSS_44 92 DDR_A_DQS6 221 DQS6_c DM6_n/DBl6_n 222
    93 CB1/NC
    VSS_45
    CB0/NC
    VSS_46
    94 SPD Address = 0H 223 DQS6_t
    VSS_80
    VSS_79
    DQ54
    224 DDR_A_D54
    1

    95 96 DDR_A_D55 225 226


    B 97 DQS8_c DM8_n/DBl_n/NC 98 RD9 227 DQS5 VSS_81 228 DDR_A_D50 B
    99 DQS8_t VSS_47 100 @ DDR_A_D51 229 VSS_82 DQ50 230
    101 VSS_48 CB6/NC 102 1K_0402_1% 231 DQ51 VSS_83 232 DDR_A_D63
    103 CB2/NC VSS_49 104 DDR_A_D61 233 VSS_84 DQ60 234
    2

    105 VSS_50 CB7/NC 106 235 DQ61 VSS_85 236 DDR_A_D59


    107 CB3/NC VSS_51 108 DDR_A_D60 237 VSS_86 DQ57 238
    DDR_A_CKE0 VSS_52 RESET_n DDR_A_CKE1 DDR4_A_DRAMRST# 6 DQ56 VSS_87 DDR_A_DQS#7
    6 DDR_A_CKE0 109 110 239 240
    CKE0 CKE1 DDR_A_CKE1 6 DDRA_MA_DM7 VSS_88 DQS7_c DDR_A_DQS7
    111 112 241 242
    DDR_A_BG1 113 VDD_1 VDD_2 114 DDR_A_ACT_N 243 DM7_n/DBl7_n DQS7_t 244
    6 DDR_A_BG1 DDR_A_BG0 BG1 ACT_n DDR_A_ALERT_N DDR_A_ACT_N 6 DDR_A_D56 VSS_89 VSS_90 DDR_A_D62
    115 116 245 246
    6 DDR_A_BG0 BG0 ALERT_n DDR_A_ALERT_N 6 DQ62 DQ63
    117 118 247 248
    DDR_A_MA12 119 VDD_3 VDD_4 120 DDR_A_MA11 DDR_A_D57 249 VSS_91 VSS_92 250 DDR_A_D58
    DDR_A_MA9 121 A12 A11 122 DDR_A_MA7 251 DQ58 DQ59 252
    A9 A7 RD10 APU_SMB_CK0 VSS_93 VSS_94 APU_SMB_DA0
    123 124 253 254
    DDR_A_MA8 VDD_5 VDD_6 DDR_A_MA5 7,9,15 APU_SMB_CK0 SCL SDA SA0_CHA_P APU_SMB_DA0 7,9,15
    125 126 2 1 255 256
    DDR_A_MA6 A8 A5 DDR_A_MA4 +3VS VDDSPD SA0
    127 128 257 258
    129 A6 A4 130 259 VPP_1 VTT 260 SA1_CHA_P
    VDD_7 VDD_8 1 0_0402_5% VPP_2 SA1
    CD30 1 1
    EMC_NS@ CD28 CD29 261 262
    0.1U_0402_10V7-K GND_1 GND_2
    ARGOS_D4AR0-26005-1P40 2 0.1U_0402_10V7-K 2.2U_0402_6.3V6-M ARGOS_D4AR0-26005-1P40
    2 2
    ME@ ME@

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/16 Deciphered Date 2018/06/01 DDR4 CH-A PRIMARY


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 14 of 65
    5 4 3 2 1
    5 4 3 2 1

    +0.6VS

    +1.2V
    1 1
    CD41 CD39 CD40

    1
    0.1U_0402_10V7-K
    RD11 1U_0402_6.3V6-K 2 2 4.7U_0402_6.3V6-M
    @
    +1.2V
    1K_0402_1%

    2
    1 1 1 1 1 1 1 1
    CD31 CD32 CD33 CD34 CD35 CD36 CD37 CD38
    M_VREF_CA_DIMMB
    10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M
    2 2 2 2 2 2 2 2
    +2.5V
    CD@ CD@

    1
    1 CD@
    D RD12 CD42 1 1 1 D
    CD43 CD44 CD45 CD73
    1K_0402_1% 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K +1.2V
    2 1U_0402_6.3V6-K 180P_0402_50V8-J
    2

    2 2 2

    2 2 2 2 2 2 2 2 1 CD62 1
    CD47 CD48 CD49 CD50 CD51 CD52 CD53 CD54 CD63 @ 100U_1206_6.3V6M
    @
    0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 100U_1206_6.3V6M
    1 1 1 1 1 1 1 1 2 2
    CD@
    EMC@

    DDRA_MB_DM[0..7] 6

    DDR_B_D[0..63] 6

    DDR_B_MA[0..13] 6

    DDR_B_DQS#[0..7] 6

    DDR_B_DQS[0..7] 6

    Layout Node: +1.2V


    Place Close DIMMs

    1
    RD13
    +2.5V +1.2V JDIMM2B +1.2V +0.6VS
    1K_0402_1%
    +1.2V JDIMM2A +1.2V

    2
    DDR_B_MA3 131 132 DDR_B_MA2
    DDR_B_MA1 133 A3 A2 134
    A1 EVENT_n/NF DDR_B_EVENT# 6
    1 2 135 136
    DDR_B_D5 3 VSS_1 VSS_2 4 DDR_B_D4 SB_CLK_DDR0 137 VDD_9 VDD_10 138 SB_CLK_DDR1
    DQ5 DQ4 6 SB_CLK_DDR0 SB_CLK_DDR#0 CK0_t CK1_t/NF SB_CLK_DDR#1 SB_CLK_DDR1 6
    5 6 139 140
    DDR_B_D1 VSS_3 VSS_4 DDR_B_D0 6 SB_CLK_DDR#0 CK0_c CK1_c/NF SB_CLK_DDR#1 6
    7 8 141 142
    9 DQ1 DQ0 10 DDR_B_PARITY 143 VDD_11 VDD_12 144 DDR_B_MA0
    C DDR_B_DQS#0 VSS_5 VSS_6 DDRA_MB_DM0 6 DDR_B_PARITY Parity A0 C
    11 12
    DDR_B_DQS0 13 DQS0_C DM0_n/DBl0_n 14
    15 DQS0_t VSS_7 16 DDR_B_D6 DDR_B_BA1 145 146 DDR_B_MA10
    DDR_B_D7 VSS_8 DQ6 6 DDR_B_BA1 BA1 A10/AP
    17 18 147 148
    19 DQ7 VSS_9 20 DDR_B_D2 DDR_B_CS0# 149 VDD_13 VDD_14 150 DDR_B_BA0
    DDR_B_D3 VSS_10 DQ2 6 DDR_B_CS0# DDR_B_WE# CS0_n BA0 DDR_B_RAS# DDR_B_BA0 6
    21 22 6 DDR_B_WE# 151 152 DDR_B_RAS# 6
    23 DQ3 VSS_11 24 DDR_B_D12 153 A14/WE_n A16/RAS_n 154
    DDR_B_D13 25 VSS_12 DQ12 26 DDR_B_ODT0 155 VDD_15 VDD_16 156 DDR_B_CAS#
    DQ13 VSS_13 DDR_B_D8 6 DDR_B_ODT0 DDR_B_CS1# ODT0 A15/CAS_n DDR_B_MA13 DDR_B_CAS# 6
    27 28 157 158
    DDR_B_D9 VSS_14 DQ8 6 DDR_B_CS1# CS1_n A13
    29 30 159 160
    31 DQ9 VSS_15 32 DDR_B_DQS#1 DDR_B_ODT1 161 VDD_17 VDD_18 162
    DDRA_MB_DM1 VSS_16 DQS1_c DDR_B_DQS1 6 DDR_B_ODT1 ODT1 C0/CS2_n/NC M_VREF_CA_DIMMB
    33 34 163 164
    35 DM1_n/DBl_n DQS1_t 36 165 VDD_19 VREFCA 166 SA2_CHB_P
    DDR_B_D15 37 VSS_17 VSS_18 38 DDR_B_D14 167 C1/CS3_n/NC SA2 168
    DQ15 DQ14 DDR_B_D37 VSS_53 VSS_54 DDR_B_D36 1 1 1
    39 40 169 170
    DDR_B_D10 41 VSS_19 VSS_20 42 DDR_B_D11 171 DQ37 DQ36 172 CD56 CD57 CD58
    43 DQ10 DQ11 44 DDR_B_D33 173 VSS_55 VSS_56 174 DDR_B_D32
    DDR_B_D21 VSS_21 VSS_22 DDR_B_D20 +3VS +3VS +3VS DQ33 DQ32 2 2 2

    1000P_0402_50V7-K

    2.2U_0402_6.3V6-M

    0.1U_0402_10V7-K
    45 46 175 176
    DQ21 DQ20 DDR_B_DQS#4 VSS_57 VSS_58 DDRA_MB_DM4 @
    47 48 177 178
    DDR_B_D17 49 VSS_23 VSS_24 50 DDR_B_D16 DDR_B_DQS4 179 DQS4_c DM4_n/DBl4_n 180
    DQ17 DQ16 DQS4_t VSS_59
    1

    1
    51 52 181 182 DDR_B_D39
    DDR_B_DQS#2 53 VSS_25 VSS_26 54 DDRA_MB_DM2 RD14 RD15 RD16 DDR_B_D38 183 VSS_60 DQ39 184
    DDR_B_DQS2 55 DQS2_c DM2_n/DBl2_n 56 @ @ 185 DQ38 VSS_61 186 DDR_B_D35
    57 DQS2_t VSS_27 58 DDR_B_D22 10K_0402_5% 10K_0402_5% 10K_0402_5% DDR_B_D34 187 VSS_62 DQ35 188
    DDR_B_D23 59 VSS_28 DQ22 60 189 DQ34 VSS_63 190 DDR_B_D45
    2

    2
    61 DQ23 VSS_29 62 DDR_B_D18 DDR_B_D44 191 VSS_64 DQ45 192
    DDR_B_D19 63 VSS_30 DQ18 64 SA0_CHB_P SA1_CHB_P SA2_CHB_P 193 DQ44 VSS_65 194 DDR_B_D41
    65 DQ19 VSS_31 66 DDR_B_D28 DDR_B_D40 195 VSS_66 DQ41 196
    DDR_B_D29 67 VSS_32 DQ28 68 197 DQ40 VSS_67 198 DDR_B_DQS#5
    DQ29 VSS_33 VSS_68 DQS5_c

    2
    DDR_B_D24 DDRA_MB_DM5 DDR_B_DQS5
    2

    69 70 199 200
    DDR_B_D25 71 VSS_34 DQ24 72 201 DM5_n/DBl5_n DQS5_t 202
    DQ25 VSS_35 RD18 VSS_69 VSS_70
    73 74 DDR_B_DQS#3 0_0402_5% 0_0402_5% DDR_B_D46 203 204 DDR_B_D47
    DDRA_MB_DM3 VSS_36 DQS3_c DDR_B_DQS3 0_0402_5% RD19 DQ46 DQ47
    75 76 RD17 205 206
    77 DM3_n/DBl3_n DQS3_t 78 DDR_B_D42 207 VSS_71 VSS_72 208 DDR_B_D43

    1
    VSS_37 VSS_38 DQ42 DQ43
    1

    DDR_B_D30 DDR_B_D31
    1

    79 80 209 210
    81 DQ30 DQ31 82 @ DDR_B_D52 211 VSS_73 VSS_74 212 DDR_B_D53
    DDR_B_D26 83 VSS_39 VSS_40 84 DDR_B_D27 213 DQ52 DQ53 214
    85 DQ26 DQ27 86 DDR_B_D49 215 VSS_75 VSS_76 216 DDR_B_D48
    87 VSS_41 VSS_42 88 +1.2V 217 DQ49 DQ48 218
    89 CB5/NC CB4/NC 90 DDR_B_DQS#6 219 VSS_77 VSS_78 220 DDRA_MB_DM6
    91 VSS_43 VSS_44 92 SPD Address = 2H DDR_B_DQS6 221 DQS6_c DM6_n/DBl6_n 222
    93 CB1/NC CB0/NC 94 1023: change 0 ohm to R SHORT 223 DQS6_t VSS_79 224 DDR_B_D54
    VSS_45 VSS_46 VSS_80 DQ54
    1

    95 96 DDR_B_D55 225 226


    97 DQS8_c DM8_n/DBl_n/NC 98 @ RD20 227 DQS5 VSS_81 228 DDR_B_D50
    B 99 DQS8_t VSS_47 100 DDR_B_D51 229 VSS_82 DQ50 230 B
    101 VSS_48 CB6/NC 102 1K_0402_1% 231 DQ51 VSS_83 232 DDR_B_D60
    103 CB2/NC VSS_49 104 DDR_B_D61 233 VSS_84 DQ60 234
    2

    105 VSS_50 CB7/NC 106 235 DQ61 VSS_85 236 DDR_B_D57


    107 CB3/NC VSS_51 108 DDR4_B_DRAMRST# DDR_B_D56 237 VSS_86 DQ57 238
    DDR_B_CKE0 109 VSS_52 RESET_n 110 DDR_B_CKE1 DDR4_B_DRAMRST# 6 239 DQ56 VSS_87 240 DDR_B_DQS#7
    6 DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 6 DDRA_MB_DM7 VSS_88 DQS7_c DDR_B_DQS7
    111 112 241 242
    DDR_B_BG1 113 VDD_1 VDD_2 114 DDR_B_ACT_N 243 DM7_n/DBl7_n DQS7_t 244
    6 DDR_B_BG1 DDR_B_BG0 BG1 ACT_n DDR_B_ALERT_N DDR_B_ACT_N 6 DDR_B_D62 VSS_89 VSS_90 DDR_B_D63
    115 116 245 246
    6 DDR_B_BG0 BG0 ALERT_n DDR_B_ALERT_N 6 DQ62 DQ63
    117 118 247 248
    DDR_B_MA12 119 VDD_3 VDD_4 120 DDR_B_MA11 DDR_B_D58 249 VSS_91 VSS_92 250 DDR_B_D59
    DDR_B_MA9 121 A12 A11 122 DDR_B_MA7 251 DQ58 DQ59 252
    A9 A7 1 RD21 APU_SMB_CK0 VSS_93 VSS_94 APU_SMB_DA0
    123 124 7,9,14 APU_SMB_CK0 253 254
    DDR_B_MA8 VDD_5 VDD_6 DDR_B_MA5 SCL SDA SA0_CHB_P APU_SMB_DA0 7,9,14
    125 126 CD59 2 1 255 256
    DDR_B_MA6 A8 A5 DDR_B_MA4 +3VS VDDSPD SA0
    127 128 EMC_NS@ 257 258
    129 A6 A4 130 2 0.1U_0402_10V7-K 259 VPP_1 VTT 260 SA1_CHB_P
    VDD_7 VDD_8 0_0402_5% VPP_2 SA1
    1 1
    CD60 CD61 261 262
    GND_1 GND_2
    ARGOS_D4AR0-26005-1P40 0.1U_0402_10V7-K 2.2U_0402_6.3V6-M ARGOS_D4AR0-26005-1P40
    2 2
    ME@ ME@

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/16 Deciphered Date 2018/06/01 DDR4 CH-B PRIMARY


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU 1.0
    Date: Tuesday, April 10, 2018 Sheet 15 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 VGA Notes List
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 16 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 ATI_R17M-M1-70_PCIE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 17 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 ATI_R17M-M1-70_Main_MSIC
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 18 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 ATI_R17M-M1-70_TMDP
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 19 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 ATI_R17M-M1-70_DP Power
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 20 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/16 Deciphered Date 2018/06/01 ATI_R17M-M1-70_Power


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 21 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 ATI_R17M-M1-70_MEM IF
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 22 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 ATI_R17M-M1-70_VRAM_A
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 23 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 ATI_R17M-M1-70_VRAM_B
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 24 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    M.2 SSD(M TYPE)

    +3VS
    C C

    2
    R6901
    0_0805_5%

    1
    @
    JSSD1

    1 2 +3VS_SSD
    3 GND_1 3.3V_1 4
    PCIE3_SSD_CRX_DTX_N 5 GND_2 3.3V_2 6
    5 PCIE3_SSD_CRX_DTX_N PCIE3_SSD_CRX_DTX_P PERN3 N/C_2
    7 8
    5 PCIE3_SSD_CRX_DTX_P PERP3 N/C_3
    9 10
    PCIE3_SSD_CTX_DRX_N_C 11 GND_3 DAS/DSS#/LED1# 12
    5 PCIE3_SSD_CTX_DRX_N_C PCIE3_SSD_CTX_DRX_P_C PETN3 3.3V_3
    13 14
    5 PCIE3_SSD_CTX_DRX_P_C PETP3 3.3V_4
    15 16
    PCIE2_SSD_CRX_DTX_N 17 GND_4 3.3V_5 18
    5 PCIE2_SSD_CRX_DTX_N PCIE2_SSD_CRX_DTX_P PERN2 3.3V_6
    19 20
    5 PCIE2_SSD_CRX_DTX_P PERP2 N/C_4
    21 22
    PCIE2_SSD_CTX_DRX_N_C 23 GND_5 N/C_5 24
    5 PCIE2_SSD_CTX_DRX_N_C PETN2 N/C_6

    1
    PCIE2_SSD_CTX_DRX_P_C 25 26
    5 PCIE2_SSD_CTX_DRX_P_C PETP2 N/C_7
    27 28 R3100
    PCIE1_SSD_CRX_DTX_N 29 GND_6 N/C_8 30
    5 PCIE1_SSD_CRX_DTX_N PERN1 N/C_9 10K_0402_5%
    PCIE1_SSD_CRX_DTX_P 31 32
    5 PCIE1_SSD_CRX_DTX_P PERP1 N/C_10 @
    33 34

    2
    PCIE1_SSD_CTX_DRX_N_C 35 GND_7 N/C_11 36 @
    5 PCIE1_SSD_CTX_DRX_N_C PCIE1_SSD_CTX_DRX_P_C PETN1 N/C_12 SSD_DEVSLP
    37 38 R901 1 2 0_0402_5%
    5 PCIE1_SSD_CTX_DRX_P_C PETP1 DEVSLP SSD_DEVSLP 7
    39 40
    PCIE0_SSD_CRX_DTX_N 41 GND_8 N/C_13 42
    5 PCIE0_SSD_CRX_DTX_N PCIE0_SSD_CRX_DTX_P PERN0/SATA-B+ N/C_14
    43 44
    5 PCIE0_SSD_CRX_DTX_P PERP0/SATA-B- N/C_15
    45 46
    PCIE0_SSD_CTX_DRX_N_C 47 GND_9 N/C_16 48
    5 PCIE0_SSD_CTX_DRX_N_C PCIE0_SSD_CTX_DRX_P_C PETN0/SATA-A- N/C_17 SSD_RST#
    49 50
    B 5 PCIE0_SSD_CTX_DRX_P_C PETP0/SATA-A+ PERST# CLKREQ_PCIE7_SSD# B
    51 52
    CLK_PCIE_SSD# GND_10 CLKREQ# CLKREQ_PCIE7_SSD# 9
    53 54 TP264 1
    9 CLK_PCIE_SSD# CLK_PCIE_SSD REFCLKN PEWAKE#
    55 56
    9 CLK_PCIE_SSD REFCLKP N/C_18
    57 58
    GND_11 N/C_19
    59 NC NC 60
    61 NC NC 62
    63 NC NC 64
    65 NC NC 66 @
    67 68 SUSCLK_SSD R902 1 2 0_0402_5% RTCCLK_R
    SSD_DET N/C_1 SUSCLK RTCCLK_R 9,37
    R701 69 70
    SSD_DTCT# 2 1 0_0402_5% SSD_DTCT#_R 71 PEDET 3.3V_7 72
    41 SSD_DTCT# GND_12 3.3V_8
    @ 73 74
    75 GND_13 3.3V_9
    GND_14
    2 1 1
    77 76 @
    PEG1 PEG2 C6902 C6901 C6903
    10U_0402_6.3V6-M .01U_0402_50V7-K 4.7U_0402_6.3V6-M
    ARGOS_NASM0-S6705-TSH4 1 2 2
    1023：Add SSD detect function
    ME@

    0814: Follow 720s for reserves

    +3VS_SSD

    +3VS_SSD
    1

    R904
    1

    @
    10K_0201_5% R801 1 @ 2 0_0402_5% R800
    2

    @ 10K_0201_5%
    R903 1 2 0_0402_5% SSD_DET
    A 9 SSD_SATA_PCIE_DET# D747 A
    2

    PLT_RST#_R_G 3
    7 PLT_RST#_R_G SSD_RST#
    1
    1

    APU_SSD_RST# 2
    7 APU_SSD_RST#
    @
    R905
    SSD_DET# BAT54AWT1G_SOT323-3
    0--SATA
    2

    10K_0201_5%

    1--PCIE R02
    2

    @ 100K_0402_5%
    Security Classification LC Future Center Secret Data Title
    1

    Issued Date 2017/02/16 Deciphered Date 2018/06/01 BLANK page


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 25 of 65

    5 4 3 2 1
    5 4 3 2 1

    LCDVDD Circuit
    +LCDVDD_CON
    +3VS
    W= 60 mil
    W= 60 mil 5
    U1
    1 +LCDVDD_CON
    IN OUT Q1
    @
    2 @ R2 2N7002WT1G_SC-70-3
    1 GND 1 2 1 3 LOGO_LED_CON

    S
    APU_ENVDD_R +3VALW

    4.7U_0603_6.3V6-K
    C1 4 3
    1U_0402_6.3VA-K EN OCB 2.2K_0402_5%
    2 1 1
    SY6288C20AAC_SOT23-5
    C2 C255

    1
    D D
    1U_0402_6.3VA-K

    G
    2
    2 2
    RC102
    R3
    100K_0402_5% LOGO_LED# 1 2
    42 LOGO_LED#

    2
    3.6K_0402_5%

    LOGO LED

    VIH 1.35V

    R6
    F7
    V9B+ 2A 80 mil 1 2 C3 2A 80 mil 1 2 +LEDVDD

    4.7U_0805_25V6-K
    3A_32V_ERBRD3R00X
    R391 0_0805_5%
    1
    APU_ENVDD 2 1 0_0402_5% APU_ENVDD_R @
    8 APU_ENVDD
    @
    2

    C C

    +3VS

    eDP/CMOS/LOGO-LED CONN.
    Dooku JINN

    R9
    D_J_CTL leave as NC conntect to GND
    2 1 D_J_CTL by EDP cable

    100K_0402_5% JLCD1
    1
    1
    +LEDVDD +LEDVDD W= 80 mil 2
    2
    3
    4 3
    5 4
    6 5
    @ D_J_CTL 7 6
    9 D_J_CTL PANEL_BKLT_CTRL 7
    R10 1 2 0_0402_5% 8 PANEL_BKLT_CTRL 8
    BKOFF# 9 8
    42 BKOFF# 9
    10
    EXC24CH900U_4P 11 10
    USB20_N5_CAMERA 4 3 USB20_N5_CAMERA_R 12 11
    10 USB20_N5_CAMERA 4 3 12
    13
    CPU_EDP_HPD 14 13
    B USB20_P5_CAMERA USB20_P5_CAMERA_R 8 CPU_EDP_HPD 14 B
    1 2 15
    +3VS_CMOS 10 USB20_P5_CAMERA 1 2 16 15
    L21 EMC@ 17 16
    +3VS_DMIC +LCDVDD_CON 17
    +LCDVDD_CON W= 60 mil 18
    18
    R11 1 2 0_0402_5% 19
    BKOFF# 20 19
    C8 C9 CPU_EDP_AUX# C4 1 2 0.1U_0402_10V7-K CPU_EDP_AUX#_CON 21 20
    @ 8 CPU_EDP_AUX#
    EMC_NS@ EMC_NS@ CPU_EDP_HPD CPU_EDP_AUX C5 1 2 0.1U_0402_10V7-K CPU_EDP_AUX_CON 22 21
    8 CPU_EDP_AUX
    1

    R12 23 22
    2200P_0402_50V7-K

    2200P_0402_50V7-K

    R13 CPU_EDP_TX0+ C6 1 2 0.1U_0402_10V7-K CPU_EDP_TX0+_CON 24 23


    100K_0402_5%

    1 1 8 CPU_EDP_TX0+
    1

    CPU_EDP_TX0- C7 1 2 0.1U_0402_10V7-K CPU_EDP_TX0-_CON 25 24


    100K_0402_5%

    8 CPU_EDP_TX0- 25
    26
    +3VS CPU_EDP_TX1+ C10 1 2 0.1U_0402_10V7-K CPU_EDP_TX1+_CON 27 26
    8 CPU_EDP_TX1+
    2

    2 2 CPU_EDP_TX1- C11 1 2 0.1U_0402_10V7-K CPU_EDP_TX1-_CON 28 27


    8 CPU_EDP_TX1- 28
    29
    2

    30 29 41
    2

    F24 DMIC_DATA 31 30 GND1 42


    38 DMIC_DATA DMIC_CLK 31 GND2
    1A_32V_ERBRD1R00X

    32 43
    38 DMIC_CLK 32 GND3
    15/12/10 AMD req. 33 44
    USB20_N5_CAMERA_R 34 33 GND4 45
    USB20_P5_CAMERA_R 35 34 GND5 46
    36 35 GND6 47
    1

    LOGO_LED_CON 36 GND7
    0.5A 37
    37 GND8
    48
    38 49
    R14 +3VS_DMIC 38 GND9
    R15
    1 2 0_0402_5%
    +3VS_CMOS
    W= 40 mil 39
    39 GND10
    50
    1 2 0_0402_5% 40 51
    40 GND11
    HIGHS_WS12401-S0151-HF
    1023: change 0 ohm to R SHORT
    ME@

    EMC requset. Close to JLCD ESD request

    A +LEDVDD +LCDVDD_CON LOGO_LED# A


    3

    2 RF_NS@ 1 D1
    C12 RF_NS@ EMC@
    2200P_0402_50V7-K C13 PESD5V0U2BT_SOT23-3
    2200P_0402_50V7-K
    1 2
    1

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 eDP CONN
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 26 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 DP MUX
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 27 of 65
    5 4 3 2 1
    5 4 3 2 1

    EXC24CH900U_4P
    EXC24CH900U_4P HDMI_TX2+_REOUT 4 3 HDMI_TX2+_CON
    HDMI_TX0+_REOUT 4 3 HDMI_TX0+_CON 4 3
    4 3
    HDMI_TX2-_REOUT 1 2 HDMI_TX2-_CON
    HDMI_TX0-_REOUT 1 2 HDMI_TX0-_CON 1 2
    1 2 L2 EMC@
    L1 EMC@

    D D
    EXC24CH900U_4P EXC24CH900U_4P
    HDMI_TX1+_REOUT 4 3 HDMI_TX1+_CON HDMI_TXC+_REOUT 4 3 HDMI_TXC+_CON
    4 3 4 3

    HDMI_TX1-_REOUT 1 2 HDMI_TX1-_CON HDMI_TXC-_REOUT 1 2 HDMI_TXC-_CON


    1 2 1 2
    L3 EMC@ L4 EMC@

    +3VS +3VS

    Vgs(th) Max >=2.0V

    5
    G
    +3VS Q23B
    R1015

    1
    C
    RP2 2 1 2 150K_0402_5% HDMI_HPD_CON

    2
    1 4 HDMI_CLK 4 3 HDMI_CLK_CON B

    S
    8 HDMI_CLK

    D
    2 3 HDMI_DAT E MMBT3904WH_SOT323-3 R1016

    3
    L2N7002KDW1T1G_SOT363-6 HDMI_HPD Q24 100K_0402_5%
    8 HDMI_HPD

    2
    2K_0404_4P2R_5%

    2
    Q23A

    1
    R20
    +5VS_HDMI 100K_0402_5%
    1 6 HDMI_DAT_CON

    S
    8 HDMI_DAT

    1
    C C
    L2N7002KDW1T1G_SOT363-6

    RP1
    1 4 HDMI_CLK_CON
    2 3 HDMI_DAT_CON

    1.8K_0404_4P2R_5%

    +5VS_HDMI

    PMOS ｜ ｜= < 2A ; Vgs(th)<-1.2 V


    Id
    +5VS +5VS_HDMI_F +5VS_HDMI

    HDMI CONN.
    F25
    1 2

    1.1A_8V_1206L110THYR JHDMI1 ME@


    200mA 1
    HDMI_HPD_CON 19
    D2 RCLAMP0524PATCT_SLP2510P8-10-9 C16 18 HP_DET
    0.1U_0402_6.3V7-K 17 +5V
    2 HDMI_DAT_CON 16 DDC/CEC_GND
    1 3 Q22 HDMI_CLK_CON 15 SDA

    S
    9 1 14 SCL
    +5VS_HDMI HDMI_HPD_CON 8 HDMI_HPD_CON +5VS_HDMI Reserved
    2 LP2301ALT1G_SOT23-3 13 20
    HDMI_CLK_CON 7 4 HDMI_CLK_CON HDMI_TXC-_CON 12 CEC GND1

    G
    2
    HDMI_DAT_CON 6 5 HDMI_DAT_CON 11 CK- 21
    SUSP HDMI_TXC+_CON 10 CK_shield GND2
    51 SUSP 9V-->5.1V HDMI_TX0-_CON CK+
    9 22
    8 D0- GND3
    13V-->7.4V HDMI_TX0+_CON 7 D0_shield 23
    EMC@ HDMI_TX1-_CON 6 D0+ GND4
    3

    0823:Change Fuse to 1.1A follow LNV SPEC 5 D1-


    HDMI_TX1+_CON 4 D1_shield
    B B
    HDMI_TX2-_CON 3 D1+
    2 D2-
    HDMI_TX2+_CON 1 D2_shield
    D2+

    SINGA_2HE3Y62-000111F
    D3 RCLAMP0524PATCT_SLP2510P8-10-9
    H_HDMI_TX0+ CRE1 1 2 0.1U_0402_10V7-K HDMI_TX0+_REOUT
    8 H_HDMI_TX0+

    HDMI_TXC+_CON 9 1 HDMI_TXC+_CON
    HDMI_TXC-_CON 8 2 HDMI_TXC-_CON H_HDMI_TX0- CRE2 1 2 0.1U_0402_10V7-K HDMI_TX0-_REOUT
    HDMI_TX0+_CON HDMI_TX0+_CON 8 H_HDMI_TX0-
    7 4
    HDMI_TX0-_CON 6 5 HDMI_TX0-_CON

    H_HDMI_TX1+ CRE3 1 2 0.1U_0402_10V7-K HDMI_TX1+_REOUT


    8 H_HDMI_TX1+

    EMC@ HDMI_TX0+_CON RRE1 1 2 499_0402_1% HDMI_GND


    3

    H_HDMI_TX1- CRE4 1 2 0.1U_0402_10V7-K HDMI_TX1-_REOUT HDMI_TX0-_CON RRE2 1 2 499_0402_1%


    8 H_HDMI_TX1- HDMI_TX1+_CON RRE3 1 2 499_0402_1%
    HDMI_TX1-_CON RRE4 1 2 499_0402_1%
    HDMI_TX2+_CON RRE5 1 2 499_0402_1%
    H_HDMI_TX2+ CRE5 1 2 0.1U_0402_10V7-K HDMI_TX2+_REOUT HDMI_TX2-_CON RRE6 1 2 499_0402_1%
    8 H_HDMI_TX2+ HDMI_TXC+_CON RRE7 1 2 499_0402_1%
    HDMI_TXC-_CON RRE8 1 2 499_0402_1%

    D4 RCLAMP0524PATCT_SLP2510P8-10-9 H_HDMI_TX2- CRE6 1 2 0.1U_0402_10V7-K HDMI_TX2-_REOUT


    8 H_HDMI_TX2-

    1
    D

    +3VS 2
    G
    HDMI_TX1-_CON 9 1 HDMI_TX1-_CON H_HDMI_TXC+ CRE7 1 2 0.1U_0402_10V7-K HDMI_TXC+_REOUT Q4 S
    8 H_HDMI_TXC+

    3
    HDMI_TX1+_CON 8 2 HDMI_TX1+_CON 2N7002WT1G_1N_SC-70-3
    HDMI_TX2-_CON 7 4 HDMI_TX2-_CON
    A HDMI_TX2+_CON HDMI_TX2+_CON A
    6 5
    H_HDMI_TXC- CRE8 1 2 0.1U_0402_10V7-K HDMI_TXC-_REOUT
    8 H_HDMI_TXC-

    EMC@
    3

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 HDMI CONN
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 28 of 65
    5 4 3 2 1
    5 4 3 2 1

    SATA HDD Redriver +3VS

    +3VS

    1
    D D
    @
    R21
    4.7K_0201_5%
    U3
    Close APU

    2
    7 10
    EN VDD1 20
    SATA_CTX_DRX_P0 C17 1 2 .01U_0402_16V7-K SATA_CTX_C_DRX_P0 1 VDD2
    5 SATA_CTX_DRX_P0 SATA_CTX_DRX_N0 SATA_CTX_C_DRX_N0 2 A_INP
    5 SATA_CTX_DRX_N0 C18 1 2 .01U_0402_16V7-K 6 R22 1 2 5.1K_0402_1%
    A_INN REXT 16 DEW
    SATA_CRX_DTX_P0 C19 1 2 .01U_0402_16V7-K SATA_CRX_C_DTX_P0 5 DEW
    5 SATA_CRX_DTX_P0 SATA_CRX_DTX_N0 SATA_CRX_C_DTX_N0 4 B_OUTP A_DE
    C20 1 2 .01U_0402_16V7-K 9
    5 SATA_CRX_DTX_N0 B_OUTN A_DE B_DE
    8
    A_EQ1 17 B_DE
    A_EQ2 18 A_EQ1 15 SATA_PTX_DRX_P0 C21 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P0
    SATA_PTX_C_DRX_P0 30
    B_EQ1 19 A_EQ2 A_OUTP 14 SATA_PTX_DRX_N0 C22 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N0
    SATA_PTX_C_DRX_N0 30
    B_EQ2 13 B_EQ1 A_OUTN
    B_EQ2 11 SATA_PRX_DTX_P0 C23 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P0
    B_INP SATA_PRX_DTX_N0 C24 SATA_PRX_C_DTX_N0 SATA_PRX_C_DTX_P0 30
    3 12 1 2 .01U_0402_16V7-K
    GND1 B_INN SATA_PRX_C_DTX_N0 30
    21
    EPAD
    PS8527C_TQFN20_4X4

    C C

    B B

    +3VS +3VS +3VS +3VS +3VS +3VS +3VS

    +3VS
    1

    R23 R24 R25 R26 R27 R28


    4.7K_0402_5% 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% R29 @
    4.7K_0201_5%
    2

    A_EQ1 A_EQ2 B_EQ1 B_EQ2 A_DE B_DE DEW


    1 1 1
    1

    1
    1

    R30 R31 R33 R34 R35 C25 C26 C27


    @ 4.7K_0402_5% @ 4.7K_0402_5% R32 @ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% R36 @ .01U_0402_16V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K
    @ 4.7K_0402_5% 4.7K_0201_5% 2 2 2
    2

    2
    2

    Close to pin 10. Close to pin 20.

    Equalization level setting for Channel x(x=A/B), De-emphasis level setting for Channel x(x=A/B), De-emphasis widith adjustment,
    internally tied to VDD/2 internally tied to VDD/2 internally pulled down
    [x_EQ2, x_EQ1] == [x_DE] == [DEW] ==
    L/M: for channel loss up to 2.4dB M: -3.5dB (default) M: for SATA3(default)
    L/L: for channel loss up to 7.4dB L: 0dB L: for SATA3
    L/H: for channel loss up to 14.4dB H: -6dB H: for SATA2
    M/M: for channel loss up to 12.2dB (default)
    M/L: for channel loss up to 9.4dB
    M/H: for channel loss up to 13.3dB
    H/M: for channel loss up to 6.2dB
    H/L: for channel loss up to 11.2dB
    H/H: for channel loss up to 5dB
    A A

    Follow Vendor suggest

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 BLANK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 29 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    SATA HDD CONN. SATA HDD CONN.

    +5VS
    1A
    C JHDD1 ME@ C

    @
    R396 1 2 0_0805_5% +5VS_HDD 1
    +5VS 1
    2
    3 2
    4 3
    5 4
    1 1 1 1 5
    C28 C29 C30 C31 HDD_DETECT# 6
    @ @ 41 HDD_DETECT# 7 6
    10U_0805_10V6-K 10U_0805_10V6-K 1U_0402_10V6-K 0.1U_0402_10V7-K 8 7
    2 2 2 2 SATA_PRX_C_DTX_P0 9 8
    @ 29 SATA_PRX_C_DTX_P0 SATA_PRX_C_DTX_N0 9
    10
    29 SATA_PRX_C_DTX_N0 10
    11
    SATA_PTX_C_DRX_N0 12 11
    29 SATA_PTX_C_DRX_N0 SATA_PTX_C_DRX_P0 12
    29 SATA_PTX_C_DRX_P0 13 15
    14 13 GND15 16
    14 GND16

    HIGHS_FC5AF141-3181H

    R390
    HDD_DEVSLP 2 1 0_0402_5%
    7 HDD_DEVSLP
    @

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 SATA HDD
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 30 of 65
    5 4 3 2 1
    5 4 3 2 1

    +VBUS_CONN +5VALW +LDO_3V3


    1

    40V PROPECTION

    1
    R45

    1
    200K_0402_1%
    R41 @
    R42
    0_0402_5%
    RA=R42 Wait symbol AON7264 +VBUS_Protect
    590K_0402_1%
    2

    D Q167 D

    2
    AON7264E_DFN8-5

    2
    VMON R971 1
    LOC_PWR_MON 0.005_1206_1% 2
    1 2 5 3
    +VBUS_CONN
    1

    1
    1 @
    R40 R47 @

    4
    10K_0402_1% R46
    10K_0402_1% RB=R47
    10K_0402_1%
    R972
    2 47_0402_5%
    2

    2
    10U_0805_25V6-K 1 2
    2

    C904
    R968 @
    @ 10_0402_1% 1
    @ C905
    1 2

    1
    2 1 2
    0.47U_0402_25V6-K R969
    C903 100K_0402_1%
    0.01U_0603_50V7-K

    1
    1 @
    @

    5
    R965
    @
    20K_0402_1%

    VIN

    ISENSE

    DRV

    VOUT
    R973

    2
    1 8 1 2
    @ VCNTL POK +LDO_3V3
    10 @ U17 7 100K_0402_1%
    VINSEL OCSET @

    1
    R967 9 6
    +3VL 3.9K_0402_5% EN DELAY

    1
    GND
    1
    1 R975

    2
    R974 27.4K_0402_1%
    @
    100K_0402_1% C906

    11
    C 0.1U_0402_25V6-K C

    2
    4.7K_0402_5%1 2 R51 EC_SMB_CK2 2
    @ @

    2
    R970
    @
    0_0402_5% APL3542AQBI-TRG_TDFN10_3X3
    4.7K_0402_5%1 2 R52 EC_SMB_DA2 1 2
    4.7K_0402_5% 1 2 R56 INT#_TYPEC @
    +LDO_3V3
    +LDO_3V3

    4.7K_0402_5% 1 2 R54 I2C1_IRQ#

    4.7K_0402_5%1 2 R393 REPETER_SDA


    +VCON_IN
    4.7K_0402_5%1 2 R394 REPETER_SCL

    R48 2 @ 1 0_0603_5% +VCON_IN_R

    +LDO_3V3

    1
    C32
    10U_0603_10V6-K +5V_IN

    2
    4.7K_0402_5%1 2 R962 SRC_PS_EN

    10U_0402_6.3V6-M
    @

    4.7U_0402_6.3V6M
    1 3
    D

    4.7K_0402_5%1 @ 2 R961 SRC_PS_FO


    Q6 1 1
    AO3413_SOT23-3 C33 C34
    VDS=-20
    G
    2

    SB93413000J
    B VGS=+-8V B
    2 2
    Id=3A
    Vth=-1v +LDO_3V3
    TYPEC_GPIO10 R55 2 1 47K_0402_5%
    1
    +VBUS_CONN
    C35 4.7U_0402_6.3V6M
    U5
    2

    13

    21

    15
    VCON_IN

    5V_IN

    LDO_3V3
    1

    R49 R57
    150_0603_1% SNK_PS_EN 7 11 TYPEC_REN_R 2 1 0_0402_5% TYPEC_REN
    32 SNK_PS_EN SNK_PS_ACK AUX_N/MGPIO5 C_DM/BB_DM VBUS_DSCHG TYPEC_REN 33
    6 10 @
    32 SNK_PS_ACK AUX_P/MGPIO4 C_DP/BB_DP C36 1 2 220P_0402_50V7-J
    High enable discharge
    2

    INT#_TYPEC_CPU R43 1 @ 2 0_0402_5% I2C1_IRQ# 9 14 USBC_CC2


    Low disable discharge 10 INT#_TYPEC_CPU SRC_PS_FO H_DM/MGPIO3 CC2 USBC_CC1 USBC_CC2 33
    1 @ 2 8 12 USBC_CC1 33
    32 SRC_PS_FO R976 0_0402_5% H_DP/MGPIO2 CC1
    C37 1 2 220P_0402_50V7-J
    1

    R50 D
    VBUS_DSCHG 1 2 2 Q5
    G 2N7002WT1G_1N_SC-70-3 TYPEC_GPIO10 22 1 INT#_TYPEC_R R58 2 1 INT#_TYPEC INT#_TYPEC 42
    0_0402_5% S SB000019400 I2C_EN/GPIO10 RTS5457-GR SM_INT/GPIO4 @ 0_0402_5%
    3
    1

    SRC_PS_EN 5 24 EC_SMB_DA2_R R215 2 1 EC_SMB_DA2


    R53 32 SRC_PS_EN I2C_INT/GPIO9 SM_SDA/GPIO6 EC_SMB_DA2 42
    @ 0_0402_5%
    VDS=60 REPETER_SDA 23 3 EC_SMB_CK2_R R216 2 1 EC_SMB_CK2
    100K_0402_5% 10,33 REPETER_SDA I2C_SDA/GPIO8 SM_SCL/GPIO5 EC_SMB_CK2 42
    VGS=20 @ 0_0402_5%
    REPETER_SCL
    Id=320mA 10,33 REPETER_SCL 4
    2

    1023: change 0 ohm to R SHORT I2C_SCL/GPIO7


    R59
    20 1 2 6.2K_0402_1%
    REXT
    LOC_PWR_MON R60 0_0402_5%
    19 16 1 2
    LOC_PWR_MON DB_CFG @
    SRC_PS_FLT 18 2 DDIP3_HPD
    32 SRC_PS_FLT IMON_MGPIO8 HPD/GPIO3 DDIP3_HPD 8,33
    A VMON 17 25 A
    VMON_MGPIO9 E-PAD

    RTS5457-GR_QFN24_4X4

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 MUX & PD
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 31 of 65
    5 4 3 2 1
    A B C D E

    +5VALW +VCON_IN

    R61
    2 1

    0_0603_5%

    1023: change 0 ohm to R SHORT


    1 +5V_IN 1

    RB751V-40_SOD323-2 D5
    2 1

    Vr=30V
    If=200mA

    +VBUS_CONN

    RB751V-40_SOD323-2 D6 U6
    2 1 3 4
    IN OUT
    1
    C38 need 35V P/N R62 1 2 100K_0402_5% 1 ADJ
    6
    Vr=30V EN 1

    1
    2.2U_0603_50V6-K C39
    Ifsm=200mA 2 5 2 R63
    GND NC 47P_0402_50V8-J
    73.2K_0402_1%

    2
    SYV634DEC_DFN6_2X2 2
    C40

    2
    2.2U_0402_10V6-K

    1
    1
    D
    2
    42 PD_VBUS_C_CTRL1_EC G Q7 vref0.6V

    2
    2N7002KW_SOT323-3
    R64 S SB000009Q8J R65

    3
    100K_0402_5% 10K_0402_1%
    2 +5VALW 2

    1
    +VBUS_CONN
    +LDO_3V3
    1 1
    C41 C42
    3A

    1
    100U_1206_6.3V6-M 1U_0603_25V7-K
    2 2 J7

    1
    JUMP_43X118

    1
    @

    2
    R66 R67
    10K_0402_1% 10K_0402_1%

    2
    +LDO_3V3 R68

    2
    D7 2 @ 1
    SCS00006S00
    U7
    2

    RB751V-40_SOD323-2 +VBUS_Protect
    R69 A1 B1 2 1 10K_0402_1%
    A2 VIN1 VCP1 B2 @ U8
    10K_0402_1% VIN2 VCP2 C1
    VCP3
    1

    31 SRC_PS_FLT SRC_PS_FLT A4 C2 B2 B3
    FLT# VBUS1 D1 C2 VBUS1 OVLO A2 SNK_PS_ACK
    31 SRC_PS_EN SRC_PS_EN VBUS2 VBUS2 ACK SNK_PS_ACK 31
    B4 D2 D2
    EN VBUS3 E1 VBUS3 C3
    31 SRC_PS_FO SRC_PS_FO C4 A3 VSYSTEM2 E2 VBUS4 GND1 D3
    FO ILIM VBUS5 GND2 E3
    1 GND3
    1

    B3 A1
    GND1 VINT1
    1

    3 C3 R72 C43 B1 A3 SNK_PS_EN 3


    R70 R71 GND2 D3 16K_0402_1% 4.7U_0805_50V6-K C1 VINT2 EN# SNK_PS_EN 31
    GND3 2 VINT3
    100K_0402_5% 100K_0402_5%
    CAP
    D4
    close U4301.D2 D1
    VINT4 SNK_PS_EN need to check SNK_PS_ENˇ s behavi or
    2

    1
    NX5P3290UKZ_WLCSP16 1 1
    2

    NX20P5090UK_WLCSP15 R73 R74


    C44 C45 100K_0402_5%@ 0_0402_5%

    2
    1000P_0402_50V7-K
    2
    2.2U_0603_50V6-K 1 close U4302.B2

    2
    C46
    4.7U_0805_50V6-K @
    2
    1

    R500
    @ 100K_0402_5%
    2
    2N7002KW_SOT323-3

    D
    2 Type_C_I_CTRL_P2
    @ G Type_C_I_CTRL_P2 42

    S Q34
    3

    R501
    100K_0402_5%
    2

    4 @ 4

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 RTS5455/POWER SWITCH
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 32 of 65
    A B C D E
    5 4 3 2 1

    @
    R88 1 2 2M_0402_1% USBC_DPAUX2
    +3V_REDP

    @
    R85 1 2 100K_0402_5% APU_DP3_AUXN_R R90 1 2 2M_0402_1% USBC_DPAUX1
    +3VALW +3V_REDP
    R76
    1 2 0_0603_5%
    R87 1 2 100K_0402_5% APU_DP3_AUXP_R

    10U_0805_10V6-K

    0.1U_0402_16V7-K

    0.1U_0402_16V7-K

    0.1U_0402_16V7-K

    0.1U_0402_16V7-K
    1 1 1 1 1

    C47 C50 C51 C52 C53 +LDO_3V3

    2 2 2 2 2
    +3V_REDP
    1

    C58
    1U_0402_10V6-K

    1
    +3V_REDP R1006 U10 2
    Check
    0 = 3.3-V configuration I/O voltage, 3.3-V I2C interface (Default) L = DisplayPort Disabled. 1K_0402_5% 10
    D 1 = 1.8-V configuration I/O voltage, 1.8-V I2C interface 0814: Follow DG change to 0.33U H = DisplayPort Enabled. VPWR D

    20

    28
    1

    6
    U18 USBC_DPAUX1 15 1 USBC_DPAUX1_CONN
    When I2C_EN = 0, this pin is not used by device.

    2
    1

    USBC_DPAUX2 14 SBU1 C_SBU1 2 USBC_DPAUX2_CONN

    VCC_3

    VCC_4
    VCC_1

    VCC_2
    R89 USBC0_1_RXP0 C60 1 20.33U_0402_10V6-KUSBC0_1_RXP0_R 9 40 TYPEC0_RXP2 TUSB_CTL1 SBU2 C_SBU2
    10 USBC0_1_RXP0 USBC0_1_RXN0
    @ 1K_0402_5% C62 1 20.33U_0402_10V6-KUSBC0_1_RXN0_R 10 URX2P DRX2P 39 TYPEC0_RXN2 USBC_CC1 12 4 USBC_CC1_CONN
    10 USBC0_1_RXN0 USBC0_1_TXP0 31 USBC_CC1
    C59 1 20.22U_0402_10V6-KUSBC0_1_TXP0_R 12 URX2N DRX2N 37 TYPEC0_TXP2 USBC_CC2 11 CC1 C_CC1 5 USBC_CC2_CONN

    2
    10 USBC0_1_TXP0 USBC0_1_TXN0 C61 1 20.22U_0402_10V6-KUSBC0_1_TXN0_R 13 UTX2P DTX2P 36 TYPEC0_TXN2 31 USBC_CC2 CC2 C_CC2
    2

    10 USBC0_1_TXN0 UTX2N DTX2N R1005 20 7


    TUSB_SEL APU_DP3_AUXP C67 1 2 0.1U_0402_10V7-K APU_DP3_AUXP_R 24 8 TUSB_DIR0 @ 100K_0402_5% 19 D1 RPD_G1 +LDO_3V3
    8 APU_DP3_AUXP APU_DP3_AUXN APU_DP3_AUXN_R AUXP DIR0 TUSB_DIR1 USB20_P_CON D2
    C69 1 2 0.1U_0402_10V7-K 25 11 17 6
    8 APU_DP3_AUXN AUXN DIR1 USB20_N_CON D3 RPD_G2
    R95 16 R91

    1
    1

    TUSB_SWAP 5 USBC_DPAUX1_MUX 2
    27 1 USBC_DPAUX1 D4 9 1 2
    R92 TUSB_SLP 7 SWAP SBU1 USBC_DPAUX2_MUX 2
    26 @ 1 0_0402_5% USBC_DPAUX2 3 FLT
    1K_0402_5% SLP_S0# SBU2 @ 0_0402_5% VBIAS 8 10K_0402_5%
    USBC0_0_TXP0 USBC0_0_TXP0_R TYPEC0_TXP1 2 GND1
    C64 1 2 0.22U_0402_10V6-K 16 33 R94 13
    10 USBC0_0_TXP0 USBC0_0_TXN0 C63 1 2 0.22U_0402_10V6-K USBC0_0_TXN0_R 15 UTX1P DTX1P 34 TYPEC0_TXN1 GND2 18
    C68 SA000086810
    2

    10 USBC0_0_TXN0 USBC0_0_RXP0 C66 1 2 0.33U_0402_10V6-K USBC0_0_RXP0_R 19 UTX1N DTX1N 30 TYPEC0_RXP1 GND3 21


    10 USBC0_0_RXP0 USBC0_0_RXN0 USBC0_0_RXN0_R URX1P DRX1P TYPEC0_RXN1 0.1U_0603_50V7-K THERMAL_PAD
    C65 1 2 0.33U_0402_10V6-K 18 31 1
    10 USBC0_0_RXN0 URX1N DRX1N R97 TPD8S300RUKR_WQFN20_3X3
    TUSB_I2CEN 17 21 REPETER_SCL_F 2 1 REPETER_SCL
    TUSB_UEQ0/A0 I2C_EN FLIP/SCL REPETER_SCL 10,31
    0814: Follow DG change to 0.33U 35 22 REPETER_SDA_F 2 @ 1 0_0402_5% REPETER_SDA
    TUSB_UEQ1/A1 UEQ0/A0 CTL0/SDA REPETER_SDA 10,31
    2 23 TUSB_CTL1 R96 @ 0_0402_5%
    UEQ1/A1 CTL1 32 DDIP3_HPD
    TUSB_DEQ0 HPDIN DDIP3_HPD 8,31
    38
    TUSB_DEQ1 29 DEQ0 14 TUSB_SEL
    +3V_REDP +3V_REDP +3V_REDP DEQ1 VIO_SEL
    TUSB_CFG0 3
    TUSB_CFG1 4 CFG0 41
    CFG1 GND
    I2C_EN=0 GPIO MODE
    1

    I2C_EN=1 I2C enable


    R93 R99 R100 TUSB544RNQR_WQFN40_4X6
    1K_0402_5% @ 1K_0402_5% @ 1K_0402_5% D39 EMC@ EMC@ D40

    +3V_REDP USB20_P_CON 1 2 2 1USB20_N_CON


    2

    +3V_REDP 1 2 2 1
    TUSB_I2CEN TUSB_UEQ0/A0 TUSB_UEQ1/A1 Check
    PESD5V0H1BSF SOD962 PESD5V0H1BSF SOD962 Reserves
    1

    1
    D41 EMC_NS@ EMC_NS@ D42

    1
    R101 R102 R103 R1000
    @ 20K_0402_5% 20K_0402_5% 20K_0402_5% R998 @ 1K_0402_5% USBC_CC2_CONN 1 2 2 1USBC_CC1_CONN
    @ 1K_0402_5% 1 2 2 1
    2

    2
    PESD5V0H1BSF SOD962 PESD5V0H1BSF SOD962

    2
    TUSB_DIR1 D43 EMC_NS@ EMC_NS@ D44
    Address 00 TUSB_DIR0
    USBC_DPAUX2_CONN
    1 2 2 1USBC_DPAUX1_CONN

    2
    1 2 2 1

    2
    R400 R999
    C TYPEC_REN 2 1 0_0402_5% TUSB_SLP R997 100K_0402_5% PESD5V0H1BSF SOD962 PESD5V0H1BSF SOD962 C
    31 TYPEC_REN @ 100K_0402_5%
    +3V_REDP

    1
    +3V_REDP

    1
    R400: for low consumption mode
    TUSB_I2CEN
    0 – RX Detect disabled R401&R1005&R1003: PWR Down mode for reserves
    R401 1 @ 2 0_0402_5%

    1 – RX Detect enabled (Default)


    1
    1

    R110
    R109 @ 1K_0402_5% +3V_REDP
    @ 1K_0402_5% +3V_REDP
    0 – Do not swap channel directions and EQ settings (Default)
    2

    1. – Swap channel directions and EQ settings


    2

    TUSB_SLP

    1
    TUSB_SWAP

    1
    R1004
    2

    R1002 @ 1K_0402_5%
    2

    R106 @ 1K_0402_5%
    R114 @ 100K_0402_5%

    2
    100K_0402_5%

    2
    +3V_REDP REPETER_SDA_F
    1

    REPETER_SCL_F
    1

    2
    2
    R1003
    0929：Change TUSB544 SLP enable to PD drive

    1
    R1007 @ R1001 @ 100K_0402_5%
    100K_0402_5%
    @ 1K_0402_5%

    1
    1
    2
    DDIP3_HPD

    I2C mode

    2
    EQ setting R1008
    100K_0402_5%
    +3V_REDP +3V_REDP

    1
    +3V_REDP
    +3V_REDP
    1

    R78 R75
    1

    R84
    1

    R989 @ 1K_0402_5% @ 1K_0402_5% 1027: TI request


    @ 1K_0402_5% R120 1 @ 2 0_0402_5%
    @ 1K_0402_5%
    2

    2
    2

    B TUSB_CFG0 TUSB_CFG1 EXC24CH900U_4P B


    2

    TUSB_DEQ1 R111 1 @ 2 0_0402_5% USB20_P0 4 3 USB20_P_CON


    TUSB_DEQ0 10 USB20_P0 4 3
    1

    1
    1

    R82 R77 EXC24CH900U_4P USB20_N0 1 2 USB20_N_CON


    10 USB20_N0
    1

    R86 20K_0402_5% 20K_0402_5% TYPEC0_RXP1 C99 1 2 TYPEC0_RXP1_R 4 3 TYPEC_CON_RXP1 1 2


    R990 20K_0402_5% @ @ 0.22U_0201_10V6-K 4 3 L9 EMC@
    20K_0402_5% @
    2

    @ TYPEC0_RXN1 C100 1 2 TYPEC0_RXN1_R 1 2 TYPEC_CON_RXN1 R122 1 @ 2 0_0402_5%


    2

    0.22U_0201_10V6-K 1 2
    2

    L6 EMC@

    R116 1 @ 2 0_0402_5%

    ESD request
    R105 1 @ 2 0_0402_5% D37

    1 TYPEC_CON_TXN1
    L5 EMC@ CH1
    TYPEC0_RXP2 C97 1 2 TYPEC0_RXP2_R 1 2 TYPEC_CON_RXP2 TYPEC_CON_TXN1 9 2 TYPEC_CON_TXP1
    0.22U_0201_10V6-K 1 2 NC_4 CH2
    L22 EMC@ TYPEC_CON_TXP1 8
    BLM18KG300TN1D_2P TYPEC0_RXN2 C98 1 2 TYPEC0_RXN2_R 4 3 TYPEC_CON_RXN2 NC_3
    1 2 +VBUS_CONN_L 0.22U_0201_10V6-K 4 3 3
    +VBUS_CONN EXC24CH900U_4P VN
    TYPEC_CON_RXN1 7
    L23 EMC@ R112 1 @ 2 0_0402_5% NC_2
    BLM18KG300TN1D_2P TYPEC_CON_RXP1 6 4 TYPEC_CON_RXN1
    +VBUS_CONN 1 2 NC_1 CH3

    5 TYPEC_CON_RXP1
    ESD 5G
    EMC_NS@ CH4
    2 2 2
    1

    UCLAMP2271P.TNT SGP1610N2

    1 D12
    C79 EMC@ C80 EMC@ C81 EMC@ JUSB1
    1

    USBC_CC2_CONN AOZ8808DI-05_DFN-10-10-9_2P5X1
    C78 EMC@ 100P_0402_50V8J 100P_0402_50V8J 1000P_0402_50V7-K 21 17 R117 1 @ 2 0_0402_5%
    1 1 1 16 Vbus4 CC2 5 USBC_CC1_CONN EMC@
    1000P_0402_50V7-K Vbus3 CC1
    2 9
    4 Vbus2 EXC24CH900U_4P
    Vbus1 TYPEC0_TXP1 2 MUX_TYPEC_C_TXP1 TYPEC_CON_TXP1
    2

    C74 1 4 3 D38
    USB20_N_CON 19 0.22U_0201_10V6-K 4 3
    2

    18 Dn2 1 TYPEC_CON_TXP2
    7 Dp2 TYPEC0_TXN1 C75 1 2 MUX_TYPEC_C_TXN1 1 2 TYPEC_CON_TXN1 CH1
    USB20_P_CON 6 Dn1 0.22U_0201_10V6-K 1 2 TYPEC_CON_TXP2 9 2 TYPEC_CON_TXN2
    Dp1 34 L7 EMC@ NC_4 CH2
    TYPEC_CON_RXN2 10 GND14 33 TYPEC_CON_TXN2 8
    TYPEC_CON_RXP2 11 SSRXn2 GND13 32 R118 1 @ 2 0_0402_5% NC_3
    SSRXp2 GND12 31 3
    A TYPEC_CON_TXN2 15 GND11 30 VN A
    TYPEC_CON_TXP2 14 SSTXn2 GND10 29 TYPEC_CON_RXP2 7
    SSTXp2 GND9 28 NC_2
    TYPEC_CON_RXN1 22 GND8 27 TYPEC_CON_RXN2 6 4 TYPEC_CON_RXP2
    TYPEC_CON_RXP1 23 SSRXn1 GND7 26 NC_1 CH3
    SSRXp1 GND6 25 R119 1 @ 2 0_0402_5%
    TYPEC_CON_TXN1 3 GND5 24 5 TYPEC_CON_RXN2
    TYPEC_CON_TXP1 2 SSTXn1 GND4 13 CH4
    SSTXp1 GND3 12 L8 EMC@
    GND2 1 TYPEC0_TXP2 C76 1 2 MUX_TYPEC_C_TXP2 1 2 TYPEC_CON_TXP2
    USBC_DPAUX2_CONN 20 GND1 1 2 AOZ8808DI-05_DFN-10-10-9_2P5X1
    0.22U_0201_10V6-K
    USBC_DPAUX1_CONN 8 SBU2 EMC@
    SBU1 TYPEC0_TXN2 C77 1 2 MUX_TYPEC_C_TXN2 4 3 TYPEC_CON_TXN2
    0.22U_0201_10V6-K 4 3

    HIGHS_UB11126-A5A0B-1H EXC24CH900U_4P
    ME@ R121 1 @ 2 0_0402_5% Title
    Security Classification LC Future Center Secret Data
    Issued Date 2017/02/16 Deciphered Date 2018/06/01 TYPE-C
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 33 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 Switch
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 34 of 65
    5 4 3 2 1
    5 4 3 2 1

    On Board (LEFT-Front)

    +5VALW USB POWER SWITCH +USB_PWR_S2

    TABLE of POWER SWITCH (U6401)


    W=80mils 5
    U11
    1
    W=80mils
    D IN OUT Vendor LCFC P/N Description D
    2
    1
    GND SILERGY SA000074Q00 S IC SY6288D20AAC SOT23 5P POWER SWITCH
    USB_ON# 4 3 USB_OC0#
    C82
    36,42 USB_ON# ENB OCB USB_OC0# 10 GMT SA000079400 S IC G517F2T11U SOT-23 5P POWER SWITCH
    0.1U_0402_10V6-K SY6288D20AAC_SOT23-5
    2 SA000074Q00

    +USB_PWR_S2

    D17

    1 USB3P1_TXP_CON
    L10 CH1
    USB3P1_TXN C83 1 2 0.22U_0402_10V6-K USB3P1_TXN_C 4 3 USB3P1_TXN_CON USB3P1_TXP_CON 9 2 USB3P1_TXN_CON
    10 USB3P1_TXN 4 3 NC_4 CH2 1
    1 1
    USB3P1_TXN_CON 8 C84 C300 C85 @
    USB3P1_TXP C87 1 2 0.22U_0402_10V6-K USB3P1_TXP_C 1 2 USB3P1_TXP_CON NC_3 470P_0402_50V7-K
    10 USB3P1_TXP 1 2 2
    3 100U_1206_6.3V6M 100U_1206_6.3V6M
    EXC24CH900U_4P VN 2 2
    USB3P1_RXP_CON @
    EMC@ 7
    SM070003X00 NC_2
    USB3P1_RXN_CON USB3P1_RXP_CON
    L11
    6
    NC_1 CH3
    4 C51, C50 near JUSB1
    USB3P1_RXN C70 1 2 0.33U_0402_10V6-K USB3P1_RXN_C 4 3 USB3P1_RXN_CON
    10 USB3P1_RXN 4 3 USB3P1_RXN_CON
    5
    CH4
    USB3P1_RXP C71 1 2 0.33U_0402_10V6-K USB3P1_RXP_C 1 2 USB3P1_RXP_CON
    10 USB3P1_RXP 1 2 +USB_PWR_S2 +USB_PWR_S2
    AOZ8808DI-05_DFN-10-10-9_2P5X1
    EXC24CH900U_4P EMC@
    EMC@ JUSB2
    SM070003X00 USB3P1_TXP_CON 9
    D18 1 StdA_SSTX+
    USB20_N1_CON 1 6 USB20_P1_CON USB3P1_TXN_CON 8 VBUS
    USB20_P1_CON 3 StdA_SSTX-
    L12 7 D+
    USB20_N1 4 3 USB20_N1_CON USB20_N1_CON 2 GND_1 10
    10 USB20_N1 4 3 USB3P1_RXP_CON D- GND_2
    2 5 6 11
    4 StdA_SSRX+ GND_3 12
    USB20_P1 1 2 USB20_P1_CON USB3P1_RXN_CON 5 PGND GND_4 13
    C C
    10 USB20_P1 1 2 StdA_SSRX- GND_5
    EXC24CH900U_4P 3 4 SINGA_2UB2306-000111F
    EMC@ ME@
    SM070003X00 CM1293A-04SO_SC-74-6
    EMC@

    +5VALW
    +USB_PWR_S1
    On Board (LEFT-Back)
    L13
    U12 USB3P2_TXN C88 1 2 0.22U_0402_10V6-K USB3P2_TXN_C 4 3 USB3P2_TXN_CON
    10 USB3P2_TXN 4 3

    1 16 ILIM_HI R124 1 2 20K_0402_1% USB3P2_TXP C89 1 2 0.22U_0402_10V6-K USB3P2_TXP_C 1 2 USB3P2_TXP_CON


    IN ILIM_HI 10 USB3P2_TXP 1 2
    USB20_N2 2 15 ILIM_LO R123 1 @ 2 20K_0402_1% EXC24CH900U_4P
    10 USB20_N2 DM_OUT ILIM_LO SM070003X00
    USB20_P2 3 14 EMC@
    10 USB20_P2 DP_OUT GND
    4 13 USB_OC1# L14
    ILIM_SEL FAULT USB_OC1# 10 USB3P2_RXN C72 2 1 0.33U_0402_10V6-K USB3P2_RXN_C 4 3 USB3P2_RXN_CON
    AOU_EN 10 USB3P2_RXN 4 3
    42 AOU_EN 5 12
    EN OUT
    AOU_CTL1 6 11 USB20N2 USB3P2_RXP C73 2 1 0.33U_0402_10V6-K USB3P2_RXP_C 1 2 USB3P2_RXP_CON
    42 AOU_CTL1 CLT1 DM_IN 10 USB3P2_RXP 1 2
    7 10 USB20P2 EXC24CH900U_4P
    CLT2 DP_IN SM070003X00
    E_PAD

    AOU_CTL3 8 9 AOU_DET# EMC@


    42 AOU_CTL3 CLT3 STATUS AOU_DET# 42
    B B
    L15
    17

    SN1702001RTER_WQFN16_3X3 USB20P2 4 3 USB20_P2_CON


    4 3
    1
    C90 USB20N2 1 2 USB20_N2_CON
    0.1U_0402_10V7-K 1 2
    2@ EXC24CH900U_4P
    EMC@
    SM070003X00

    +USB_PWR_S1
    D19

    1 USB3P2_TXP_CON
    0815：Change TPS2546 to SN1702001 CH1
    USB3P2_TXP_CON 9 2 USB3P2_TXN_CON
    NC_4 CH2 1 1 1
    C92 C301 C91
    USB3P2_TXN_CON 8
    NC_3 100U_1206_6.3V6M 100U_1206_6.3V6M 470P_0402_50V7-K
    3 2 2 2
    VN @ @
    USB3P2_RXP_CON 7
    NC_2
    USB3P2_RXN_CON 6 4 USB3P2_RXP_CON
    NC_1 CH3

    5 USB3P2_RXN_CON +USB_PWR_S1
    CH4
    JUSB3
    AOZ8808DI-05_DFN-10-10-9_2P5X1 1
    EMC@ USB20_N2_CON 2 VBUS
    USB20_P2_CON 3 D-
    D20 4 D+
    USB20_N2_CON 1 6 USB20_P2_CON USB3P2_RXN_CON 5 GND
    USB3P2_RXP_CON 6 Stda_SSRX- 10
    +USB_PWR_S1 7 Stda_SSRX+ GND2 11
    USB3P2_TXN_CON 8 GND_DRAIN GND3 12
    2 5 USB3P2_TXP_CON 9 Stda_SSTX- GND4 13
    A A
    Stda_SSTX+ GND5
    FOX_UEA111Y-R1001A-7H
    ME@
    3 4

    CM1293A-04SO_SC-74-6
    EMC@

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 USB3 P1/2 CONN.
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 35 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    IO_40_Pin conn
    +3VS +5VALW +3VALW
    +3VL
    JIOB1
    1
    2 1
    3 2
    C 4 3 C
    5 4
    6 5
    7 6
    8 7
    9 8
    10 9
    PLT_RST# 11 10
    7,37,42 PLT_RST# LAN_WAKE# 11
    42 LAN_WAKE# 12
    CLKREQ_PCIE1_LAN# 13 12
    9 CLKREQ_PCIE1_LAN# CLKREQ_PCIE2_CR# 13
    14
    9 CLKREQ_PCIE2_CR# PWRBTN_LED# 14
    15
    42 PWRBTN_LED# 15
    ON/OFF# 16
    42 ON/OFF# USB_ON# 16
    17
    35,42 USB_ON# USB_OC2# 17
    18
    10 USB_OC2# LID_SW# 18
    19
    42 LID_SW# 19
    20
    USB20_P3 21 20
    USB2.0 10
    10
    USB20_P3
    USB20_N3
    USB20_N3 22
    23
    21
    22
    PCIE1_CRX_DTX_N 24 23
    5 PCIE1_CRX_DTX_N PCIE1_CRX_DTX_P 24
    25
    5 PCIE1_CRX_DTX_P 25
    26
    PCIE1_CTX_C_DRX_N 27 26
    GBE LAN PHY 5
    5
    PCIE1_CTX_C_DRX_N
    PCIE1_CTX_C_DRX_P
    PCIE1_CTX_C_DRX_P 28
    29
    27
    28
    CLK_PCIE_LAN 30 29
    9 CLK_PCIE_LAN CLK_PCIE_LAN# 30
    31
    9 CLK_PCIE_LAN# 31
    32
    PCIE2_CRX_DTX_N 33 32
    5 PCIE2_CRX_DTX_N PCIE2_CRX_DTX_P 33
    34
    5 PCIE2_CRX_DTX_P 34
    35
    B
    Card Reader 5 PCIE2_CTX_C_DRX_N
    PCIE2_CTX_C_DRX_N
    PCIE2_CTX_C_DRX_P
    36
    37
    35
    36
    B

    5 PCIE2_CTX_C_DRX_P 37
    38
    CLK_PCIE_CR# 39 38 41
    9 CLK_PCIE_CR# CLK_PCIE_CR 39 GND1
    40 42
    9 CLK_PCIE_CR 40 GND2
    I-PEX_20374-040E-31
    ME@

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 IO BOARD CONN.
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 36 of 65
    5 4 3 2 1
    5 4 3 2 1

    +3VS

    1
    R125
    2 0_0603_5%
    +3VS_WLAN
    TYPE-A NGFF CARD FOR WLAN
    3.2H CONNECTOR +3VS_WLAN
    D D
    JWLBT1
    1 2
    USB20_P_WLAN 3 GND1 3.3VAUX1 4
    10 USB20_P_WLAN USB20_N_WLAN USB_D+ 3.3VAUX2
    5 6
    10 USB20_N_WLAN
    7 USB_D- KEY A LED1#
    8
    GND2 NC
    9 NC NC 10
    11 NC NC 12
    13 NC NC 14
    15 16
    NC LED2#
    17 18
    19 MLDIR_SENSE GND16 20
    21 DP_ML3N DP_AUXN 22
    23 DP_ML3P DP_AUXP 24
    25 GND3 GND13 26
    27 DP_ML2N DP_ML1N 28
    29 DP_ML2P DP_ML1P 30
    31 GND4 GND14 32
    33 DP_HPD DP_ML0N 34
    PCIE5_CTX_C_DRX_P 35 GND5 DP_ML0P 36
    5 PCIE5_CTX_C_DRX_P
    PCIE5_CTX_C_DRX_N 37 PETP0 GND15 38
    5 PCIE5_CTX_C_DRX_N PETN0 RESERVED1
    39 40
    PCIE5_CRX_DTX_P 41 GND6 RESERVED2 42
    5 PCIE5_CRX_DTX_P PCIE5_CRX_DTX_N PERP0 RESERVED3
    43 44
    5 PCIE5_CRX_DTX_N PERN0 COEX3
    45 46
    CLK_PCIE_WLAN 47 GND7 COEX2 48
    9 CLK_PCIE_WLAN CLK_PCIE_WLAN# REFCLKP0 COEX1 RTCCLK_R
    9 CLK_PCIE_WLAN# 49 50 RTCCLK_R 9,25
    51 REFCLKN0 SUSCLK 52 PLT_RST#
    WLAN_CLKREQ_Q# GND8 PERST0# BT_ON_R PLT_RST# 7,36,42
    53 54 R133 1 21K_0402_5%
    WLAN_WAKE#_R CLKREQ0# W_DISABLE2# RF_OFF# BT_ON 7
    C 1 2 55 56 C
    +3VS_WLAN PEWAKE0# W_DISABLE1# RF_OFF# 7
    57 58
    R132
    CHECK 0324 10K_0402_5%
    59 GND9
    PETP1
    I2C_DATA
    I2C_CLK
    60
    61 62 R134 2 @ 1 0_0402_5% EC_RX 42
    @ 63 PETN1 ALERT# 64 EC_TX_R R135 2 @ 1 0_0402_5%
    GND10 RESERVED4 PLT_RST# EC_TX 42
    65 66
    67 PERP1 PERST1# 68
    69 PERN1 CLKREQ1# 70
    R268 1 GND11 PEWAKE1#

    1
    42 WLAN_WAKE# 2 0_0402_5% 71 72 2
    73 REFCLKP1 3.3VAUX4 74 @ C258 R136
    @ 75 REFCLKN1 3.3VAUX5
    GND12 0.1U_0201_6.3V6-K
    100K_0402_5%
    76 77 1

    2
    PEG1 PEG2
    DEREN_40-42191-06701RHF
    ME@

    +3VS
    +3VS_WLAN
    1

    R267 AOAC@
    2
    G

    Q165 10K_0402_5%
    2

    AOAC@ 3 1 WLAN_CLKREQ_Q#
    B 9 CLKREQ_PCIE3_WLAN# B
    S

    2N7002KW_SOT323-3

    R266 1 2 0_0402_5%

    If support AOAC, NC R266;


    if not support AOAC, stuff R266.

    +3VS_WLAN

    2 2 2
    C94 C95 C96
    Vgs(th) = -0.65V (tpy), -1V (max) @
    Rds(on) = 56 (typ), 80 (max) ; Vgs = -4.5V, Id = -3A
    0.1U_0201_6.3V6-K 1U_0402_6.3V6-K 10U_0402_6.3V6-M
    Q8 AOAC@ 1 1 1
    @
    S

    +3VALW 3 1 +3VS_WLAN
    AO3413_SOT23-3
    C908
    0.1U_0201_6.3V6-K
    G
    2

    2 1
    A A

    @
    WLAN_PWRON# 1 2
    42 WLAN_PWRON#
    R137 AOAC@
    10K_0402_5% 1
    Security Classification LC Future Center Secret Data Title
    C93 AOAC@
    .01U_0402_16V7-K M.2 SOCKET 1 WLAN
    2 Issued Date 2017/02/16 Deciphered Date 2018/06/01
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 37 of 65
    5 4 3 2 1
    5 4 3 2 1

    +1.8V_LDO +1.65V_LDO +3V_LDO


    +5VS VREF 1V65 LDO 3V3
    LDO 1V8 +3VS
    @ +5VS_CLASSD
    0_0805_5% 2 1 RA1 CA1 CA4
    CA2 CA3 1

    CA5

    CA6

    CA7

    CA8

    CA9
    CA10

    4.7U_0603_10V6-K

    0.1U_0402_10V7-K
    1 1 2 1 1 1 1 1 0.1U_0402_10V7-K
    C3505 close Pin7

    4.7U_0603_10V6-K

    0.1U_0402_10V7-K
    1 1 CA11
    2
    D D

    0.1U_0402_10V7-K

    4.7U_0603_10V6-K

    0.1U_0402_10V7-K

    1U_0402_6.3VA-K

    0.1U_0402_10V7-K
    2.2U_0402_6.3V6-M
    2 2 1 2 2 2 2 2
    2 2

    X5R CAP X5R CAP


    +3VS +3VS_VDDO

    Close to Pin13,16 RA2


    1 @ 2
    0_0402_5%
    1
    UA1 CA12
    0.1U_0402_10V7-K
    APU_AZ_RST# 9 3
    RESET# FILT_1.8V 7
    +1.8V_LDO
    +1.5VS_VDDIO
    CA12 close Pin2 2
    VDD_IO 2
    APU_AZ_BITCLK VDDO_3.3 +3VS_VDDO
    5 18 +3VS_DVDD
    BIT_CLK DVDD_3.3
    APU_AZ_SYNC 8 27 +3VL
    RA3 SYNC AVDD_3.3 +3V_LDO
    29 1 @ 2
    7 APU_AZ_SDIN0
    APU_AZ_SDIN0 1 2
    33_0402_5%
    APU_AZ_SDIN0_R 6 CX11852 VREF_1.65V 28
    +1.65V_LDO
    +5VS_AVDD
    RA4 0_0402_5%
    APU_AZ_SDOUT 4 SDATA_IN AVDD_5V +3V_AVDD_HP
    SDATA_OUT DA2 +3VALW
    PC_BEEP 10 12 SPK_L2+ @ 1 2
    39 PC_BEEP SPKR_MUTE# PC_BEEP LEFT+ SPK_L1- SPK_L2+ 39
    39 14 1
    SPKR_MUTE# LEFT- SPK_L1- 39
    RB751V-40_SOD323-2
    JSENSE 38 17 SPK_R2+ CA13 SCS00008K00
    39 JSENSE 37 JSENSE RIGHT+ 15 SPK_R1- SPK_R2+ 39
    1U_0402_6.3VA-K
    GPIO1/PORTC_R_MIC RIGHT- SPK_R1- 39 2
    36 35
    DMIC_CLK EMC@1 RA7 2
    33_0402_5% MIC_CLK_R 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34 CA13 close Pin24
    DMIC_DATA DMIC_DATA_R DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB +MICBIASB
    RA20 1 @ 2 0_0402_5% 1
    26 DMIC_DATA DMIC_DAT/GPIO1 33 PORTB_R
    RC Close connector PORTB_R_LINE 32 PORTB_L PORTB_R 39
    PORTB_L_LINE PORTB_L 39 +3VS_DVDD +3VS
    +5VS_CLASSD CA14 1 2 0.1U_0402_10V7-K 11
    CLASS-D_REF 30 EXT_MIC_A
    1 PORTD_A_MIC EXT_MIC_A 39
    13 31 EXT_MIC_B 1 @ 2
    @ LPWR_5.0 PORTD_B_MIC EXT_MIC_B 39
    C CA15 16 RA8 0_0402_5% C
    22P_0402_50V8-J RPWR_5.0 25 HGNDA
    2 W= 80mils CA16 1 2 1U_0402_6.3V6-K 19 HGNDA 26 HGNDB
    HGNDA 39,40 X7R CAP, Please Close Pin18
    FLY_P HGNDB HGNDB 39,40
    20
    FLY_N 24
    AVDD_HP +3V_AVDD_HP 1
    +AVEE 21
    +AVEE AVEE HP_OUTR
    23 CA17
    PORTA_R HP_OUTL HP_OUTR 39
    CA18 41 22 1U_0402_6.3VA-K
    GND PORTA_L HP_OUTL 39 2
    HP indicate
    2.2U_0402_6.3V6-M

    Should be CX11852-11Z_QFN40_5X5
    2 connect to
    GNDA Apple --> EXT_MIC_A, HGNDB
    Nokia --> EXT_MIC_B, HGNDA +5VS_AVDD +5VS

    1 @ 2
    RA9 0_0402_5%
    38 31
    1 AGND 1

    DMIC_CLK CA19
    26 DMIC_CLK 0.1U_0402_10V7-K
    APU_AZ_RST# 2
    7 APU_AZ_RST# DGND
    APU_AZ_BITCLK
    7 APU_AZ_BITCLK 21
    APU_AZ_SYNC
    7 APU_AZ_SYNC
    APU_AZ_SDOUT
    11 Please Close Pin28
    7 APU_AZ_SDOUT

    2
    CA20 Close to UA1 +3VS_VDDO
    W= 300mils
    EMC@
    1 +1.5VS +1.8VS
    150P_0402_50V8-J EMC_NS@ CA21 1 2 0.1U_0402_10V7-K @
    B 1 2 +1.5VS_VDDIO B
    1

    RA11 0_0402_5%
    RA10 EMC@ CA22 1 2 0.1U_0402_10V7-K
    RA12
    47K_0402_5% 1 2 0_0402_5%

    EMC@ CA23 1 2 0.1U_0402_10V7-K @ 1


    2

    CA24
    @ 0.1U_0402_10V7-K
    APU_AZ_RST# DA1 2
    EC_MUTE# SPKR_MUTE#
    42 EC_MUTE#
    1 2
    GND GNDA
    RB751V-40_SOD323-2
    SCS00008K00
    CA20 close Pin7
    APU_AZ_BITCLK @
    1

    1 2
    RA13 RA19 0_0402_5%
    1

    1 10K_0402_5%
    CA32 RA14
    10P_0402_50V8-J EMC@ 10K_0402_5%
    2

    2 @
    2

    0823： Chaneg from 1.5V to 1.8V HDA for codec


    @

    Close Codec
    0206: Reserve a Cap on APU_AZ_RST#(ENC@) close to Codec. 0402_0.1uF

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 CX11852
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 38 of 65
    5 4 3 2 1
    5 4 3 2 1

    PC Beep RA15
    1 2 CA25 1 2 0.1U_0402_10V7-K

    4.7K_0402_5%

    EXT. MIC/LINE IN Apple --> EXT_MIC_A, HGNDB


    Nokia --> EXT_MIC_B, HGNDA
    EC Beep
    D 42 BEEP# D

    PC_BEEP
    PC_BEEP 38
    PCH Beep R138
    7 APU_SPKR EXT_MIC_A 1 2 100_0402_5% CA27 1 2 2.2U_0402_6.3V6-K HGNDB
    38 EXT_MIC_A HGNDB 38,40
    R139
    EXT_MIC_B 100_0402_5%
    1 2 CA28 1 2 2.2U_0402_6.3V6-K HGNDA
    38 EXT_MIC_B HGNDA 38,40

    Changed CA29 & CA30 from 1uF to 2.2uF/X5R


    to meet Port-D(headset-Mic) THD+N <= -65 dB

    RA18
    1 2 CA29 1 2 0.1U_0402_10V7-K

    4.7K_0402_5%

    C C

    HeadPhone/LINE OUT
    +3VS

    R140

    1
    1 2 3K_0402_5% +MICBIASB R141 +5VS
    1K_0402_1%
    R142

    1
    HP_OUTL 1 2 HP_OUTL_CON
    38 HP_OUTL HP_OUTL_CON 40

    2
    JSENSE R144 1 2 2.49K_0402_1% R702
    R143 38 JSENSE
    CA30 10K_0402_5%
    PORTB_L 1 2 1 2 75_0402_5%
    38 PORTB_L
    39.2K_0402_1%

    2
    @

    1
    10U_0603_6.3V6-M R145 1 2 D
    100_0402_5% 2 JSENSE_CON
    JSENSE_CON 40
    G
    R146
    S Q169

    3
    1 2 3K_0402_5% +MICBIASB 2N7002WT1G_1N_SC-70-3
    SB00000YY00
    R147
    HP_OUTR 1 2 HP_OUTR_CON
    38 HP_OUTR HP_OUTR_CON 40
    R148 R703 1 2 0_0402_5%
    CA31
    PORTB_R 1 2 1 2 75_0402_5%
    38 PORTB_R
    @
    10U_0603_6.3V6-M
    100_0402_5%

    CA31, CA32 change to 4.7U for Quality requirement 0929：Add Jsense reserves detect for normal close

    B B

    SPK CONN.
    EMC@
    L16 1 2 BLM18PG221SN1D_2P SPK_L-_CON
    38 SPK_L1-
    EMC@
    L17 1 2 BLM18PG221SN1D_2P SPK_L+_CON
    38 SPK_L2+
    EMC@
    L18 1 2 BLM18PG221SN1D_2P SPK_R-_CON
    38 SPK_R1-
    EMC@
    L19 1 2 BLM18PG221SN1D_2P SPK_R+_CON
    38 SPK_R2+

    EMC@
    C102 1 2 1000P_0402_50V7-K SPK_L-_CON
    A
    EMC@ JSPK1 A
    C103 1 2 1000P_0402_50V7-K SPK_L+_CON SPK_L-_CON 1
    EMC@ SPK_L+_CON 2 1
    C104 1 2 1000P_0402_50V7-K SPK_R-_CON SPK_R-_CON 3 2
    EMC@ SPK_R+_CON 4 3
    C105 1 2 1000P_0402_50V7-K SPK_R+_CON 4
    5
    6 GND1
    GND2
    EMI parts Close to connector
    HIGHS_WS33040-S0351-HF
    ME@ Title
    Security Classification LC Future Center Secret Data
    Issued Date 2017/02/16 Deciphered Date 2018/06/01 AUDIO CONNECTOR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom C 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 39 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    JAUHP1
    HGNDB 4
    38,39 HGNDB 4

    HGNDA 3
    38,39 HGNDA HP_OUTL_CON 3
    1
    39 HP_OUTL_CON 1
    7
    7
    HP_OUTR_CON 2
    39 HP_OUTR_CON 2
    5
    5
    JSENSE_CON 6
    C
    39 JSENSE_CON 6 C
    SINGA_2SJ3092-003111F
    ME@
    1 1
    C106 C107
    100P_0402_50V8-J 100P_0402_50V8-J
    2 EMC@ 2 EMC@

    NEED CHECK PIN DEFINE


    GNDA GNDA

    Vendor suggestion. Reserve for EMI.


    Close to JAUHP.

    ESD request C108


    0.1U_0402_10V7-K
    EMC@
    HGNDA GNDA JSENSE_CON 1 2
    HGNDB
    HP_OUTL_CON HP_OUTR_CON
    B C109 B
    0.1U_0402_10V7-K
    3

    2
    EMC_NS@
    D22 D23 D24 1 2
    PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3
    EMC@ EMC@ EMC@
    1

    GND GNDA

    GND GND GND

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 AUDIO JACK SENSE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 40 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    +3VALW

    1
    R151

    10K_0402_1%

    2
    DEVICE_DETECT# R152 1 2 15K_0402_1% HDD_DETECT#
    42 DEVICE_DETECT# HDD_DETECT# 30

    R153 1 2 51K_0402_5% KB_BLK_DTCT#


    KB_BLK_DTCT# 46
    C C

    R700 1 2 33K_0402_1% SSD_DTCT#


    SSD_DTCT# 25

    1025 ：Change SSD DTCT# to 33K, KB_BLT to 51K

    Vcc 3.3V
    R151 10K +/- 5%
    DEVICE_DETECT1# 1.98V 1.675V 1.772V 2.759V 2.533V 3.3V
    HDD_DETECT# V V V X X X
    B KB_BLK_DTCT# X V X X V X B

    WWAN_DTCT# X X V V X X

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 DEVICE_DETECT# TABLE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 41 of 65
    5 4 3 2 1
    5 4 3 2 1

    RE1
    2 1 CLK_PCI_EC_R
    9 CLK_PCI_EC

    0_0402_5%

    +3VL_EC
    +3VL +3VL_EC
    RE4
    All capacitors close to EC
    1 2 WRST# @
    RE35 1 2 0_0603_5% +3VL_EC CE1 CE2 CE3 CE4 CE5 CE6
    100K_0402_5% 1
    CE7

    0.1U_0402_10V7-K

    0.1U_0402_10V7-K

    0.1U_0402_10V7-K

    0.1U_0402_10V7-K

    0.1U_0402_10V7-K

    0.1U_0402_10V7-K
    +1.8V_SPI
    1U_0402_10V6-K 1 1 1 1 1 1
    2 +3VL_AVCC
    @ @
    D D

    RE38
    2 2 2 2 2 2

    0_0402_5%
    RE27 0_0402_5%
    EC_RTCRST#_ON 2 @ 1 WLAN_RTCRST#
    12 EC_RTCRST#_ON

    0_0402_5%
    2
    1
    +3VS
    0_0402_5% CE8
    WLAN_WAKE# RE28 2 @ @ +3VL_EC +3VL_AVCC
    @ 1 0.1U_0402_10V7-K1 2
    37 WLAN_WAKE#
    @

    1
    2
    R958 2 10_0603_5%
    +3VL_AVCC

    74 RE37
    PD_VBUS_C_CTRL1_EC 2 RE31 1 0_0402_5%
    32 PD_VBUS_C_CTRL1_EC UE1

    114
    121

    106

    127

    112
    11

    26
    50
    92

    12
    1 1

    VCC

    AVCC

    VCORE
    VSTBY_FSPI
    VSTBY1
    VSTBY2
    VSTBY3
    VSTBY4
    VSTBY5

    VSTBY0
    VSTBY(PLL)
    +3VL_EC 0929：Change AOU detect to 3VL LPC_AD0 10 24 LOGO_LED# CE9 CE10
    9 LPC_AD0 LPC_AD1 EIO0/LAD0/GPM0(3) PWM0/GPA0 KBD_BL_PWM LOGO_LED# 26
    9 25 0.1U_0402_10V7-K 1000P_0402_50V7-K
    9 LPC_AD1 LPC_AD2 EIO1/LAD1/GPM1(3) PWM1/GPA1 EC_ON2_3V KBD_BL_PWM 46 2 2
    8 28 EC_ON2_3V 57,58
    9 LPC_AD2 LPC_AD3 EIO2/LAD2/GPM2(3) PWM2/GPA2 PWRBTN_LED# R959
    RE39 1 2 10K_0402_5% AOU_DET# 7 29 @
    9 LPC_AD3 EIO3/LAD3/GPM3(3) PWM3/GPA3 PWRBTN_LED# 36
    LPC_RST# 22 PWM 30 APUPWR_EN EC_AGND 2 10_0603_5%
    9 LPC_RST# CLK_PCI_EC_R ERST#/LPCRST#/GPD2 PWM4/GPA4 EC_FAN_PWM APUPWR_EN 59
    +3VALW 13 31
    LPC_FRAME# 6 ESCK/LPCCLK/GPM4(3) PWM5/GPA5 EC_FAN_PWM 48
    9 LPC_FRAME# ECS#/LFRAME#/GPM5(3) EC_FAN_SPEED
    47
    @ TACH0A/GPD6(3) AOU_CTL3 EC_FAN_SPEED 48
    RE23 1 2 10K_0402_5% AOU_DET# 48
    Remove GPU_VR_HOT# same with 320G TACH1A/TMA1/GPD7(3) AOU_CTL3 35
    WLAN_RTCRST# 126
    RE24 1 2 10K_0402_5% KB_FN SERIRQ 5 GA20/GPB5(3) 66 DEVICE_DETECT#
    9 SERIRQ ALERT#/SERIRQ/GPM6(3) ADC0/GPI0(3) DEVICE_DETECT# 41 @RE25
    EC_SMI# 15 67 PAD_DISABLE Board_WLAN 0_0402_5%2 1 Type_C_I_CTRL_P2
    7 EC_SMI# EC_SCI# 23 PLTRST#/ECSMI#/GPD4(3)LPC ADC1/GPI1(3) 68 BATT_TEMP PAD_DISABLE 46 Type_C_I_CTRL_P2 32
    9 EC_SCI# ECSCI#/GPD3 ADC2/GPI2(3) BATT_TEMP 55,56
    RPE2 WRST# 14 69 EC_ON3_VDDP
    WRST# ADC3/GPI3(3) FAN_ID EC_ON3_VDDP 58 RE26 WLAN_PWRON#
    1 8 KSO1 KBRST# 4 70 2 1 WLAN_PWRON# 37
    9 KBRST# KBRST#/GPB6(3) ADC4/GPI4(3) FAN_ID 48
    2 7 KSO2 0_0402_5%
    3 6 FAN_ID
    LAN_WAKE#
    A/D D/A @
    4 5

    10K_0804_8P4R_5%
    46 TP4_RESET
    TP4_RESET 113
    CRX0/GPC0
    IT8996 TACH2/GPJ0(3)
    GPJ1(3)
    DAC2/TACH0B/GPJ2(3)
    76
    77
    78
    INT#_TYPEC
    0_0402_5% 2 RE21
    VR_APU_PWRGD
    1
    INT#_TYPEC
    PM_SLP_S5#
    VR_APU_PWRGD
    31
    PM_SLP_S5#
    59
    7,9 +3VL_EC
    AOU_DET# 123 CAPSLK_LED#
    C
    35 AOU_DET# CTX0/TMA0/GPB2(3) CIR
    LQFP DAC3/TACH1B/GPJ3(3)
    79

    94 EC_SMB_CK3
    CAPSLK_LED# 46
    EC_ON2_3V 1
    RE5 @
    2 100K_0402_5%
    C

    +5VALW CRX1/SIN1/SMCLK3/GPH1/ID1 EC_SMB_CK3 8,50 0929：No mirror ，fo r sequenc e chang e


    95 EC_SMB_DA3
    +3VS CTX1/SOUT1/GPH2/SMDAT3/ID2 GSENSE_INT EC_SMB_DA3 8,50
    KSO0 36 122 GSENSE_INT 50
    KSO1 37 KSO0/PD0 DTR1#/SBUSY/GPG1/ID7 34 EC_MUTE# +3VS
    KSO1/PD1 PWM7/RIG1#/GPA7 LID_CLOSE# EC_MUTE# 38
    +3VL_EC KSO2 38 35 LID_CLOSE# 46
    RE32 KSO3 39 KSO2/PD2 RTS1#/GPE5 73 Board_WLAN EC_FAN_PWM RE6 1 @ 2 10K_0402_5%
    KSO3/PD3 UART port ADC7/CTS1#/GPI7(3)
    1 2 100K_0402_5% USB_ON# KSO4 40 72 PSYS PSYS 56
    KSO5 41 KSO4/PD4 ADC6/DSR1#/GPI6(3) 71 ADP_I
    KSO5/PD5 ADC5/DCD1#/GPI5(3) ADP_I 56
    KSO6 42 CAPSLK_LED# RE17 1 @ 2 10K_0402_5%
    10K_0402_5%1 RE34 2 EC_FAN_SPEED KSI[0..7] KSO7 43 KSO6/PD6 16 EC_RX
    46 KSI[0..7] KSO7/PD7 RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7(3) EC_TX EC_RX 37
    KSO8 44 17 RPE6
    KSO[0..17] KSO8/ACK# TXD/SOUT0/LPCPD#/GPE6 EC_TX 37 CP_DATA
    46 KSO[0..17] KSO9 45 1 4
    10K_0402_5%1 RE33 2 LID_SW# KSO10 46 KSO9/BUSY 81 BKOFF# CP_CLK 2 3
    KSO10/PE DAC5/RIG0#/GPJ5(3) BKOFF# 26
    KSO11 51 KBMX
    KSO12 52 KSO11/ERR# 33 USB_ON# 4.7K_0404_4P2R_5%
    KSO12/SLCT GINT/CTS0#/GPD5 USB_ON# 35,36
    KSO13 53 119 ENBKL ENBKL 8 EC Setting 1.8V
    KSO14 54 KSO13 DSR0#/GPG6 80 H_PROCHOT_EC
    RPE4 KSO15 55 KSO14 DAC4/DCD0#/GPJ4(3)
    1 8 SUSP# KSO16 56 KSO15
    2 7 AC_PRESENT KSO17 57 KSO16/SMOSI/GPC3(3)
    LPC_RST# KSO17/SMISO/GPC5(3) AOU_EN CE12 EMC_NS@
    3 6 85
    PS2CLK0/CEC/TMB0/GPF0 PBTN_OUT# AOU_EN 35 PWR_GOOD
    4 5 SYSON KSI0 58 86 1 2
    KSI0/STB# PS2DAT0/TMB1/GPF1 CP_CLK PBTN_OUT# 7
    KSI1 59 PS/2 89
    KSI1/AFD# PS2CLK2/GPF4 CP_DATA CP_CLK 46
    100K_0804_8P4R_5% KSI2 60 90
    KSI2/INIT# PS2DAT2/GPF5 CP_DATA 46 10P_0402_50V8-J
    For EMC, close to UE1 KSI3
    KSI4
    61
    62 KSI3/SLIN# STRIP RISK GPIO
    KSI4 RE18
    CE11 2 1 0.1U_0402_10V7-K KSI5 63 125 0_0402_5% 2 1 APU_THERMTRIP# APU_THERMTRIP# 8
    KSI6 64 KSI5 SSCE1#/GPG0 100 EC_Mirror
    EMC_NS@ KSI6 SPI ENABLE SSCE0#/GPG2
    KSI7 65
    KSI7 32 BEEP#
    EC_SMB_DA4 PWM6/SSCK/GPA6 BEEP# 39 +3VL_EC
    118
    49,58 EC_SMB_DA4 EC_SMB_CK4 SMDAT2/PECIRQT#/GPF7(3)
    117
    49,58 EC_SMB_CK4 EC_SMB_DA1 SMCLK2/PECI/GPF6(3) OTP_RESET
    116 120 RE7
    55,56 EC_SMB_DA1 EC_SMB_CK1 SMDAT1/GPC2 TMRI0/GPC4(3) OTP_RESET 54 EC_ON_5V
    115 SM BUS 124 SUSP# 1 2 100K_0402_5%
    55,56 EC_SMB_CK1 EC_SMB_DA2 SMCLK1/GPC1 TMRI1/GPC6(3) SUSP# 51,58,64
    88
    31 EC_SMB_DA2 EC_SMB_CK2 SMDAT0/GPF3
    87
    B 31 EC_SMB_CK2 SMCLK0/GPF2 B
    110 ON/OFF#
    PWRSW/GPB3 ON/OFF# 36
    111
    XLP_OUT/GPB4 109 LID_SW#
    +3VL_EC LAN_WAKE# LID_SW#/GPB1 LID_SW# 36
    36 LAN_WAKE# 21 108 ACPRN
    PM_SLP_S3# RE20 RI2#/GPD1 AC_IN#/GPB0
    7 PM_SLP_S3# 0_0402_5% 2 1 18 WAKE UP
    RPE5 SYSON 107 RI1#/GPD0(3)
    EC_SMB_CK1 58 SYSON GPE4/BTN# +3VL_EC
    1 8
    2 7 EC_SMB_DA1
    3 6 EC_SMB_CK4 EC_SPI_CLK 105 84 AOU_CTL1 @
    EC_SMB_DA4 9 EC_SPI_CLK EC_SPI_CS1# FSCK/GPG7 EGCLK/GPE3 EC_ON_5V AOU_CTL1 35 EC_Mirror
    4 5 9 EC_SPI_CS1# 101 83 EC_ON_5V 57 RE8 1 2 10K_0402_5%
    EC_SPI_SI 102 FSCE#/GPG3 EGCS#/GPE2 82 +0.9VALW_PWRGD
    9 EC_SPI_SI EC_SPI_SO FMOSI/GPG4 EXTERNAL SERIAL FLASH EGAD/GPE1 +0.9VALW_PWRGD 58
    2.2K_0804_8P4R_5% 9 EC_SPI_SO 103
    FMISO/GPG5 RE9 1 2 10K_0402_5%
    +3VL_EC AC_PRESENT 2 RE22 1 0_0402_5% 128 19 TPM_PLT_RST#
    7 AC_PRESENT EC_WAKE# GPJ6/THERMTRIP_SHUTDOWN# L80HLAT/BAO/GPE0 KB_FN TPM_PLT_RST# 44
    7 EC_WAKE#
    2
    GPJ7
    CLOCK
    L80LLAT/GPE7
    20 KB_FN 46 EC Setting 1.8V 1. Version CX : Don't Support Mirror Code
    Version DX/EX/FX : Support Mirror Code
    1

    3 PLT_RST#
    GPH7 PLT_RST# 7,36,37
    99 0_0402_5% 2 RE19 1 PWR_GOOD
    RE10
    GPIO ID6/GPH6 98 ACOFF
    ACOFF 56
    PWR_GOOD 7 2. For Mirror Code
    "H" --> Enable
    100K_0402_5% ID5/GPH5 97 PWR_STATUS_LED#
    ID4/GPH4 BATT_CHG_LED# PWR_STATUS_LED# 47
    96
    BATT_CHG_LED# 47
    "L" --> Disable (Default)
    2

    @ JSW2 ID3/GPH3 93 EC_RSMRST#


    CLKRUN#/ID0/GPH0 EC_RSMRST# 7
    *
    AVSS
    VSS1

    VSS2
    VSS3
    VSS4
    VSS5

    ON/OFF# 2 1 EC Setting 1.8V


    SHORT PADS
    1

    27
    49
    91
    104

    75

    IT8996E-256-DX_LQFP128_14X14 IT8996E-256-DX AC IN, need to conf i r mt he pi ni s Hi gh or L o w ac t i ve w


    hi le pulg AC IN
    EC_AGND
    PROCHOT# For factory EC f l as h +3VL_EC
    (EC asserts PROCHOT# signal by driving high, 1 EC_SMB_CK1 ACPRN 1
    RE11
    2 100K_0402_5%
    the level shif t er must i nvert it and dri ve t he pr ocess or si de PR OC HOT# l o w.) IT1 @1 EC_SMB_DA1 RE12 2 1 0_0402_5%
    ACIN 56
    IT2 @1
    IT3 @1
    IT4 @1
    A IT5 @ A
    VR_HOT#RE15 2 1 0_0402_5% H_PROCHOT# CE13 1 2 100P_0402_50V8-J
    56,58,59 VR_HOT# H_PROCHOT# 8
    1 KSI7 @
    H_PROCHOT_EC RE36 2 1 0_0402_5% IT6 @1 KSI6
    IT7 @1 WRST#
    IT8 @
    1

    D
    1
    H_PROCHOT_EC 2 CE14
    G
    QE2 S 47P_0402_50V8-J Title
    Security Classification LC Future Center Secret Data
    3

    2N7002WT1G_1N_SC-70-3 2
    @
    @ Issued Date 2017/02/16 Deciphered Date 2018/06/01 8996
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 42 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    Screw Hole
    H2 H3 H25 H26
    PAD_C6P0D3P4 PAD_C6P0D3P4 PAD_C6P0D3P4 PAD_C6P0D3P4

    CPU @ @ @ @

    1
    H24
    PAD_CB6P0D3P2

    WLNN @

    1
    H28 H6 H7 H8 H9 H10
    C PAD_C8P0D2P3 H29 PAD_C6P0D2P8 PAD_CT6P0B8P0D2P3 PAD_C8P0D2P3 PAD_O2P6X3P2D2P6X3P2 PAD_C2P8D2P3 C
    PAD_C3P5D2P5

    @ @ @ @ @ @
    1

    1
    @

    1
    H14 H15 H16
    H11 H12 PAD_C8P0D2P3 PAD_C2P8D2P3 PAD_C2P8D2P3
    PAD_O2P6X3P65D2P6X3P65 PAD_O2P3X2P8D2P3X2P8

    @ @ @

    1
    @ @
    1

    H18 H19 H20 H23


    PAD_C6P0D2P3 PAD_C2P8D2P3 PAD_C6P0D2P3 PAD_C2P4D2P4N H22
    PAD_O2P4X2P9D2P4X2P9N

    @ @ @ @
    1

    1
    @

    1
    B B

    PCB Fedical Mark PAD


    FD1 FD2 FD3 FD4 FD5 FD6
    1

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 SKEW
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 43 of 65
    5 4 3 2 1
    A B C D E

    TPM IC +1.8VS
    +1.8VS_TPM

    @
    RG3561 2 0_0402_5%

    1 1
    +1.8VALW
    TPM@
    RG3571 2 0_0402_5%

    +3VALW

    +1.8VS_TPM

    1@
    1 C111
    @ 10U_0603_6.3V6-M
    C110
    please close device VDD/GND pins 2
    0.1U_0402_10V7-K
    2
    TPM@
    RG3581 2 0_0402_5%
    1 1
    TPM@ TPM@

    22
    C112 C113

    1
    0.1U_0402_10V7-K 10U_0603_6.3V6-M 10K_0402_5% UTPM1 SLB9670VQ2.0_VQFN32_5X5
    2 2 R154 TPM@

    VDD3

    VDD2

    NCI/VDD1
    D25
    2 1 2 SPI_CS_R# 2 1 18 2
    9 SPI_CS2#_TPM PIRQ# TPM_GP2
    3 2 1
    NCI1 +1.8VS_TPM
    @ 4
    RB751V-40_SOD323-2 SPI_SI_R 21 NCI2 5 R155 TPM@
    SCS00008K00 SPI_SO_R 24 MOSI NCI3 10 10K_0402_5%
    MISO NCI4 11
    NCI5 12
    NCI6 13
    SPI_CS_R# 20 NCI7 14
    SPI_SI RG1 2 1 0_0402_5% SPI_SI_R CS# VDD/NCI8 15
    9 SPI_SI SPI_SO SPI_SO_R SPI_CLK_R NCI9
    RG2 2 1 0_0402_5% 19 16
    9 SPI_SO SCLK GND/NCI10 25
    TPM_PLT_RST# 17 NCI11 26
    RST# NCI12 27
    @ NCI13
    R156 1 2 10K_0402_5% SPI_CS_R# 6 28
    +1.8VS_TPM GPIO NCI14 31
    SPI_CLK RG3 2 1 0_0402_5% SPI_CLK_R 7 NCI15
    9 SPI_CLK PP

    1
    29
    NC1 R157 @
    30
    NC2 10K_0402_5%

    GND1

    GND2

    GND3

    GND4

    GND5

    2
    2

    23

    32

    33
    +1.8VS_TPM

    3 3
    1

    R158
    SA000075L50
    10K_0402_5%
    2

    TPM_PLT_RST#
    42 TPM_PLT_RST#

    1
    @
    C909
    0.1U_0402_10V7-K
    2

    NOTE:
    Check timing sequence in SDV phase.

    5 ms < t
    NOTE:
    1) It is recommended to connect the TPM to the system's
    standby voltage to improve performance.
    2) SPI_RST# must be asserted for at least 5 msec after
    4 0 < t VSB power-up. 4
    VSB 3) VSB may come up anytime before VDD power-up,
    but not after VDD power-up.
    4) SPI_RST# may be asserted together with VDD power
    negation, but should not at any point exceed 0.5V
    VDD above the VDD power level.
    1 ms < t
    Security Classification LC Future Center Secret Data Title
    Issued Date 2017/02/16 Deciphered Date 2018/06/01 TPM
    SPI_RST#
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 44 of 65
    A B C D E
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 TOUCH PAD/FPR/Smart Card
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom C 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 45 of 65
    5 4 3 2 1
    5 4 3 2 1

    KSI[0..7]
    42 KSI[0..7]
    KSO[0..17]
    42 KSO[0..17]

    42 KB_FN
    KB_FN Keyboard CONN
    +3VS +5VS +3VS +5VS
    NUMLOCK_LED CAPSLK_LED

    1
    0817:Follow Intel
    R159 R160 R161 R162
    @ 300_0402_5% 300_0402_5% 300_0402_5% 300_0402_5% +3VS +3VS
    @ @

    2
    R163 R164
    1 2 100_0402_5% NUMLOCK_LED 1 @
    2 100_0402_5% CAPSLK_LED
    D D

    3
    D D
    2 Q9A 5 Q9B
    7 NUMLOCK_LED# 42 CAPSLK_LED#

    1
    G L2N7002KDW1T1G_SOT363-6 G L2N7002KDW1T1G_SOT363-6 JKB1

    2
    R174 40 42
    40 GND2

    1
    1 S 1 S R166 R167 R168 R169 R170 R171 R172 R173 0_0402_5% 39 41

    4
    39 GND1

    1
    R165 15K_0402_5% 15K_0402_5% 15K_0402_5% 15K_0402_5% 15K_0402_5% 15K_0402_5% 15K_0402_5% 15K_0402_5% NUMLOCK_LED 38
    @ @ KSO17 37 38
    C114 R175 C115 @ 100K_0402_5% @ @ @ @ @ @ @ @

    2
    100P_0402_50V8J @ 100K_0402_5% 100P_0402_50V8J KSO16 36 37

    1
    2 EMC@ 2 EMC@ @ TP4MIDDLE 35 36

    2
    2 TP4RIGHT 34 35
    TP4LEFT 33 34
    32 33
    CAPSLK_LED 31 32
    30 31
    KB_FN 29 30
    F4_LED 28 29
    F1_LED 27 28
    FN_LED 26 27
    +3VS +5VS +3VS_KB 25 26
    +3VS +5VS KSO11 24 25
    KSO8 23 24
    F4_LED F1_LED 23

    1
    KSO10 22
    22
    1

    1
    KSO12 21
    R179 KSO9 20 21
    R176 R177 R178 300_0402_5% KSO13 19 20
    @ 300_0402_5% 300_0402_5% 300_0402_5% @ KSO15 18 19

    2
    @ KSO5 17 18
    2

    2
    R180 R181 KSO7 16 17
    1 2 100_0402_5% F4_LED 1 @
    2 100_0402_5% F1_LED KSO6 15 16
    KSO3 14 15
    KSO1 13 14
    13
    6

    3
    D D KSI5 12
    2 Q10A 5 Q10B KSO2 11 12
    9 F4_LED# G 7 F1_LED# G KSO4 10 11
    L2N7002KDW1T1G_SOT363-6 L2N7002KDW1T1G_SOT363-6
    KSI0 9 10
    1 9
    1

    1
    1 S S KSI2 8
    1

    4
    R182 C117 R183 KSO0 7 8
    @ @ KSI1 6 7
    C116 100K_0402_5% 100P_0402_50V8J 100K_0402_5%
    100P_0402_50V8J 2 EMC@ KSI4 5 6
    2 EMC@ KSO14 4 5
    2

    2
    KSI6 3 4
    @ @ KSI7 2 3
    KSI3 1 2
    1

    2
    HIGHS_FC5AF401-3181H
    D27 ME@
    PESD5V0U2BT_SOT23-3
    EMC@
    C C

    FnLock_LED

    1
    +3VS +5VS
    1

    R184 R185
    @ 300_0402_5% 300_0402_5%
    @
    2

    R186
    1 2 100_0402_5% FN_LED
    1

    D
    2 Q11
    9 FN_LED#
    G 2N7002WT1G_1N_SC-70-3
    S SB000019400
    3
    1

    1 @
    R187
    C118 100K_0402_5%
    100P_0402_50V8J @
    2 EMC@
    2

    Click Pad +3VS

    Track Point
    B B

    1
    R521
    0_0402_5% +5VS +3VS

    2
    @ ME@

    2
    HIGHS_FC5AF121-2121H +5VS +5VS_TPCP R1012 R189
    1 @ 0_0402_5% 0_0402_5%
    APU_SMB1_CLK 2 1 @
    7 APU_SMB1_CLK 2
    3 R188 1 2 0_0402_5%

    1
    TP4DATA 4 3 +3VS
    TP4CLK 5 4 @
    APU_SMB1_DATA 6 5 R1011 1 @ 2 0_0402_5% JTP1
    7 APU_SMB1_DATA 6 +3VS_TPCP
    7 1
    LID_CLOSE# 8 7 TP4DATA 2 1
    42 LID_CLOSE# CP_CLK 9 8 TP_RESET_R 3 2
    42 CP_CLK CP_DATA 10 9 TP4MIDDLE 4 3
    42 CP_DATA 11 10 13 TP4RIGHT 5 4
    PAD_DISABLE 12 11 GND1 14 TP4LEFT 6 5
    42 PAD_DISABLE 12 GND2 7 6
    +3VS_TPCP +3VS_TPCP TP4CLK 8 7
    JCP1 9 8
    KBD_BL_PWM 10 9
    42 KBD_BL_PWM KB_BLK_DTCT# 11 10 13
    41 KB_BLK_DTCT# 12 11 GND1 14
    12 GND2

    1
    R190 R191
    10K_0402_5% @ 10K_0402_5%
    @ JAE_FL10F012HA1R3000
    ME@

    2
    R192 1 2 100K_0402_5% PAD_DISABLE TP_RESET_R
    +3VS +3VS_TPCP

    C119 1 2 0.1U_0402_10V7-K LID_CLOSE# R193 1 2 100K_0402_5% RPE7

    3
    D 1 4 TP4CLK +3VS_TPCP
    TP_RESET# 5 Q12B 2 3 TP4DATA 1 1
    G L2N7002KDW1T1G_SOT363-6
    4.7K_0404_4P2R_5% C120 C121
    S 22U_0603_6.3V6-M 22U_0603_6.3V6-M

    4
    6
    D +3VALW 2 2
    2 @ @
    Q12A
    42 TP4_RESET G L2N7002KDW1T1G_SOT363-6
    SB000013A00 R196 2 @ 1 100K_0402_5% KB_BLK_DTCT#
    S

    1
    A TP4CLK CP_DATA A
    @

    1
    R197 1 2 100K_0402_5% KBD_BL_PWM
    TP4DATA CP_CLK R600
    @ 10K_0402_5%
    1 1 R198
    2

    2
    C122 C123 D28 2 1
    100P_0402_50V8J 100P_0402_50V8J PESD5V0U2BT_SOT23-3
    2 EMC_NS@ 2 EMC_NS@ EMC@ 0_0402_5%
    @
    1

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 CP/TPOINT/KB CONN.
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 46 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    POWER ADAPTER Bi-COLOR(ORANGE/WHITE)

    +3VALW
    C C

    1
    R307
    @ 300_0402_5%

    LED1

    2
    1/16W_270_5%_0402 1 2 R200 BATT_CHG_LED R303 1 2 0_0402_5% BATT_CHG_LED_R A1 C
    ORG

    R300 1 2 0_0402_5% PWR_STATUS_LED_R


    A2

    6
    D WHI
    BATT_CHG_LED# 2 Q18A 1222A-S2ST3D-C30-2C-FTK_ORG_WHI
    42 BATT_CHG_LED# G L2N7002KDW1T1G_SOT363-6 SC50000GM00

    2
    1 1023: change 0 ohm to R SHORT S LED LTW-327DSKF-5A 3X1 ORANGE/WHITE
    1

    S R304

    1
    C151 R308 0_0402_5%
    @
    100P_0402_50V8J 100K_0402_5%
    2 EMC_NS@

    1
    2

    1023: change 0 ohm to R SHORT


    @
    +5VALW

    1
    R305
    @ 300_0402_5%
    B B

    2
    R306
    1 2 PWR_STATUS_LED
    1/16W_330_5%_0402

    3
    Q18B D
    PWR_STATUS_LED# 5
    42 PWR_STATUS_LED# G
    1 1 L2N7002KDW1T1G_SOT363-6
    R301 S

    4
    C152 100K_0402_5%
    @
    100P_0402_50V8J
    2 EMC_NS@
    2

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 POWER LED
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 47 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    FAN CONN.

    +5VS

    1023: change 0 ohm to R SHORT


    40mil JFAN1

    1
    7
    R201 6 GND2
    0_0603_5% GND1
    5
    42 EC_FAN_PWM 5
    4

    2
    3 4
    +5VS_FAN 42 EC_FAN_SPEED 3
    2
    1 2
    C
    42 FAN_ID 1 C
    1 HIGHS_WS33050-S0351-HF
    ME@
    @ C907
    0.1U_0402_10V7-K
    2

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 FAN CONNECTOR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 48 of 65
    5 4 3 2 1
    R520
    Close to THU1 REMOTE+_R 2 1 0_0402_5% REMOTE+
    REMOTE+_R @
    1 R900
    C128 REMOTE-_R 2 1 0_0402_5% REMOTE-
    @
    2200P_0402_50V7-K
    2 REMOTE-_R

    REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:


    Trace width/space:10/10 mil
    Trace length:<8"
    change to main source SB00000ZJ00 01/16 JT

    REMOTE+

    1
    1
    Near Charge
    Q168

    C
    C130
    2 B
    SMSC thermal sensor 100P_0402_50V8-J
    2
    LMBT3904WT1G_SOT323-3

    placed near APU

    E
    REMOTE-
    +3VS

    3
    THU1
    1 8 TH_SMB_CK4
    VDD SCL
    REMOTE+_R 2 7 TH_SMB_DA4
    1 D+ SDA
    C126
    REMOTE-_R 3 6 +3VS
    0.1U_0402_10V6-K D- ALERT#
    2 1 2 4 5
    +3VS R202
    10K_0402_5% T_CRIT# GND
    NCT7718W_MSOP8

    Address 1001_101xb TH_SMB_CK4 1


    RP14
    4
    TH_SMB_DA4 2 3

    2.2K_0404_4P2R_5%

    0929：Change Thermal sensor SMB3 to SMB4

    +VLP

    1
    C902

    1
    0.1U_0603_16V7-K

    2
    R952
    16.9K_0402_1%

    U16

    2
    1 8 NTC_V_1
    VCC TMSNS1
    2 7 OTP_N_002 1 R951 2
    +3VS @ GND RHYST1
    R9501 2 OTP_N_003 3 6 11.8K_0402_1%
    54,57 MAINPWON 0_0402_5% OT1 TMSNS2
    4 5
    OT2 RHYST2

    100K_0402_1%_NCP15WF104F03RC
    G718TM1U_SOT23-8
    2
    G

    1
    Vgs(th) Max >=2.0V

    RT7
    EC_SMB_CK4 6 1 TH_SMB_CK4 over temperature threshold:
    S

    42,58 EC_SMB_CK4
    D

    RSET=3*RTMH

    2
    Q30A
    2N7002KDWH_SOT363-6
    100+/-30C
    1 R678 2 0_0402_5%
    Hysteresis temperature threshold.
    RHYST=(RSET*RTML)/(3*RTML-RSET)
    5
    G

    @ 80+/-30C
    EC_SMB_DA4 3 4 TH_SMB_DA4
    S

    42,58 EC_SMB_DA4
    D

    Q30B
    2N7002KDWH_SOT363-6
    1 R679 2 0_0402_5%
    @
    1024: Add lever shift
    Security Classification LC Future Center Secret Data Title
    Issued Date 2017/02/16 Deciphered Date 2018/06/01 Thermal Sensor
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 49 of 65
    A B C D E

    +3VS +3VS_GS
    RG4
    1 2

    0_0402_5%

    1023: change 0 ohm to R SHORT


    1 1

    +3VS_GS TABLE
    RG9 TABLE of G-Sersor (UG5701)
    10K_0402_5% P/N ADDR_SEL Address
    @ Vendor P/N LCFC P/N
    1 2 GSENSE_INT
    BOSCH BMA255 SA00005YJ00
    H 32h (W) & 33h (R)
    Kionix KX022-1020 SA000081E00 BMA255
    +3VS_GS L 30h (W) & 31h (R)
    2

    RG10 H 3Eh (W) & 3Fh (R)


    @ 10K_0402_5% KX022-1020
    L 3Ch (W) & 3Dh (R)

    APS G-Sensor
    1

    ADDR_SEL
    1

    0_0402_5%
    RG11
    1023: change 0 ohm to R SHORT
    2

    2 +3VS_GS 2

    1
    0_0402_5%
    RG8 1023: change 0 ohm to R SHORT

    2
    UGSEN1
    ADDR_SEL 1 12 EC_SMB_CK3_G RG355 1 2 0_0402_5%
    SDO SCL EC_SMB_CK3 8,42
    8,42 EC_SMB_DA3 RG12 1 2 0_0402_5% EC_SMB_DA3_G 2 11
    +3VS_GS 3 SDA PS 10
    4 VDDIO CSB 9
    RG5 1 2 0_0402_5% GSENSE_INT_R 5 NC GND 8
    42 GSENSE_INT INT1 GNDIO
    1 Test_Point_12MIL 6 7 1
    TP151 INT2 VDD
    1 2
    2 BMA255_LGA12_2X2 C915
    C916 1023: change 0 ohm to R SHORT CG34 100P_0402_50V8J
    SA00005YJ00 2@
    100P_0402_50V8J CG35 0.1U_0402_10V6-K
    2@ 0.1U_0402_10V6-K 1
    1

    CLOSE VDDIO CLOSE VDD

    3 3

    4 4

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 G SENSOR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 50 of 65
    A B C D E
    1 2 3 4 5

    3/5VS load Switch


    Check 5VLP +5VALW To +5VS
    V9B+ +5VALW 2
    R204
    1 0_0402_5% 3VSON
    +3VALW To +3VS
    A @ A
    +3VALW
    Check 1 VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=18mohm

    1
    C140 +3VS

    1
    R955 @ U13 @
    R208 0.1U_0402_10V7-K 1 14 +3VS_LS J10 1 2 JUMP_43X118
    300K_0402_1% @ 1K_0402_5% 2 2 VIN1_1 VOUT1_2 13 1 2
    VIN1_2 VOUT1_1 1
    1

    2
    3VSON 3 12 C131 1 2 1000P_0402_50V7-K @ C132

    2
    SUSP 9V-->5.1V R205 C134 ON1 CT1 0.1U_0402_10V7-K
    28 SUSP 1U_0402_6.3V6-K 2
    SUSP# 2 1 0_0402_5% 5VSON +5VALW 4 11
    13V-->7.4V @ 2 VBIAS GND

    1
    +5VALW 5VSON 5 10 C136 1 2 1000P_0402_50V7-K
    1 ON2 CT2
    R960 C141 +5VS
    402K_0402_1% @ 6 9 @
    0.1U_0402_10V7-K 7 VIN2_1 VOUT2_2 8 +5VS_LS J12 1 2 JUMP_43X118
    2 VIN2_2 VOUT2_1 1 2
    1
    2

    1 15
    GPAD @ C137

    1
    D
    C139 TPS22966DPUR_WSON14_2X3 0.1U_0402_10V7-K
    2 1U_0402_6.3V6-K 2
    42,58,64 SUSP# 2
    G Q16
    S 2N7002WT1G_SC-70-3
    3

    +5VS

    +5VS
    +3VALW
    1 @
    C914 0.1U_0402_10V7-K
    @ C912 1 2
    0.1U_0402_10V7-K
    2

    B Reserves for split moat B

    SB000013Q00，SB00001B300 AON7400
    +0.9VALW_VDDP to +VDDP 10A request
    V9B+ 9V--13V
    +1.8VALW to +1.8VS 2A request
    Load MOS N MOS Id =< 40A Vgs(th) Max >= 2.6V
    Rds(on) >= 7.5mohm Load MOS N MOS Id =< 40A Vgs(th) Max >= 2.6V
    +0.9VALW_VDDP Q25 +0.9VS_VDDP Rds(on) >= 7.5mohm
    +/- 1.5% AON6414AL_DFN8-5 +/- 1.5%
    +1.8VALW
    Q28
    +1.8VS

    AON6414AL_DFN8-5
    1
    1 2 1 1 1
    1

    1
    C305 5 3 R311 1 2 C314
    @ 10U_0603_6.3V6M C310 C311 5 3 10U_0603_6.3V6M C315
    10U_0603_6.3V6M 1 1U_0402_6.3V6-K @ 1U_0402_6.3V6-K
    2

    2
    2 2 10U_0603_6.3V6M 2
    1 1 1
    4

    @ C306 C307 2 C313

    4
    0.1U_0201_6.3V6-K @ @ C312 @
    C
    2 0.01U_0201_25V6-K 0.1U_0201_6.3V6-K 0.01U_0201_25V6-K C
    2 1.8VS_GATE 2 2
    V9B+
    R312 R318
    0.9VS_GATE_R
    2 1 1.8VS_GATE_R 2 1 0_0402_5% 1.8VS_GATE 1 R320 2150K_0402_5%
    @ 0_0402_5% @
    1

    1
    D Q29
    1 R314 1
    C308 C316 2 SUSP
    820K_0402_5% G
    R322
    0.01U_0201_25V6-K 0.01U_0201_25V6-K 1M_0402_5%
    2 @ 2 S 2N7002KW_SOT323-3
    2

    3
    +0.9VS_VDDP

    For DisCharge
    +1.8VS
    +0.6VS
    1

    R209 R953
    1

    D D
    @ 470_0402_5% @ 470_0402_5%
    R954
    @ 470_0402_5%
    2

    2
    6

    Q166A D
    SUSP 2
    1

    D
    Q166B D Title
    2 SUSP
    G
    SUSP 5 Security Classification LC Future Center Secret Data
    CHM1022VESGP_SOT-563-6 G
    G
    Q17
    S Issued Date 2017/02/16 Deciphered Date 2018/06/01 3VS/5VS/1.1VS/VDDIO_RUN
    1

    S CHM1022VESGP_SOT-563-6
    3

    @ @ S
    4

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    2N7002WT1G_SC-70-3 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    @
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 51 of 65

    1 2 3 4 5
    5 4 3 2 1

    D D

    +3VL

    +RTC_LDO

    2
    D30 50mA
    RB751V-40_SOD323-2
    JRTC1 +RTCBATT
    D31
    +RTC_33 +RTC_LS +RTC_LDO
    R210 U15 @

    1
    1 1 2 2 1 2 3 J15 2 1 JUMP_43X39
    1 2 VIN VOUT 2 1
    2 3 1K_0402_1%
    1 RB751V-40_SOD323-2
    GND1

    1
    4 C149
    C GND2 C148 1 4 C
    GND ENABLE

    2
    @ 1U_0402_6.3V6-K 10U_0603_6.3V6M JCLR1

    2
    ME@ 2 NCP698SQ15T1G_SC-82AB4 SHORT PADS
    HIGHS_WS33020-S0351-HF R211 1 2 10K_0402_5% @

    1
    1
    C150
    @ 1U_0402_6.3V6-K
    2
    VFB=0.8V

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/16 Deciphered Date 2018/06/01 3VS/5VS/1.1VS/VDDIO_RUN
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 52 of 65

    5 4 3 2 1
    5 4 3 2 1

    VDDP / 6A
    CONVERTOR
    +VLP/ 100mA
    Richtek +1.8VA / 3A
    LV6228CGQUF +5VALW/8A
    PWM RICHTEK
    CONTROLLER +1.2V / 6A
    EC_ON2_3V EN
    D
    FOR SYSTEM PGOOD +5V_PWRGD
    D

    LV5075A
    SYSTEM2 +2.5V /1A
    TI
    +3VL/ 100mA
    BQ25700A V9B+ Silergy FOR SYSTEM LDO
    TYPE-C Battery Charger SYX198BQNC POWER
    +3VALW/8A
    Buck-Boost PWM
    EC_ON_5V EN PGOOD +3V_PWRGD SYSON EN1
    +0.6VS / 1A
    FOR SYSTEM
    EC_ON2_3V
    EN2

    EC_ON3_VDDP EN3
    SMBus Richtek VDDC_VDD/TDC 35A SUSP# EN4

    RT3662ACGQW
    FOR CPUCORE VDDCR_SOC/TDC 10A PGOOD PG for all MOIC power rail
    PAGE 58
    APUPWR_EN EN PGOOD
    PGOOD_NB IMVPPOK

    Batt. MOSFET
    RICHTEK
    C C

    RT8068AZQW +1.5VS/0.5A

    SUSP# EN FOR VDDP


    RESERVE FOR PMIC

    Battery

    B B

    A A

    <Variant Name>

    Security Classification LC Future Center Secret Data Title

    Issued Date Deciphered Date Block Diagram

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 53 of 65
    5 4 3 2 1
    5 4 3 2 1

    PD2
    PD1
    1SS355VMTE-17
    1SS355VMTE-17 PR1 PR2 1 2
    PR53
    100K_0402_1% 10K_0402_1% VSYSTEM2
    49,57 MAINPWON 1 2 2 1 1 2 1 2
    1 2
    V9B+
    0_0402_5% PD3

    2
    1SS355VMTE-17
    20171023

    3
    D D
    PQ1
    E
    2B PR3
    PMBT3906 750K_0402_5%

    1
    C

    1
    VDD_SOC VDDC_VDD P1 VDDC_VDD P2
    540_0402NEW_30% 540_0402NEW_30% 540_0402NEW_30%

    1
    C PRT1 PRT2 PRT3
    PQ2 2 2 1 2 1 2 1
    PMBT3904 B
    E 2

    1
    D
    PC1 2
    OTP_RESET 42
    1U_0603_25V7-K G
    1 S

    3
    2 1 2 1

    PQ3 PRT6 PRT5


    2N7002WT1G 540_0402NEW_30% 540_0402NEW_30%

    CHARGER 1.2V

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/03/14 Deciphered Date 2017/03/01 DCIN / VIN Detector
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 54 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    VMB2 VMB
    PF2 PL3 EMC@
    JBATT1
    12A_32V_0501012.WRS BLM18KG300TN1D_2P
    1 2 1 1 2
    1 BATT+
    9 2
    PTH1 2 EC_SMCA
    10 3
    3
    4 EC_SMDA PL4 EMC@
    PTH2 4
    5
    5
    EMC@ BLM18KG300TN1D_2P
    EMC@

    2
    11 6 1 2
    PTH3 6 7 PC9 PC10
    12 7 8 1000P_0402_50V 0.01U_0402_25V

    1
    PTH4 8

    3
    C C

    PESD5V0U2BT_SOT23-3
    HIGHS_WS33081-S0201-HF
    1

    1
    EMC_NS@
    ME@ PR15
    PR14

    PD7
    100_0402_1%

    1
    100_0402_1%
    2

    2
    EC_SMB_CK1 42,56

    EC_SMB_DA1 42,56
    PR16
    100K_0402_1%
    2 1 +3VL

    B 1 2 B
    BATT_TEMP 42,56
    PR17
    10K_0402_1%

    A A
    <Variant Name>

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/03/14 Deciphered Date 2017/03/01 BATTERY CONN/PH1
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 55 of 65
    5 4 3 2 1
    5 4 3 2 1

    PJ101
    2 1
    2 1
    @ JUMP_43X79
    D D

    201701025

    VSYSTEM2
    EMC_NS@
    PL101
    1UH_PCMB053T-1R0MS_7A_20% PR102 PQ102
    EMC@ PL102 PQ101
    EMC_NS@ EMC_NS@ 1 2 VSYSTEM3
    0.01_1206_1%
    1 2 VBUS
    BSC0923NDI_PG-TISON-8-7
    PR106 56_0402_5%
    2.2UH_CMLE063T-2R2MS_10A_20%
    1 2 EMC@ SIZ340DTT1_POWERPAIR_3X3-9-10
    EMC@ EMC@ V9B+_P 2
    PJ102
    1
    2 1 V9B+

    9
    EMC@
    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K
    33U_D2_25VM_R40M
    2 2

    1
    10_0201_1%

    1000P_0201_50V7-K
    PC101 PC102 @ JUMP_43X79

    10U_0805_25V6K

    0.1U_0402_25V6-K

    0.1U_0402_25V6-K
    0.01U_0201_25V7-K
    1

    1
    EMC@

    PR103

    PC106

    PC110

    PC111

    PC112

    PC113

    PC114

    PC115

    PC116

    PC123
    PR104 5 0.047U_0402_25V7K 0.047U_0402_25V7K 7 10
    0.1U_0402_25V6-K

    0.1U_0402_25V6-K

    1
    EMC@
    +

    PC109
    10_0201_1% 2 4 PR105 6 4
    PC143

    PC144
    1

    1
    1 1

    PC107

    PC140

    PC139

    PC108

    PC104

    PC105
    @PC117 3 56_0402_5% 5 3

    330P_0402_50V7-K
    2

    2
    2

    2
    PC103
    0.1U_0402_25V7K PR107
    EMC@ 2

    1 2

    12
    2 2 1 2.2_0603_5% PR108
    2

    PC118
    2.2_0603_5% PC119

    0.01U_0402_25V7K
    2 330P_0402_50V7-K PQ103

    2
    @ 2 30 25 AON7401

    1
    BTST1 BTST2

    1
    0_0201_5%

    0_0201_5%

    PC121
    1
    LX1_CHG LX2_CHG

    PR109

    PR110
    PC120 32 23 2 PR111
    0.01U_0402_25V7K 1 SW1 SW2 3 0.01_1206_1%

    1
    1 DL1_CHG 29 26 DL2_CHG 5 1 2
    LODRV1 LODRV2 BATT+

    2
    PC122 DH1_CHG 31 24 DH2_CHG PC125

    10U_0805_25V6K
    20170710

    0.1U_0402_25V7K
    1 1

    1
    HIDRV1 HIDRV2

    @ PC146
    0.47U_0603_25V6-K 1 2

    1U_0402_25V6-K

    1U_0402_25V6-K
    0.1U_0402_25V7K
    PC124

    PC126
    1 22

    1
    VBUS VSYS

    PC127

    PC128
    0.1U_0402_25V7K

    2
    C @PC129 2 21 BATDRV# 2 2 C
    1U_0402_25V6-K ACN BATDRV#

    2
    1 2 3 20
    ACP SRP
    1 2 VDDA 7 PU101 19
    BQ25700_VDD VDDA SRN PR113 10_0603_5% 1 2
    BQ25700ARSNR_QFN32_4X4 BQ25700_VDD

    1
    PR112 6 28 1 2 PR114 10_0603_5% 1 2
    10_0402_1% PR115 PR116 40.2K_0201_1% ILIM_HIZ REGN PC130 2.2U_0402_10V6-K
    255K_0201_1% 1 2 1 2 PC132 680P_0201_25V7-K
    1 PC131 1800P_0201_25V7-K 16 17 1 2 1 2
    2 1 PC133 COMP1 COMP2 PR117 20K_0201_1%

    2
    PC134 100P_0201_50V7-K 1 2
    1U_0402_25V6-K 42,58,59 VR_HOT# 1 2 11 18 PC135 15P_0201_25V8-J

    1
    2 PR119 0_0201_5% PROCHOT# CELL_BATPRES
    PR121
    1 2 13

    220K_0201_5%
    42,55 EC_SMB_CK1 SCL

    PR118
    PR120 0_0402_5% 8 1 2 ADP_I 42
    1 2 12 IADPT
    42,55 EC_SMB_DA1 PR122 0_0402_5% SDA 9 1 2 0_0402_5%

    2
    1 2 4 IBAT PR124 0_0201_5%
    42 ACIN CHRG_OK
    PR125 0_0402_5% 10 1 2 PSYS 42
    1 2 5 PSYS PR126 0_0201_5%
    PR127 0_0201_5% ENZ_OTG 27 VDDA
    PGND

    1
    15 add PSYS, connect to EC

    100P_0201_50V7-K

    100P_0201_50V7-K

    100P_0201_50V7-K
    1

    1
    CMPOUT 33

    30K_0402_1%
    PR128
    PAD

    1
    PR150
    100K_0201_1% 14 PR129
    PR131 CMPIN

    1
    D

    PC136

    PC138

    PC137
    137K_0402_1% PR123
    1 2 2 PQ105 82K_0201_1%

    1
    42 ACOFF G 2N7002WT1G_SC-70-3

    2
    S

    2
    0_0402_5%

    2
    B B

    PR133
    10K_0201_1%

    1
    1
    D
    PR130

    1
    2 100K_0201_1%
    G PQ104
    42,55 BATT_TEMP S

    2
    1
    2N7002WT1G_SC-70-3
    PR132
    1M_0201_5%

    2
    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/05 Deciphered Date 2014/12/31 CHARGER


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EE480 NM-B421
    Date: Tuesday, April 10, 2018 Sheet 56 of 65
    5 4 3 2 1
    5 4 3 2 1

    +3VALW
    FSW=750 KHz
    V9B+ @
    TDC:8A
    D
    2
    PJ201
    1 EMC@ EMC@ +3V_VIN 7 2 +3V_PWRGD
    OCP:11A D

    2 1 EN2 PG

    2200P_0402_25V7-K

    1
    PR202 PC203

    10U_0805_25V6-K

    10U_0805_25V6-K
    0.1U_0402_25V6-K
    +3VALW

    1
    JUMP_43X79 PR201 8 6 +3VBS 1 2 1 2

    PC232

    PC201
    IN BS

    PC202

    PC229
    1M_0402_5% PL201 8A
    0_0603_5% 0.1U_0603_25V7-M 2.2UH_PCMB063T-2R2MS_8A_20%
    EMC@ EMC@ PJ202

    2
    9 10 +3VLX 1 2 +3VALW_P 2 1

    2
    GND LX 2 1

    EMC_NS@
    20171023 @JUMP_43X118

    2
    3V_ON 1 4 +3VALW_OUT 1 2 +3VALW_P
    EN1 OUT PR203 0_0402_5% PR204
    100mA

    2200P_0402_25V7-K
    22U_0805_6.3V6-M

    22U_0805_6.3V6-M

    22U_0805_6.3V6-M

    22U_0805_6.3V6-M

    0.1U_0402_25V6
    4.7_0603_5%

    1
    +3VALW_FB 3 5 PR205 1 2 0_0603_5%

    PC204

    PC205

    PC206

    PC207

    PC210

    PC211
    PR206 FB LDO +3VL

    2 1
    EC_ON2_3V 1
    42,58 EC_ON2_3V 2 1 EMC_NS@

    2
    PC208
    PU201 4.7U_0603_6.3V6-K PC209
    0_0402_5%
    @PR5978 SYX198BQNC_QFN10_3X3 680P_0402_50V7K

    1
    0_0402_5% 2
    1 2

    1
    2
    @PC213 PR208
    20171025 0.1U_0402_25V6-K 1M_0402_5% change PR205 to 0603 size 2017.7.4

    1
    PC212 PR207
    +3VL

    2
    0.01U_0402_25V7-K 1K_0402_1%
    1 2 1 2
    100K_0402_1%
    1

    PR216
    100K_0402_1%
    1

    PR217

    C 5V_ON C
    2

    D
    +3VALW

    1
    D
    2 PQ201A
    2

    G 2N7002KDWH_SOT363-6 2 PQ202
    3

    2N7002WT1G_SC-70-3
    47K_0402_1%

    D G
    1

    1
    5 S
    PR5979

    49,54 MAINPWON S
    1

    3
    G PR209
    @
    100K_0402_5%
    PQ201B S
    4

    PR210
    2

    2
    2N7002KDWH_SOT363-6 0_0402_5%
    @ add 5V maipwron protection 2017.7.3 +3V_PWRGD 1 2

    follow INTEL 2017.04.05


    @ PR211
    +5V_PWRGD 1 2 +5VALW_PG 58 +5VALW
    0_0402_5% 20171023 FSW=750 KHz
    V9B+ PR212
    PC217
    0.1U_0603_25V7-M
    TDC:8A
    +5VBS 1 2 1 2 OCP:12A
    0_0603_5%

    PU202
    7

    1
    @ SH000006O0J
    8A

    BOOT
    PGOOD
    +5VALW
    2
    PJ203
    1 EMC@ EMC@ +5V_VIN 5 2 PL202
    2 1 VIN LX1
    EMC@ EMC@ 2
    B 1UH_PCMC063T-1R0MN_11A_20% PJ204 B
    2200P_0402_25V7-K

    3 +5VLX 1 2 +5VALW_P 1
    10U_0805_25V6-K

    10U_0805_25V6-K
    0.1U_0402_25V6-K

    LX2 2 1
    1

    JUMP_43X79 20171025
    PC233

    PC215

    PC214

    PC216

    LV6228CGQUF_UQFN12_3X3 @JUMP_43X118

    2
    EMC_NS@

    10P_0402_50V8-J
    2

    2
    5V_ON 6 10 5V_FB

    2200P_0402_25V7-K
    22U_0805_6.3V6-M

    22U_0805_6.3V6-M

    22U_0805_6.3V6-M

    22U_0805_6.3V6-M

    22U_0805_6.3V6-M

    22U_0805_6.3V6-M

    0.1U_0402_25V6
    1U_0402_6.3V6-K
    EN VOUT 1
    PR214

    0_0402_5%

    PC234
    1

    1
    4.7_0603_5%

    PC6075

    PR5980

    PC219

    PC220

    PC221

    PC222

    PC223

    PC224

    PC227

    PC228
    80.6K_0402_1%

    0.1U_0402_25V6-K

    PR5957
    1

    12

    1
    CLK
    2

    PR5987 11 1 2 2
    PR5988

    PC6074

    +VLP @

    2
    LDO
    EMC_NS@
    0_0402_5%

    2
    42 EC_ON_5V 1 2 0_0603_5%
    1

    1
    9 20171023 PC226

    1K_0402_1%
    2

    VCC
    AGND

    PGND

    1 2

    PR226
    680P_0402_50V7K

    1
    add PC6074 same with edge INTEL
    +5V_VCC @ PR223 +5VALW_P
    0_0402_5% @
    8

    2
    5V_FB
    +5VALW

    1
    LV6228C RT6228A @
    1

    @ PR225
    2

    PR220 NC 0 PR220 15K_0402_5%


    0_0402_5% PC218 PC225
    PR221 0 NC 1U_0603_6.3V7-K 4.7U_0603_6.3V6-K
    1

    2
    2

    PC225 4.7U 1U
    PR5957 0 NC
    1

    PR223 NC 0 FOLLOW INTEL 2017.04.14


    PR215 FOLLOW INTEL 2017.04.14
    A A
    PR5980 0 115K 0_0402_5%

    PR225 NC 15K
    2

    PC234 NC 10P
    <Variant Name>
    PR226 NC 1K
    Security Classification LC Future Center Secret Data Title
    PC6075 1U NC
    Issued Date 2017/03/14 Deciphered Date 2017/03/01 3VALWP/5VALWP
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 57 of 65
    5 4 3 2 1
    A B C D

    1 1

    change VDDP enable to EC_ON3


    +5VALW LV5075_VCC

    PR1902 1 2 0_0402_5% LV5075_VDDQ_EN


    42 SYSON PR1903 1 2 10_0603_5%

    PR1904 1 2 0_0402_5% LV507_2.5V_EN PR1905 1 2 0_0402_5%


    +5VALW_PG 57

    PR1906 1 2 0_0402_5% LV5075_VDDP_EN


    EC_ON3_VDDP
    +1.2V_B+
    PR1908 1 2 0_0402_5% LV5075_1P8VA_EN
    42,57 EC_ON2_3V
    1
    PR1909 2 10_0402_5%
    PR1910 1 2 0_0402_5% LV5075_VTT_EN
    42,51,64 SUSP#

    0.1U_0402_25V7-K
    2.2U_0603_6.3V6-K

    LV5075_PMIC_EN
    0.1U_0402_25V7-K

    LV5075_VSYS
    PC1903
    10.1U_0402_25V7-K

    10.1U_0402_25V7-K

    10.1U_0402_25V7-K

    10.1U_0402_25V7-K

    10.1U_0402_25V7-K

    1
    1M_0402_5%

    PC1901

    PC1902
    2

    2
    @

    28

    27

    41
    PU1901
    1

    9
    Vout=0.9V± 45mV

    VSYS

    PMIC_EN
    VCC

    GND
    PC19052

    PC19062

    PC19072

    PC19082

    PC19092
    LV507_2.5V_EN EC_SMB_DA4
    PR5990

    29 25
    EN_LDO1 SDA EC_SMB_DA4 42 OCP=8~10A
    2

    1 26 EC_SMB_CK4
    +3VALW
    EN_LDO2 SCL EC_SMB_CK4 42 OVP=(1.15~1.25)*Vout
    @ @ @ @ @ LV5075_VDDP_EN 11 24 LV5075_ALERT# PR1912 1 2 0_0402_5%
    EN_V1P0A T_ALERT_B VR_HOT# 42,56,59 UVP=(0.55~0.65)*Vout
    LV5075_1P8VA_EN 16 22 +0.9VALW_PWRGD
    ADD EC_ON3 pull down EN_V1P8A POK_V1P0A @ Fsw=1.2MHZ
    LV5075_VDDQ_EN 31 21 LV5075_1.8VA_PG
    EN_VDDQ POK_V1P8A
    2 +5VALW LV5075_VTT_EN 36 23 LV5075_VDDQ_PGOOD 2

    EN_VTT POK_VDDQ +0.9VALW_VDDP


    100K_0402_5%

    100K_0402_5%

    100K_0402_5%
    1

    1.5A @ LV5075_LX_1P0
    @ 6A
    PR1913

    PR1914

    PR1915

    PJ1901 12 PL1901 PJ1902


    1 2 LV5075_VDDP_VIN 7 LX_V1P0A_12 13 1 2 +VDDP_P 2 1

    22U_0603_6.3V6-M
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    LV5075AGQV_VQFN40_5X5
    1 2 8 VIN_V1P0A_7 LX_V1P0A_13 14 0.33UH_PCMB063T-R33MS_21A_20% 2 1
    Vout=1.8V± 90mV

    0.1U_0402_25V6-K 0.1U_0402_25V6-K
    VIN_V1P0A_8 LX_V1P0A_14
    1

    1
    PC1914
    PC1910

    PC1911

    PC1912

    PC1913

    PC1915

    PC1916

    PC1917
    JUMP_43X39 15 JUMP_43X79
    2

    LX_V1P0A_15
    @ @ +0.9VALW_PWRGD 42 +3VALW EMC_NS@ 10 +1.8VALW OCP=4.8~6A
    2

    2
    VO_V1P0A
    @ @
    OVP=(1.15~1.25)*Vout
    LV5075_1.8VA_PG 2A PJ1903 17 LV5075_LX_1P8 PL1902 PJ1904
    3A
    1 2 LV5075_V1P8_VIN 19 LX_V1P8A_17 18 1 2 +1.8VA_P 2 1
    UVP=(0.55~0.65)*Vout
    1 2 VIN_V1P8A_19 LX_V1P8A_18 @ @ 2 1
    1UH_PH041H-1R0MS_3.8A_20%
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    Fsw=1.2MHZ
    1

    1
    PC1918

    PC1919

    PC1920

    PC1921

    PC1922

    PC1923
    JUMP_43X39 20 JUMP_43X79
    LV5075_VDDQ_PGOOD VO_V1P8A_20
    EMC_NS@
    2

    2
    33 LV5075_UG_1.2V
    38 UGATE_VDDQ PR1916
    PC1924 1 2 10U_0603_6.3V6-M +1.2V_PWM VIN_VTT 32 LV5075_BST_1.2V 1 2 LV5075_BST_1.2V_R
    PJ1905 BOOT_VDDQ
    1A @
    1 2 +0.6VSP 39 0_0603_5% PC1925
    Vout=0.6V± 30mV +0.6VS 1 2 VTT 34 LV5075_LX_1.2V 1 2
    @ @

    LV5075_LX_1P0

    LV5075_LX_1P8
    PHASE_VDDQ
    1

    JUMP_43X79
    Current Limit :Min 1.44A PC1926 40 35 LV5075_LG_1.2V 0.1U_0603_25V7-M
    22U_0603_6.3V6-M VSNS_VTT LGATE_VDDQ
    Vout=2.5V± 125mV
    2

    PR1917 37 +1.2V_PWM
    +3VALW 1 2 LV5075_CS 30 VSNS_VDDQ
    Current Limit :Min 1.5A
    33K_0402_1% CS_VDDQ +2.5V
    @ @ @ UVP=(0.55~0.65)*Vout

    2
    PJ1906 PJ1907
    1A 2 1 LV5075_2.5V_VIN 5 6 +2.5VA_P 1 2
    1A PR1918 PR1919

    10U_0603_6.3V6-M
    2 1 VIN_LDO1 LDO1 1 2
    4.7_0603_5% 4.7_0603_5%
    1

    PC1928
    JUMP_43X39
    JUMP_43X39 PC1927
    V9B+ EMC_NS@ EMC_NS@

    1P0_SN 1

    1P8_SN 1
    10U_0603_6.3V6-M
    Vout=1.8V± 54mV
    2

    2
    3
    4 LDO2 Current Limit :Min 1.5A
    VIN_LDO2 2
    FB_LDO2 UVP=(0.55~0.65)*Vout

    1
    PC1930 PC1931
    680P_0402_50V7-K 680P_0402_50V7-K
    3
    1.5A 3

    2
    EMC_NS@ EMC_NS@
    FB=0.75V @
    +1.2V_B+ EMC@ 2
    PJ1908
    1
    2 1

    2200P_0402_25V7-K
    0.1U_0402_25V6-K
    EMC@
    JUMP_43X79

    10U_0805_25V6-K

    10U_0805_25V6-K
    1

    1
    PC1929

    PC1945

    PC1932

    PC1933
    2

    2
    5
    PQ1901

    D
    AON7408L_DFN8-5

    LV5075_UG_1.2V 4
    G @
    PJ5903
    2 1 +1.2V

    S3
    S2
    S1
    2 1
    JUMP_43X79@

    3
    2
    1
    PL1903 PJ1911
    LV5075_LX_1.2V 1 2 +1.2V_PWM 2 1
    0.47UH_PCME063T-R47MS_25A_20% 2 1
    JUMP_43X79

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    330U_D2_2V_Y
    5 1
    PR1922

    1
    +

    PC1936

    PC1937

    PC1938

    PC1939

    PC1940

    PC1941

    PC1942
    PQ1902 4.7_0805_5%
    D

    AON7380_DFN8-5
    EMC_NS@

    2
    2
    LV5075_LG_1.2V 4

    1.2V_SN
    G
    S3
    S2
    S1

    @ @
    SB00001E900, S TR AON7380 1N DFN in BOM @
    3
    2
    1

    1
    PC1943
    680P_0402_50V7-K Vout=1.2V± 60mV
    EMC_NS@ OCP=15A
    2
    OVP=(1.15~1.25)*Vout
    4 UVP=(0.55~0.65)*Vout 4

    Fsw=1MHZ

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/03/14 Deciphered Date 2017/03/01 PWR-SYSTEM


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JINN/DOOKU 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Date: Tuesday, April 10, 2018 Sheet 58 of 65
    A B C D
    5 4 3 2 1

    V9B+
    APU_VDDC_VIN
    PJ5901 @
    RF_NS@ EMC@ EMC@ 2 1 6A
    2 1
    JUMP_43X118
    EMC@

    2200P_0402_25V7-K
    47P_0402_50V8-J

    33U_D2_25VM_R40M

    33U_D2_25VM_R40M

    33U_D2_25VM_R40M
    1 1 1 1 PL5904
    BLM18KG300TN1D_2P

    10U_0805_25V6-K

    10U_0805_25V6-K
    PC5970

    1
    + + +

    PC5904
    PC5905 FIX EE noise 1 2

    PC6069

    PC5986

    PC5987

    PC5988
    PC5903
    5
    PRE-PWROK METAL VID CODES 0.1U_0402_25V6-K 20180125
    KELVIN close to APU side PQ5901 2 PL5905

    2
    TPCA8065-H 2 2 2 BLM18KG300TN1D_2P
    SVC SVD Boot Voltage 1 2
    1 2
    8 VDDCR_VSS_SENSE VDDC_UGATE2
    D 0 0 1.1V PR5901
    0_0402_5%
    PC6076 PR5991
    4
    EMC@ D
    20171023 2 1 2 1 +VDDC_VDD
    0 1 1.0V 2 1
    680P_0402_50V7-K 100_0402_5%
    1 0 0.9V(Default) PR5902

    3
    2
    1
    PL5901
    100_0402_1% @ @ 1 2 1 2 0.24UH_PCME063T-R24MS1R145_35A_20%
    1 1 0.8V +VDDC_VDD 1 2 VDDC_BOOT2 1 2 VDDC_BOOT2_R 1 2 VDDC_PHASE2 1 2 35A
    PR5903 PC5906 PC5907
    PR5907

    2
    180P_0402_50V8-J 47P_0402_50V8-J PC5908
    100_0402_1% 2.2_0603_5%

    1
    0.22U_0603_25V7-K PR5909
    +1.8VS 2 1 1 2 1 2 1.47K_0402_1% 1 1 1 1
    8 VDDCR_VCC_SENSE PR5908

    330U_D2_2V_Y

    330U_D2_2V_Y

    330U_D2_2V_Y

    330U_D2_2V_Y
    PR5904 PR5905
    4.7_0805_5% + + + +
    10K_0402_1% PR5906 PR5915

    PC5911

    PC5912

    PC5957

    PC5956
    1
    0_0402_5% PC5909 35.7K_0402_1% 2 1

    2
    VDDC_LGATE2
    330P_0402_50V7-K
    1 2 1 2
    4 4
    EMC_NS@ 976_0402_1%
    2 2 2 2 GPU_VDDC

    1VDDC_SN2
    PR5993 0_0402_5%
    PQ5902 PQ5903
    PC5920
    1 2
    FSW=300KHz
    @ VDDC_ISEN2P Slew rate:12.5mv/us
    2

    20171023 TPCA8057-H TPCA8057-H

    3
    2
    1

    3
    2
    1
    PR5981
    10K_0402_1%
    PR5986
    10K_0402_1%
    PR5985
    10K_0402_1% PC5919
    0.47U_0402_25V6-K
    TDC=35A EDC=45A
    PR5975
    1000P_0402_50V7-K
    VDDC_ISEN1N
    OCP=60A
    1 PR5913 2
    OVP=VID+300mV
    1

    2
    APU_SVC APUPWR_EN_R
    @ @ @ 42 APUPWR_EN
    1 2
    +3VS EMC_NS@ 1_0402_1% Load Line=0.6mohm
    APU_SVD Ripple:+/-20mv

    1
    0_0402_5%

    2
    PC6071 PR5971
    KELVIN routing
    MAX AC: VID_VDDC +95mv
    APU_SVT
    0.1U_0402_25V6-K 10K_0402_1% MIN AC: VID_VDDC -80mv

    1
    VDDC_ISEN1P

    2
    2

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    PR5982 PR5983 PR5984 1 2
    VDDC_ISEN1N VR_APU_PWRGD 42
    10K_0402_1% 10K_0402_1% 10K_0402_1% PR5916 0_0402_5% APU_VDDC_VIN

    1
    PC5921

    PC5922

    PC5923

    PC5924

    PC5925

    PC5926

    PC5973

    PC5974

    PC5975

    PC5976
    20171023
    RF_NS@ EMC_NS@ EMC_NS@
    1

    VDDC_ISEN2P

    2
    @ @ @

    2200P_0402_25V7-K
    47P_0402_50V8-J
    +3VS 1 @ @ @ @

    3662_PGOOD
    VDDC_COMP

    10U_0805_25V6-K

    10U_0805_25V6-K
    1

    1
    VDDC_VSEN
    PC5932

    3662_RGND

    PC5989

    PC5990

    PC5930

    PC5931
    VDDC_BOOT2

    VDDC_FB
    1 2 0.1U_0402_25V6-K

    2
    VDDC_UGATE2 2
    PC5927

    1
    0.1U_0402_25V6-K
    APU_SVC

    5
    RG354
    3662_VREF PU5901 PQ5904

    10
    1K_0402_5%

    1
    RT3662ACGQW_WQFN40_5X5 TPCA8065-H
    APU_SVD

    BOOT2

    UGATE2
    ISEN1N

    ISEN1P

    ISEN2P
    VSEN

    FB

    RGND

    PGOOD
    COMP
    2

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    C C
    @ 40 VDDC_PHASE2 VDDC_UGATE1 4
    APU_SVT

    1
    PHASE2

    PC5962

    PC5963

    PC5958

    PC5959

    PC5960

    PC5961

    PC5977

    PC5978

    PC5979

    PC5980
    1 2 APU_VR_HOT_L 11 39 VDDC_LGATE2
    42,56,58 VR_HOT# VRHOT_L LGATE2
    PR5956 0_0402_5%

    2
    VDDC_TSEN VDDC_BOOT1
    0.1U_0201_25V6-K

    12 38

    3
    2
    1
    2

    TSEN BOOT1
    0.1U_0201_25V6-K

    0.1U_0201_25V6-K

    PL5902
    PC6079

    PC6080

    PC6081

    3662_SET1 VDDC_UGATE1
    2

    20171024 13 37 0.24UH_PCME063T-R24MS1R145_35A_20%
    @ @ @ @
    316K_0402_1%

    316K_0402_1%
    26.7K_0402_1%

    SET1 UGATE1 VDDC_BOOT1 1 2 VDDC_BOOT1_R 1 2 VDDC_PHASE1 1 2


    1

    VDDC_IMON 14 36 VDDC_PHASE1
    PR5919

    PR5921

    PR5920

    PR5974

    1
    IMON PHASE1 PC5994
    3662_VREF VDDC_LGATE1 2.2_0603_5%

    2
    15 35 20171023 0.22U_0603_25V7-K
    PR5924
    1

    VREF_PINSET LGATE1 PR5932


    @ SOC_IMON 3662_PVCC 4.7_0805_5%
    delete PWROK pull high 16 34 PR5925 1 2
    @ @
    20171025 IMON_NB PVCC 0_0603_5% +5VALW 1.47K_0402_1%

    2
    APU_POK_R 3662_VCC
    8 APU_PWROK
    1 2 18 17 1 2
    EMC_NS@ PR5911

    1
    3662_SET1 PWROK VCC VDDC_LGATE1 4 4 2 1
    PR5926 0_0402_5% PR5927

    1VDDC_SN1
    1 2 APU_SVC_R 19 33 SOC_LGATE
    PR5929 2.2_0603_5% 976_0402_1%
    VDDC_TSEN 8 APU_SVC SVC LGATE_NB
    1 2 PR5928 0_0402_5%
    60.4K_0402_1% 1 2 APU_SVD_R 20 32 SOC_PHASE
    PQ5905 PQ5906 PC5918
    8 APU_SVD

    1
    SVD PHASE_NB

    2.2U_0402_10V6-K
    PR5930 0_0402_5% TPCA8057-H TPCA8057-H 1 2
    PH5901

    3
    2
    1

    3
    2
    1
    1 2 APU_SVT_R 21 31 SOC_UGATE
    PC5935 PC5936

    PC5934
    8 APU_SVT SVT UGATE_NB VDDC_ISEN1P

    ISENN_NB

    ISENP_NB

    COMP_NB

    BOOT_NB
    1 2 PR5931 0_0402_5% 1000P_0402_50V7-K 0.47U_0402_25V6-K

    TSEN_NB
    2.2U_0402_10V6-K

    2
    EMC_NS@

    VDDIO

    FB_NB

    2
    100K_0402_1%_TSM0B104F4251RZ

    GND
    VDDC_ISEN1N

    VIN
    1 2

    EN
    PR5934
    SOC_TSEN PR5933
    1 2
    1_0402_1%

    41

    22

    23

    24

    25

    26

    27

    28

    29

    30
    60.4K_0402_1%
    PH5902

    APUPWR_EN_R
    3662_VDDIO
    1 2 KELVIN routing

    SOC_COMP

    SOC_BOOT
    SOC_TSEN

    3662_VIN
    100K_0402_1%_TSM0B104F4251RZ

    SOCI_FB
    2

    2.2_0603_5%
    620_0402_1%

    24K_0402_1%

    24K_0402_1%

    2 1
    +1.8VS
    PR5935

    PR5936

    PR5937

    1U_0402_6.3V6-K
    PR5938

    1
    PC5937
    1

    PC5938
    0.1U_0402_25V6-K

    2
    1 2

    1 2
    SOC_ISEN1N
    PR5939
    APU_VDDC_VIN

    0.47U_0402_25V6-K
    4.7_0603_5%

    1
    976_0402_1%

    PC5939
    PR5940
    PC5940
    0.1U_0402_25V6-K

    2
    B B
    VDDCR_SOC

    2
    SOC_ISEN1P

    KELVIN close to APU side


    APU_VDDCR_SOC PL5906
    VDDCI=0.875V
    BLM18KG300TN1D_2P V9B+ FSW=300KHz
    1 2
    Slew rate :12.5mv/us
    EMC@ TDC=10A EDC=15A
    1 2 1 2
    3662_VREF OCP=20A
    PR5942
    12.7K_0402_1%
    +VDDCR_SOC 1
    PR5941
    2
    PC5944 PC5945 EMC@ EMC@ 2
    PJ5902 @
    1 1A OVP=VID+300mA
    1 2 180P_0402_50V8-J 47P_0402_50V8-J 2 1
    Ripple:+/-20mv

    2200P_0402_25V7-K
    100_0402_1%
    2

    JUMP_43X79
    SOC_FB_R
    PR5943 PR5947 PR5948 2 1 1 2 1 2 MAX AC: VID_VDDCR_SOC +70mv

    10U_0805_25V6-K

    10U_0805_25V6-K
    PH5903 8 VDDCR_SOC_VCC_SENSE

    1
    3.9_0402_1% 13.7K_0402_1% 4.42K_0402_1% PR5944 PC5943

    PC5941
    PC5992

    PC5942
    VDDC_IMON MIN AC: VID_VDDCR_SOC -40mv

    5
    1 2 1 2 1 2 0_0402_5% PR5945 PR5946 0.1U_0402_25V6-K
    10K_0402_1% 35.7K_0402_1% PQ5907
    1

    2
    100K_0402_1%_TSM0B104F4251RZ 2 TPCA8065-H
    PR5992 PC6077
    PC5947
    1

    PR5951 20171023 330P_0402_50V7-K 1 2 1 2


    1

    change VDDC inductor to SH00000XE00 SOC_UGATE 4


    PC5954 21.5K_0402_1%
    0.47U_0402_25V6-K 1 2 VDDCR_VSS_SENSE @
    2

    100_0402_5% 680P_0402_50V7-K
    PR5952 PR5953 @ @
    +VDDCR_SOC
    PH5904
    4.75K_0402_1% 29.4K_0402_1% follow richtek suggestion

    3
    2
    1
    1 2 1 2 1 2 SOC_IMON 2 1 PL5903
    0.24UH_PCME063T-R24MS1R145_35A_20%
    10A
    PR5954 SOC_PHASE SOC_PHASE
    100_0402_1%
    1 2
    100K_0402_1%_TSM0B104F4251RZ

    1
    @
    SOC_BOOT PR5950
    2SOC_BOOT_R

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    1 1 2
    EMC@ 4.7_0805_5% 1 1

    330U_D2_2V_Y

    330U_D2_2V_Y
    PR5949

    1
    PC5946 + +

    PC6070

    PC5964

    PC5950

    PC5951

    PC5952

    PC5953

    PC5965

    PC5966

    PC5967

    PC5968

    PC5971

    PC5972
    2.2_0603_5%

    2
    0.22U_0603_25V7-K

    1VDDCI_SN1

    2
    2 2
    SOC_LGATE 4 20171023
    @ @ @ @
    PQ5908
    TPCA8057-H EMC@ PC5955

    3
    2
    1
    680P_0402_50V7-K

    2
    SOC_ISEN1P 1 2 try to cost down
    PR5955
    1.47K_0402_1% PR5977
    SOC_ISEN1N 1 2
    A A

    0_0402_5%

    add PR5977 2017.03.29

    KELVIN routing

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/03/14 Deciphered Date 2017/03/01 PWR-VDDC/SOC
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Re v
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JINN/DOOKU 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Date : Tuesday, April 10, 2018 Sheet 59 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/03/14 Deciphered Date 2017/03/01 PWR-GPU
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JINN/DOOKU 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Date: Tuesday, April 10, 2018 Sheet 60 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A
    Security Classification LC Future Center Secret Data Title
    Issued Date 2017/03/14 Deciphered Date 2017/03/01 +0.95VGS
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 61 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A Security Classification LC Future Center Secret Data Title A

    Issued Date 2017/03/14 Deciphered Date 2017/03/01 +1.8VGS


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 62 of 65
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    <Variant Name>

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/03/14 Deciphered Date 2017/03/01 +1.35VGS


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 63 of 65
    5 4 3 2 1
    5 4 3 2 1

    Vout=1.5V± 5%

    D TDC=0.2A D

    Vset=1.5V± 5%
    OCP=3A
    Vref=0.6V
    FSW=1MHZ
    @PJ3001 PL3001
    JUMP_43X39 1UH_PH041H-1R0MS_3.8A_20%

    4
    0.2A PU3001 EMC_NS@ [email protected]
    2 1 VIN_+1.5VSP 10 1 +1.5VSP_LX 1 2
    +3VALW

    PG
    2 1 PVIN2 LX1 +1.5VSP

    2
    9 2 @
    PVIN1 LX2

    1
    PR3001

    1
    PC3001 PC3002 8 3 4.7_0603_5%
    SVIN1 LX3 EMC_NS@

    1
    10U_0603_10V 10U_0603_10V

    2
    RT8068AZQW_WDFN10_3X3 PR3002 PC3003

    2 1
    @ @

    2200P_0402_25V7-K
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    0.1U_0402_25V6
    30K_0402_1% 22P_0402_50V

    1
    5 6 PC3004

    GND

    2
    EN FB @

    PC3005

    PC3006

    PC3007

    PC3008
    NC
    PR3003 EMC_NS@ 680P_0402_50V @

    2
    1 2 EN_1.5VSP
    42,51,58 SUSP#

    11

    7
    C C
    @
    54.9K_0402_1%

    1
    @ @ @

    1
    @PR3004 PC3009
    1M_0402_5% 0.1U_0402_25V6-K

    2
    PR3005

    1
    @ 20K_0402_1%
    PJ3002

    2
    +1.5VSP 2 1 +1.5VS
    @ 2 1

    JUMP_43X39
    @

    Reserve for PMIC

    B B

    A A

    Title
    +1.5VS

    Size Document Number Re v


    B <Doc> 1.0

    Date: Tuesday, April 10, 2018 Sheet 64 of 65


    5 4 3 2 1
    5 4 3 2 1

    +VDDC_VDD

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    220U_B3_2.5VM_R35M
    560U 2V M D2 LESR3M

    560U 2V M D2 LESR3M
    D
    1 1 1 D

    1
    PC514

    PC515

    PC516

    PC517

    PC518

    PC519

    PC520

    PC521

    PC522

    PC523

    PC544

    PC545
    PC550
    + + +

    2
    2
    @ 2 @@ 2

    @ @ @ @ @ @

    +VDDCR_SOC
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    220U_B3_2.5VM_R35M
    560U 2V M D2 LESR3M
    1 1
    1

    1
    PC524

    PC525

    PC526

    PC527

    PC528

    PC529

    PC530

    PC531

    PC532

    PC533

    PC546

    PC547
    + +
    C C
    2

    2
    2
    @ 2
    @
    @ @ @ @ @ @ @ @ @

    B B

    A A

    <Variant Name>

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/03/14 Deciphered Date 2017/03/01 VCCCPUCORE DECOUPLING
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. JINN/DOOKU
    Date: Tuesday, April 10, 2018 Sheet 65 of 65
    5 4 3 2 1

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