Compal Confidential: Gx00/Gx00 DIS M/B Schematics Document

A B C D E
1 1
2
Compal Confidential 2
Gx00/Gx00 DIS M/B Schematics Document

Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
AMD Mars XT / SUN Pro
2013-02-27
3 3
LA-9631P
REV:1.0
4 4
1bios.ru Security Classification

Issued Date 2011/06/15
Compal Secret Data
Deciphered Date 2012/07/11 Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9631P
Date: Wednesday, February 27, 2013 Sheet 1 of 60
A B C D E
A B C D E
Compal confidential
Project Name : VIWGP (14") / VIWGR (15")
1
Chief River 1
AMD MARS XT M2 128 bits PEG 8x Intel Memory Bus 204pin DDRIII-SO-DIMM X2
/ SUN PRO M2 64 bits Gen2 / Gen3 Processor Dual Channel BANK 0, 1, 2 Page 12, 13
VRAM 512MB/1GB/2GB 　1600MHz
DDR3　
MARS XT : DDR3 x 8
SUN PRO : DDR3 x 4 Page 23~32
Ivy Bridge 　1333MHz
DDR3　
　1066MHz
DDR3　
rPGA989
37.5mm x 37.5mm
Page 5~11
FDI *8 DMI2 *4
2.7GT/s 5GT/s
2 LVDS Conn. Left USB3.0 x2 Right USB2.0 Int. Camera

2
Page 33
USB30 x2 USB30 Port 0,1 USB20 Port 9 USB20 Port 3
Page 45 Page 45 Page 33
HDMI Conn. USB20 x6 Touch Screen Card Reader

Page 35
Realtek RTS5170
USB20 Port 2
Page 45 USB20 Port 11 page 28
CRT Conn. Intel
Page 34
PCH
LAN Panther Point SATA Gen3 HDD Conn.
PCIe Port 0 PCIe x1
RJ45 Conn. Atheros SATA Port 0
Page 38 Page 40
AR8162/QCA8172(10/100)
Page 37
FCBGA 989Balls
25mm x 25mm SATA ODD Conn.
SATA Port 2
Page 40
3 PCIe Mini Card PCIe x1
3
WLAN Audio Codec

PCIe Port 1
Page 36 AZALIA CONEXANT
CX20757
Page 41
Page 14~22
Int. MIC Conn. Int. Speaker Conn. Audio Combo Jacks

Sub-borad Page 41 Page 41
HP & MIC Page 41
SPI ROM EC
15" 2MB + 4MB ENE KB9012
14" Page 14 Page 42
Power/B
(LID)
LS9631
4 4
USB/B ODD/B Thermal Sensor Touch Pad Int. KBD

Page 39 Page 43 Page 43
1bios.ru
IO/B
LS9632
(Card Reader)
LS9634
Switch/B
(LED, LID)
Security Classification
Compal Secret Data
MB Block Diagram
LS9633 LS9635 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
LA-9631P
A B C D E
A B C D E
Voltage Rails BOARD ID Table

SIGNAL
Board ID PCB Revision STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+5VS
0 0.1 Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+3VS
1
power 2 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
plane +1.5VS
+V1.05S_VCCP
3 S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1 1
+5VALW +1.5V +VCC_CORE

4
5 S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+B +VGA_CORE
+3VALW +VCC_GFXCORE_AXG
6 S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.8VS
7
State +0.75VS
+1.05VS
Vcc 3.3V
Board ID / SKU ID Table for AD channel
R694 100K +/- 1%
Board ID R695 VAD_BID min V AD_BID typ VAD_BID max EC AD
0 0 0 V 0 V 0 V 0x00 - 0x0B MP
1 12K +/- 1% 0.347V 0.354V 0.360V 0x0C - 0x1C PVT
2 15K +/- 1% 0.423V 0.430V 0.438V 0x1D - 0x26 DVT
S0
O O O O 3 20K +/- 1% 0.541V 0.550V 0.559V 0x27 - 0x30 EVT
S3
O O O X
2 2
S5 S4/AC
O O X X USB Port Table BOM Structure Table
S5 S4/ Battery only 3 External Item BOM Structure
O X X X USB 2.0 Port USB Port VIWGP (14") 14@
S5 S4/AC & Battery 0 USB Port (Left Side)USB3.0 VIWGR (15") 15@
don't exist X X X X UHCI0
1 USB Port (Left Side)USB3.0 HDMI Logo 45@
2 Touch Screen LAN 10/100 8162@
UHCI1
3 Camera LAN 10/100 8172@
EHCI1
4 LAN Switch mode SWR@
UHCI2
5 LAN LDO Mode LDO@
EC SM Bus1 address EC SM Bus2 address 6 LAN Gas tube GAS@
UHCI3
7 Camera CMOS@
Device Address Device Address
8 HDMI HDMI@
Smart Battery 0001 011x Thermal Sensor 0100 1100 UHCI4
9 USB Port (Right Side USB-BD) PCH is HM76 HM76@
10 Mini Card(WLAN) PCH is HM70 HM70@
PCH SM Bus address AMD-GPU SM Bus address EHCI2 UHCI5
3 11 Card Reader PCH is NM70 NM70@ 3
12 VGA is Mars XT Mars@

Device Address Device Address UHCI6
DDR_JDIMM1 1010 000x A0h Internal thermal sensor 0100 0001 41h
13 VGA is Sun Pro Sun@
DDR_JDIMM2 1010 010x A4h
For VGA PX@
For VRAM and Strap X76@
For UMA Strap UMA@
Microphone MIC@
Touch Screen TS@
SMBUS Control Table Connector ME@
Board ID for EVT EVT@
Board ID for DVT DVT@
Thermal
SOURCE VGA BATT KB9012 SODIMM WLAN Sensor PCH Board ID for PVT PVT@
For USB2.0 (All PCH) USB2@
SMB_EC_CK1
SMB_EC_DA1
KB9012 X V
+3VALW
X X X X X For USB3.0 (HM76,HM70) USB3@
+3VALW
For share ROM SROM@
SMB_EC_CK2
SMB_EC_DA2
KB9012 V
+3VGS
X X X X +3VS
V V
+3VALW
For non-share ROM NOSROM@
+3VS
PCH_SMBCLK
X X X V V X X
4 4
PCH
PCH_SMBDATA +3VALW +3VS +3VS
1bios.ru
X X X X X X X
PCH_SML0CLK
PCH
PCH_SML0DATA +3VALW
Security Classification Compal Secret Data Compal Electronics, Inc.
SML1CLK
SML1DATA
V
PCH
+3VALW +3VGS
X V
+3VS
X X +3VS
V X Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
Notes List
Size
Document Number Rev
B 1.0
LA-9631P
A B C D E
5 4 3 2 1
Power-Up/Down Sequence
Mars XT VRAM STRAP "Mars" has the following requirements with regards to power-supply
sequencing to avoid damaging the ASIC:
X76@ X76@ ‧ All the ASIC supplies must reach their respective nominal voltages within 20 ms
Vendor R_pu R_pd of the start of the ramp-up sequence, though a shorter ramp-up duration is
UV5, UV6, UV7, UV8 ID PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1 ]
UV9, UV10, UV11, UV12 RV20 RV27 preferred. The maximum slew rate on all rails is 50 mV/µs.
Samsung 2048Mbits ‧ The external pull ups on the DDC/AUX signals (if applicable) should ramp up
D ZZZ4 SA000068U00 before or after both VDDC and VDD_CT have ramped up. D
2GBytes MS2G@ 128Mx16 K4W2G1646E-BC1A 0 0 0 0 NC 4.75K
‧ VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
Micron 2048Mbits should reach 90% before VDD_CT starts to ramp up (or vice versa).
ZZZ5 SA000067500 ‧ For power down, reversing the ramp-up sequence is recommended.
2GBytes MM2G@ 128Mx16 MT41J128M16JT-093G:K 1 0 0 1 8.45K 2K
Hynix 2048Mbits
ZZZ6 SA000065300
2GBytes MH2G@ 128M16 H5TQ2G63DFR-N0C 2 0 1 0 4.53K 2K
Samsung 1028Mbits
ZZZ7 SA00004GS00
1GBytes MS1G@ 64Mx16 K4W1G1646G-BC11 3 0 1 1 6.98K 4.99K
Hynix 2048Mbits
ZZZ15 SA00006H400 VDDR3(3.3VGS)
2GBytes MH2GN@ 128Mx16 H5TC2G63FFR-11C 4 1 0 0 4.53K 4.99K
Hynix 1024Mbits PCIE_VDDC(0.95VGSV)
ZZZ8 SA000041SB0
1GBytes MH1G@ 64Mx16 H5TQ1G63EFR-11C 7 1 1 1 4.75K NC
VDDR1(1.5VGS)
ZZZ4 ZZZ5 ZZZ6 ZZZ15 ZZZ7 ZZZ8
C C
VDDC/VDDCI(1.12V)
Samsung_2G Micron_2G Hynix_2G Hynix_2G Samsung_1G Hynix_1G
MS2G@ MM2G@ MH2G@ MH2GN@ MS1G@ MH1G@
X7646738L01 X7646738L02 X7646738L09 X7646738L10 X7646738L03 X7646738L04
VDD_CT(1.8V)
PERSTb
Sun PRO VRAM STRAP

REFCLK
X76@ X76@
Vendor R_pu R_pd
ID PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1 ] Straps Reset
UV9, UV10, UV11, UV12 RV20 RV27
Samsung 4096Mbits
ZZZ9 SA000068R00
2GBytes SS2G@ 256Mx16 K4W4G1646B-HC11 0 0 0 0 NC 4.75K Straps Valid
Micron 4096Mbits
ZZZ10 SA000065D00
2GBytes SM2G@ 1
256Mx16/1866 MT41K256M16HA-107G:E 0 0 1 8.45K 2K Global ASIC Reset
B B
Hynix 4096Mbits
ZZZ11 SA00006DG00 T4+16clock
2GBytes SH2G@ 256MX16 H5TQ4G63MFR-11C 2 0 1 0 4.53K 2K
Samsung 2048Mbits
ZZZ12 SA000068U00
1GBytes SS1G@ 128Mx16 K4W2G1646E-BC1A 3 0 1 1 6.98K 4.99K
Hynix 2048Mbits
ZZZ16 SA00006H400
1GBytes SH1GN@ 128Mx16 H5TC2G63FFR-11C 4 1 0 0 4.53K 4.99K
Micron 2048Mbits
ZZZ13 SA000067500
1GBytes SM1G@ 128Mx16 MT41J128M16JT-093G:K 6 1 1 0 3.4K 10K
Hynix 2048Mbits
ZZZ14 SA000065300
1GBytes SH1G@ 128M16 H5TQ2G63DFR-N0C 7 1 1 1 4.75K NC
ZZZ9 ZZZ10 ZZZ11 ZZZ12 ZZZ13 ZZZ14 ZZZ16
A A
Samsung_2G Micron_2G Hynix_2G Samsung_1G Micron_1G Hynix_1G Hynix_1G

SS2G@ SM2G@ SH2G@ SS1G@ SM1G@ SH1G@ SH1GN@
1bios.ru
X7646738L05 X7646738L06 X7646738L11 X7646738L07 X7646738L08 X7647538L01 X7646738L13

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
VGA Notes List
Size Document Number
Rev
Custom 1.0
LA-9631P
5 4 3 2 1
5 4 3 2 1
ZZZ1 14@ ZZZ2 15@
PEG_ICOMPI and RCOMPO signals should be

shorted and routed
14"_DIS_PCB_LA9631P 15"_DIS_PCB_LA9631P
with - max length = 500 mils - typical
DA6000WO000 DA6000WO100 +V1.05S_VCCP impedance = 43 mohms
PCB 0N1 LA-9631P REV0 M/B DIS 3 PCB 0N2 LA-9631P REV0 M/B DIS 5
PEG_ICOMPO signals should be routed with -
1
max length = 500 mils
R1
D
24.9_0402_1% - typical impedance = 14.5 mohms D
JCPU1A
2
J22 PEG_COMP
PEG_ICOMPI J21
B27 PEG_ICOMPO H22
<16> DMI_CRX_PTX_N0 DMI_RX#[0] PEG_RCOMPO PEG Static Lane Reversal - CFG2 is for the 16x
<16> DMI_CRX_PTX_N1 B25
A25 DMI_RX#[1]
<16> DMI_CRX_PTX_N2 DMI_RX#[2]
<16> DMI_CRX_PTX_N3 B24 K33 1: Normal Operation; Lane # definition matches
DMI_RX#[3] PEG_RX#[0] M35
PEG_RX#[1] CFG2 socket pin map definition
<16> DMI_CRX_PTX_P0 B28 L34
B26 DMI_RX[0] PEG_RX#[2] J35
<16> DMI_CRX_PTX_P1 DMI_RX[1] PEG_RX#[3]
A24 J32 0:Lane Reversed
<16> DMI_CRX_PTX_P2
*
DMI
B23 DMI_RX[2] PEG_RX#[4] H34
<16> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] H31
G21 PEG_RX#[6] G33
<16> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] PCIE_CRX_GTX_N[0..7] <23>
E22 G30 PCIE_CRX_GTX_N7
<16> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PCIE_CRX_GTX_N6
<16> DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
D21 E34 PCIE_CRX_GTX_N5
<16> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] E32 PCIE_CRX_GTX_N4
G22 PEG_RX#[11] D33 PCIE_CRX_GTX_N3
<16> DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12]
D22 D31 PCIE_CRX_GTX_N2
F20 B33 PCIE_CRX_GTX_N1
PCI EXPRESS* - GRAPHICS

C21 C32 PCIE_CRX_GTX_N0
J33
PEG_RX[0] L35
PEG_RX[1] K34
A21 PEG_RX[2] H35
<16> FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3]
C H19 H32 C
E19 G34
F18 G31
Intel(R) FDI
B21 F33 PCIE_CRX_GTX_P[0..7] <23>
C20 F30 PCIE_CRX_GTX_P7
D18 E35 PCIE_CRX_GTX_P6
E17 E33 PCIE_CRX_GTX_P5
<16> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] F32 PCIE_CRX_GTX_P4
PEG_RX[11] D34 PCIE_CRX_GTX_P3
A22 PEG_RX[12] E31 PCIE_CRX_GTX_P2
<16> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
G19 C33 PCIE_CRX_GTX_P1
E20 B32 PCIE_CRX_GTX_P0
G18
<16> FDI_CTX_PRX_P3 FDI0_TX[3]
B20 M29
<16> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32
D19 M31
F17 L32
<16> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] L29
J18 PEG_TX#[4] K31
+V1.05S_VCCP <16> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
<16> FDI_FSYNC1
J17 K28
FDI1_FSYNC PEG_TX#[6] J30
PEG_TX#[7] PCIE_CTX_GRX_N[0..7] <23>
<16> FDI_INT H20 J28 PCIE_CTX_GRX_C_N7 C9 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N7
FDI_INT PEG_TX#[8] H29 PCIE_CTX_GRX_C_N6 C10 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N6
PEG_TX#[9]
1
<16> FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_C_N5 C11 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N5

R7 H17 FDI0_LSYNC PEG_TX#[10] E29 PCIE_CTX_GRX_C_N4 C12 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N4
<16> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
24.9_0402_1% F27 PCIE_CTX_GRX_C_N3 C13 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N3
PEG_TX#[12] D28 PCIE_CTX_GRX_C_N2 C14 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N2
PEG_TX#[13] F26 PCIE_CTX_GRX_C_N1 C15 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N1
2
PEG_TX#[14] E25 PCIE_CTX_GRX_C_N0 C16 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N0

EDP_COMP A18 PEG_TX#[15]
B
A17 eDP_COMPIO M28 B
eDP_COMPIO and ICOMPO signals eDP_ICOMPO PEG_TX[0]
eDP_HPD B16 M33
should be shorted near balls eDP_HPD# PEG_TX[1] M30
PEG_TX[2] L31
and routed with typical PEG_TX[3]
C15 L28
impedance <25 mohms D15 eDP_AUX PEG_TX[4] K30
eDP_AUX# PEG_TX[5] K27
eDP
PEG_TX[6] J29
PEG_TX[7] PCIE_CTX_GRX_P[0..15] <23>
C17 J27 PCIE_CTX_GRX_C_P7 C25 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P7
F16 eDP_TX[0] PEG_TX[8] H28 PCIE_CTX_GRX_C_P6 C26 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P6
C16 eDP_TX[1] PEG_TX[9] G28 PCIE_CTX_GRX_C_P5 C27 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P5
G15 eDP_TX[2] PEG_TX[10] E28 PCIE_CTX_GRX_C_P4 C28 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P4
eDP_TX[3] PEG_TX[11] F28 PCIE_CTX_GRX_C_P3 C29 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P3
C18 PEG_TX[12] D27 PCIE_CTX_GRX_C_P2 C30 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P2
E16 eDP_TX#[0] PEG_TX[13] E26 PCIE_CTX_GRX_C_P1 C31 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P1
D16 eDP_TX#[1] PEG_TX[14] D25 PCIE_CTX_GRX_C_P0 C32 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P0
F15 eDP_TX#[2] PEG_TX[15]
eDP_TX#[3]
TYCO_2013620-2_IVY BRIDGE
ME@
A A

Compal Secret Data
PROCESSOR(1/7) DMI,FDI,PEG
Custom 1.0
LA-9631P
5 4 3 2 1
5 4 3 2 1
JCPU1B
D D
A28
C26 BCLK A27 CLK_CPU_DMI <15>
MISC
CLOCKS
<19> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15>
AN34
SKTOCC# A16 2 R12 1 1K_0402_5%
+V1.05S_VCCP DPLL_REF_CLK A15 2 R13 1 1K_0402_5%
DPLL_REF_CLK# +V1.05S_VCCP
T48 H_CATERR# AL33

CATERR#
R9 1
62_0402_5%
THERMAL
AN33 R8 H_DRAMRST#
<42> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
2
R15 +V1.05S_VCCP
DDR3
MISC
56_0402_5%
H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 2 R16 1 140_0402_1%
<42,46,47,54> H_PROCHOT# PROCHOT# SM_RCOMP[0] A5 SM_RCOMP1 2 R17 1 25.5_0402_1%
SM_RCOMP[1] A4 SM_RCOMP2 2 R18 1 200_0402_1%
SM_RCOMP[2]
AN32 DDR3 Compensation Signals
<19> H_THRMTRIP# THERMTRIP#
RP13
XDP_TRST# 8 1
AP29 XDP_PRDY# XDP_TDI 7 2
PRDY# AP27 XDP_PREQ# XDP_TMS 6 3
PREQ# XDP_TCK 5 4
1
AR26 XDP_TCK
C TCK AR27 XDP_TMS 51_0804_8P4R_5% C46 C
PWR MANAGEMENT
TMS
JTAG & BPM

AM34 AP30 XDP_TRST# 100P_0402_50V8J
<16> H_PM_SYNC
2
PM_SYNC TRST#
@
AR28 XDP_TDI
TDI AP26 XDP_TDO
AP33 TDO
<19> H_CPUPWRGD UNCOREPWRGOOD
ESD
2
R29 AL35 XDP_DBRESET# R28 2 1 1K_0402_5%

DBR# +3VS
1 R27 1 2 PM_DRAM_PWRGD_R V8
C549 130_0402_5% SM_DRAMPWROK
10K_0402_5%
1
AT28 XDP_BPM#0
22P_0402_50V8J BPM#[0] AR29 XDP_BPM#1 C45
1
2 BPM#[1] AR30 XDP_BPM#2 47P_0402_50V8J
2
BUF_CPU_RST# AR33 BPM#[2] AT30 XDP_BPM#3
RESET# BPM#[3] AP32 XDP_BPM#4
BPM#[4] AR31 XDP_BPM#5
BPM#[5] AT31 XDP_BPM#6
ESD BPM#[6] AR32 XDP_BPM#7 ESD
BPM#[7]
+3VALW
ME@
Buffered reset to CPU

+1.5V_CPU_VDDQ
+3VS
B B
1
R30
U1 200_0402_5% +V1.05S_VCCP
5
1 R161 2 1
P
+3VS B
10K_0402_5% 4 PM_SYS_PWRGD_BUF R32
2 O 75_0402_5%
<16> PM_DRAM_PWRGD A
G
5
74AHC1G09GW_TSSOP5 R34 U2
3
43_0402_1% 1 3V
P
BUF_CPU_RST# 1 2 BUFO_CPU_RST# 4 NC
Y 2 PCH_PLTRST#
A PCH_PLTRST# <18>
G
SN74LVC1G07DCKR_SC70-5
A A

Compal Secret Data
PROCESSOR(2/7) PM,XDP,CLK
Custom 1.0
LA-9631P
5 4 3 2 1
5 4 3 2 1
JCPU1C JCPU1D
<13> DDR_B_D[0..63]
AB6 AE2
<12> DDR_A_D[0..63] SA_CLK[0] AA6 M_CLK_DDR0 <12> SB_CLK[0] AD2 M_CLK_DDR2 <13>
DDR_A_D0 C5 SA_CLK#[0] V9 M_CLK_DDR#0 <12> DDR_B_D0 C9 SB_CLK#[0] R9 M_CLK_DDR#2 <13>
D5 SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA <12> A7 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <13>
DDR_A_D1 DDR_B_D1
DDR_A_D2 D3 SA_DQ[1] DDR_B_D2 D10 SB_DQ[1]
DDR_A_D3 D2 SA_DQ[2] DDR_B_D3 C8 SB_DQ[2]
DDR_A_D4 D6 SA_DQ[3] AA5 DDR_B_D4 A9 SB_DQ[3] AE1
C6 SA_DQ[4] SA_CLK[1] AB5 M_CLK_DDR1 <12> A8 SB_DQ[4] SB_CLK[1] AD1 M_CLK_DDR3 <13>
DDR_A_D5 DDR_B_D5
C2 SA_DQ[5] SA_CLK#[1] V10 M_CLK_DDR#1 <12> D9 SB_DQ[5] SB_CLK#[1] R10 M_CLK_DDR#3 <13>
DDR_A_D6 DDR_B_D6
D C3 SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA <12> D8 SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB <13> D
DDR_A_D7 DDR_B_D7
DDR_A_D8 F10 SA_DQ[7] DDR_B_D8 G4 SB_DQ[7]
DDR_A_D9 F8 SA_DQ[8] DDR_B_D9 F4 SB_DQ[8]
DDR_A_D10 G10 SA_DQ[9] AB4 DDR_B_D10 F1 SB_DQ[9] AB2
DDR_A_D11 G9 SA_DQ[10] RSVD_TP[1] AA4 DDR_B_D11 G1 SB_DQ[10] RSVD_TP[11] AA2
DDR_A_D12 F9 SA_DQ[11] RSVD_TP[2] W9 DDR_B_D12 G5 SB_DQ[11] RSVD_TP[12] T9
DDR_A_D13 F7 SA_DQ[12] RSVD_TP[3] DDR_B_D13 F5 SB_DQ[12] RSVD_TP[13]
DDR_A_D14 G8 SA_DQ[13] DDR_B_D14 F2 SB_DQ[13]
DDR_A_D15 G7 SA_DQ[14] DDR_B_D15 G2 SB_DQ[14]
DDR_A_D16 K4 SA_DQ[15] AB3 DDR_B_D16 J7 SB_DQ[15] AA1
DDR_A_D17 K5 SA_DQ[16] RSVD_TP[4] AA3 DDR_B_D17 J8 SB_DQ[16] RSVD_TP[14] AB1
DDR_A_D18 K1 SA_DQ[17] RSVD_TP[5] W10 DDR_B_D18 K10 SB_DQ[17] RSVD_TP[15] T10
DDR_A_D19 J1 SA_DQ[18] RSVD_TP[6] DDR_B_D19 K9 SB_DQ[18] RSVD_TP[16]
DDR_A_D20 J5 SA_DQ[19] DDR_B_D20 J9 SB_DQ[19]
DDR_A_D21 J4 SA_DQ[20] DDR_B_D21 J10 SB_DQ[20]
DDR_A_D22 J2 SA_DQ[21] AK3 DDR_B_D22 K8 SB_DQ[21] AD3
DDR_A_D23 K2 SA_DQ[22] SA_CS#[0] AL3 DDR_CS0_DIMMA# <12> DDR_B_D23 K7 SB_DQ[22] SB_CS#[0] AE3 DDR_CS2_DIMMB# <13>
DDR_A_D24 M8 SA_DQ[23] SA_CS#[1] AG1 DDR_CS1_DIMMA# <12> DDR_B_D24 M5 SB_DQ[23] SB_CS#[1] AD6 DDR_CS3_DIMMB# <13>
DDR_A_D25 N10 SA_DQ[24] RSVD_TP[7] AH1 DDR_B_D25 N4 SB_DQ[24] RSVD_TP[17] AE6
DDR_A_D26 N8 SA_DQ[25] RSVD_TP[8] DDR_B_D26 N2 SB_DQ[25] RSVD_TP[18]
DDR_A_D27 N7 SA_DQ[26] DDR_B_D27 N1 SB_DQ[26]
DDR_A_D28 M10 SA_DQ[27] DDR_B_D28 M4 SB_DQ[27]
DDR_A_D29 M9 SA_DQ[28] AH3 DDR_B_D29 N5 SB_DQ[28] AE4
DDR_A_D30 N9 SA_DQ[29] SA_ODT[0] AG3 M_ODT0 <12> DDR_B_D30 M2 SB_DQ[29] SB_ODT[0] AD4 M_ODT2 <13>
M_ODT1 <12> M_ODT3 <13>
DDR SYSTEM MEMORY B

DDR_A_D31 M7 SA_DQ[30] SA_ODT[1] AG2 DDR_B_D31 M1 SB_DQ[30] SB_ODT[1] AD5
DDR SYSTEM MEMORY A

DDR_A_D32 AG6 SA_DQ[31] RSVD_TP[9] AH2 DDR_B_D32 AM5 SB_DQ[31] RSVD_TP[19] AE5
DDR_A_D33 AG5 SA_DQ[32] RSVD_TP[10] DDR_B_D33 AM6 SB_DQ[32] RSVD_TP[20]
DDR_A_D34 AK6 SA_DQ[33] DDR_B_D34 AR3 SB_DQ[33]
DDR_A_D35 AK5 SA_DQ[34] DDR_B_D35 AP3 SB_DQ[34]
DDR_A_D36 AH5 SA_DQ[35] DDR_B_D36 AN3 SB_DQ[35]
DDR_A_D37 AH6 SA_DQ[36] C4 DDR_A_DQS#0 DDR_A_DQS#[0..7] <12> DDR_B_D37 AN2 SB_DQ[36] D7 DDR_B_DQS#0 DDR_B_DQS#[0..7] <13>
DDR_A_D38 AJ5 SA_DQ[37] SA_DQS#[0] G6 DDR_A_DQS#1 DDR_B_D38 AN1 SB_DQ[37] SB_DQS#[0] F3 DDR_B_DQS#1
C DDR_A_D39 AJ6 SA_DQ[38] SA_DQS#[1] J3 DDR_A_DQS#2 DDR_B_D39 AP2 SB_DQ[38] SB_DQS#[1] K6 DDR_B_DQS#2 C
DDR_A_D40 AJ8 SA_DQ[39] SA_DQS#[2] M6 DDR_A_DQS#3 DDR_B_D40 AP5 SB_DQ[39] SB_DQS#[2] N3 DDR_B_DQS#3
DDR_A_D41 AK8 SA_DQ[40] SA_DQS#[3] AL6 DDR_A_DQS#4 DDR_B_D41 AN9 SB_DQ[40] SB_DQS#[3] AN5 DDR_B_DQS#4
DDR_A_D42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 DDR_A_DQS#5 DDR_B_D42 AT5 SB_DQ[41] SB_DQS#[4] AP9 DDR_B_DQS#5
DDR_A_D43 AK9 SA_DQ[42] SA_DQS#[5] AR12 DDR_A_DQS#6 DDR_B_D43 AT6 SB_DQ[42] SB_DQS#[5] AK12 DDR_B_DQS#6
DDR_A_D44 AH8 SA_DQ[43] SA_DQS#[6] AM15 DDR_A_DQS#7 DDR_B_D44 AP6 SB_DQ[43] SB_DQS#[6] AP15 DDR_B_DQS#7
DDR_A_D45 AH9 SA_DQ[44] SA_DQS#[7] DDR_B_D45 AN8 SB_DQ[44] SB_DQS#[7]
DDR_A_D46 AL9 SA_DQ[45] DDR_B_D46 AR6 SB_DQ[45]
DDR_A_D48 AP11 SA_DQ[47] DDR_B_D48 AR9 SB_DQ[47]
DDR_A_D49 AN11 SA_DQ[48] D4 DDR_A_DQS0 DDR_A_DQS[0..7] <12> DDR_B_D49 AJ11 SB_DQ[48] C7 DDR_B_DQS0 DDR_B_DQS[0..7] <13>
DDR_A_D50 AL12 SA_DQ[49] SA_DQS[0] F6 DDR_A_DQS1 DDR_B_D50 AT8 SB_DQ[49] SB_DQS[0] G3 DDR_B_DQS1
DDR_A_D51 AM12 SA_DQ[50] SA_DQS[1] K3 DDR_A_DQS2 DDR_B_D51 AT9 SB_DQ[50] SB_DQS[1] J6 DDR_B_DQS2
DDR_A_D52 AM11 SA_DQ[51] SA_DQS[2] N6 DDR_A_DQS3 DDR_B_D52 AH11 SB_DQ[51] SB_DQS[2] M3 DDR_B_DQS3
DDR_A_D53 AL11 SA_DQ[52] SA_DQS[3] AL5 DDR_A_DQS4 DDR_B_D53 AR8 SB_DQ[52] SB_DQS[3] AN6 DDR_B_DQS4
DDR_A_D54 AP12 SA_DQ[53] SA_DQS[4] AM9 DDR_A_DQS5 DDR_B_D54 AJ12 SB_DQ[53] SB_DQS[4] AP8 DDR_B_DQS5
DDR_A_D55 AN12 SA_DQ[54] SA_DQS[5] AR11 DDR_A_DQS6 DDR_B_D55 AH12 SB_DQ[54] SB_DQS[5] AK11 DDR_B_DQS6
DDR_A_D56 AJ14 SA_DQ[55] SA_DQS[6] AM14 DDR_A_DQS7 DDR_B_D56 AT11 SB_DQ[55] SB_DQS[6] AP14 DDR_B_DQS7
DDR_A_D57 AH14 SA_DQ[56] SA_DQS[7] DDR_B_D57 AN14 SB_DQ[56] SB_DQS[7]
DDR_A_D59 AK15 SA_DQ[58] DDR_B_D59 AT14 SB_DQ[58]
DDR_A_D60 AL14 SA_DQ[59] DDR_B_D60 AT12 SB_DQ[59]
DDR_A_D61 AK14 SA_DQ[60] AD10 DDR_A_MA0 DDR_A_MA[0..15] <12> DDR_B_D61 AN15 SB_DQ[60] AA8 DDR_B_MA0 DDR_B_MA[0..15] <13>
DDR_A_D62 AJ15 SA_DQ[61] SA_MA[0] W1 DDR_A_MA1 DDR_B_D62 AR15 SB_DQ[61] SB_MA[0] T7 DDR_B_MA1
DDR_A_D63 AH15 SA_DQ[62] SA_MA[1] W2 DDR_A_MA2 DDR_B_D63 AT15 SB_DQ[62] SB_MA[1] R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] W7 DDR_A_MA3 SB_DQ[63] SB_MA[2] T6 DDR_B_MA3
SA_MA[3] V3 DDR_A_MA4 SB_MA[3] T2 DDR_B_MA4
SA_MA[4] V2 DDR_A_MA5 SB_MA[4] T4 DDR_B_MA5
SA_MA[5] W3 DDR_A_MA6 SB_MA[5] T3 DDR_B_MA6
AE10 SA_MA[6] W6 DDR_A_MA7 AA9 SB_MA[6] R2 DDR_B_MA7
<12> DDR_A_BS0 AF10 SA_BS[0] SA_MA[7] V1 DDR_A_MA8 <13> DDR_B_BS0 AA7 SB_BS[0] SB_MA[7] T5 DDR_B_MA8
<12> DDR_A_BS1 V6 SA_BS[1] SA_MA[8] W5 DDR_A_MA9 <13> DDR_B_BS1 R6 SB_BS[1] SB_MA[8] R3 DDR_B_MA9
B <12> DDR_A_BS2 SA_BS[2] SA_MA[9] AD8 <13> DDR_B_BS2 SB_BS[2] SB_MA[9] AB7 B
DDR_A_MA10 DDR_B_MA10
SA_MA[10] V4 DDR_A_MA11 SB_MA[10] R1 DDR_B_MA11
SA_MA[11] W4 DDR_A_MA12 SB_MA[11] T1 DDR_B_MA12
AE8 SA_MA[12] AF8 DDR_A_MA13 AA10 SB_MA[12] AB10 DDR_B_MA13
<12> DDR_A_CAS# AD9 SA_CAS# SA_MA[13] V5 <13> DDR_B_CAS# AB8 SB_CAS# SB_MA[13] R5
DDR_A_MA14 DDR_B_MA14
<12> DDR_A_RAS# AF9 SA_RAS# SA_MA[14] V7 DDR_A_MA15 <13> DDR_B_RAS# AB9 SB_RAS# SB_MA[14] R4 DDR_B_MA15
<12> DDR_A_WE# SA_WE# SA_MA[15] <13> DDR_B_WE# SB_WE# SB_MA[15]
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

ME@
+1.5V ME@
1
R37
1K_0402_5%
R38
1K_0402_5%
2
3 1 1 2
S
H_DRAMRST# DDR3_DRAMRST#_R
<6> H_DRAMRST# DDR3_DRAMRST# <12,13>
2
Q2
R39 LBSS138LT1G_SOT-23-3
G
2
4.99K_0402_1%
1
@
A 1 R48 2 DRAMRST_CNTRL_PCH_R A
<10,15> DRAMRST_CNTRL_PCH
0_0402_5%
1bios.ru 1
2
C35
0.047U 16V K X7R 0402
Compal Secret Data
PROCESSOR(3/7) DDRIII
Eiffel used 0.01u AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
Module design used 0.047u DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-9631P
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor
CFG2
1
R41
1K_0402_1%
PX@
2
D D
Interl request AH26 short GND

JCPU1E check on EVT phase PEG Static Lane Reversal - CFG2 is for the 16x
1: Normal Operation; Lane # definition matches

AH27 PAD T13 CFG2
AK28 VCC_DIE_SENSE AH26 socket pin map definition
AK29 CFG[0] VSS_DIE_SENSE
CFG2 AL26 CFG[1]
0:Lane Reversed
CFG4
AL27
AK26
AL29
CFG[2]
CFG[3]
CFG[4] RSVD28
L7
AG7
*
CFG5 CFG4
CFG6 AL30 CFG[5] RSVD29 AE7
CFG[6] RSVD30
1
CFG7 AM31 AK2
AM32 CFG[7] RSVD31
AM30 CFG[8] W8 @ R42
CFG
AM28 CFG[9] RSVD32 1K_0402_1%
+VCC_GFXCORE_AXG AM26 CFG[10]
2
AN28 CFG[11] AT26
+VCC_CORE AN31 CFG[12] RSVD33 AM33
AN26 CFG[13] RSVD34 AJ27
CFG[14] RSVD35
2
@ AM27
R252 AK31 CFG[15]
AN29 CFG[16]
49.9_0402_1% CFG[17]
2
@ Display Port Presence Strap

R253
1
49.9_0402_1% T8
C RSVD37 J16 C
1 : Disabled; No Physical Display Port
VCC_AXG_VAL_SENSE AJ31 RSVD38 H16 CFG4 * attached to Embedded Display Port
1
R82 1 @ 2 100_0402_1% VSS_AXG_VAL_SENSE AH31 VAXG_VAL_SENSE RSVD39 G16

VCC_VAL_SENSE AJ33 VSSAXG_VAL_SENSE RSVD40
R88 1 2 100_0402_1% VSS_VAL_SENSE AH33 VCC_VAL_SENSE
@
VSS_VAL_SENSE 0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
AJ26 AR35
RSVD5 RSVD_NCTF1 AT34
RESERVED
RSVD_NCTF2 AT33
VSS_AXG_VAL_SENSE RSVD_NCTF3 AP35 CFG6
RSVD_NCTF4 AR34
RSVD_NCTF5 CFG5
VSS_VAL_SENSE
1
F25
F24 RSVD8 PX@ R43 @ R44
RSVD9
2
@ @ F23 1K_0402_1% 1K_0402_1%

R255 R257 D24 RSVD10 B34
G25 RSVD11 RSVD_NCTF6 A33
49.9_0402_1% 49.9_0402_1%
2
G24 RSVD12 RSVD_NCTF7 A34
E23 RSVD13 RSVD_NCTF8 B35
1
D23 RSVD14 RSVD_NCTF9 C35

C30 RSVD15 RSVD_NCTF10
A31 RSVD16
B30 RSVD17
B29 RSVD18
D30 RSVD19 AJ32
B31 RSVD20 RSVD51 AK32
RSVD21 RSVD52 PCIE Port Bifurcation Straps
A30
C29 RSVD22
RSVD23
11: (Default) x16 - Device 1 functions 1 and 2 disabled
AN35
B J20 BCLK_ITP AM35 B
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
B18 RSVD24
RSVD25
BCLK_ITP#
* disabled
01: Reserved - (Device 1 function 1 disabled ; function
J15 AT2 2 enabled)
RSVD27 RSVD_NCTF11 AT1
RSVD_NCTF12 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
AR1
RSVD_NCTF13
B1 CFG7
KEY
1
@R45
@ R45
1K_0402_1%
2
ME@
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB

CFG7 de assertion
A
0: PEG Wait for BIOS for training A

Compal Secret Data
PROCESSOR(4/7) RSVD,CFG
Custom 1.0
LA-9631P
5 4 3 2 1
5 4 3 2 1
JCPU1F POWER +V1.05S_VCCP

+VCC_CORE
QC=94A 8.5A
DC=53A
AG35
AG34 VCC1 AH13
AG33 VCC2 VCCIO1 AH10
AG32 VCC3 VCCIO2 AG10
D AG31 VCC4 VCCIO3 AC10 D
AG30 VCC5 VCCIO4 Y10
AG29 VCC6 VCCIO5 U10
AG28 VCC7 VCCIO6 P10
AG27 VCC8 VCCIO7 L10
AG26 VCC9 VCCIO8 J14
AF35 VCC10 VCCIO9 J13
AF32 VCC13 VCCIO12 H14
AF29 VCC16 VCCIO15 G14
PEG AND DDR

AF26 VCC19 VCCIO18 F14
AD35 VCC20 VCCIO19 F13
AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12
AD30 VCC25 VCCIO24
AD29 VCC26 E11
AD28 VCC27 VCCIO25 D14
AC35 VCC30 VCCIO28 D11
AC34 VCC31 VCCIO29 C14
AC30 VCC35 VCCIO33 B14
C AC29 VCC36 VCCIO34 B12 C
AC28 VCC37 VCCIO35 A14
AA35 VCC40 VCCIO38 A11
AA34 VCC41 VCCIO39
AA33 VCC42 J23
AA32 VCC43 VCCIO40
AA31 VCC44 +V1.05S_VCCP
AA30 VCC45
AA29 VCC46
AA28 VCC47
AA27 VCC48
AA26 VCC49
Y35 VCC50
CORE SUPPLY
Y34 VCC51
Y33 VCC52
Y32 VCC53
VCC54
1
Y31
Y30 VCC55 R46
Y29 VCC56
VCC57 75_0402_5%
Y28
Y27 VCC58
VR_SVID_CLK series-resistors close to VR
2
Y26 VCC59
V35 VCC60
V34 VCC61 AJ29 H_CPU_SVIDALRT# 1 R47 2 43_0402_5%
SVID
V33 VCC62 VIDALERT# AJ30 VR_SVID_ALRT# <54>

V32 VCC63 VIDSCLK AJ28 VR_SVID_CLK <54>
V31 VCC64 VIDSOUT VR_SVID_DAT <54>
V30 VCC65
V29 VCC66 2 1 130_0402_5%
VCC67
R50 +V1.05S_VCCP 0.1uF on power side
V28
B V27 VCC68 B
V26 VCC69
U35 VCC70
U34 VCC71
U33 VCC72
U32 VCC73
U31 VCC74
U30 VCC75
U29 VCC76
U28 VCC77 VCC_SENCE 100ohm +-1% pull-up to VCC near processor
U27 VCC78
U26 VCC79
R35 VCC80 +VCC_CORE
R34 VCC81
R33 VCC82
VCC83
1
R32
R31
R30
VCC84
VCC85
Trace Impedance =27-33 ohm R51
R29
R28
VCC86
VCC87
Trace Length Matc < 25 mils 100_0402_1%
SENSE LINES
2
R27 VCC88 AJ35
R26 VCC89 VCC_SENSE AJ34 VCCSENSE <54>
P35 VCC90 VSS_SENSE VSSSENSE <54>
P34 VCC91
VCC92
1
P33
P32 VCC93 B10 R54
P31 VCC94 VCCIO_SENSE A10 1 VCCIO_SENSE <52>
VSSIO_SENSE_L R74 2VSSIO_SENSE 100_0402_1%
P30 VCC95 VSS_SENSE_VCCIO 10_0402_1%
P29 VCC96
2
P28 VCC97
VCC98 R74 & R79 put together +V1.05S_VCCP
P27
P26 VCC99 R79
A VCC100 2 1 A
VSSIO_SENSE_L <52>
10_0402_1%
1bios.ru
VSS_SENCE 100ohm +-1% pull-down to GND near processor
TYCO_2013620-2_IVY BRIDGE Security Classification Compal Secret Data

ME@
PROCESSOR(5/7) PWR,BYPASS
Custom 1.0
LA-9631P
5 4 3 2 1
5 4 3 2 1
+1.5V +1.5V_CPU_VDDQ
Q6
1
D LBSS138LT1G_SOT-23-3
2
+VREF_DQ_DIMMA G DRAMRST_CNTRL_PCH <15,7>
+VREF_DQ_DIMMB S
3
<45> SUSP +V_DDR_REFA_R
+V_DDR_REFB_R
U3
DMN3030LSS-13_SOP8L-8
B+ 8 1 AP4800
1
7 2 D
D 6 3 Id=9.6A DRAMRST_CNTRL_PCH 2 D
1
5 G
R56 S
3
82K_0402_5% Q9
4
LBSS138LT1G_SOT-23-3
2
R885 R02 M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
RUN_ON_CPU1.5VS3 1 2
1
15K_0402_1% 1
1
D +VCC_GFXCORE_AXG
2 Q4 R57 C97
G 2N7002H_SOT23-3 330K_0402_5% 0.047U_0603_25V7K
1
S @ 2
2
R616
10_0402_1%
2
+VCC_GFXCORE_AXG JCPU1G
POWER VCC_AXG_SENSE <54>
AT24 AK35
SENSE
LINES
AT23 VAXG1 VAXG_SENSE AK34 +1.5V_CPU_VDDQ
VAXG2 VSSAXG_SENSE VSS_AXG_SENSE <54>
AT21
VAXG3
1
AT20
AT18 VAXG4 R626
VAXG5
1
AT17 10_0402_1%
AR24 VAXG6
AR23 VAXG7 R67
+V_SM_VREF should
2
AR21 VAXG8 1K_0402_1%
AR20 VAXG9 have 20 mil trace width
2
AR18 VAXG10 AL1 +V_SM_VREF_CNT
C
AR17 VAXG11 SM_VREF C
VAXG12
1
AP24 1
VREF
AP23 VAXG13
AP21 VAXG14 C98 R78
AP20 VAXG15 B4 +V_DDR_REFA_R .1U_0402_16V7K 1K_0402_1%
AP18 VAXG16 SA_DIMM_VREFDQ D1 +V_DDR_REFB_R 2
2
AP17 VAXG17 SB_DIMM_VREFDQ
AN24 VAXG18
AN23 VAXG19
AN21 VAXG20
AN20 VAXG21 +1.5V_CPU_VDDQ
AN18 VAXG22
DDR3 -1.5V RAILS

AN17 VAXG23
AM24 VAXG24 AF7
GRAPHICS
AM23 VAXG25 VDDQ1 AF4
AM21 VAXG26 VDDQ2 AF1
VAXG27 VDDQ3 1
AM20 AC7 1 1 1 1
VAXG28 VDDQ4
C117
C119
C120
C122
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
AM18 AC4 @ + C123
AM17 VAXG29 VDDQ5 AC1 220U_6.3V_M
AL24 VAXG30 VDDQ6 Y7
AL23 VAXG31 VDDQ7 Y4 2 2 2 2 2
AL21 VAXG32 VDDQ8 Y1
AL20 VAXG33 VDDQ9 U7
AK24 VAXG36 VDDQ12 P7
AK20 VAXG39 VDDQ15
AK18 VAXG40
AK17 VAXG41
AJ24 VAXG42
AJ23 VAXG43
AJ21 VAXG44
AJ20 VAXG45 +VCCSA
B B
AJ18 VAXG46
AJ17 VAXG47 M27 +VCCSA
AH24 VAXG48 VCCSA1 M26
SA RAIL
VAXG49 VCCSA2 1 1 1 1
C124
C125
C126
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
AH23 L26
AH21 VAXG50 VCCSA3 J26 + C128 @
AH20 VAXG51 VCCSA4 J25 330U_D2_2.5VY_R9M
AH18 VAXG52 VCCSA5 J24 2 2 2
AH17 VAXG53 VCCSA6 H26 2
VAXG54 VCCSA7 H25
VCCSA8
1.8V RAIL
H23
+1.8VS VCCSA_SENSE +VCCSA_SENSE <51>
R69 0_0805_5% 1.5A
1 2 +1.8VS_VCCPLL B6
A6 VCCPLL1 C22
MISC
VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <51>

C345
C130
C132
22U_0805_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
@ 1 1 1 A2 C24
VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 <51>
@
2 2 2 A19
VCCIO_SEL
ME@
A IVY Bridge drives VCCIO_SEL low A
VCCP_PWRCTRL:0
1bios.ru
Sandy Bridge is NC for A19
VCCP_PWRCTRL:1
Security Classification Compal Secret Data

PROCESSOR(6/7) PWR
Custom 1.0
LA-9631P
5 4 3 2 1
5 4 3 2 1
JCPU1H JCPU1I
AT35 AJ22
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22
AT27 VSS3 VSS83 AJ13 T34 VSS161 VSS234 F19
AT25 VSS4 VSS84 AJ10 T33 VSS162 VSS235 E30
D D
AT7 VSS10 VSS90 AH35 T27 VSS168 VSS241 E13
AT4 VSS11 VSS91 AH34 T26 VSS169 VSS242 E10
AT3 VSS12 VSS92 AH32 P9 VSS170 VSS243 E9
AR25 VSS13 VSS93 AH30 P8 VSS171 VSS244 E8
AR10 VSS18 VSS99 AH19 N35 VSS176 VSS249 E3
AR2 VSS21 VSS102 AH4 N32 VSS179 VSS252 D35
AP34 VSS22 VSS103 AG9 N31 VSS180 VSS253 D32
AP25 VSS25 VSS106 AF6 N28 VSS183 VSS256 D20
AP22 VSS26 VSS107 AF5 N27 VSS184 VSS257 D17
AP19 VSS27 VSS108 AF3 N26 VSS185 VSS258 C34
AP16 VSS28 VSS109 AF2 M34 VSS186 VSS259 C31
AP13 VSS29 VSS110 AE35 L33 VSS187 VSS260 C28
C
AN30 VSS34 VSS115 AE30 L6 VSS192 VSS265 C1 C
AN27 VSS35 VSS116 AE29 L5 VSS193 VSS266 B22
AN25 VSS36 VSS117 AE28 L4 VSS194 VSS267 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 AE9 L1 B13
AN13 VSS40 VSS121 AD7 K35 VSS198 VSS271 B11
AN10 VSS41 VSS122 AC9 K32 VSS199 VSS272 B9
AM29 VSS44 VSS125 AC5 J34 VSS202 VSS275 B5
AM25 VSS45 VSS126 AC3 J31 VSS203 VSS276 B3
AM22 VSS46 VSS127 AC2 H33 VSS204 VSS277 B2
AM19 VSS47 VSS128 AB35 H30 VSS205 VSS278 A35
AM2 VSS54 VSS135 AB28 H10 VSS212 VSS285
AM1 VSS55 VSS136 AB27 H9 VSS213
AL34 VSS56 VSS137 AB26 H8 VSS214
AL31 VSS57 VSS138 Y9 H7 VSS215
B B
AL13 VSS63 VSS144 W35 H1 VSS221
AL10 VSS64 VSS145 W34 G35 VSS222
AK33 VSS68 VSS149 W30 G23 VSS226
AK22 VSS72 VSS153 W26 F34 VSS230
AK19 VSS73 VSS154 U9 F31 VSS231
AK16 VSS74 VSS155 U8 F29 VSS232
AK13 VSS75 VSS156 U6 VSS233
AK10 VSS76 VSS157 U5
AK7 VSS77 VSS158 U3
AK4 VSS78 VSS159 U2
AJ25 VSS79 VSS160
VSS80
A A
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE
ME@ Security Classification CompalME@

Secret Data Compal Electronics, Inc.
PROCESSOR(7/7) VSS
1bios.ru
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
LA-9631P
5 4 3 2 1
5 4 3 2 1
+VREF_DQ_DIMMA +1.5V +1.5V

[email protected]
<7> DDR_A_D[0..63]
DDR3 SO-DIMM A <7> DDR_A_DQS[0..7]
JDIMM1
<7> DDR_A_DQS#[0..7]
+VREF_DQ_DIMMA 1 2
3 VREF_DQ VSS1 4 DDR_A_D4
VSS2 DQ4 <7> DDR_A_MA[0..15]
2.2U_0603_6.3V4Z
.1U_0402_16V7K
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5
C134
C133
1 1 DDR_A_D1 7 8
9 DQ1 VSS3 10 DDR_A_DQS#0
DDR_A_DM0 11 VSS4 DQS#0 12 DDR_A_DQS0
13 DM0 DQS0 14
D 2 2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6 +1.5V D
DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
19 DQ3 DQ7 20 RP15
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12 8 1
DQ8 DQ12 +VREF_DQ_DIMMA
DDR_A_D9 23 24 DDR_A_D13 7 2
25 DQ9 DQ13 26 6 3
VSS9 VSS10 +VREF_DQ_DIMMB
@ DDR_A_DQS#1 27 28 DDR_A_DM1 5 4
DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <13,7>
31 32 1K_0804_8P4R_1%
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14
37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20 +1.5V
43 DQ17 DQ21 44 RP16
DDR_A_DQS#2 45 VSS15 VSS16 46 DDR_A_DM2 8 1
DQS#2 DM2 +VREF_CA
DDR_A_DQS2 47 48 7 2
49 DQS2 VSS17 50 DDR_A_D22 6 3
VSS18 DQ22 +VREF_CB
DDR_A_D18 51 52 DDR_A_D23 5 4
DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28 1K_0804_8P4R_1%
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
65 DM3 DQS3 66
71 DQ27 DQ31 72
VSS25 VSS26
C DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA C
<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<7> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
<7> M_CLK_DDR0 M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1 OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
CK0 CK1 M_CLK_DDR1 <7>
<7> M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
CK0# CK1# M_CLK_DDR#1 <7>
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
Layout Note: (10uF_0603_6.3V)*8
A10/AP BA1 DDR_A_BS1 <7>
<7> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS#
DDR_A_RAS# <7>
Place near DIMM
111 BA0 RAS# 112
<7> DDR_A_WE# DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA# (0.1uF_402_10V)*4
WE# S0# DDR_CS0_DIMMA# <7>
<7> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 <7>
117 118
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1
A13 ODT1 M_ODT1 <7> +VREF_CA
DDR_CS1_DIMMA# 121 122
<7> DDR_CS1_DIMMA# S1# NC2 +1.5V
123 124
125 VDD17 VDD18 126 +VREF_CA
127 NCTEST VREF_CA 128
VSS27 VSS28
.1U_0402_16V7K
2.2U_0603_6.3V4Z
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36
C135
C136
DDR_A_D33 131 132 DDR_A_D37 1 1 1
DQ33 DQ37
C139
C140
C141
C142
C143
C144
C145
C146
C147
C148
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
133 134 1 1 1 1 1 1 1 @ 1 1 1
DDR_A_DQS#4 135 VSS29 VSS30 136 DDR_A_DM4 + C149 @
B DDR_A_DQS4 137 DQS#4 DM4 138 220U_6.3V_M B
139 DQS4 VSS31 140 DDR_A_D38 2 2
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39 2 2 2 2 2 2 2 2 2 2 2
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45 @
DDR_A_D41 149 DQ40 DQ45 150
155 DM5 DQS5 156
VSS37 VSS38 VDDQ(1.5V) =
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
DQ43 DQ47 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
161 162
DQ48 DQ52 6*0603 10uf (PER CONNECTOR) Layout Note:
DDR_A_D49 165 166 DDR_A_D53
167 DQ49 DQ53 168 Place near DIMM
DDR_A_DQS#6 169 VSS41 VSS42 170 DDR_A_DM6
DQS#6 DM6 VTT(0.75V) =
DDR_A_DQS6 171 172 7/28 Update connect GND directly
173 DQS6 VSS43 174 DDR_A_D54
VSS44 DQ54 3*0805 10uf 4*0402 1uf
DDR_A_D50 175 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178 +0.75VS
DQ51 VSS45 VREF =
179 180 DDR_A_D60 DDR_A_DM0
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61 DDR_A_DM1
DQ56 DQ61 1*0402 0.1uf 1*0402 2.2uf
DDR_A_D57 183 184 DDR_A_DM2
185 DQ57 VSS47 186 DDR_A_DQS#7 DDR_A_DM3
VSS48 DQS#7 VDDSPD (3.3V)=
C150
C152
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_A_DM7 187 188 DDR_A_DQS7 DDR_A_DM4
189 DM7 DQS7 190 DDR_A_DM5
VSS49 VSS50 1*0402 0.1uf 1*0402 2.2uf 1 1
DDR_A_D58 191 192 DDR_A_D62 DDR_A_DM6
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63 DDR_A_DM7
195 DQ59 DQ63 196
197 VSS51 VSS52 198 2 2
199 SA0 EVENT# 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 <13,15,36> Layout Note:
2.2U_0603_6.3V4Z
.1U_0402_16V7K
A 201 202 SMB_CLK_S3 A

SA1 SCL SMB_CLK_S3 <13,15,36>
Place near DIMM
C155
C156
1 1 203 204 +0.75VS

VTT1 VTT2
205 206 [email protected]
G1 G2
2 2 LCN_DAN06-K4806-0103
ME@ Security Classification Compal Secret Data Compal Electronics, Inc.

@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
1bios.ru
Custom 1.0
LA-9631P
5 4 3 2 1
5 4 3 2 1
+VREF_DQ_DIMMB [email protected]
<7> DDR_B_D[0..63]
+1.5V +1.5V
<7> DDR_B_DQS[0..7]
JDIMM2
<7> DDR_B_DQS#[0..7]
+VREF_DQ_DIMMB 1 2
3 VREF_DQ VSS1 4 DDR_B_D4
VSS2 DQ4 <7> DDR_B_MA[0..15]
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 7 DQ0 DQ5 8
DQ1 VSS3
2.2U_0603_6.3V4Z
.1U_0402_16V7K
9 10 DDR_B_DQS#0
DDR_B_DM0 11 VSS4 DQS#0 12 DDR_B_DQS0
1 1 DM0 DQS0
13 14
VSS5 VSS6
C158
C157
D DDR_B_D2 15 16 DDR_B_D6 D
DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
2 2 19 DQ3 DQ7 20
@ DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS9 VSS10 28 DDR_B_DM1
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <12,7>
31 32
DDR_B_D10 33 VSS11 VSS12 34 DDR_B_D14
For Arranale only +VREF_DQ_DIMMB DDR_B_D11 35 DQ10 DQ14 36 DDR_B_D15
supply from a external 1.5V voltage divide 37 DQ11 DQ15 38
circuit. DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21
43 DQ17 DQ21 44
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D28
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3
65 DM3 DQS3 66
71 DQ27 DQ31 72
VSS25 VSS26
C DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB C
<7> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <7>
75 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<7> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<7> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <7>
<7> M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 <7>
105 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
Layout Note: (10uF_0603_6.3V)*8
A10/AP BA1 DDR_B_BS1 <7>
<7> DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS#
DDR_B_RAS# <7>
Place near DIMM
111 BA0 RAS# 112
<7> DDR_B_WE# DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS2_DIMMB# (0.1uF_402_10V)*4
WE# S0# DDR_CS2_DIMMB# <7>
<7> DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2
CAS# ODT0 M_ODT2 <7>
117 118
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3
A13 ODT1 M_ODT3 <7> +VREF_CB
DDR_CS3_DIMMB# 121 122
<7> DDR_CS3_DIMMB# S1# NC2 +1.5V
123 124
125 VDD17 VDD18 126 +VREF_CB
NCTEST VREF_CA
.1U_0402_16V7K
2.2U_0603_6.3V4Z
127 128
VSS27 VSS28
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36
C159
C160
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
DDR_B_D33 131 132 DDR_B_D37 1 1
DQ33 DQ37
C163
C164
C165
C166
C167
C168
C169
C170
C171
C172
133 134 1 1 1 1 1 1 1 @ 1 1 1
B DDR_B_DQS4 137 DQS#4 DM4 138 B
139 DQS4 VSS31 140 DDR_B_D38 2 2
DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39 2 2 2 2 2 2 2 2 2 2
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44 @
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
DM5 DQS5 VDDQ(1.5V) =
155 156
DQ42 DQ46 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
DDR_B_D43 159 160 DDR_B_D47
161 DQ43 DQ47 162
VSS39 VSS40 6*0603 10uf (PER CONNECTOR) Layout Note:
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53 Place near DIMM
167 DQ49 DQ53 168
VSS41 VSS42 VTT(0.75V) =
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 171 DQS#6 DM6 172
DQS6 VSS43 3*0805 10uf 4*0402 1uf
173 174 DDR_B_D54
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55 +0.75VS
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D60 DDR_B_DM0
VSS46 DQ60 1*0402 0.1uf 1*0402 2.2uf
DDR_B_D56 181 182 DDR_B_D61 DDR_B_DM1
DDR_B_D57 183 DQ56 DQ61 184 DDR_B_DM2
DQ57 VSS47 VDDSPD (3.3V)=
C174
C176
1U_0402_6.3V6K
1U_0402_6.3V6K
185 186 DDR_B_DQS#7 DDR_B_DM3
DDR_B_DM7 187 VSS48 DQS#7 188 DDR_B_DQS7 DDR_B_DM4
DM7 DQS7 1*0402 0.1uf 1*0402 2.2uf 1 1
189 190 DDR_B_DM5
DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D62 DDR_B_DM6
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63 DDR_B_DM7
195 DQ59 DQ63 196 2 2
197 VSS51 VSS52 198
199 SA0 EVENT# 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 <12,15,36>
2.2U_0603_6.3V4Z
.1U_0402_16V7K
A 1 2 201 202 SMB_CLK_S3 A

+3VS SA1 SCL SMB_CLK_S3 <12,15,36> Layout Note:
C177
C178
1 1 R97 10K_0402_5% 203 204 +0.75VS

VTT1 VTT2 [email protected] Place near DIMM
205 206
@ G1 G2
2 2 TYCO_2-2013287-1
ME@ Security Classification Compal Secret Data Compal Electronics, Inc.

DDRIII-SODIMM SLOT2
1bios.ru
1.0
LA-9631P
5 4 3 2 1
5 4 3 2 1
PCH_RTCX1
CLRP2 CMOS setting
W=20mils W=20mils Shunt Clear CMOS
1 2 PCH_RTCX2
+RTCVCC +RTCBATT R98 10M_0402_5% Open Keep CMOS
2
R99 @
1K_0402_5% R104 CLRP3 TPM setting
1 2 0_0402_5%
Y1 Shunt Clear ME RTC Registers
1
1 1 2
C179 32.768KHZ_12.5PF_CM31532768DZFT Open Keep ME RTC Registers
1U_0603_10V4Z 1 1
C181
2 C180 18P_0402_50V8J
D 18P_0402_50V8J D
2 2
U4A
SHORT PADS
CLRP2
+RTCVCC @
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 <42>
1
R101 1 2 1M_0402_5% SM_INTRUDER# A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 <42>
LPC
C183 PCH_RTCX2 C20 B37 LPC_AD2 EC and Mini card debug port
RTCX2 FWH2 / LAD2 LPC_AD2 <42>
R102 1 2 330K_0402_5% PCH_INTVRMEN 1U_0603_10V4Z C37 LPC_AD3
2
1 2 2 D20 FWH3 / LAD3 LPC_AD3 <42>
PCH_RTCRST#
R103 20K_0402_5% RTCRST# D36 LPC_FRAME#
INTVRMEN 1 2 PCH_SRTCRST# G22 FWH4 / LFRAME# LPC_FRAME# <42>
SRTCRST# E36
： Integrated VRM enable
H： R100 20K_0402_5%
* 1 LDRQ0#
1
SHORT PADS
CLRP3
： Integrated VRM disable SM_INTRUDER# K22 K36
RTC
L： @
INTRUDER# LDRQ1# / GPIO23
C182
(INTVRMEN should always be pull high.) 1U_0603_10V4Z PCH_INTVRMEN C17 V5 SERIRQ
SERIRQ <42>
2
2 INTVRMEN SERIRQ
AM3 SATA_DTX_C_IRX_N0
+3VS SATA0RXN SATA_DTX_C_IRX_N0 <40>
HDA_BIT_CLK N34 AM1 SATA_DTX_C_IRX_P0
HDA_BCLK SATA0RXP SATA_DTX_C_IRX_P0 <40>
AP7 SATA_ITX_C_DRX_N0 HDD
SATA 6G
SATA0TXN SATA_ITX_C_DRX_N0 <40>
R105 1 @ 2 1K_0402_5% HDA_SPKR HDA_SYNC L34 AP5 SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_P0 <40>
HDA_SYNC SATA0TXP
HIGH= Enable ( No Reboot ) HDA_SPKR T10 AM10
<41> HDA_SPKR SPKR SATA1RXN AM8
LOW= Disable (Default)
* HDA_RST# K34
HDA_RST#
SATA1RXP
SATA1TXN
AP11
AP10
SATA1TXP
C +3V_PCH HDA_SDIN0 E34 AD7 SATA_DTX_C_IRX_N2 C
<41> HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_DTX_C_IRX_N2 <40>
AD5 SATA_DTX_C_IRX_P2 ODD
SATA2RXP SATA_DTX_C_IRX_P2 <40>
R106 2 @ 1 1K_0402_5% ME_FLASH G34 AH5 SATA_ITX_C_DRX_N2
HDA_SDIN1 SATA2TXN AH4 SATA_ITX_C_DRX_N2 <40>
SATA_ITX_C_DRX_P2
SATA2TXP SATA_ITX_C_DRX_P2 <40>
Low = Disabled (Default) C34
* HDA_SDIN2 AB8
IHDA
High = Enabled [Flash Descriptor Security Overide] A34 SATA3RXN AB10
HDA_SDIN3 SATA3RXP AF3
SATA3TXN AF1
ME_FLASH A36 SATA3TXP
+3V_PCH <42> ME_FLASH HDA_SDO Y7
SATA
SATA4RXN Y5
R108 2 1 1K_0402_5% HDA_SYNC PCH_GPIO33 C36 SATA4RXP AD3
HDA_DOCK_EN# / GPIO33 SATA4TXN AD1
PCH_GPIO13 N32 SATA4TXP
HDA_DOCK_RST# / GPIO13 Y3
This signal has a weak internal pull-down
SATA5RXN Y1
On Die PLL VR is supplied by SATA5RXP
1.5V when smapled high AB3
PCH_JTAG_TCK J3 SATA5TXN AB1
* 1.8V when sampled low
Needs to be pulled High for Chief River platfrom
JTAG_TCK SATA5TXP
PCH_JTAG_TMS H7 Y11 R111
JTAG_TMS SATAICOMPO +V1.05S_VCCP
JTAG
37.4_0402_1%
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
+5VS JTAG_TDI SATAICOMPI
PCH_JTAG_TDO H1
JTAG_TDO AB12 R113 +V1.05S_VCCP
HDA_BIT_CLK SATA3RCOMPO
<41> HDA_BITCLK_AUDIO For EMI 49.9_0402_1%
2
G
Q10 AB13 SATA3_COMP 1 2

RP12 LBSS138LT1G_SOT-23-3 SATA3COMPI
8 1 HDA_SYNC_R 3 1 HDA_SYNC
<41> HDA_SYNC_AUDIO
7 2 SPI_CLK_PCH_R T3 AH1 RBIAS_SATA3 1 2
S
6 3 SPI_CLK SATA3RBIAS R115

2
B 5 4 HDA_RST# SPI_SB_CS0# Y14 750_0402_1% B

<41> HDA_RST_AUDIO# SPI_CS0#
R878
33_0804_8P4R_5% 1M_0402_5% T1
SPI_CS1#
SPI
ME_FLASH P3 SATALED#
<41> HDA_SDOUT_AUDIO SATALED#
1
SPI_SI V4 V14 PCH_GPIO21 Share ROM

SPI_MOSI SATA0GP / GPIO21
SPI_SO_R U3 P1 BBS_BIT0_R @
check with vender SPI_MISO SATA1GP / GPIO19 RP2
Del Q10 check with codec SPI_SO_R 1 8 EC_SPI_SO
2 7 EC_SPI_SO <42>
PANTHER-POINT_FCBGA989 SPI_SI EC_SPI_SI
VDDIO using 3VALW HM76@ SPI_CLK_PCH_R 3 6 EC_SPI_CLK
EC_SPI_SI <42>
EC_SPI_CLK <42>
SA00005FH70 SPI_SB_CS0# 4 5 EC_SPI_CS#
EC_SPI_CS# <42>
S IC BD82HM76 SLJ8E C1 BGA 989P PCH C38!
SPI_CLK_PCH_R 0_0804_8P4R_5%
U4 HM70@ +3V_ROM
Share ROM
1
R124
33_0402_5% R127 1 2 SPI_WP# +3V_ROM
@ 3.3K_0402_5%
SA00005MQ80
2
IC BD82HM70 SJTNV C1 BGA 989P PCH C38! R129 1 2 SPI_HOLD# U5

3.3K_0402_5% SPI_SB_CS0# 1 8
SPI_SO_R 1 R131 2 SPI_SO_L 2 CS# VCC 7 SPI_HOLD#
DPDG1.1 C190 For EMI U4 NM70@
SO HOLD#
22P_0402_50V8J 0_0402_5% SPI_WP# 3 6 SPI_CLK_1 1 R133 2 SPI_CLK_PCH_R
@ 4 WP# SCLK 5 0_0402_5% SPI_SI
+3VS @ GND SI
For EMI @
RP17 W25Q64FVSSIQ_SO8 For EMI
BBS_BIT0_R 8 1 SA000039A30
R124;c190 close to U4.T3 pin SA00005WU60 SATALED# 7 2 S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM
S IC BD82NM70 SLJTA C1 BGA 989P PCH C38! PCH_GPIO16 6 3
A <19> PCH_GPIO16 SERIRQ 5 4 A
10K_0804_8P4R_5%

Compal Secret Data
PCH (1/9) SATA,HDA,SPI, LPC, XDP
Custom 1.0
LA-9631P
Date: Wednesday, March 06, 2013 Sheet 14 of 60
5 4 3 2 1
5 4 3 2 1
U4B
Q60A
2N7002DW-T/R7_SOT363-6
PCIE_PRX_DTX_N1 BG34 6 1 SMB_CLK_S3
<37> PCIE_PRX_DTX_N1 PERN1 SMB_CLK_S3 <12,13,36>
LAN PCIE_PRX_DTX_P1 BJ34 E12 PCH_GPI011 2 R134 1 10K_0402_5%
<37> PCIE_PRX_DTX_P1 PERP1 SMBALERT# / GPIO11 +3V_PCH
C192 1 2 .1U_0402_16V7K PCIE_PTX_DRX_N1 AV32
<37> PCIE_PTX_C_DRX_N1
C193 1 2 .1U_0402_16V7K PCIE_PTX_DRX_P1 AU32 PETN1 H14 PCH_SMBCLK DIMM1
2
<37> PCIE_PTX_C_DRX_P1 PETP1 SMBCLK
<36> PCIE_PRX_DTX_N2
PCIE_PRX_DTX_N2 BE34
PERN2 SMBDATA
C9 PCH_SMBDATA
+3VS DIMM2
5
PCIE_PRX_DTX_P2 BF34
WLAN
<36> PCIE_PRX_DTX_P2
<36> PCIE_PTX_C_DRX_N2
C194 1 2 .1U_0402_16V7K PCIE_PTX_DRX_N2 BB32 PERP2
PETN2
Mini Card
C195 1 2 .1U_0402_16V7K PCIE_PTX_DRX_P2 AY32 3 4 SMB_DATA_S3
<36> PCIE_PTX_C_DRX_P2 PETP2 SMB_DATA_S3 <12,13,36>
SMBUS
A12 DRAMRST_CNTRL_PCH
BG36 SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <10,7>
2N7002DW-T/R7_SOT363-6
BJ36 PERN3 C8 PCH_SML0CLK
PERP3 SML0CLK Q60B
D AV34 2 R139 1 D
PETN3 +3V_PCH
AU34 G12 PCH_SML0DATA 1K_0402_5%
PETP3 SML0DATA Q61A
BF36 PCH_HOT# 2 R140 1 10K_0402_5% 2N7002DW-T/R7_SOT363-6
PERN4 +3V_PCH
BE36 6 1 EC_SMB_CK2
AY34 PERP4 C13 EC_SMB_CK2 <24,39,42>
BB34 PETN4 SML1ALERT# / PCHHOT# / GPIO74
PETP4 E14 SML1CLK VGA
2
BG37 SML1CLK / GPIO58
PCI-E*
BH37 PERN5
PERP5 SML1DATA / GPIO75
M16 SML1DATA
+3VS EC
5
AY36
BB36 PETN5
PETP5
Thermal Sensor
3 4 EC_SMB_DA2
BJ38 EC_SMB_DA2 <24,39,42>
BG38 PERN6 2N7002DW-T/R7_SOT363-6
AU36 PERP6 M7
Controller
PETN6 CL_CLK1 Q61B
AV36 +3V_PCH
PETP6 +3V_PCH
Link
BG40 T11
PERN7 CL_DATA1
2
BJ40
AY40 PERP7
PETN7
2
BB40 P10 R143
PETP7 CL_RST1# R544 R545
10K_0402_5%
BE38 2.2K_0402_5% 2.2K_0402_5%
1
BC38 PERN8
AW38 PERP8
1
AY38 PETN8 CLK_REQ_VGA# <24> PCH_SML0CLK
PETP8
M10 1 R145 2 10K_0402_5% PCH_SML0DATA
R153 1 @ 2 0_0402_5% CLK_PCIE_LAN#_R Y40 PEG_A_CLKRQ# / GPIO47 @
<37> CLK_PCIE_LAN# CLKOUT_PCIE0N
LAN R154 1 @ 2 0_0402_5% CLK_PCIE_LAN_R Y39
<37> CLK_PCIE_LAN CLKOUT_PCIE0P AB37
For EMI CLK_PCIE_VGA#_R R168 1 @ 2 0_0402_5%
C J2 CLKOUT_PEG_A_N AB38 CLK_PCIE_VGA# <23> C
CLK_PCIE_VGA_R R172 1 @ 2 0_0402_5%
CLOCKS
<37> CLKREQ_LAN# 2 1 10K_0402_5% PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA <23>
R152
<36> CLK_PCIE_WLAN1#
+3V_PCH
R156 1 @ 2 0_0402_5% CLK_PCIE_WLAN1#_R AB49
CLKOUT_PCIE1N CLKOUT_DMI_N
AV22 CLK_CPU_DMI#
CLK_CPU_DMI# <6>
For EMI +3V_PCH
+3VS
R165 1 @ 2 0_0402_5% CLK_PCIE_WLAN1_R AB47 AU22 CLK_CPU_DMI
<36> CLK_PCIE_WLAN1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <6>
WLAN For EMI RP23
M1 SML1DATA 8 1
<36> CLKREQ_WLAN# PCIECLKRQ1# / GPIO18
+3VS R158 2 1 10K_0402_5% AM12 EC_SMB_DA2 7 2
CLKOUT_DP_N AM13 SML1CLK 6 3
AA48 CLKOUT_DP_P EC_SMB_CK2 5 4
AA47 CLKOUT_PCIE2N
CLKOUT_PCIE2P BF18 CLK_BUF_CPU_DMI# R155 1 2 10K_0402_5% 2.2K_0804_8P4R_5%
PCH_GPIO20 V10 CLKIN_DMI_N BE18 CLK_BUF_CPU_DMI R157 1 2 10K_0402_5%
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P +3V_PCH
Y37 BJ30 CLKIN_DMI2# R159 1 2 10K_0402_5% +3VS

Y36 CLKOUT_PCIE3N CLKIN_GND1_N BG30 CLKIN_DMI2 R160 1 2 10K_0402_5% RP24
CLKOUT_PCIE3P CLKIN_GND1_P PCH_SMBCLK 8 1
PCH_GPIO25 A8 SMB_CLK_S3 7 2
PCIECLKRQ3# / GPIO25 G24 CLK_BUF_DREF_96M# R162 1 2 10K_0402_5% PCH_SMBDATA 6 3
CLKIN_DOT_96N E24 CLK_BUF_DREF_96M R163 1 2 10K_0402_5% SMB_DATA_S3 5 4
Y43 CLKIN_DOT_96P
Y45 CLKOUT_PCIE4N 2.2K_0804_8P4R_5%
CLKOUT_PCIE4P AK7 CLK_BUF_PCIE_SATA# R164 1 2 10K_0402_5%
PCH_GPIO26 L12 CLKIN_SATA_N AK5 CLK_BUF_PCIE_SATA R166 1 2 10K_0402_5%
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
V45 K45 CLK_BUF_ICH_14M R167 1 2 10K_0402_5%

V46 CLKOUT_PCIE5N REFCLK14IN
CLKOUT_PCIE5P
PCH_GPIO44 L14 H45 CLK_PCI_LPBACK
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <18>
B B
AB42 V47 XTAL25_IN
AB40 CLKOUT_PEG_B_N XTAL25_IN V49 XTAL25_OUT
CLKOUT_PEG_B_P XTAL25_OUT
PCH_GPIO56 E6 R171 +V1.05S_VCCP
PEG_B_CLKRQ# / GPIO56 90.9_0402_1%
Y47 XCLK_RCOMP 1 2
V40 XCLK_RCOMP
V42 CLKOUT_PCIE6N
CLKOUT_PCIE6P XTAL25_IN
PCH_GPIO45 T13
PCIECLKRQ6# / GPIO45 27M_SSC XTAL25_OUT 1 2
V38 K43 R169 1M_0402_5%
V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS
CLKOUT_PCIE7P F47 3 4
PCH_GPIO46 K12 CLKOUTFLEX1 / GPIO65 OSC NC
PCIECLKRQ7# / GPIO46 H47 2 1
AK14 CLKOUTFLEX2 / GPIO66 NC OSC
PCIE_CLK_8N AK13 CLKOUT_ITPXDP_N K49 PCH_GPIO67 Y2
PCIE_CLK_8P CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 PCH_GPIO67 <19>
1 25MHZ_10PF_7V25000014 1
BIOS Request SKU ID C196 C197
PANTHER-POINT_FCBGA989 12P_0402_50V8J 12P_0402_50V8J
2 2
HM76@
A A

Compal Secret Data
PCH (2/9) PCIE, SMBUS, CLK
Custom 1.0
LA-9631P
5 4 3 2 1
5 4 3 2 1
+RTCVCC
DSWODVREN R179 2 1 330K_0402_5%
R183 2 @ 1 330K_0402_5%
D D
DSWODVREN - On Die DSW VR Enable
U4C * H：Enable
L：Disable
@ DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

<5> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <5>
U15 DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
MC74VHC1G08DFT2G SC70 5P DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
3
DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3

1 BC12 FDI_CTX_PRX_N4
G
<42,54> VGATE A FDI_RXN4 FDI_CTX_PRX_N4 <5>

4 SYS_PWROK DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5
Y <5> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <5>
PCH_PWROK 2 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
B <5> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <5>
P
DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7

<5> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <5>
DMI_CTX_PRX_P3 BJ20
<5> DMI_CTX_PRX_P3
5
DMI3RXP
1
@ BG14 FDI_CTX_PRX_P0
FDI_RXP0 FDI_CTX_PRX_P0 <5>
R180 DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1
<5> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <5>
10K_0402_5% DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
+3VS DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4
FDI_CTX_PRX_P4 <5>
2
<5> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4
DMI
FDI
BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 <5>
DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6
<5> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <5>
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7
<5> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <5>
DMI_CRX_PTX_P2 AY18
<5> DMI_CRX_PTX_P2 AU18 DMI2TXP
DMI_CRX_PTX_P3
<5> DMI_CRX_PTX_P3 DMI3TXP AW16 FDI_INT
FDI_INT FDI_INT <5>
+V1.05S_VCCP BJ24 AV12 FDI_FSYNC0
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <5>
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <5>
R177 49.9_0402_1%
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
C DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <5> C
R178 750_0402_1%
4mil width and place BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 <5>
within 500mil of the PCH
A18 DSWODVREN
DSWVRMEN
SUSACK# is only used on platform
that support the Deep Sx state.
System Power Management

C12 E22 EC_RSMRST#
SUSACK# DPWROK
SYS_RST# K3 B9
<19> SYS_RST# SYS_RESET# WAKE# PCIE_WAKE# <36>
SYS_PWROK P12 N3 PM_CLKRUN#

<42> SYS_PWROK SYS_PWROK CLKRUN# / GPIO32
R299 10K_0402_5%
L22 G8 SUS_STAT# 2 1
<42> PCH_PWROK PWROK SUS_STAT# / GPIO61
PCH_PWROK L10 N14

APWROK SUSCLK / GPIO62 SUSCLK <42>
PM_DRAM_PWRGD B13 D10

<6> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <42>
C21 H4
<42> EC_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <42>
+3V_PCH
SUSWARN# K16 F4
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <42>
2 R192 1 300_0402_5% PM_DRAM_PWRGD
B E20 G10 Can be left NC when IAMT is not support on the platfrom B
<42> PBTN_OUT# PWRBTN# SLP_A#
R194 2 1 10K_0402_5% SUSWARN#
D29 1 2 AC_PRESENT_R H20 G16

<24,42,46,48> ACIN ACPRESENT / GPIO31 SLP_SUS#
CH751H-40PT_SOD323-2
R197 2 1 10K_0402_5% EC_RSMRST# PCH_GPIO72 E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <6>
@
RI# A10 K14 Can be left NC if no use integrated LAN.
RI# SLP_LAN# / GPIO29
PANTHER-POINT_FCBGA989
HM76@
+3V_PCH
R309 1 2 200K_0402_5% AC_PRESENT_R
+3V_PCH
RP25
8 1 PCIE_WAKE#
A 7 2 RI# A
6 3 EC_SMI#
5 4 EC_SMI# <19,42>
1bios.ru
10K_0804_8P4R_5%

PCH (3/9) DMI,FDI,PM,
Custom 1.0
LA-9631P
5 4 3 2 1
5 4 3 2 1
U4D
R438
D 2 1 ENBKL J47 AP43 D
<42> ENBKL L_BKLTEN SDVO_TVCLKINN
M45 AP45
<33> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
100K_0402_1% P45 AM42
<33> PCH_PWM L_BKLTCTL SDVO_STALLN AM40
EDID_CLK T40 SDVO_STALLP
<33> EDID_CLK K47 L_DDC_CLK AP39
EDID_DATA
<33> EDID_DATA L_DDC_DATA SDVO_INTN AP40
CTRL_CLK T45 SDVO_INTP
CTRL_DATA P39 L_CTRL_CLK
+3VS L_CTRL_DATA
2 R206
2.37K_0402_1% 1 LVDS_IBG AF37 P38 HDMICLK_NB
LVD_IBG SDVO_CTRLCLK HDMICLK_NB <35>
AF36 M39 HDMIDAT_NB
LVD_VBG SDVO_CTRLDATA HDMIDAT_NB <35>
RP14 LVD_VREF AE48
8 1 EDID_DATA AE47 LVD_VREFH AT49
7 2 EDID_CLK LVD_VREFL DDPB_AUXN AT47
6 3 CTRL_DATA DDPB_AUXP AT40
DDPB_HPD TMDS_B_HPD# <35>
5 4 CTRL_CLK AK39
<33> LVDS_ACLK# LVDSA_CLK#
LVDS
AK40 AV42 TMDS_B_DATA2#_PCHHDMI@ C200 1 2 .1U_0402_16V7K
<33> LVDS_ACLK LVDSA_CLK DDPB_0N HDMI_TX2-_CK <35>
2.2K_0804_8P4R_5% AV40 TMDS_B_DATA2_PCH HDMI@ C201 1 2 .1U_0402_16V7K HDMI D2
AN48 DDPB_0P AV45 TMDS_B_DATA1#_PCHHDMI@ 1 2 HDMI_TX2+_CK <35>
C202 .1U_0402_16V7K
<33> LVDS_A0# AM47 LVDSA_DATA#0 DDPB_1N AV46 TMDS_B_DATA1_PCH HDMI@ 1 2 HDMI_TX1-_CK <35>
C203 .1U_0402_16V7K HDMI D1
<33> LVDS_A1# LVDSA_DATA#1 DDPB_1P HDMI_TX1+_CK <35>
Digital Display Interface

AK47 AU48 TMDS_B_DATA0#_PCHHDMI@ C204 1 2 .1U_0402_16V7K HDMI
C <33> LVDS_A2# AJ48 LVDSA_DATA#2 DDPB_2N AU47 TMDS_B_DATA0_PCH HDMI@ 1 2 HDMI_TX0-_CK <35> C
C205 .1U_0402_16V7K HDMI D0
LVDSA_DATA#3 DDPB_2P HDMI_TX0+_CK <35>
AV47 TMDS_B_CLK#_PCH HDMI@ C206 1 2 .1U_0402_16V7K
AN47 DDPB_3N AV49 TMDS_B_CLK_PCH 1 2 HDMI_CLK-_CK <35>
HDMI@ C207 .1U_0402_16V7K HDMI CLK
<33> LVDS_A0 AM49 LVDSA_DATA0 DDPB_3P HDMI_CLK+_CK <35>
<33> LVDS_A1 LVDSA_DATA1
AK49
<33> LVDS_A2 AJ47 LVDSA_DATA2 P46
LVDSA_DATA3 DDPC_CTRLCLK CAP move on Conn, side
P42
RP20 DDPC_CTRLDATA
8 1 DAC_BLU AF40
7 2 DAC_GRN AF39 LVDSB_CLK# AP47
6 3 DAC_RED LVDSB_CLK DDPC_AUXN AP49
5 4 AH45 DDPC_AUXP AT38
AH47 LVDSB_DATA#0 DDPC_HPD
150_0804_8P4R_1% AF49 LVDSB_DATA#1 AY47
AF45 LVDSB_DATA#2 DDPC_0N AY49
Max = 800 mils LVDSB_DATA#3 DDPC_0P
DDPC_1N
AY43
AH43 AY45
AH49 LVDSB_DATA0 DDPC_1P BA47
AF47 LVDSB_DATA1 DDPC_2N BA48
AF43 LVDSB_DATA2 DDPC_2P BB47
DAC_BLU LVDSB_DATA3 DDPC_3N BB49
<34> DAC_BLU DDPC_3P
DAC_GRN
<34> DAC_GRN N48 M43
B B
DAC_RED P49 CRT_BLUE DDPD_CTRLCLK M36
<34> DAC_RED T49 CRT_GREEN DDPD_CTRLDATA
CRT_RED
AT45
DDPD_AUXN
CRT
CRT_DDC_CLK T39 AT43
<34> CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
CRT_DDC_DATA M40 BH41
<34> CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD
BB43
+3VS M47 DDPD_0N BB45
<34> CRT_HSYNC M49 CRT_HSYNC DDPD_0P BF44
<34> CRT_VSYNC CRT_VSYNC DDPD_1N BE44
DDPD_1P BF42
DDPD_2N
1
CRT_IREF T43 BE42

R559 R524 T42 DAC_IREF DDPD_2P BJ42
CRT_IRTN DDPD_3N
1
2.2K_0402_5% 2.2K_0402_5% BG42

R211 DDPD_3P
1K_0402_1% PANTHER-POINT_FCBGA989
2
CRT_DDC_CLK
2
CRT_DDC_DATA HM76@
A A

PCH (4/9) LVDS,CRT,DP,HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 1.0
LA-9631P
1bios.ru
5 4 3 2 1
5 4 3 2 1
+3VS
RP1
PCI_PIRQA# 1 10
PCI_PIRQD# 2 9 PCH_GPIO2 U4E
PCI_PIRQC# 3 8 DGPU_PWR_EN AY7
PCI_PIRQB# 4 7 PCH_GPIO4 RSVD1 AV7
5 6 PCH_GPIO3 BG26 RSVD2 AU3
+3VS BJ26 TP1 RSVD3 BG4
BH25 TP2 RSVD4
8.2K_1206_10P8R_5% BJ16 TP3 AT10
BG16 TP4 RSVD5 BC8
AH38 TP5 RSVD6
D TP6 D
AH37 AU2
AK43 TP7 RSVD7 AT4
+3VS AK45 TP8 RSVD8 AT3
RP7 C18 TP9 RSVD9 AT1
8 1 DGPU_HOLD_RST# N30 TP10 RSVD10 AY3
7 2 PCH_WL_OFF# H3 TP11 RSVD11 AT5
6 3 PCH_GPIO5 AH12 TP12 RSVD12 AV3
5 4 PCH_GPIO52 AM4 TP13 RSVD13 AV1
AM5 TP14 RSVD14 BB1
8.2K_0804_8P4R_5% Y13 TP15 RSVD15 BA3
K24 TP16 RSVD16 BB5
Pull-up resistors are not required TP17 RSVD17
L24 BB3
on these signals AB46 TP18 RSVD18 BB7
R292 1 @ 2 8.2K_0402_5% PCH_GPIO51 AB45 TP19 RSVD19 BE8
TP20 RSVD20
RSVD
BD4
R557 1 @ 2 8.2K_0402_5% PCH_GPIO53 RSVD21 BF6
RSVD22
B21 AV5
M20 TP21 RSVD23 AV10
AY16 TP22 RSVD24
BG46 TP23 AT8
TP24 RSVD25
AY5
RSVD26 BA2
USB3_RX1_N BE28 RSVD27
<44> USB3_RX1_N USB3Rn1
<44> USB3_RX2_N USB3_RX2_N BC30 AT12
USB3_RX3_N BE32 USB3Rn2 RSVD28 BF3
C USB3Rn3 RSVD29 C
Boot BIOS Strap bit1 BBS1 USB3_RX4_N BJ32
USB3_RX1_P BC28 USB3Rn4
<44> USB3_RX1_P USB3Rp1
Boot BIOS <44> USB3_RX2_P USB3_RX2_P BE30 USB Debug Port = Port1 and Port9
USB3_RX3_P BF32 USB3Rp2
Bit11 Bit10 Destination USB3_RX4_P BG32 USB3Rp3
USB3Rp4 USBP0N
C24 USB20_N0
USB20_N0 <44>
USB3_TX1_N AV26 A24 USB20_P0 LEFT USB
<44> USB3_TX1_N USB3Tn1 USBP0P USB20_P0 <44>
0 1 Reserved USB3_TX2_N BB26 C25 USB20_N1 (USB 3.0)
<44> USB3_TX2_N USB3Tn2 USBP1N USB20_N1 <44>
GNT1#/ USB3_TX3_N AU28 B25 USB20_P1 LEFT USB
USB3Tn3 USBP1P USB20_P1 <44>
1 0 Reserved USB3_TX4_N AY30 C26 USB20_N2
GPIO51 USB3_TX1_P AU26 USB3Tn4 USBP2N A26 USB20_P2
USB20_N2 <44>
<44> USB3_TX1_P
USB3_TX2_P AY26 USB3Tp1 USBP2P K28 USB20_N3
USB20_P2 <44> Touch Screen
1 1 SPI (Default)
* <44> USB3_TX2_P
USB3_TX3_P AV28 USB3Tp2
USB3Tp3
USBP3N
USBP3P
H28 USB20_P3
USB20_N3
USB20_P3
<33>
<33> USB Camera
0 0 LPC USB3_TX4_P AW30 E28
USB3Tp4 USBP4N D28
USBP4P C28
USBP5N A28
USBP5P C29
USBP6N B29
PCI_PIRQA# K40 USBP6P N28
PCI_PIRQB# K38 PIRQA# USBP7N M28
PIRQB# USBP7P
PCI
PCI_PIRQC# H38 L30
PCI_PIRQD# G38 PIRQC# USBP8N K30
PIRQD# USBP8P G30 USB20_N9
USBP9N USB20_N9 <44>
C46 E30 USB20_P9 RIGHT USB
<23> DGPU_HOLD_RST# REQ1# / GPIO50 USBP9P USB20_P9 <44>
USB
PCH_GPIO52 C44 C30 USB20_N10
REQ2# / GPIO52 USBP10N USB20_N10 <36>
E40 A30 USB20_P10 WLAN
<25,42,51,53> DGPU_PWR_EN REQ3# / GPIO54 USBP10P USB20_P10 <36>
B L32 USB20_N11 B
USBP11N USB20_N11 <43>
PCH_GPIO51 D47 K32 USB20_P11 CARD READER
GNT1# / GPIO51 USBP11P USB20_P11 <43>
PCH_GPIO53 E42 G32
PCH_WL_OFF# F46 GNT2# / GPIO53 USBP12N E32
<36> PCH_WL_OFF# GNT3# / GPIO55 USBP12P C32
USBP13N A32
PCH_GPIO2 G42 USBP13P
GPIO55 PIRQE# / GPIO2
PCH_GPIO3 G40
PCH_WL_OFF# R215 1 @ 2 1K_0402_5% PCH_GPIO4 C42 PIRQF# / GPIO3 C33 USBRBIAS 1 R218 2
PCH_GPIO5 D44 PIRQG# / GPIO4 USBRBIAS# 22.6_0402_1%
PIRQH# / GPIO5
B33
Within 500 mils
PCI_PME# K10 USBRBIAS
A16 swap overide Strap/Top-Block PME#
Swap Override jumper For LEFT USB3.0 Port
PCH_PLTRST# C6 A14 USB_OC0#
<6> PCH_PLTRST# PLTRST# OC0# / GPIO59 USB_OC0# <44>
Low=A16 swap K20 USB_OC1#
OC1# / GPIO40 B17 USB_OC2#
override/Top-Block OC2# / GPIO41
PCI_GNT3# Swap Override enabled 22_0402_5% 1 2 R219 CLK_PCI_LPBACK_R H49 C16 USB_OC3#
<15> CLK_PCI_LPBACK CLKOUT_PCI0 OC3# / GPIO42
High=Default 22_0402_5% 1 2 R220 CLK_PCI_EC_R H43 L16 USB_OC4#
* <42> CLK_PCI_EC
CLK_PCI_DB_R J48 CLKOUT_PCI1
CLKOUT_PCI2
OC4# / GPIO43
OC5# / GPIO9
A16 USB_OC5#
USB_OC4# <44>
+3V_PCH
For EMI K42 D14 USB_OC6# For RIGHT USB2.0 Port
CLKOUT_PCI3 OC6# / GPIO10 RP18
H40 C14 USB_OC7#
CLKOUT_PCI4 OC7# / GPIO14 USB_OC0# 1 10
USB_OC1# 2 9 USB_OC4#
PANTHER-POINT_FCBGA989 USB_OC2# 3 8 USB_OC5#
USB_OC3# 4 7 USB_OC6#
HM76@ 5 6 USB_OC7#
+3V_PCH
A A
10K_1206_10P8R_5%
1bios.ru
@ R222
1 2 PCH_PLTRST#
<23,36,37,42> PLT_RST#
0_0402_5%
1
1
C208 @ R223
1U_0402_6.3V6K
2
100K_0402_5%
PCH (5/9) PCI, USB
2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9631P 1.0
5 4 3 2 1
5 4 3 2 1
+3VS +3VS +3VS
PCH_GPIO69 PCH_GPIO70 Function
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
NM70@ NM70@ HM70@ Mars@
1 1 NM70 R702 R703 R703 PCH_GPIO71 Function R704

10K_0402_5%
1
PCH_GPIO69 PCH_GPIO70 PCH_GPIO71
Reserved 1 Mars XT
1 0
2
10K_0402_5%
10K_0402_5%
0 Sun Pro R706
HM70@ HM76@ HM76@
D
0 1 HM70 R707 R707 R705
200K_0402_5%
Sun@
D
10K_0402_5%
1
0 0 HM76
U4F
PCH_GPIO0 T7 C40 PCH_GPIO68

BMBUSY# / GPIO0 TACH4 / GPIO68
PCH_GPIO1 A42 B41 PCH_GPIO69
GPIO28 TACH1 / GPIO1 TACH5 / GPIO69
On-Die PLL Voltage Regulator PCH_GPIO6 H36 C41 PCH_GPIO70 +3VS
TACH2 / GPIO6 TACH6 / GPIO70
This signal has a weak internal pull up
EC_SCI# E38 A40 PCH_GPIO71
<42> EC_SCI# TACH3 / GPIO7 TACH7 / GPIO71
2
H：On-Die voltage regulator enable
* L：On-Die PLL Voltage Regulator disable <16,42> EC_SMI#
EC_SMI# C10
GPIO8
R236
10K_0402_5%
R240 1 @ 2 1K_0402_5% PCH_GPIO28 PCH_GPIO12 C4
+3V_PCH LAN_PHY_PW R_CTRL / GPIO12
1
1 R230 2 1K_0402_5% EC_LID_OUT# G2 P4 +3VS
GPIO15 A20GATE GATEA20 <42>
<42> EC_LID_OUT# AU16
PCH_GPIO16 U2 PECI
<14> PCH_GPIO16 SATA4GP / GPIO16 P5 KBRST# KBRST# R226 1 2 10K_0402_5%
* PCH_GPIO27 (Have internal Pull-High) <53> DGPU_PWROK
RCIN# KBRST# <42>
GPIO
D40 AY11
High: VCCVRM VR Enable TACH0 / GPIO17 PROCPW RGD H_CPUPWRGD <6>
CPU/MISC
PU on power side
Low: VCCVRM VR Disable PCH_BT_ON# T5 AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP#
H_THRMTRIP# <6>
C
SCLOCK / GPIO22 THRMTRIP# R239 390_0402_5% C
1 2 10K_0402_5% <36> PCH_BT_ON# E8 T14
R245 @ PCH_GPIO27 ODD_EN
+3V_PCH <40> ODD_EN GPIO24 INIT3_3V#
PCH_GPIO27 E16 AY1
R241 GPIO27 DF_TVS INIT3_3V
1 2 10K_0402_5% PCH_GPIO28 P8 This signal has weak internal PU,can't pull low
GPIO28 AH8
1 R242 2 10K_0402_5% K1 TS_VSS1
GPIO36, 37 +3VS
INTEL_BT_OFF#
STP_PCI# / GPIO34 +1.8VS
AK11
+3VS When Unused as GPIO or SATA*GP PCH_GPIO35 K4 TS_VSS2
+3VS <36> INTEL_BT_OFF# GPIO35
Use 8.2K-10K pull-down to ground. TS_VSS3
AH10 DMI Termination Voltage
PCH_GPIO36 V8
SATA2GP / GPIO36
1
1
AK10 Set to Vcc when HIGH
M5 TS_VSS4
R244 @ R250 @ PCH_GPIO37
SATA3GP / GPIO37
NV_CLE
10K_0402_5% 10K_0402_5% Set to Vss when LOW R216
PCH_GPIO38 N2 P37 2.2K_0402_5%
SLOAD / GPIO38 NC_1
2
2
PCH_GPIO37 PCH_GPIO36 PCH_GPIO39 M3 NV_CLE 2 1
SDATAOUT0 / GPIO39 H_SNB_IVB# <6>
R217 1K_0402_5%
1
PCH_GPIO48 V13 BG2 Weak internal CLOSE TO THE BRANCHING POINT

SDATAOUT1 / GPIO48 VSS_NCTF_15
1
PU,Do not pull low

R881 PCH_GPIO49 V3 BG48
10K_0402_5% R547 @ SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
10K_0402_5% PCH_GPIO57 D6 BH3
2
GPIO57 VSS_NCTF_17
2
BH47
@ VSS_NCTF_18
A4 BJ4
VSS_NCTF_1 VSS_NCTF_19
A44 BJ44
B VSS_NCTF_2 VSS_NCTF_20 B
A45 BJ45
NCTF
A46 BJ46
+3VS VSS_NCTF_4 VSS_NCTF_22
BIOS Request SKU ID
A5 BJ5
RP10 VSS_NCTF_5 VSS_NCTF_23
+3VS 8 1 PCH_GPIO39 A6 BJ6
7 2 SYS_RST# VSS_NCTF_6 VSS_NCTF_24
SYS_RST# <16>
6 3 PCH_BT_ON# B3 C2
5 4 PCH_GPIO35 VSS_NCTF_7 VSS_NCTF_25
B47 C48
10K_0804_8P4R_5% VSS_NCTF_8 VSS_NCTF_26
2
1
10K_0402_5%
10K_0402_5%
BD1 D1
BD49 D49
R711 R246 VSS_NCTF_10 VSS_NCTF_28
UMA@ UMA@ BE1 E1
1
PCH_GPIO38 BE49 E49
PCH_GPIO67 BF1 F1
PCH_GPIO67 <15> VSS_NCTF_13 VSS_NCTF_31
BF49 F49
2
1
10K_0402_5%
10K_0402_5%
R708 R298 PANTHER-POINT_FCBGA989

PX@ PX@
PCH_GPIO38 PCH_GPIO67 Function HM76@
1
A A
0 0 SG(Optimus / PX)
0 1 Reserved Security Classification Compal Secret Data
1 0 DIS PCH (6/9) GPIO, CPU, MISC
1bios.ru
Custom 1.0
1 1 UMA DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-9631P
5 4 3 2 1

5 4 3 2 1
L1 Change to 1 ohm P/N

+V1.05S_VCCP U4G POWER S RES 1/10W 1 +-1% 0603
+3VS PCH Power Rail Table
Near AA23
1300mA L1 1_0603_1% Refer to CPU EDS R1.5
AA23 U48 +VCCADAC 2 1
AC23 VCCCORE[1] 1mA VCCADAC
VCCCORE[2] 1 1 1 1 S0 Iccmax
1U_0402_6.3V6K
C210
1U_0402_6.3V6K
C211
1U_0402_6.3V6K
C212
1 1 1 1 AD21 C395@ Voltage Rail Voltage Current (A)
CRT
VCCCORE[3]
10U_0603_6.3V6M
C209
AD23 U47 C213 C214 C215 10U_0603_6.3V6M
AF21 VCCCORE[4] VSSADAC 0.01U_0402_16V7K .1U_0402_16V7K 10U_0603_6.3V6M
VCC CORE
AF23 VCCCORE[5] 2 2 2 2
VCCCORE[6]
V_PROC_IO 1.05 0.001
D 2 2 2 2 AG21 +3VS D
AG23 VCCCORE[7]
AG24 VCCCORE[8] AK36
VCCCORE[9] 1mA VCCALVDS V5REF 5 0.001
AG26
AG27 VCCCORE[10] AK37
AG29 VCCCORE[11] VSSALVDS
VCCCORE[12]
V5REF_Sus 5 0.001
AJ23 +1.8VS
VCCCORE[13]
LVDS
AJ26 AM37 L2
AJ27 VCCCORE[14] VCCTX_LVDS[1]
VCCCORE[15]
0.1UH_MLF1608DR10KT_10%_1608 Vcc3_3 3.3 0.228
AJ29 AM38 +VCCTX_LVDS 2 1
AJ31 VCCCORE[16] VCCTX_LVDS[2]
1 1 1 0.1uH inductor, 200mA
VCCCORE[17] AP36
+V1.05S_VCCP
60mA VCCTX_LVDS[3] VccADAC 3.3 0.001
C216 C217 C218
AP37 0.01U_0402_16V7K 0.01U_0402_16V7K 22U_0805_6.3V6M
AN19 VCCTX_LVDS[4] 2 2 2
VCCIO[28]
VccADPLLA 1.05 0.075
+VCCAPLLEXP BJ22 +3VS VccADPLLB 1.05 0.075

VCCAPLLEXP Near V33
This pin can be left as no connect in V33
AN16 VCC3_3[6]
HVCMOS
VccCore 1.05 1.3
On-Die VR enabled mode (default). VCCIO[15]
1
AN17
VCCIO[16] V34
VCC3_3[7]
C219 VccDMI 1.05 0.042
.1U_0402_16V7K
AN21 2
VCCIO[17]
VccIO 1.05 3.709
AN26 +1.5VS
VCCIO[18]
AN27 3711mA AT16 VccASW 1.05 0.903
VCCIO[19] VCCVRM[3]
+V1.05S_VCCP AP21 +V1.05S_VCCP
C
Near AN16 VCCIO[20] Near AT20 C
VccSPI 3.3 0.01
AP23 AT20
VCCIO[21] VCCDMI[1]
1
+V1.05S_VCCP
1U_0402_6.3V6K
C222
1U_0402_6.3V6K
C223
1U_0402_6.3V6K
C224
1U_0402_6.3V6K
C225
DMI
1 1 1 1 1 AP24 Near AB36 VccDSW 3.3 0.001
VCCIO[22]
10U_0603_6.3V6M
C221
VCCIO
C220
AP26 AB36 1U_0402_6.3V6K
VCCIO[23] 20mA VCCCLKDMI 2
1 VccDFTERM 1.8 0.002
2 2 2 2 2 AT24
VCCIO[24] C226
1U_0402_6.3V6K VccRTC 3.3 6 uA
AN33 2
VCCIO[25]
AN34 AG16 VccSus3_3 3.3 0.065
+3VS VCCIO[26] VCCDFTERM[1]
Share ROM
BH29 AG17 +1.8VS VccSusHDA 3.3 / 1.5 0.01
VCC3_3[3] 190mAVCCDFTERM[2]
DFT / SPI
1 Near AG16
C227
.1U_0402_16V7K +1.5VS AJ16 +3V_ROM VccVRM 1.8 / 1.5 0.167
VCCDFTERM[3]
2 1
AP16 C228
VCCVRM[2] AJ17
VCCDFTERM[4]
.1U_0402_16V7K VccCLKDMI 1.05 0.075
This pin can be left as no connect in +1.05VS_VCCAPLL_FDI BG6 2
On-Die VR enabled mode (default). +V1.05S_VCCP VccAFDIPLL
VccSSC 1.05 0.095
AP17 Near V1
VCCIO[27] V1 VccDIFFCLKN 1.05 0.055
FDI
20mA VCCSPI
1
AU20
+V1.05S_VCCP VCCDMI[2] C230 VccALVDS 3.3 0.001
1U_0402_6.3V6K
B PANTHER-POINT_FCBGA989 2 B
VccTX_LVDS 1.8 0.04
HM76@
Share ROM
+3VALW +3V_ROM +3VS
@
1 R413 2
0_0402_5%
@
Q21
AO3413_SOT23 @
+5VALW R419
D
3 1 1 2
.1U_0402_16V7K
C243
1 @ 0_0402_5%
@
G
2
R418
100K_0402_5%
2
2
@ Q22
1
R40 D
1 2 PCH_PWR_EN_R 2
<42> PCH_PWR_EN
.1U_0402_16V7K
0_0402_5% G
.1U_0402_16V7K
C237
C252
1 2N7002H_SOT23-3 S 1 @
3
@
@
A 2 2 A

Compal Secret Data
PCH (7/9) PWR
Custom 1.0
LA-9631P
5 4 3 2 1
5 4 3 2 1
Have internal VRM

+3VS +V1.05S_VCCP R268 @
0_0603_5%
2 1 +VCCACLK
Near T38
+3V_PCH
Near T16 U4J POWER +V1.05S_VCCP
1 1
10U_0603_6.3V6M
C231
1U_0402_6.3V6K
C232
1 AD49 N26
@ VCCACLK VCCIO[29] +3VALW +3V_PCH
2 2 1 PJ1
C234 P26
.1U_0402_16V7K T16 VCCIO[30] C233 2 1
D 2 VCCDSW3_3 3mA P28 1U_0402_6.3V6K D
VCCIO[31] 2 JUMP_43X118
2 1 +PCH_VCCDSW V12 T27
DCPSUSBYP VCCIO[32]
C235 @ T29
.1U_0402_16V7K T38 VCCIO[33] +3V_PCH
+3VS VCC3_3[5]
On-Die PLL Voltage Regulator
H：On-Die PLL voltage regulator enable T23
+VCCAPLL_CPY_PCH BH23 119mA VCCSUS3_3[7]
VCCAPLLDMI2 +3V_PCH
.1U_0402_16V7K
C236
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 T24 1
AL29 VCCSUS3_3[8]
,VCCAPLLSATA +V1.05S_VCCP VCCIO[14] V23
VCCSUS3_3[9]
USB
2 1
+VCCSUS1 AL24 V24
DCPSUS[3] VCCSUS3_3[10] C238
1
P24 .1U_0402_16V7K
@ C239 VCCSUS3_3[6] 2 +V1.05S_VCCP
1U_0402_6.3V6K AA19
2 VCCASW[1] T26
+V1.05S_VCCP AA21 VCCIO[34]
Near AA19 VCCASW[2]
1010mA
AA24 M26 +PCH_V5REF_SUS
VCCASW[3] 1mA V5REF_SUS
1 1
22U_0805_6.3V6M
C241
22U_0805_6.3V6M
C242
AA26
Clock and Miscellaneous

VCCASW[4] AN23 +VCCA_USBSUS
AA27 DCPSUS[4]
2 2 VCCASW[5] AN24
VCCSUS3_3[1] +3V_PCH
AA29
VCCASW[6]
AA31
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN +3V_PCH
C VCCASW[8] 1mA V5REF C
1 1 1
1U_0402_6.3V6K
C244
1U_0402_6.3V6K
C245
1U_0402_6.3V6K
C246
AC27
VCCASW[9] N20
VCCSUS3_3[2] 1
+V1.05S_VCCP AC29
PCI/GPIO/LPC
2 2 2 VCCASW[10] N22 C247
AC31 VCCSUS3_3[3] 1U_0402_6.3V6K
VCCASW[11] P20 2 +3VS +5VALW +3V_PCH
AD29 VCCSUS3_3[4]
VCCASW[12] P22
VCCSUS3_3[5]
2
AD31 1
VCCASW[13] C249 R275 D1
W21 AA16 .1U_0402_16V7K 10_0402_5% CH751H-40PT_SOD323-2
VCCASW[14] VCC3_3[1]
L6 W23 W16 2 +3VS
1
1 2 +1.05VS_VCCA_A_DPL VCCASW[15] VCC3_3[8] +PCH_V5REF_SUS
10UH_LB2012T100MR_20% W24 T34 1
VCCASW[16] VCC3_3[4]
1 1
1U_0402_6.3V6K
C251
22U_0805_6.3V6M
C187
1U_0402_6.3V6K
C253
1 1 1 @ W26 C240
+ C250 VCCASW[17] C254 0.1U_0603_25V7K
220U_6.3V_M W29 +3VS .1U_0402_16V7K 2
VCCASW[18] 2
2 2 2 2 W31 AJ2
VCCASW[19] VCC3_3[2] +V1.05S_VCCP
1
W33
VCCASW[20] AF13
@ VCCIO[5] C255 +5VS +3VS
2 .1U_0402_16V7K 1
+VCCRTCEXT N16
+1.5VS DCPRTC AH13 C257
1 VCCIO[12]
2
C258 1U_0402_6.3V6K
.1U_0402_16V7K Y49 AH14 2 R279 D2
VCCVRM[4] VCCIO[13] CH751H-40PT_SOD323-2
10_0402_5%
2
B AF14 B
Near AF17
1
+1.05VS_VCCA_A_DPL BD47 VCCIO[6] +PCH_V5REF_RUN
+V1.05S_VCCP VCCADPLLA 80mA
SATA
AK1 +VCCSATAPLL 1
+1.05VS_VCCA_A_DPL BF47 VCCAPLLSATA
1 VCCADPLLB 80mA
+1.5VS On-Die PLL Voltage Regulator
C256 H：On-Die PLL voltage regulator enable C248
1U_0402_6.3V6K AF11 1U_0603_10V6K
AF17 VCCVRM[1] +V1.05S_VCCP 2
2 VCCIO[7] VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
AF33
Near AF33 AF34 VCCDIFFCLKN[1]
55mA AC16 ,VCCAPLLSATA
AG34 VCCDIFFCLKN[2] VCCIO[2]
+V1.05S_VCCP VCCDIFFCLKN[3]
1 AC17 1
VCCIO[3] C261
C259 AG33 AD17 1U_0402_6.3V6K
1U_0402_6.3V6K VCCSSC 95mA VCCIO[4]
2 2
+VCCSST V16 +V1.05S_VCCP
DCPSST
Near AG33 C263
1
+V1.05S_VCCP
1 .1U_0402_16V7K +1.05VM_VCCSUS T17 T21
V19 DCPSUS[1] VCCASW[22]
C262 2 DCPSUS[2]
MISC
1U_0402_6.3V6K +V1.05S_VCCP V21

2 VCCASW[23]
CPU
Near BJ8 BJ8

V_PROC_IO 1mA T19
@ @ VCCASW[21]
1 1
+RTCVCC +3V_PCH
C265
C266
4.7U_0603_6.3V6K
.1U_0402_16V7K
A22 P32
10mA VCCSUSHDA
RTC
2 2 VCCRTC
HDA
C268
C269
1U_0402_6.3V6K
.1U_0402_16V7K
1 1 1
PANTHER-POINT_FCBGA989 C271
A .1U_0402_16V7K A
2 2 HM76@ 2
@
2011/06/15 2012/07/11 Title
Issued Date Deciphered Date PCH (8/9) PWR
1bios.ru
Custom 1.0
LA-9631P
5 4 3 2 1
5 4 3 2 1
U4I
AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
B11 VSS[162] VSS[262] K46
D U4H B15 VSS[163] VSS[263] K7 D
H5 B19 VSS[164] VSS[264] L18
VSS[0] B23 VSS[165] VSS[265] L2
AA17 AK38 B27 VSS[166] VSS[266] L20
AA2 VSS[1] VSS[80] AK4 B31 VSS[167] VSS[267] L26
AB11 VSS[5] VSS[84] AL16 F45 VSS[171] VSS[271] M12
AB14 VSS[6] VSS[85] AL17 BB12 VSS[172] VSS[272] P16
AB39 VSS[7] VSS[86] AL19 BB16 VSS[173] VSS[273] M18
AC19 VSS[12] VSS[91] AL27 BB30 VSS[178] VSS[278] M34
AC33 VSS[16] VSS[95] AL48 BC14 VSS[182] VSS[282] M46
AC34 VSS[17] VSS[96] AM11 BC18 VSS[183] VSS[283] M8
AC48 VSS[18] VSS[97] AM14 BC2 VSS[184] VSS[284] N18
AD10 VSS[19] VSS[98] AM36 BC22 VSS[185] VSS[285] P30
AD11 VSS[20] VSS[99] AM39 BC26 VSS[186] VSS[286] N47
AD19 VSS[23] VSS[102] AM46 BC36 VSS[189] VSS[289] T33
AD26 VSS[25] VSS[104] AN2 BC42 VSS[191] VSS[291] P43
AD27 VSS[26] VSS[105] AN29 BC48 VSS[192] VSS[292] P47
AD33 VSS[27] VSS[106] AN3 BD46 VSS[193] VSS[293] P7
AD34 VSS[28] VSS[107] AN31 BD5 VSS[194] VSS[294] R2
C AD36 VSS[29] VSS[108] AP12 BE22 VSS[195] VSS[295] R48 C
AD37 VSS[30] VSS[109] AP19 BE26 VSS[196] VSS[296] T12
AD38 VSS[31] VSS[110] AP28 BE40 VSS[197] VSS[297] T31
AD39 VSS[32] VSS[111] AP30 BF10 VSS[198] VSS[298] T37
AD40 VSS[34] VSS[113] AP38 BF16 VSS[200] VSS[300] W34
AD46 VSS[38] VSS[117] AP8 BF26 VSS[204] VSS[304] V11
AD8 VSS[39] VSS[118] AR2 BF28 VSS[205] VSS[305] V17
AE2 VSS[40] VSS[119] AR48 BD3 VSS[206] VSS[306] V26
AE3 VSS[41] VSS[120] AT11 BF30 VSS[207] VSS[307] V27
AF10 VSS[42] VSS[121] AT13 BF38 VSS[208] VSS[308] V29
AF12 VSS[43] VSS[122] AT18 BF40 VSS[209] VSS[309] V31
AD14 VSS[44] VSS[123] AT22 BF8 VSS[210] VSS[310] V36
AD16 VSS[45] VSS[124] AT26 BG17 VSS[211] VSS[311] V39
AF16 VSS[46] VSS[125] AT28 BG21 VSS[212] VSS[312] V43
AF19 VSS[47] VSS[126] AT30 BG33 VSS[213] VSS[313] V7
AF24 VSS[48] VSS[127] AT32 BG44 VSS[214] VSS[314] W17
AF26 VSS[49] VSS[128] AT34 BG8 VSS[215] VSS[315] W19
AF27 VSS[50] VSS[129] AT39 BH11 VSS[216] VSS[316] W2
AF38 VSS[53] VSS[132] AT7 BH19 VSS[219] VSS[319] Y12
AF4 VSS[54] VSS[133] AU24 H10 VSS[220] VSS[320] Y38
AF42 VSS[55] VSS[134] AU30 BH27 VSS[221] VSS[321] Y4
AF46 VSS[56] VSS[135] AV16 BH31 VSS[222] VSS[322] Y42
AF8 VSS[59] VSS[138] AV30 BH39 VSS[225] VSS[325] BG29
AG19 VSS[60] VSS[139] AV38 BH43 VSS[226] VSS[328] N24
B AG2 VSS[61] VSS[140] AV4 BH7 VSS[227] VSS[329] AJ3 B
AG31 VSS[62] VSS[141] AV43 D3 VSS[228] VSS[330] AD47
AG48 VSS[63] VSS[142] AV8 D12 VSS[229] VSS[331] B43
AH11 VSS[64] VSS[143] AW14 D16 VSS[230] VSS[333] BE10
AH3 VSS[65] VSS[144] AW18 D18 VSS[231] VSS[334] BG41
AH36 VSS[66] VSS[145] AW2 D22 VSS[232] VSS[335] G14
AH39 VSS[67] VSS[146] AW22 D24 VSS[233] VSS[337] H16
AH40 VSS[68] VSS[147] AW26 D26 VSS[234] VSS[338] T36
AH7 VSS[71] VSS[150] AW34 D34 VSS[237] VSS[343] C22
AJ19 VSS[72] VSS[151] AW36 D38 VSS[238] VSS[344] AP13
AJ21 VSS[73] VSS[152] AW40 D42 VSS[239] VSS[345] M14
AJ24 VSS[74] VSS[153] AW48 D8 VSS[240] VSS[346] AP3
AJ33 VSS[75] VSS[154] AV11 E18 VSS[241] VSS[347] AP1
AJ34 VSS[76] VSS[155] AY12 E26 VSS[242] VSS[348] BE16
AK12 VSS[77] VSS[156] AY22 G18 VSS[243] VSS[349] BC16
AK3 VSS[78] VSS[157] AY28 G20 VSS[244] VSS[350] BG28
VSS[79] VSS[158] G26 VSS[245] VSS[351] BJ28
PANTHER-POINT_FCBGA989 G28 VSS[246] VSS[352]
G36 VSS[247]
G48 VSS[248]
HM76@ VSS[249]
H12
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
A A
PANTHER-POINT_FCBGA989
1bios.ru
HM76@

PCH (9/9) VSS
Custom 1.0
LA-9631P
5 4 3 2 1
A B C D E
PCIE_CTX_GRX_P[7..0] UV1A PCIE_CRX_GTX_P[7..0]

<5> PCIE_CTX_GRX_P[7..0] PCIE_CRX_GTX_P[7..0] <5>
<5> PCIE_CTX_GRX_N[7..0]
PCIE_CTX_GRX_N[7..0] PART 1 0F 9 PCIE_CRX_GTX_N[7..0]
PCIE_CRX_GTX_N[7..0] <5> LVDS Interface
UV1D
1 1
PCIE_CTX_GRX_P0 AA38 Y33 PCIE_CRX_C_GTX_P0 0.22U_0402_10V6K 1 2 CV1 PX@ PCIE_CRX_GTX_P0 PART 7 0F 9
Y37 PCIE_RX0P PCIE_TX0P Y32
PCIE_CTX_GRX_N0 PCIE_CRX_C_GTX_N0 0.22U_0402_10V6K 1 2 CV2 PX@ PCIE_CRX_GTX_N0
PCIE_RX0N PCIE_TX0N
AK27
RSVD/VARY_BL AJ27
PCIE_CTX_GRX_P1 Y35 W33 PCIE_CRX_C_GTX_P1 0.22U_0402_10V6K 1 2 CV3 PX@ PCIE_CRX_GTX_P1 RSVD/DIGON
W36 PCIE_RX1P PCIE_TX1P W32 PCIE_CRX_C_GTX_N1 LVDS CONTROL
PCIE_CTX_GRX_N1 0.22U_0402_10V6K 1 2 CV4 PX@ PCIE_CRX_GTX_N1
PCIE_RX1N PCIE_TX1N
PCIE_CTX_GRX_P2 W38 U33 PCIE_CRX_C_GTX_P2 0.22U_0402_10V6K 1 2 CV5 PX@ PCIE_CRX_GTX_P2 AK35

V37 PCIE_RX2P PCIE_TX2P U32 PCIE_CRX_C_GTX_N2 TXCBP_DPB3P
PCIE_CTX_GRX_N2 0.22U_0402_10V6K 1 2 CV6 PX@ PCIE_CRX_GTX_N2 AL36
PCIE_RX2N PCIE_TX2N TXCBM_DPB3N
AJ38
PCIE_CTX_GRX_P3 V35 U30 PCIE_CRX_C_GTX_P3 0.22U_0402_10V6K 1 2 CV7 PX@ PCIE_CRX_GTX_P3 TX3P_DPB2P AK37
U36 PCIE_RX3P PCIE_TX3P U29 PCIE_CRX_C_GTX_N3 TX3M_DPB2N
PCIE_CTX_GRX_N3 0.22U_0402_10V6K 1 2 CV8 PX@ PCIE_CRX_GTX_N3
PCIE_RX3N PCIE_TX3N
AH35
TX4P_DPB1P AJ36
PCIE_CTX_GRX_P4 U38 T33 PCIE_CRX_C_GTX_P4 0.22U_0402_10V6K 1 2 CV9 PX@ PCIE_CRX_GTX_P4 TX4M_DPB1N
T37 PCIE_RX4P PCIE_TX4P T32
PCIE_CTX_GRX_N4 PCIE_CRX_C_GTX_N4 0.22U_0402_10V6K 1 2 CV10 PX@ PCIE_CRX_GTX_N4 AG38
PCIE_RX4N PCIE_TX4N TX5P_DPB0P AH37
TX5M_DPB0N
PCIE_CTX_GRX_P5 T35 T30 PCIE_CRX_C_GTX_P5 0.22U_0402_10V6K 1 2 CV11 PX@ PCIE_CRX_GTX_P5 AF35
R36 PCIE_RX5P PCIE_TX5P T29 NC#AF35
PCIE_CTX_GRX_N5 PCIE_CRX_C_GTX_N5 0.22U_0402_10V6K 1 2 CV12 PX@ PCIE_CRX_GTX_N5 AG36
PCIE_RX5N PCIE_TX5N NC#AG36
LVTMDP
PCIE_CTX_GRX_P6 R38 P33 PCIE_CRX_C_GTX_P6 0.22U_0402_10V6K 1 2 CV13 PX@ PCIE_CRX_GTX_P6
P37 PCIE_RX6P PCIE_TX6P P32
PCIE_CTX_GRX_N6 PCIE_CRX_C_GTX_N6 0.22U_0402_10V6K 1 2 CV14 PX@ PCIE_CRX_GTX_N6
PCIE_RX6N PCIE_TX6N
AP34
TXCAP_DPA3P AR34
PCIE_CTX_GRX_P7 P35 P30 PCIE_CRX_C_GTX_P7 0.22U_0402_10V6K 1 2 CV15 PX@ PCIE_CRX_GTX_P7 TXCAM_DPA3N
N36 PCIE_RX7P PCIE_TX7P P29
PCIE_CTX_GRX_N7 PCIE_CRX_C_GTX_N7 0.22U_0402_10V6K 1 2 CV16 PX@ PCIE_CRX_GTX_N7 AW37
PCIE_RX7N PCIE_TX7N TX0P_DPA2P AU35
2 TX0M_DPA2N 2
N38 N33 AR37
M37 NC NC N32 TX1P_DPA1P AU39
NC NC TX1M_DPA1N
PCI EXPRESS INTERFACE AP35
M35 N30 TX2P_DPA0P AR35
L36 NC NC N29 TX2M_DPA0N
NC NC
AN36
NC AP37
L38 L33 NC
K37 NC NC L32
NC NC
K35 L30 Mars@ MARS XT M2 FCBGA 962

J36 NC NC L29
NC NC
J38 K33
H37 NC NC K32
NC NC
H35 J33
G36 NC NC J32
NC NC
G38 K30
F37 NC NC K29
NC NC
F35 H33
E37 NC NC H32
NC NC
3 3
CLOCK +3VGS
CLK_PCIE_VGA AB35
<15> CLK_PCIE_VGA AA36 PCIE_REFCLKP
CLK_PCIE_VGA#
<15> CLK_PCIE_VGA# PCIE_REFCLKN
5
2
P
CALIBRATION <18> DGPU_HOLD_RST# B 4 GPU_RST#
Y30 RV1 1 PX@ 2 1.69K_0402_1% 1 Y
PCIE_CALR_TX +0.95VGS <18,36,37,42> PLT_RST# A
G
PX@
2 PX@ 1 AH16 Y29 RV3 1 PX@ 2 1K_0402_1% UV2
+0.95VGS
3
TEST_PG PCIE_CALR_RX MC74VHC1G08DFT2G SC70 5P
RV2 1K_0402_5%
GPU_RST# AA30
PERSTB
1
PX@ Mars@ MARS XT M2 FCBGA 962

RV4 SA000061J60
100K_0402_5% S IC 216-0842000 A0 MARS XT M2 BGA C38!
2
UV1 Sun@
SUN PRO M2 C38

SA00006BA20
S IC 216-0841000 A0 SUN PRO M2 BGA C38!
4 4

Compal Secret Data
ATI_MarsXTX_M2_PCIE/LVDS
Custom 1.0
LA-9631P
A B C D E
A B C D E
UV1B CONFIGURATION STRAPS RECOMMENDED SETTINGS

PART 2 0F 9 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
MUTI GFX GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET X = DESIGN DEPENDANT
T1 GENLK_CLK AD29 GENLK_CLK AU24 NA = NOT APPLICABLE
AC29 NC AV23
T2 GENLK_VSYNC GENLK_VSYNC NC
AT25 STRAPS STRAPS MLPS DESCRIPTION OF DEFAULT SETTINGS Default Setting
AJ21 NC AR24
SWAPLOCKA DPA NC
AK21 SWAPLOCKB Transmitter Power Savings Enable
AU26 TX_PWRS_ENB PS_1[4] 0:50% Tx output swing X
NC
AV25 1:Full Tx output swing
NC
+3VGS
AR8 AT27 PCIE Transmitter De-emphasis Enable
NC NC
AU8 NC AR26 TX_DEEMPH_EN PS_1[5] 0:Tx de-emphasis disabled X
AP8 NC 2 1 100K_0402_5%
DBG_CNTL0 GPU_GPIO5 RV5 @ 1:Tx de-emphasis enabled
AW8 NC AR30
1 NC 1
AR3 AT29 PCIE Gen3 Enable
NC NC
AR1 THM_ALERT# RV6 2 @ 1 2.2K_0402_5% BIF_GEN3_EN_A PS_1[1] (NOTE:RESERVED for Thames/Seymour and should 1
NC
AU1 DBG_DATA0 AV31 be strapped to 0)
AU3 NC AU30
DBG_DATA1 DPB NC
AW3 DBG_DATA2 0:GEN3 not support at power-on
AP6 AR32 1:GEN3 supported at power-on
DBG_DATA3 NC
AW5 AT31
DBG_DATA4 NC
AU5 DBG_DATA5 VGA control
AR6 AT33 BIF_VGA DIS PS_2[4] 0:VGA controller capacity enabled 0
DBG_DATA6 NC
AW6 DBG_DATA7 AU32 1:VGA controller capacity disabled (for multi-GPU)
NC
AU6
DBG_DATA8
AT7 AU14 Serial ROM type or Memory Aperture Size Select
DBG_DATA9 NC
AV7 DBG_DATA10 AV13 ROMIDCFG[2:0] PS_0[3..1] If PS_2[3]=0, defines memory aperture size XXX
AN7 NC
DBG_DATA11 If PS_2[3]=1, defines ROM type
AV9 DBG_DATA12 AT15 100 - 512Kbit M25P05A (ST)
NC
AT9 AR14 101 - 1Mbit M25P10A (ST)
DBG_DATA13 NC
AR10 101 - 2Mbit M25P20 (ST)
DBG_DATA14 DPC
AW10 DBG_DATA15 AU16 101 - 4Mbit M25P40 (ST)
AU10 NC AV15
DBG_DATA16 NC 101 - 8Mbit M25P80 (ST)
AP10 DBG_DATA17 100 - 512Kbit Pm25LV010 (Chingis)
AV11 AT17 101 - 1Mbit Pm25LV010 (Chingis)
DBG_DATA18 NC
AT11 AR16
DBG_DATA19 NC
AR12 DBG_DATA20
AW12 AU20 Enable external BIOS ROM device
DBG_DATA21 NC
AU12 DBG_DATA22 AT19 BIOS_ROM_EN PS_2[3] 0:Disabled X
NC
AP12 1:Enabled
DBG_DATA23
AT21
NC
AR20 00 - No audio function
NC
AUD[1] NA 01 - Audio for DP only XX
VGA_SMB_CK2 AJ23 DPD AU22 10 - Audio for DP and HDMI if dongle is detected
SMBCLK SMBus NC
VGA_SMB_DA2 AH23 AV21 AUD[0] NA 11 - Audio for both DP and HDMI
SMBDATA NC
AT23 HDMI must only be enabled on systems that are
NC AR22 legally entitled. It isthe responsibility of the system
NC
AK26 SCL designer to ensure that the system is entitled to
AJ26 I2C support this feature.
SDA
2 AD39 VGA_R 2
R AD37
GENERAL PURPOSE I/O T24 CEC_DIS PS_0[4] Reserved for future ASIC 0
GPU_GPIO0 AH20 AVSSN
<53> GPU_GPIO0
AH18
GPIO_0
AE36 VGA_G
AVDD MarsCRB Design NOTE:ALLOW FOR PULLUP PADS FOR THE
GPIO_1 G
@ AN16
GPIO_2 AVSSN
AD35 T25 120ohm 1 1 RESERVED STRAPS BUT DO NOT INSTALL
DV1 RESISTOR
RB751V_SOD323
B
AF37 VGA_B 0.1u 1 1 IF THESE GPIOS ARE USEED, THEY MUST KEEP
1 2 GPU_GPIO5 AH17 AE38 T26 LOW AND NOT CONFLICT DURING RESET
<16,42,46,48> ACIN
GPU_VID5 AJ17
GPIO_5_AC_BATT
GPIO_6_TACH
AVSSN 1u 1 1
<53> GPU_VID5 AK17 DAC1 AC36
GPIO_7_BLON HSYNC 10u 1 1 RESERVED PS_1[3] Reserved 0
AJ13 HSYNC AC38 VSYNC T4
GPIO_8_ROMSO VSYNC
AH15 T6 RESERVED PS_1[2] Reserved 0
GPIO_9_ROMSI
AJ16 GPIO_10_ROMSCK
AK16 AB34 RV11 1 PX@ 2 499_0402_1% +AVDD +1.8VGS RESERVED NA Reserved 0
GPIO_11 RSET
AL16
GPIO_12
AM16 GPIO_13 AD34 +AVDD (1.8V@70mA AVDD) 1 @ 2 RESERVED NA Reserved (for Thames/Whistler/Seymour only) 0
AM14 AVDD AE34 LV1
GPIO_14_HPD2 AVSSQ
GPU_VID1 AM13 0_0402_5%
CV17
CV18
CV19
GPIO_15_PWRCNTL_0
.1U_0402_16V7K
1U_0402_6.3V6K
10U_0603_6.3V6M
<53> GPU_VID1 (1.8V@117mA VDD1DI)
AK14 AC33 +VDD1DI 1 1 1 STRAPS TO INDICATE THE NUMBER OF AUDIO
GPIO_16 VDD1DI
THM_ALERT# AG30 AC34 AUD_PORT_CONN_PINSTRAP[2] PS_3[5] CAPABLE DISPLAY OUTPUTS XXX
GPIO_17_THERMAL_INT VSS1DI
AN14 GPIO_18_HPD3 111 = 0 usable endpoints
@ RV12 1 2 10K_0402_5% AM17
GPIO_19_CTF AUD_PORT_CONN_PINSTRAP[1] PS_3[4] 110 = 1 usable endpoints
2 2 2
@
GPU_VID2 AL13 GPIO_20_PWRCNTL_1 V13 101 = 2 usable endpoints
<53> GPU_VID2 NC
AJ14 U13 AUD_PORT_CONN_PINSTRAP[0] PS_0[5] 100 = 3 usable endpoints
GPIO_21 NC
AK13 AF33 011 = 4 usable endpoints
GPIO_22_ROMCSB NC
CLK_REQ_VGA# AN13 CLKREQB AF32 010 = 5 usable endpoints
<15> CLK_REQ_VGA# NC AA29
NC 001 = 6 usable endpoints
AG21 +VDD1DI +1.8VGS 000 = all endpoints are usable
NC
GPU_VID3 AG32 AC32
<53> GPU_VID3 GPIO_29 NC
GPU_VID4 AG33 1 @ 2
<53> GPU_VID4 GPIO_30
AC31 LV2
AJ19 NC_SVI2 AD30 0_0402_5%
CV20
CV21
CV22
GENERICA
.1U_0402_16V7K
1U_0402_6.3V6K
10U_0603_6.3V6M
NC_SVI2
AK19 GENERICB AD32 1 1 1
NC_SVI2
AJ20
GENERICC
AK20
AJ24
GENERICD VDD1DI MarsCRB Design
GENERICE_HPD4 2 2 2
120ohm 1 1
@
@
AH26
GENERICF_HPD5
AH24 GENERICG_HPD6
3
0.1u 1 1 3
PS_0
AM34 PS_0
1u 1 1 MLPS Strap
AC30 10u 1 1
CEC_1
0.60 V level, Please Bits[5:4] Bits[3:1] Capacitor R_pu R_pd
AK24 AD31 PS_1
VREFG Divider ans HPD1 MLPS PS_1
+1.8VGS +VREFG_GPU cap close to ASIC PS_0[5:1] 11 000 NC NC 4.75K
PX@
2 RV13 1 499_0402_1% +VREFG_GPU AH13 DBG_VREFG PS_2 AG31 PS_2
PX@ PS_1[5:1] 01 001 82nF 8.45K 2K
2 RV14 1 249_0402_1%
BACO
2 1 .1U_0402_16V7K PX_EN AL21 AD33 PS_3 PS_2[5:1] 11 000 NC NC 4.75K
PX_EN PS_3
CV23
PX@ Mapping to VRAM type please refer to page 4
PS_3[5:1] 11 XXX NC X X
DEBUG DDC/AUX +1.8VGS
1 @ 2 TESTEN AM26 VGA_CLK
+3VGS DDC1CLK
RV18 5.11K_0402_5% AN26 VGA_DAT T27
DDC1DATA
1 PX@ 2 AD28 T28
TESTEN
RV19 1K_0402_5% AM27
AUX1P
1
AL27
AUX1N
GPIO_28_FDO MLPS
JTAG_TRSTB AM23 JTAG_TRSTB AM19 X76@ RV20 @ RV21 PX@RV22
PX@ RV22 @ RV23
DDC2CLK
H Disable JTAG_TDI AN23 AL19 8.45K_0402_1% 8.45K_0402_1% 8.45K_0402_1% 8.45K_0402_1%
JTAG_TDI DDC2DATA +3VGS
JTAG_TCK AK23
JTAG_TCK
2
L Enable JTAG_TMS AL24 JTAG_TMS AN20 PS_0
AM24 AUX2P AM20
JTAG_TDO JTAG_TDO PS_1
AUX2N
PS_2
AL30 +3VGS PS_3
NC
1
AM30 @ @
NC
1
RV24 RV25 @ 1@ 1 PX@ 1 @ 1
THERMAL AL29 10K_0402_5% 10K_0402_5% CV26 CV27 CV29 CV28
NC
0_0402_5% 1 RV16 2 @ THERM_D+ AF29 DPLUS AM29 X76@ RV27 PX@RV28
PX@ RV28 PX@RV29
PX@ RV29 PX@RV30
PX@ RV30
<39> REMOTE1+ NC
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.082U_0402_16V7K
2
0_0402_5% 1 RV17 2 @ THERM_D- AG29 4.75K_0402_1% 4.75K_0402_1% 2K_0402_1% 4.75K_0402_1%

<39> REMOTE1- DMINUS
2
1 @ 2 GPIO_28_FDO AN21 2 2 2 2
+3VGS NC
2
4 RV26 10K_0402_5% AM21 VGA_SMB_CK2 1 6 4
1 PX@ 2 AK32 NC EC_SMB_CK2 <15,39,42>
GPIO_28_FDO
5
RV31 10K_0402_5% AK30 QV3A @

NC
1bios.ru
AL31 AK29 2N7002DW-T/R7_SOT363-6
+1.8VGS +TSVDD TS_A NC
(1.8V@13mA TSVDD) VGA_SMB_DA2 4 3
DDCVGACLK
AJ30
EC_SMB_DA2 <15,39,42> Place CLOSE VGA CHIP
1 @ 2 +TSVDD AJ32 AJ31 QV3B @
TSVDD DDCVGADATA
LV3 AJ33 TSVSS 2N7002DW-T/R7_SOT363-6
.1U_0402_16V7K
1U_0402_6.3V6K
10U_0603_6.3V6M
0_0402_5%
CV30
CV31
CV32
1 1 1
Mars@ MARS XT M2 FCBGA 962
TSVDD MarsCRB Design Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 2
120ohm 1 1 Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
PX@
PX@
0.1u 1 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_MarsXTX_M2_Main_MSIC
1u 1 1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
10u 1 1
LA-9631P
A B C D E
A B C D E
UV1C
PART 9 0F 9
+1.8VGS @ +MPV18
LV4 (MPLL_PVDD:1.8V@130mA )
MPLL_PVDD MarsCRB Design 2 1 AV33 XTALIN RV32 1 2 1M_0402_5%
XTALIN
220ohm 1 1
10U_0603_6.3V6M
1U_0402_6.3V6K
.1U_0402_16V7K
CV33
CV34
CV35
0_0603_5%
0.1u 1 1 1 1 1 YV1
4 3 XTALOUT
1u 1 1 NC
OSC
1
10u 1 1 2 2 2
XTALIN 1
OSC NC
2 1
PX@
PX@
PX@
AU34 XTALOUT 2 2
XTALOUT
27MHZ 10PF +-20PPM X3G027000DA1H
CV36 CV37
10P_0402_50V8J 10P_0402_50V8J
+MPV18 H7 1 1
MPLL_PVDD
H8
MPLL_PVDD
+SPV18 AW34
SPLL_PVDD MarsCRB Design +1.8VGS (SPLL_PVDD:1.8V@75mA ) XO_IN
120ohm 1 1 1 @ 2 +SPV18 AM10 SPLL_PVDD
PLLS/XTAL
LV5
0.1u 1 1
CV38
CV39
CV40
0_0402_5%
10U_0603_6.3V6M
1U_0402_6.3V6K
.1U_0402_16V7K
1u 1 1 1 1 1
+SPLL_VDDC AN9 AW35
SPLL_VDDC XO_IN2
10u 1 1
2 2 2
PX@
PX@
PX@
AN10 SPLL_PVSS
+0.95VGS AK10
SPLL_VDDC MarsCRB Design +SPLL_VDDC
(SPLL_VDDC:0.95V@100mA ) AF30
CLKTESTA
AL10
NC_XTAL_PVDD CLKTESTB
120ohm 1 1 1 @ 2 AF31
NC_XTAL_PVSS
1
LV6 @ @
0.1u 1 1
CV43
CV44
CV45
10U_0603_6.3V6M
0_0402_5% CV41 CV42
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K .1U_0402_16V7K
1u 1 1 1 1 1
2
10u 1 1
1
2 2 2
PX@
PX@
PX@
@ @
RV33 RV34
51.1_0402_1% 51.1_0402_1%
2
2 2
+1.5V to +1.5VGS
+3VS to +3VGS
+1.5V +1.5VGS
+3VS +3VGS
300mil(7.2A) 3 1 4.7U_0603_6.3V6K 1U_0603_10V6K

PX@ 1
1
CV48 QV8 1 1
4.7U_0603_6.3V6K LP2301ALT1G_SOT23-3 CV46 CV47 @
AO4430: Rdson: 5.5mohm @ VGS=10V PX@ RV36
2
2 PX@ @ 470_0603_5%
UV4 2 2
2
AO4304L_SO8 +5VALW
8 1
300mil(7.2A)
1
7 2 D
6 3 2
2
5 1 PX@ 1@ G
CV49 CV50 RV39 @ RV37 PX@ RV38 PX@ S @
3
4.7U_0603_6.3V6K .1U_0402_16V7K 470_0603_5% QV7
4
PX@ 20K_0402_5% 20K_0402_5% 2N7002H_SOT23-3

2 2
1
1 PX@
1
D PX@ DGPU_PWR_EN#
B+ DGPU_PWR_EN 2 QV6 CV52
2N7002H_SOT23-3 .1U_0402_16V7K
G
RV41 240K_0402_5% 2
S
3
2 1
1
PX@ D
1 @ QV1 2 DGPU_PWR_EN#
2
PX@ PX@ 2N7002H_SOT23-3 G

3 QV2 RV42 @ CV53 S 3
3
2N7002H_SOT23-3 0_0402_5% 0.1U_0402_25V6

1
D 2
DGPU_PWR_EN# 2
1
G
S
3
+1.8VS to +1.8VGS
+1.8VS +1.8VGS
+3VALW PX@ 1
CV199 QV4
LP2301ALT1G_SOT23-3 1
1
1
4.7U_0603_6.3V6K @ @ @ R290
2 3 1
S
D
PX@ CV200 CV201
RV35 10U_0603_6.3V6M 1U_0402_6.3V6K 470_0603_5%
2
100K_0402_5% +5VALW
G
PX@ 2
2
2
DGPU_PWR_EN#
PX@ PX@
1
1 RV45 2 1 RV46 2 @ D @
DGPU_PWR_EN# 1 RV92 2 2 QV11
330K_0402_5% 62K_0402_5% 0_0402_5% G
S
3
1
D PX@ PX@ 2N7002H_SOT23-3

1
DGPU_PWR_EN 2 QV9 D CV202

<18,42,51,53> DGPU_PWR_EN
G 2N7002H_SOT23-3 DGPU_PWR_EN 2 PX@ .1U_0402_16V7K
S G QV10
3
DVT S 2N7002H_SOT23-3
3
4 4

2011/06/15
Compal Secret Data
2012/07/11 Title
Issued Date Deciphered Date
ATI_MarsXTX_M2_BACO POWER
Custom 1.0
LA-9631P
A B C D E
A B C D E
UV1G
PART 6 0F 9 UV1F
AB39 A3 PART 8 0F 9
E39 GND GND A37 +0.95VGS
GND GND DP_VDDR DP_VDDC
(DP_VDDC:0.95V@280mA/link )
F34 AA16
F39 GND GND AA18 AP31
G33 GND GND AA2 DP_VDDC AP32
GND GND DP_VDDC
.1U_0402_16V7K
10U_0603_6.3V6M
1U_0402_6.3V6K
G34 AA21 AN33
CV54
GND GND DP_VDDC
CV55
CV56
H31 AA23 AP33
H34 GND GND AA26 AN24 DP_VDDC AL33
GND GND NC DP_VDDC 1 1 1
H39 AA28 AP24 AM33
J31 GND GND AA6 AP25 NC DP_VDDC AK33
PX@
PX@
PX@
1 J34 GND GND AB12 AP26 NC DP_VDDC AK34 1
K31 GND GND AB15 AU28 NC DP_VDDC AN31 2 2 2
K34 GND GND AB17
DP_VDDR MarsCRB Design AV29 NC DP_VDDC
GND GND NC
K39
L31 GND GND
AB20
AB22
0.1u 1 1
L34 GND
GND
GND
GND
AB24 1u 1 1 AP20
NC NC
AP13
DP_VDDC MarsCRB Design
M34 AB27 AP21 AT13
M39 GND GND AC11 10u 1 1 AP22 NC NC AP14 0.1u 1 1
N31 GND GND AC13 AP23 NC NC AP15
N34 GND
GND
GND
GND
AC16 AU18 NC
NC
NC 1u 1 1
P31 AC18 AV19
P34 GND GND AC2 +1.8VGS +DP_VDDR (DP_VDDR:1.8V@237mA/link )
NC DP GND 10u 1 1
P39 GND GND AC21 AN27
R34 GND GND AC23 1 2 AH34 DP_VSSR AP27
@ +DP_VDDR
T31 GND GND AC26 AJ34 DP_VDDR DP_VSSR AP28
RV43
GND GND DP_VDDR DP_VSSR
10U_0603_6.3V6M
1U_0402_6.3V6K
.1U_0402_16V7K
T34 AC28 0_0402_5% AF34 AW24
CV57
CV58
CV59
T39 AC6 AG34 AW26
U31 GND GND AD15 AM37 DP_VDDR DP_VSSR AN29
GND GND 1 1 1 DP_VDDR DP_VSSR
U34 AD17 AL38 AP29
V34 GND GND AD20 AM32 DP_VDDR DP_VSSR AP30
PX@
PX@
PX@
V39 AD22 AW30
W31 GND GND AD24 2 2 2 DP_VSSR AW32
W34 GND GND AD27 DP_VSSR AN17
Y34 GND GND AD9 DP_VSSR AP16
Y39 GND GND AE2 DP_VSSR AP17
GND GND AE6 DP_VSSR AW14
GND AF10 DP_VSSR AW16
GND AF16 DP_VSSR AN19
GND AF18 DP_VSSR AP18
GND AF21 DP_VSSR AP19
GND GND DP_VSSR
AG17 AW20
F15 GND AG2 CALIBRATION DP_VSSR AW22
2 F17 GND GND AG20 DP_VSSR AN34 2
F19 GND GND DP_VSSR AP39
F21 GND AG6 AW28 DP_VSSR AR39
F23 GND GND AG9 NC DP_VSSR AU37
F25 GND GND AH21 DP_VSSR AF39
F27 GND GND AJ10 DP_VSSR AH39
F29 GND GND AJ11 AW18 DP_VSSR AK39
F31 GND GND AJ2 NC DP_VSSR AL34
F33 GND GND AJ28 DP_VSSR AV27
F7 GND GND AJ6 DP_VSSR AR28
F9 GND GND AK11 DP_VSSR
RV44 2 PX@ 1 150_0402_1% AM39 AV17
G2 GND GND AK31 DP_CALR DP_VSSR AR18
G6 GND GND AK7 DP_VSSR AN38
H9 GND GND AL11 DP_VSSR AM35
J2 GND GND AL14 DP_VSSR AN32
J27 GND GND AL17 DP_VSSR
J6 GND GND AL2
J8 GND GND AL20
K14 GND GND
K7 GND AL23
L11 GND AL26
L17 GND GND AL32 Mars@ MARS XT M2 FCBGA 962
L2 GND GND AL6
L22 GND GND AL8
L24 GND GND AM11
L6 GND GND AM31
M17 GND GND AM9
M22 GND GND AN11
M24 GND GND AN2
N16 GND GND AN30
N18 GND GND AN6
N2 GND GND AN8
3 N21 GND GND AP11 3
N23 GND GND AP7
N26 GND GND AP9
N6 GND GND AR5
R15 GND GND B11
R17 GND GND B13
R2 GND GND B15
R20 GND GND B17
R22 GND GND B19
R24 GND GND B21
R27 GND GND B23
R6 GND GND B25
T11 GND GND B27
T13 GND GND B29
T16 GND GND B31
T18 GND GND B33
T21 GND GND B7
T23 GND GND B9
T26 GND GND C1
U15 GND GND C39
U17 GND GND E35
U2 GND GND E5
U20 GND GND F11
U22 GND GND F13
U24 GND GND
U27 GND GND
U6 GND
V11 GND AG22
V16 GND NC
V18 GND
V21 GND
V23 GND
4 V26 GND 4
W2 GND
W6 GND
1bios.ru
Y15 GND
Y17 GND
Y20 GND
Y22 GND A39 MECH#1 TV12 PAD
Y24 GND VSS_MECH AW1 MECH#2 TV13 PAD
Y27 GND
GND
VSS_MECH
VSS_MECH
AW39 MECH#3 TV14 PAD
ATI_MarsXTX_M2_PWR_GND
Mars@ MARS XT M2 FCBGA 962 Size Document Number Rev
Custom 1.0
LA-9631P
A B C D E
A B C D E
(PCIE_VDDR:1.8V@100mA ) +PCIE_VDDR LV7

@ +1.8VGS
+1.5VGS UV1E
For GDDR5, MVDDQ = 1.5V PART 5 0F 9 +PCIE_VDDR 2 1
PCIE_VDDR MarsCRB Design
0.1u 0 2
(VDDR1:1.5V@3A,GDDR5:1125MHz ) 0_0603_5%
CV62
CV63
CV64
CV65
MEM I/O
10U_0603_6.3V6M
.1U_0402_16V7K
1U_0402_6.3V6K
0.01U_0402_16V7K
+1.5VGS AC7
VDDR1 NC
AA31 1 1 1 1 1u 2 3
AD11 AA32
AF7
VDDR1 NC AA33 10u 1 1
CV66
CV60
CV68
CV69
CV70
CV71
CV72
CV73
CV74
CV75
CV76
CV61
CV77
CV78
CV79
1 VDDR1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
NC
220U_B2_2.5VM_R35
PX@
1 1 1 1 1 1 1 1 1 1 1 1 1 1 AG10 VDDR1 AA34
NC 2 2 2 2
PX@
PX@
+
@
AJ7 W30
VDDR1 NC
@ AK8 Y31
VDDR1 NC
AL9 VDDR1 V28
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 NC_BIF_VDDC
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
G11 W29
Mars@
Mars@
Mars@
VDDR1 NC_BIF_VDDC +0.95VGS
G14 AB37
1 VDDR1 PCIE_PVDD PCIE_VDDC MarsCRB Design 1
PCIE
G17 (PCIE_VDDC:[email protected]_GEN2.0 )
VDDR1
G20
G23
VDDR1 PCIE_VDDC
G30
G31
+0.95VGS 1u 7 5
VDDR1 PCIE_VDDC
G26 H29 10u 2 1
CV80
CV81
CV82
CV83
CV84
CV85
VDDR1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
PCIE_VDDC
G29 VDDR1 H30 1 1 1 1 1 1
PCIE_VDDC
H10 J29
VDDR1 MarsCRB Design J7
VDDR1 PCIE_VDDC J30
VDDR1 PCIE_VDDC
0.01u 5 0 J9 VDDR1 PCIE_VDDC
L28
2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
K11 M28
VDDR1 PCIE_VDDC
0.1u 5 5 K13 VDDR1 PCIE_VDDC
N28
K8 R28
1u 0 5 L12
VDDR1
VDDR1
PCIE_VDDC T28
PCIE_VDDC
2.2u 5 0 L16 VDDR1 U28
L21 PCIE_VDDC +0.95VGS
VDDR1
10u 3 5 L23 VDDR1 (BIF_VDDC:[email protected])
L26 N27 +0.95VGS
220u 0 1 VDDR1 BACO BIF_VDDC
L7 T27
VDDR1 BIF_VDDC
10U_0603_6.3V6M
M11
CV86
CV87
CV88
VDDR1
1U_0402_6.3V6K
1U_0402_6.3V6K
N11 1 1 1
VDDR1
P7 VDDR1 AA15
CORE VDDC
R11 AA17
+1.8VGS +VDDC_CT VDDR1 VDDC
PX@
U11 AA20
VDDR1 VDDC 2 2 2
PX@
PX@
(VDD_CT:1.8V@13mA ) U7 AA22
VDD_CT MarsCRB Design 1 @ 2 Y11
VDDR1 VDDC AA24
VDDR1 VDDC
120ohm 1 1 LV8 Y7 VDDR1 VDDC
AA27
AB16
0_0402_5%
CV89
CV90
CV91
10U_0603_6.3V6M
1U_0402_6.3V6K
.1U_0402_16V7K
0.1u 1 1 VDDC AB18
1 1 1 VDDC
AB21
1u 1 3 VDDC AB23 +VGA_CORE
VDDC
10u 1 1 LEVEL AB26
2 2 2 VDDC
PX@
PX@
@
TRANSLATION AB28
AF26 VDDC AC17
+VDDC_CT VDD_CT VDDC
AF27 VDD_CT AC20
AG26 VDDC AC22
VDD_CT VDDC
AG27 AC24
VDDR3 MarsCRB Design VDD_CT VDDC
AC27
VDDC
120ohm 1 0 +3VGS +VDDR3
VDDC
AD18
AD21
2 (VDDR3:3.3V@25mA) I/O VDDC
2
0.1u 1 0 1 @ 2 +VDDR3 AF23
VDDR3 VDDC
AD23
LV9 AF24 VDDR3 AD26
1u 2 3 0_0402_5% AG23
VDDC
AF17
CV92
CV94
CV95
10U_0603_6.3V6M
VDDR3
1U_0402_6.3V6K
1U_0402_6.3V6K
AG24 VDDC AF20
10u 0 1 1 1 1 VDDR3 VDDC
AF22
VDDC AG16
DVP VDDC
AD12 VDDR4 AG18
2 2 2 VDDC
PX@
PX@
PX@
AF11
AF12
VDDR4
VDDR4 VDDC
AH22 VGA_CORE Cap in power side sheet
AF13 VDDR4 AH27
VDDC AH28
VDDC
M26
VDDC
AF15 N24
+1.8VGS +VDDR4 VDDR4 VDDC
@ AG11 R18
LV10 VDDR4 VDDC
( VDDR4:1.8V@300mA) AG13 VDDR4 R21
VDDR4 MarsCRB Design 2 1 +VDDR4 AG15 VDDC R23
VDDR4 VDDC
220ohm 1 1 VDDC
R26
T17
0_0603_5%
CV96
CV97
1U_0402_6.3V6K
.1U_0402_16V7K
0.1u 1 1 VDDC T20

1 1 VDDC
T22
1u 1 1 VDDC T24
VDDC
10u 1 0 U16
2 2 VDDC
PX@
PX@
U18
VDDC U21
VDDC
U23
VDDC U26
VDDC
V17
VDDC
V20
VDDC V22
VDDC
V24
VDDC V27
VDDC
Y16
VDDC
Y18
VDDC Y21
VDDC
Y23
VDDC Y26
VDDC +VGA_CORE
Y28
3 VDDC 3
(VDDCI:[email protected])
AA13
VDDCI
AB13
VDDCI AC12
VDDCI
AC15
VDDCI
AD13
VDDCI AD16
VDDCI
M15
VDDCI M16
VDDCI
M18
Route as differential pair VOLTAGE VDDCI
M23
CORE I/O
SENESE VDDCI
ISOLATED
N13
VDDCI
AF28 FB_VDDC N15
<53> VCCSENSE_VGA VDDCI N17
VDDCI
N20
VDDCI
AG28 N22
FB_VDDCI VDDCI
TV15 R12
VDDCI
R13
AH29 VDDCI R16
<53> VSSSENSE_VGA FB_GND VDDCI
T12
VDDCI
T15
VDDCI V15
VDDCI
Y13
VDDCI
4 4
1bios.ru Security Classification Compal Secret Data Compal Electronics, Inc.

ATI_MarsXTX_M2_Power
C 1.0
LA-9631P
A B C D E
A B C D E
UV1H
UV1I
PART 3 0F 9
MDB[0..63] PART 4 0F 9
GDDR5/DDR3 <31,32> MDB[0..63]
MDA0 C37 G24 MAA0 MDA[0..63]
DQA0_0 MAA0_0/MAA_0 <29,30> MDA[0..63] GDDR5/DDR3
MDA1 C35 DQA0_1 MAA0_1/MAA_1 J23 MAA1 MDB0 C5 MAB0_0/MAB_0 P8 MAB0
A35 H24 MAB[15..0] C3 DQB0_0 T9
MDA2 DQA0_2 MAA0_2/MAA_2 MAA2 MDB1 MAB0_1/MAB_1 MAB1
MAA[15..0] MAB[15..0] <31,32> DQB0_1
MDA3 E34 DQA0_3 MAA0_3/MAA_3 J24 MAA3 MDB2 E3 MAB0_2/MAB_2 P9 MAB2
MAA[15..0] <29,30> B_BA[2..0] DQB0_2
MDA4 G32 H26 MAA4 MDB3 E1 N7 MAB3
DQA0_4 MAA0_4/MAA_4 A_BA[2..0] B_BA[2..0] <31,32> DQB0_3 MAB0_3/MAB_3
MDA5 D33 J26 MAA5 MDB4 F1 N8 MAB4
DQA0_5 MAA0_5/MAA_5 A_BA[2..0] <29,30> DQB0_4 MAB0_4/MAB_4
MDA6 F32 DQA0_6 MAA0_6/MAA_6 H21 MAA6 MDB5 F3 MAB0_5/MAB_5 N9 MAB5
E32 G21 F5 DQB0_5 U9
MDA7 MAA7 MDB6 MAB6
MEMORY INTERFACE A
DQA0_7 MAA0_7/MAA_7 DQB0_6 MAB0_6/MAB_6
MDA8 D31 DQA0_8 MAA1_0/MAA_8 H19 MAA8 MDB7 G4 MAB0_7/MAB_7 U8 MAB7
DQB0_7
MDA9 F30 H20 MAA9 MDB8 H5 Y9 MAB8
MDA10 C30 L13 MAA10 MDB9 H6 W9 MAB9
MDA11 A30 DQA0_11 MAA1_3/MAA_11 G16 MAA11 MDB10 J4 MAB1_2/MAB_10 AC8 MAB10
F28 J16 K6 DQB0_10 AC9
MDA12 DQA0_12 MAA1_4/MAA_12 MAA12 MDB11 MAB1_3/MAB_11 MAB11
DQB0_11
MDA13 C28 DQA0_13 MAA1_5/MAA_BA2 H16 A_BA2 MDB12 K5 MAB1_4/MAB_12 AA7 MAB12
1 DQB0_12 1
MDA14 A28 J17 A_BA0 MDB13 L4 AA8 B_BA2
DQA0_14 MAA1_6/MAA_BA0 DQB0_13 MAB1_5/BA2
MDA15 E28 H17 A_BA1 MDB14 M6 Y8 B_BA0
DQA0_15 MAA1_7/MAA_BA1 DQB0_14 MAB1_6/BA0
MDA16 D27 DQA0_16 MDB15 M1 MAB1_7/BA1 AA9 B_BA1
DQB0_15
MEMORY INTERFACE B
MDA17 F26 A32 DQMA0 MDB16 M3
DQA0_17 WCKA0_0/DQMA_0 DQMA0 <29> DQB0_16
MDA18 C26 DQA0_18 WCKA0B_0/DQMA_1 C32 DQMA1 MDB17 M5 H3 DQMB0
DQMA1 <29> DQB0_17 WCKB0_0/DQMB_0 DQMB0 <31>
MDA19 A26 D23 DQMA2 MDB18 N4 H1 DQMB1
DQA0_19 WCKA0_1/DQMA_2 DQMA2 <29> DQB0_18 WCKB0B_0/DQMB_1 DQMB1 <31>
MDA20 F24 E22 DQMA3 MDB19 P6 T3 DQMB2
DQA0_20 WCKA0B_1/DQMA_3 DQMA3 <29> DQB0_19 WCKB0_1/DQMB_2 DQMB2 <31>
MDA21 C24 DQA0_21 WCKA1_0/DQMA_4 C14 DQMA4 MDB20 P5 T5 DQMB3
A24 A14 DQMA4 <30> R4 DQB0_20 WCKB0B_1/DQMB_3 AE4 DQMB3 <31>
MDA22 DQA0_22 WCKA1B_0/DQMA_5 DQMA5 MDB21 DQMB4
DQMA5 <30> DQB0_21 WCKB1_0/DQMB_4 DQMB4 <32>
MDA23 E24 DQA0_23 WCKA1_1/DQMA_6 E10 DQMA6 MDB22 T6 AF5 DQMB5
DQMA6 <30> DQB0_22 WCKB1B_0/DQMB_5 DQMB5 <32>
MDA24 C22 D9 DQMA7 MDB23 T1 AK6 DQMB6
DQA0_24 WCKA1B_1/DQMA_7 DQMA7 <30> DQB0_23 WCKB1_1/DQMB_6 DQMB6 <32>
MDA25 A22 MDB24 U4 AK5 DQMB7
DQA0_25 DQB0_24 WCKB1B_1/DQMB_7 DQMB7 <32>
MDA26 F22 DQA0_26 C34 QSA0 MDB25 V6
D21 EDCA0_0/QSA_0 D29 QSA0 <29> V1 DQB0_25 F6
MDA27 DQA0_27 QSA1 MDB26 QSB0
EDCA0_1/QSA_1 QSA1 <29> DQB0_26 EDCB0_0/QSB_0 QSB0 <31>
MDA28 A20 DQA0_28 D25 QSA2 MDB27 V3 K3 QSB1
MDA29 F20 E20 QSA3 MDB28 Y6 P3 QSB2
DQA0_29 EDCA0_3/QSA_3 QSA3 <29> DQB0_28 EDCB0_2/QSB_2 QSB2 <31>
MDA30 D19 E16 QSA4 MDB29 Y1 V5 QSB3
DQA0_30 EDCA1_0/QSA_4 QSA4 <30> DQB0_29 EDCB0_3/QSB_3 QSB3 <31>
MDA31 E18 DQA0_31 E12 QSA5 MDB30 Y3 AB5 QSB4
C18 EDCA1_1/QSA_5 J10 QSA5 <30> Y5 DQB0_30 EDCB1_0/QSB_4 AH1 QSB4 <32>
MDA32 DQA1_0 QSA6 MDB31 QSB5
MDA33 A18 DQA1_1 D7 QSA7 MDB32 AA4 AJ9 QSB6
MDA34 F18 MDB33 AB6 AM5 QSB7
DQA1_2 DQB1_1 EDCB1_3/QSB_7 QSB7 <32>
MDA35 D17 A34 QSA#0 MDB34 AB1
DQA1_3 DDBIA0_0/QSA_0B QSA#0 <29> DQB1_2
MDA36 A16 DQA1_4 E30 QSA#1 MDB35 AB3 G7 QSB#0
F16 DDBIA0_1/QSA_1B E26 QSA#1 <29> AD6 DQB1_3 DDBIB0_0/QSB_0B K1 QSB#0 <31>
MDA37 DQA1_5 QSA#2 MDB36 QSB#1
DDBIA0_2/QSA_2B QSA#2 <29> DQB1_4 DDBIB0_1/QSB_1B QSB#1 <31>
MDA38 D15 DQA1_6 C20 QSA#3 MDB37 AD1 P1 QSB#2
MDA39 E14 C16 QSA#4 MDB38 AD3 W4 QSB#3
DQA1_7 DDBIA1_0/QSA_4B QSA#4 <30> DQB1_6 DDBIB0_3/QSB_3B QSB#3 <31>
MDA40 F14 C12 QSA#5 MDB39 AD5 AC4 QSB#4
DQA1_8 DDBIA1_1/QSA_5B QSA#5 <30> DQB1_7 DDBIB1_0/QSB_4B QSB#4 <32>
MDA41 D13 DQA1_9 J11 QSA#6 MDB40 AF1 AH3 QSB#5
F12 DDBIA1_2/QSA_6B F8 QSA#6 <30> AF3 DQB1_8 DDBIB1_1/QSB_5B AJ8 QSB#5 <32>
MDA42 DQA1_10 QSA#7 MDB41 QSB#6
MDA43 A12 DQA1_11 MDB42 AF6 AM3 QSB#7
DQB1_10 DDBIB1_3/QSB_7B QSB#7 <32>
MDA44 D11 J21 ODTA0 MDB43 AG4
DQA1_12 ADBIA0/ODTA0 ODTA0 <29> DQB1_11
MDA45 F10 G19 ODTA1 MDB44 AH5 T7 ODTB0
DQA1_13 ADBIA1/ODTA1 ODTA1 <30> DQB1_12 ADBIB0/ODTB0 ODTB0 <31>
MDA46 A10 DQA1_14 MDB45 AH6 W7 ODTB1
C10 H27 CLKA0 AJ4 DQB1_13 ADBIB1/ODTB1 ODTB1 <32>
MDA47 DQA1_15 CLKA0 MDB46
CLKA0 <29> DQB1_14
MDA48 G13 DQA1_16 CLKA0B G27 CLKA0# MDB47 AK3 L9 CLKB0
CLKA0# <29> DQB1_15 CLKB0 CLKB0 <31>
MDA49 H13 MDB48 AF8 L8 CLKB0#
DQA1_17 DQB1_16 CLKB0B CLKB0# <31>
MDA50 J13 J14 CLKA1 MDB49 AF9
DQA1_18 CLKA1 CLKA1 <30> DQB1_17
2 MDA51 H11 DQA1_19 CLKA1B H14 CLKA1# MDB50 AG8 AD8 CLKB1 2
G10 CLKA1# <30> AG7 DQB1_18 CLKB1 AD7 CLKB1# CLKB1 <32>
MDA52 DQA1_20 MDB51
DQB1_19 CLKB1B CLKB1# <32>
MDA53 G8 DQA1_21 K23 RASA0# MDB52 AK9
RASA0B RASA0# <29> DQB1_20
MDA54 K9 K19 RASA1# MDB53 AL7 T10 RASB0#
DQA1_22 RASA1B RASA1# <30> DQB1_21 RASB0B RASB0# <31>
MDA55 K10 MDB54 AM8 Y10 RASB1#
DQA1_23 DQB1_22 RASB1B RASB1# <32>
MDA56 G9 DQA1_24 K20 CASA0# MDB55 AM7
A8 CASA0B K17 CASA1# CASA0# <29> AK1 DQB1_23 W10 CASB0#
MDA57 DQA1_25 MDB56
CASA1B CASA1# <30> DQB1_24 CASB0B CASB0# <31>
MDA58 C8 DQA1_26 MDB57 AL4 AA10 CASB1#
DQB1_25 CASB1B CASB1# <32>
MDA59 E8 CSA0B_0 K24 CSA0#_0 MDB58 AM6
DQA1_27 CSA0#_0 <29> DQB1_26
MDA60 A6 CSA0B_1 K27 MDB59 AM1 P10 CSB0#_0
DQA1_28 DQB1_27 CSB0B_0 CSB0#_0 <31>
MDA61 C6 DQA1_29 MDB60 AN4 L10
E6 M13 CSA1#_0 AP3 DQB1_28 CSB0B_1
MDA62 DQA1_30 CSA1B_0 MDB61
CSA1#_0 <30> DQB1_29
MDA63 A5 DQA1_31 CSA1B_1 K16 MDB62 AP1 AD10 CSB1#_0
DQB1_30 CSB1B_0 CSB1#_0 <32>
MDB63 AP5 AC10
L18 K21 CKEA0 DQB1_31 CSB1B_1
+VDD_MEM15_REFDA MVREFDA CKEA0 CKEA0 <29>
+VDD_MEM15_REFSA L20 MVREFSA CKEA1 J20 CKEA1 U10 CKEB0
CKEA1 <30> CKEB0 CKEB0 <31>
+VDD_MEM15_REFDB Y12 AA11 CKEB1
MVREFDB CKEB1 CKEB1 <32>
L27 NC WEA0B K26 WEA0# +VDD_MEM15_REFSB AA12
WEA0# <29> MVREFSB
N12 WEA1B L15 WEA1# N10 WEB0#
NC WEA1# <30> WEB0B WEB0# <31>
AG12 AB11 WEB1#
NC WEB1B WEB1# <32>
H23 MAA13
MAA0_8/MAA_13
1 PX@ 2 M27 MEM_CALRP0 MAA1_8/MAA_14 J19 MAA14 MAB0_8/MAB_13 T8 MAB13
RV47 120_0402_1% M21 MAA15 W8 MAB14
MAA0_9/MAA_15 MAB1_8/MAB_14
M12 M20 U12 MAB15
NC MAA1_9/RSVD MAB0_9/MAB_15
AH12 NC MAB1_9/RSVD V12
DRAM_RST AH11 DRAM_RST#_R
Mars@ MARS XT M2 FCBGA 962 Mars@ MARS XT M2 FCBGA 962
3 3
Ball to RV57 < 1"

CV100 to RV57 < 200 mil +1.5VGS
+1.5VGS +1.5VGS CV100 to RV53 < 1" +1.5VGS +1.5VGS
1
RV48
1
1
4.7K_0402_5%
RV49 RV50 @
40.2_0402_1% 40.2_0402_1% RV51 RV52
2
Mars@ Mars@ 40.2_0402_1% 40.2_0402_1%

PX@ PX@
2
2
+VDD_MEM15_REFDA +VDD_MEM15_REFSA 1 PX@ 2 1 PX@ 2 DRAM_RST#_R +VDD_MEM15_REFDB +VDD_MEM15_REFSB
<29,30,31,32> DRAM_RST# RV53 51.1_0402_1% RV54 10_0402_5%
1
1
1 1 1 1
1
2
RV56
RV55 CV98 100_0402_1% CV99 CV100 RV58 CV101 RV59 CV102
100_0402_1% 1U_0402_6.3V6K Mars@ 1U_0402_6.3V6K 120P_0402_50V9 RV57 100_0402_1% 1U_0402_6.3V6K 100_0402_1% 1U_0402_6.3V6K
2
Mars@ 2 Mars@ 2 Mars@ PX@ 4.99K_0402_1% PX@ 2 PX@ PX@ 2 PX@

2
2
PX@
1
DRAM_RST# is a daisy-chain net that connects to all VRAM

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
4 4
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
1bios.ru
Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2

ATI_MarsXTX_M2_MEM IF
C 1.0
LA-9631P
A B C D E
5 4 3 2 1
UV6
UV5 +VREFC_A1 M8 E3 MDA24

H1 VREFCA DQL0 F7 MDA30
+VREFC_A0 M8 E3 MDA23 VREFDQ DQL1 F2 MDA27
H1 VREFCA DQL0 F7 MDA19 MAA0 N3 DQL2 F8 MDA29
VREFDQ DQL1 F2 MDA22 MAA1 P7 A0 DQL3 H3 MDA25
MAA0 N3 DQL2 F8 MDA18 MAA2 P3 A1 DQL4 H8 MDA28
MAA1 P7 A0 DQL3 H3 MDA21 MAA3 N2 A2 DQL5 G2 MDA26
MAA2 P3 A1 DQL4 H8 MDA17 MAA4 P8 A3 DQL6 H7 MDA31
MAA3 N2 A2 DQL5 G2 MDA20 MAA5 P2 A4 DQL7
MAA4 P8 A3 DQL6 H7 MDA16 MAA6 R8 A5
MAA5 P2 A4 DQL7 MAA7 R2 A6 D7 MDA12
D
MAA6 R8 A5 MAA8 T8 A7 DQU0 C3 MDA10 D
MDA[0..31] MAA7 R2 A6 D7 MDA0 MAA9 R3 A8 DQU1 C8 MDA14
<28> MDA[0..31] MAA8 T8 A7 DQU0 C3 MDA5 MAA10 L7 A9 DQU2 C2 MDA11
MAA9 R3 A8 DQU1 C8 MDA1 MAA11 R7 A10/AP DQU3 A7 MDA13
MAA10 L7 A9 DQU2 C2 MDA6 MAA12 N7 A11 DQU4 A2 MDA9
MAA11 R7 A10/AP DQU3 A7 MDA3 MAA13 T3 A12 DQU5 B8 MDA15
MAA12 N7 A11 DQU4 A2 MDA4 MAA14 T7 A13 DQU6 A3 MDA8
MAA[15..0] MAA13 T3 A12 DQU5 B8 MDA2 MAA15 M7 A14 DQU7
<28,30> MAA[15..0] T7 A13 DQU6 A3 A15/BA3 +1.5VGS
MAA14 MDA7
MAA15 M7 A14 DQU7
A15/BA3 +1.5VGS A_BA0 M2 B2
A_BA1 N8 BA0 VDD D9
M2 B2 A_BA2 M3 BA1 VDD G7
<28,30> A_BA0 N8 BA0 VDD D9 BA2 VDD K2
<28,30> A_BA1 BA1 VDD VDD
M3 G7 K8
<28,30> A_BA2 BA2 VDD VDD
K2 N1
VDD K8 CLKA0 J7 VDD N9
VDD N1 CLKA0# K7 CK VDD R1
J7 VDD N9 CKEA0 K9 CK VDD R9
<28> CLKA0 CK VDD CKE/CKE0 VDD +1.5VGS
K7 R1
<28> CLKA0# CK VDD
K9 R9
<28> CKEA0 CKE/CKE0 VDD +1.5VGS K1 A1
ODTA0
CSA0#_0 L2 ODT/ODT0 VDDQ A8
K1 A1 RASA0# J3 CS/CS0 VDDQ C1
<28> ODTA0 ODT/ODT0 VDDQ RAS VDDQ
L2 A8 CASA0# K3 C9
<28> CSA0#_0 CS/CS0 VDDQ CAS VDDQ
J3 C1 WEA0# L3 D2
<28> RASA0# K3 RAS VDDQ C9 WE VDDQ E9
<28> CASA0# CAS VDDQ VDDQ
L3 D2 F1
<28> WEA0# WE VDDQ E9 F3 VDDQ H2
QSA3
VDDQ <28> QSA3 DQSL VDDQ
F1 QSA1 C7 H9
VDDQ <28> QSA1 DQSU VDDQ
QSA2 F3 H2
<28> QSA2 C7 DQSL VDDQ H9
QSA0
<28> QSA0 DQSU VDDQ DQMA3 E7 A9
<28> DQMA3 D3 DML VSS B3
DQMA1
<28> DQMA1 DMU VSS
DQMA2 E7 A9 E1
<28> DQMA2 DML VSS VSS
DQMA0 D3 B3 G8
<28> DQMA0 DMU VSS E1 G3 VSS J2
QSA#3
VSS <28> QSA#3 DQSL VSS
C G8 QSA#1 B7 J8 C
G3 VSS J2 <28> QSA#1 DQSU VSS M1
QSA#2
<28> QSA#2 DQSL VSS VSS
QSA#0 B7 J8 M9
<28> QSA#0 DQSU VSS VSS
M1 P1
VSS M9 DRAM_RST# T2 VSS P9
VSS P1 RESET VSS T1
T2 VSS P9 L8 VSS T9
<28,30,31,32> DRAM_RST# RESET VSS ZQ/ZQ0 VSS
T1
L8 VSS T9
ZQ/ZQ0 VSS
1
J1 B1
RV85 L1 NC/ODT1 VSSQ B9
NC/CS1 VSSQ
1
J1 B1 240_0402_1% J9 D1
RV84 L1 NC/ODT1 VSSQ B9 Mars@ L9 NC/CE1 VSSQ D8
J9 NC/CS1 VSSQ D1 NCZQ1 VSSQ E2
240_0402_1%
2
L9 NC/CE1 VSSQ D8 VSSQ E8
Mars@ NCZQ1 VSSQ E2 VSSQ F9
2
VSSQ E8 VSSQ G1
VSSQ F9 VSSQ G9
VSSQ G1 VSSQ
VSSQ G9 96-BALL
VSSQ SDRAM DDR3
96-BALL K4W1G1646E-HC12_FBGA96
SDRAM DDR3 X76@
K4W1G1646E-HC12_FBGA96
CLKA0 1 Mars@2 X76@
RV60 40.2_0402_1%
CLKA0# 1 Mars@2
RV61 40.2_0402_1%
1
CV195 +1.5VGS
0.01U_0402_16V7K +1.5VGS
Mars@
2
1
Mars@
1
Mars@ RV63
RV62 4.99K_0402_1%
4.99K_0402_1%
B B
15mil
2
15mil
2
+VREFC_A1
+VREFC_A0
.1U_0402_16V7K
CV104
Mars@
1
1
.1U_0402_16V7K
CV103
Mars@ RV65
1
RV64 4.99K_0402_1%
4.99K_0402_1% Mars@
2
Mars@
2
2
2
+1.5VGS +1.5VGS +1.5VGS

10U_0603_6.3V6M
CV105
1U_0402_6.3V6K
CV106
1U_0402_6.3V6K
CV107
1U_0402_6.3V6K
CV108
1U_0402_6.3V6K
CV109
1U_0402_6.3V6K
CV112
1U_0402_6.3V6K
CV113
.1U_0402_16V7K
CV125
10U_0603_6.3V6M
CV115
10U_0603_6.3V6M
CV116
1U_0402_6.3V6K
CV117
1U_0402_6.3V6K
CV118
1U_0402_6.3V6K
CV119
1U_0402_6.3V6K
CV120
1U_0402_6.3V6K
CV121
1U_0402_6.3V6K
CV122
1U_0402_6.3V6K
CV124
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Mars@
Mars@
Mars@
Mars@
Mars@
Mars@
Mars@
Mars@
Mars@
Mars@
Mars@
Mars@
Mars@
Mars@
A A

ATI_Whistler_M2_VRAM_A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-9631P 1.0
5 4 3 2 1
5 4 3 2 1
UV7
UV8
+VREFC_A2 M8 E3 MDA38
H1 VREFCA DQL0 F7 MDA36 +VREFC_A3 M8 E3 MDA49
VREFDQ DQL1 F2 MDA39 H1 VREFCA DQL0 F7 MDA51
MAA0 N3 DQL2 F8 MDA34 VREFDQ DQL1 F2 MDA48
MAA1 P7 A0 DQL3 H3 MDA35 MAA0 N3 DQL2 F8 MDA52
D
MAA2 P3 A1 DQL4 H8 MDA33 MAA1 P7 A0 DQL3 H3 MDA50 D
MAA3 N2 A2 DQL5 G2 MDA37 MAA2 P3 A1 DQL4 H8 MDA53
MAA4 P8 A3 DQL6 H7 MDA32 MAA3 N2 A2 DQL5 G2 MDA55
MAA5 P2 A4 DQL7 MAA4 P8 A3 DQL6 H7 MDA54
MAA6 R8 A5 MAA5 P2 A4 DQL7
MAA7 R2 A6 D7 MDA42 MAA6 R8 A5
MAA8 T8 A7 DQU0 C3 MDA44 MAA7 R2 A6 D7 MDA60
MAA9 R3 A8 DQU1 C8 MDA40 MAA8 T8 A7 DQU0 C3 MDA57
MDA[32..63] MAA10 L7 A9 DQU2 C2 MDA46 MAA9 R3 A8 DQU1 C8 MDA63
<28> MDA[32..63] MAA11 R7 A10/AP DQU3 A7 MDA43 MAA10 L7 A9 DQU2 C2 MDA56
MAA12 N7 A11 DQU4 A2 MDA45 MAA11 R7 A10/AP DQU3 A7 MDA61
MAA13 T3 A12 DQU5 B8 MDA41 MAA12 N7 A11 DQU4 A2 MDA59
MAA14 T7 A13 DQU6 A3 MDA47 MAA13 T3 A12 DQU5 B8 MDA62
MAA15 M7 A14 DQU7 MAA14 T7 A13 DQU6 A3 MDA58
MAA[15..0] A15/BA3 +1.5VGS MAA15 M7 A14 DQU7
<28,29> MAA[15..0] A15/BA3 +1.5VGS
A_BA0 M2 B2
<28,29> A_BA0 BA0 VDD
A_BA1 N8 D9 A_BA0 M2 B2
<28,29> A_BA1 M3 BA1 VDD G7 N8 BA0 VDD D9
A_BA2 A_BA1
<28,29> A_BA2 BA2 VDD BA1 VDD
K2 A_BA2 M3 G7
VDD K8 BA2 VDD K2
VDD N1 VDD K8
J7 VDD N9 VDD N1
<28> CLKA1 K7 CK VDD R1 J7 VDD N9
CLKA1
<28> CLKA1# CK VDD CK VDD
K9 R9 CLKA1# K7 R1
<28> CKEA1 CKE/CKE0 VDD +1.5VGS CK VDD
CKEA1 K9 R9
CKE/CKE0 VDD +1.5VGS
K1 A1
<28> ODTA1 L2 ODT/ODT0 VDDQ A8 K1 A1
ODTA1
<28> CSA1#_0 CS/CS0 VDDQ ODT/ODT0 VDDQ
J3 C1 CSA1#_0 L2 A8
<28> RASA1# RAS VDDQ CS/CS0 VDDQ
K3 C9 RASA1# J3 C1
<28> CASA1# L3 CAS VDDQ D2 K3 RAS VDDQ C9
CASA1#
<28> WEA1# WE VDDQ CAS VDDQ
E9 WEA1# L3 D2
VDDQ F1 WE VDDQ E9
QSA4 F3 VDDQ H2 VDDQ F1
<28> QSA4 DQSL VDDQ VDDQ
QSA5 C7 H9 QSA6 F3 H2
<28> QSA5 DQSU VDDQ <28> QSA6 C7 DQSL VDDQ H9
QSA7
<28> QSA7 DQSU VDDQ
C C
DQMA4 E7 A9
<28> DQMA4 DML VSS
DQMA5 D3 B3 DQMA6 E7 A9
<28> DQMA5 DMU VSS <28> DQMA6 DML VSS
E1 DQMA7 D3 B3
VSS G8 <28> DQMA7 DMU VSS E1
QSA#4 G3 VSS J2 VSS G8
<28> QSA#4 B7 DQSL VSS J8 G3 VSS J2
QSA#5 QSA#6
<28> QSA#5 DQSU VSS <28> QSA#6 DQSL VSS
M1 QSA#7 B7 J8
VSS <28> QSA#7 DQSU VSS
M9 M1
VSS P1 VSS M9
DRAM_RST# T2 VSS P9 VSS P1
<28,29,31,32> DRAM_RST# RESET VSS T1 VSS
DRAM_RST# T2 P9
L8 VSS T9 RESET VSS T1
ZQ/ZQ0 VSS L8 VSS T9
ZQ/ZQ0 VSS
1
J1 B1
NC/ODT1 VSSQ
1
RV86 L1 B9 J1 B1
J9 NC/CS1 VSSQ D1 RV87 L1 NC/ODT1 VSSQ B9
240_0402_1% NC/CE1 VSSQ NC/CS1 VSSQ
L9 D8 240_0402_1% J9 D1
Mars@ NCZQ1 VSSQ E2 Mars@ L9 NC/CE1 VSSQ D8
2
VSSQ E8 NCZQ1 VSSQ E2
2
VSSQ F9 VSSQ E8
VSSQ G1 VSSQ F9
VSSQ G9 VSSQ G1
VSSQ VSSQ G9
96-BALL VSSQ
SDRAM DDR3 96-BALL
K4W1G1646E-HC12_FBGA96 SDRAM DDR3
X76@ K4W1G1646E-HC12_FBGA96
X76@
+1.5VGS
B B
+1.5VGS
1
Mars@
CLKA1 1 Mars@2 RV67
1
RV66 40.2_0402_1% Mars@ 4.99K_0402_1%

RV68
4.99K_0402_1%
15mil
2
CLKA1# 1 Mars@2
RV69 40.2_0402_1% +VREFC_A3
15mil
2
1
CV196
.1U_0402_16V7K
CV126
0.01U_0402_16V7K +VREFC_A2 Mars@
1
Mars@ RV70
2
.1U_0402_16V7K
CV127
Mars@ 4.99K_0402_1%
1
RV71 Mars@
2
4.99K_0402_1%
2
Mars@
2
2
+1.5VGS +1.5VGS +1.5VGS

CV128
CV152
CV154
CV132
CV164
CV134
CV135
CV136
CV138
CV139
CV141
CV144
CV145
CV146
CV147
CV193
CV148
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Mars@
Mars@
Mars@
Mars@
Mars@
Mars@
Mars@
Mars@
Mars@
Mars@
Mars@
Mars@
Mars@
A A

5 4 3 2 1
5 4 3 2 1
UV9 UV10
+VREFC_B0 M8 E3 MDB19 +VREFC_B1 M8 E3 MDB26

H1 VREFCA DQL0 F7 MDB20 H1 VREFCA DQL0 F7 MDB30
VREFDQ DQL1 F2 MDB22 VREFDQ DQL1 F2 MDB24
MAB0 N3 DQL2 F8 MDB16 MAB0 N3 DQL2 F8 MDB29
MAB1 P7 A0 DQL3 H3 MDB23 MAB1 P7 A0 DQL3 H3 MDB27
MAB3 N2 A2 DQL5 G2 MDB21 MAB3 N2 A2 DQL5 G2 MDB25
MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7
D
MAB6 R8 A5 MAB6 R8 A5 D
MAB7 R2 A6 D7 MDB0 MAB7 R2 A6 D7 MDB15
MDB[0..31] MAB8 T8 A7 DQU0 C3 MDB4 MAB8 T8 A7 DQU0 C3 MDB10
<28> MDB[0..31] MAB9 R3 A8 DQU1 C8 MDB1 MAB9 R3 A8 DQU1 C8 MDB14
MAB10 L7 A9 DQU2 C2 MDB6 MAB10 L7 A9 DQU2 C2 MDB11
MAB11 R7 A10/AP DQU3 A7 MDB3 MAB11 R7 A10/AP DQU3 A7 MDB12
MAB12 N7 A11 DQU4 A2 MDB7 MAB12 N7 A11 DQU4 A2 MDB9
MAB13 T3 A12 DQU5 B8 MDB2 MAB13 T3 A12 DQU5 B8 MDB13
MAB[15..0] MAB14 T7 A13 DQU6 A3 MDB5 MAB14 T7 A13 DQU6 A3 MDB8
<28,32> MAB[15..0] A14 DQU7 A14 DQU7
MAB15 M7 MAB15 M7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS
M2 B2 B_BA0 M2 B2
<28,32> B_BA0 N8 BA0 VDD D9 N8 BA0 VDD D9
B_BA1
<28,32> B_BA1 BA1 VDD BA1 VDD
M3 G7 B_BA2 M3 G7
K2 K2
VDD K8 VDD K8
VDD N1 VDD N1
J7 VDD N9 CLKB0 J7 VDD N9
<28> CLKB0 CK VDD CK VDD
K7 R1 CLKB0# K7 R1
<28> CLKB0# CK VDD CK VDD
K9 R9 CKEB0 K9 R9
<28> CKEB0 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
K1 A1 ODTB0 K1 A1
<28> ODTB0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSB0#_0 L2 A8
<28> CSB0#_0 CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASB0# J3 C1
<28> RASB0# K3 RAS VDDQ C9 K3 RAS VDDQ C9
CASB0#
<28> CASB0# CAS VDDQ CAS VDDQ
L3 D2 WEB0# L3 D2
<28> WEB0# WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1
QSB2 F3 VDDQ H2 QSB3 F3 VDDQ H2
<28> QSB2 C7 DQSL VDDQ H9 <28> QSB3 C7 DQSL VDDQ H9
QSB0 QSB1
<28> QSB0 DQSU VDDQ <28> QSB1 DQSU VDDQ
DQMB2 E7 A9 DQMB3 E7 A9
<28> DQMB2 DML VSS <28> DQMB3 DML VSS
DQMB0 D3 B3 DQMB1 D3 B3
<28> DQMB0 DMU VSS E1 <28> DQMB1 DMU VSS E1
VSS G8 VSS G8
C C
QSB#2 G3 VSS J2 QSB#3 G3 VSS J2
<28> QSB#2 DQSL VSS <28> QSB#3 DQSL VSS
QSB#0 B7 J8 QSB#1 B7 J8
<28> QSB#0 DQSU VSS <28> QSB#1 DQSU VSS
CLKB0 1 PX@ 2 M1 M1
RV72 40.2_0402_1% VSS M9 VSS M9
VSS P1 VSS P1
T2 VSS P9 DRAM_RST# T2 VSS P9
<28,29,30,32> DRAM_RST# RESET VSS RESET VSS
CLKB0# 1 PX@ 2 T1 T1
RV73 40.2_0402_1% L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
CV197
1
0.01U_0402_16V7K J1 B1 J1 B1
PX@ RV88 L1 NC/ODT1 VSSQ B9 RV89 L1 NC/ODT1 VSSQ B9
2
J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1

240_0402_1% NC/CE1 VSSQ 240_0402_1% NC/CE1 VSSQ
L9 D8 L9 D8
PX@ NCZQ1 VSSQ E2 PX@ NCZQ1 VSSQ E2
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@
+1.5VGS
+1.5VGS
1
PX@
1
PX@ RV75
RV74 4.99K_0402_1%
4.99K_0402_1%
15mil
2
B B
15mil
2
+VREFC_B1
+VREFC_B0
.1U_0402_16V7K
CV150
PX@
1
1
.1U_0402_16V7K
CV149
PX@ RV77
1
RV76 4.99K_0402_1%
4.99K_0402_1% PX@
2
PX@
2
2
2
+1.5VGS +1.5VGS +1.5VGS

CV129
CV183
CV130
CV155
CV156
CV158
CV159
CV160
CV161
CV162
CV165
CV166
CV167
CV168
CV169
CV170
CV171
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
1U_0402_6.3V6K
.1U_0402_16V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
A A

ATI_Whistler_M2_VRAM_B
5 4 3 2 1
5 4 3 2 1
UV11 UV12
+VREFC_B2 M8 E3 MDB33 +VREFC_B3 M8 E3 MDB55

H1 VREFCA DQL0 F7 MDB37 H1 VREFCA DQL0 F7 MDB50
VREFDQ DQL1 F2 MDB35 VREFDQ DQL1 F2 MDB54
MAB0 N3 DQL2 F8 MDB39 MAB0 N3 DQL2 F8 MDB51
MAB3 N2 A2 DQL5 G2 MDB34 MAB3 N2 A2 DQL5 G2 MDB52
MDB[0..31] MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7
<28> MDB[32..63] MAB6 R8 A5 MAB6 R8 A5
MAB7 R2 A6 D7 MDB44 MAB7 R2 A6 D7 MDB56
D
MAB8 T8 A7 DQU0 C3 MDB41 MAB8 T8 A7 DQU0 C3 MDB59 D
MAB9 R3 A8 DQU1 C8 MDB47 MAB9 R3 A8 DQU1 C8 MDB63
MAB10 L7 A9 DQU2 C2 MDB43 MAB10 L7 A9 DQU2 C2 MDB62
MAB[15..0] MAB11 R7 A10/AP DQU3 A7 MDB45 MAB11 R7 A10/AP DQU3 A7 MDB57
<28,31> MAB[15..0] A11 DQU4 A11 DQU4
MAB12 N7 A2 MDB40 MAB12 N7 A2 MDB61
MAB13 T3 A12 DQU5 B8 MDB46 MAB13 T3 A12 DQU5 B8 MDB58
MAB14 T7 A13 DQU6 A3 MDB42 MAB14 T7 A13 DQU6 A3 MDB60
MAB15 M7 A14 DQU7 MAB15 M7 A14 DQU7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS
B_BA0 M2 B2 B_BA0 M2 B2
<28,31> B_BA0 N8 BA0 VDD D9 N8 BA0 VDD D9
B_BA1 B_BA1
B_BA2 M3 G7 B_BA2 M3 G7
<28,31> B_BA2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8
VDD N1 VDD N1
J7 VDD N9 CLKB1 J7 VDD N9
<28> CLKB1 CK VDD CK VDD
K7 R1 CLKB1# K7 R1
<28> CLKB1# K9 CK VDD R9 K9 CK VDD R9
CKEB1
<28> CKEB1 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
K1 A1 ODTB1 K1 A1
<28> ODTB1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSB1#_0 L2 A8
<28> CSB1#_0 J3 CS/CS0 VDDQ C1 J3 CS/CS0 VDDQ C1
RASB1#
<28> RASB1# RAS VDDQ RAS VDDQ
K3 C9 CASB1# K3 C9
<28> CASB1# CAS VDDQ CAS VDDQ
L3 D2 WEB1# L3 D2
<28> WEB1# WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1
QSB4 F3 VDDQ H2 QSB6 F3 VDDQ H2
<28> QSB4 DQSL VDDQ <28> QSB6 DQSL VDDQ
QSB5 C7 H9 QSB7 C7 H9
<28> QSB5 DQSU VDDQ <28> QSB7 DQSU VDDQ
DQMB4 E7 A9 DQMB6 E7 A9
<28> DQMB4 D3 DML VSS B3 <28> DQMB6 D3 DML VSS B3
DQMB5 DQMB7
<28> DQMB5 DMU VSS <28> DQMB7 DMU VSS
E1 E1
VSS G8 VSS G8
QSB#4 G3 VSS J2 QSB#6 G3 VSS J2
<28> QSB#4 DQSL VSS <28> QSB#6 DQSL VSS
C QSB#5 B7 J8 QSB#7 B7 J8 C
<28> QSB#5 DQSU VSS M1 <28> QSB#7 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9
<28,29,30,31> DRAM_RST# RESET VSS RESET VSS
T1 T1
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
J1 B1 J1 B1
RV90 L1 NC/ODT1 VSSQ B9 RV91 L1 NC/ODT1 VSSQ B9
J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1
240_0402_1% NC/CE1 VSSQ 240_0402_1% NC/CE1 VSSQ
L9 D8 L9 D8
PX@ NCZQ1 VSSQ E2 PX@ NCZQ1 VSSQ E2
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@
+1.5VGS
+1.5VGS
1
PX@
RV78
1
CLKB1 1 PX@ 2 PX@ 4.99K_0402_1%

RV79 40.2_0402_1% RV80
4.99K_0402_1%
15mil
2
CLKB1# 1 PX@ 2
RV81 40.2_0402_1% +VREFC_B3
15mil
2
1
1
B B
.1U_0402_16V7K
CV172
CV198 +VREFC_B2 PX@
1
0.01U_0402_16V7K RV82
1
.1U_0402_16V7K
CV173
PX@ PX@ 4.99K_0402_1%

2
RV83 PX@
2
4.99K_0402_1%
2
PX@
2
2
+1.5VGS +1.5VGS +1.5VGS

CV174
CV175
CV176
CV177
CV178
CV179
CV181
CV185
CV184
CV186
CV187
CV188
CV189
CV190
CV191
CV192
CV194
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
A A

5 4 3 2 1
5 4 3 2 1
LCD POWER CIRCUIT Camera

+3VS
W=60mils
+3VS +LCDVDD_CONN
W=60mils U72 (20 MIL)
1 +LCDVDD_CONN CMOS@ +3VS_CMOS
5 VOUT Q83
4.7U_0603_6.3V6K
VIN LP2301ALT1G_SOT23-3
D D
C516
2 1 (20 MIL)
GND
D
4 3 1
SS
1 1
1 3 CMOS@
EN 2 C518 C519 @
G
2
C4 APL3512ABI-TRG_SOT23-5 .1U_0402_16V7K R02 10U_0603_6.3V6M
1500P_0402_50V7K R435CMOS@ 2 2
2 150K_0402_5%
4.7V
<17> PCH_ENVDD <42> CMOS_ON#
1
C520 CMOS@
R408 .1U_0402_16V7K
100K_0402_5% 2
LCD Conn.
2
+LEDVDD B+
@
R813
1 2
C C
1
0_0805_5%
C541
4.7U_0805_25V6-K
2 @
JLVDS1
1
2 1 31
3 2 G1 32
4 3 G2 33
5 4 G3 34
R509 1 @ 2 0_0402_5% 6 5 G4
BKOFF# 7 6
8 7
<17> PCH_PWM 8
9
10 9
<17> LVDS_ACLK 10
11
<17> LVDS_ACLK# 11
12
BKOFF# 13 12
<42> BKOFF# <17> LVDS_A2 13
14
<17> LVDS_A2# 14
15
<17> LVDS_A1 15
1
16
<17> LVDS_A1# 16
R716 17
<17> LVDS_A0 18 17
B 10K_0402_5% <17> LVDS_A0# 18
B
<17> EDID_DATA 19
20 19
<17> EDID_CLK
2
21 20
+3VS 21
22
+LCDVDD_CONN 22
(60 MIL) 23
24 23
+3VS 24
25
26 25
+3VS_CMOS 26
USB20_P3_R 27
USB20_N3_R 28 27
CMOS
For EMI 29
30
28
29
30
<18> USB20_P3 USB20_P3 1 R688@ 2 0_0402_5% USB20_P3_R ACES_88341-3001 ME@

<18> USB20_N3 USB20_N3 1 R684@ 2 0_0402_5% USB20_N3_R
L58 @
USB20_P3 1 2 USB20_P3_R
1 2
USB20_N3 4 3 USB20_N3_R
4 3
WCM-2012-900T_4P
A A

Compal Secret Data
Deciphered Date 2012/07/11
Title
LVDS/CAMERA
Custom 1.0
LA-9631P
5 4 3 2 1
A B C D E
1 1
FCM1608CF-121T03 0603
1 2 RED
<17> DAC_RED
L30
FCM1608CF-121T03 0603
1 2 GREEN
<17> DAC_GRN
L31
FCM1608CF-121T03 0603
1 2 BLUE
<17> DAC_BLU
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
C522
C523
C524
C525
C526
C527
L32
1 1 1 1 1 1
RP22
8 1 DAC_BLU 2 2 2 2 2 2 +5V_Display
7 2 DAC_GRN
6 3 DAC_RED
5 4
150_0804_8P4R_1% JCRT1
6
PAD T66 NC11 11
For EMI RED
CRT_DDC_DAT_CONN
1
7
12
GREEN 2
8 16
2 G 2
JVGA_HS_R 13 17
BLUE 3 G
9
JVGA_VS_R 14
4
10
CRT_DDC_CLK_CONN 15
5
CONTE_80431-5K1-152
ME@
+5VS
1 1
@
C529 C531
U10
.1U_0402_16V7K .1U_0402_16V7K
2 2 1 8 1 2
VCC_SYNC BYP C6 0.22U_0402_10V6K +5V_Display
2 3 RED
+3VS VCC_VIDEO VIDEO1
1
7 4 GREEN
VCC_DDC VIDEO2 R31 R33
1 4.7K_0402_5% 4.7K_0402_5%
<17> CRT_DDC_DATA 10 5 BLUE
C537 DDC_IN1 VIDEO3
2
.1U_0402_16V7K
3 2 11 9 CRT_DDC_DAT_CONN 3
<17> CRT_DDC_CLK DDC_IN2 DDC_OUT1
13 12 CRT_DDC_CLK_CONN
<17> CRT_VSYNC SYNC_IN1 DDC_OUT2
15 14 JVGA_VS 1 R411 2 JVGA_VS_R

<17> CRT_HSYNC SYNC_IN2 SYNC_OUT1 22_0402_5%
6 16 JVGA_HS 1 R412 2 JVGA_HS_R

GND SYNC_OUT2 22_0402_5%
10P_0402_50V8J
10P_0402_50V8J
TPD7S019-15DBQR_SSOP16
@ 1 @ 1
C411
C412
2 2
4 4

Compal Secret Data
CRT Connector
Custom 1.0
LA-9631P
A B C D E
5 4 3 2 1
For EMI U73

+5V_Display
+5VS 3
W=40mils
L35 HDMI@ OUT
1
HDMI_CLK+_CK 1 2 HDMI_CLK+_CONN 1
<17> HDMI_CLK+_CK 1 2 +3VS IN
1 C543
2
HDMI_CLK-_CK 4 3 HDMI_CLK-_CONN C544 GND .1U_0402_16V7K 2
<17> HDMI_CLK-_CK 4 3
2
WCM-2012HS-900T .1U_0402_16V7K 2 AP2330W-7_SC59-3
D R485 D
L36 HDMI@ 1M_0402_5% Q93 ZZZ3 45@
HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN HDMI@ HDMI@
<17> HDMI_TX0+_CK 1 2
2
G
2N7002H_SOT23-3
For CRT and HDMI
1
<17> HDMI_TX0-_CK HDMI_TX0-_CK 4 3 HDMI_TX0-_CONN TMDS_B_HPD# 3 1
4 3 <17> TMDS_B_HPD#
D
WCM-2012HS-900T HDMI Logo
2
L37 HDMI@ RO0000003HM
<17> HDMI_TX1+_CK HDMI_TX1+_CK 1 2 HDMI_TX1+_CONN R488
1 2
20K_0402_5%
HDMI@
<17> HDMI_TX1-_CK HDMI_TX1-_CK 4 3 HDMI_TX1-_CONN JHDMI1
1
4 3 HDMI_DET 19
WCM-2012HS-900T 18 HP_DET
+5V_Display +5V
17
L38 HDMI@ HDMIDAT_R 16 DDC/CEC_GND
HDMI_TX2+_CK 1 2 HDMI_TX2+_CONN HDMICLK_R 15 SDA
<17> HDMI_TX2+_CK 1 2 SCL
14
13 Reserved
HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN HDMI_CLK-_CONN 12 CEC 20
<17> HDMI_TX2-_CK 4 3 CK- G1
11 21
WCM-2012HS-900T HDMI_CLK+_CONN 10 CK_shield G2 22
C CK+ G3 C
HDMI_TX0-_CONN 9 23
8 D0- G4
HDMI_TX0+_CONN 7 D0_shield
+3VS HDMI_TX1-_CONN 6 D0+
5 D1-
Pull up R for PCH OR VGA SIDE HDMI_TX2-_CONN 3 D1+
2 D2-
D2+
SUYIN_100042GR019M23DZL
ME@
+3VS Q63A
HDMI@ DVT
2
+5V_Display RP21 2N7002DW-T/R7_SOT363-6
8 1 HDMIDAT_NB RP26
7 2 HDMIDAT_R <17> HDMICLK_NB 1 6 HDMICLK_R HDMI_TX1+_CONN 5 4
6 3 HDMICLK_NB HDMI_TX1-_CONN 6 3
5
5 4 HDMICLK_R HDMI_CLK+_CONN 7 2
HDMI_CLK-_CONN 8 1
2.2K_0804_8P4R_5% 4 3 HDMIDAT_R
<17> HDMIDAT_NB
HDMI@ 680 +-5% 8P4R
Q63B HDMI@
B HDMI@ B
2N7002DW-T/R7_SOT363-6 RP27
HDMI_TX0+_CONN 5 4
HDMI_TX0-_CONN 6 3
HDMI_TX2+_CONN 7 2
HDMI_TX2-_CONN 8 1
ESD
680 +-5% 8P4R
HDMI@
@ D32 @ D28 @ D33
HDMIDAT_R 9 10 1 1 HDMIDAT_R HDMI_CLK-_CONN 9 10 1 1 HDMI_CLK-_CONN HDMI_TX0+_CONN 9 10 1 1 HDMI_TX0+_CONN
HDMICLK_R 8 9 2 2 HDMICLK_R HDMI_CLK+_CONN 8 9 2 2 HDMI_CLK+_CONN HDMI_TX0-_CONN 8 9 2 2 HDMI_TX0-_CONN

+3VS
HDMI_DET 7 7 4 4 HDMI_DET HDMI_TX1-_CONN 7 7 4 4 HDMI_TX1-_CONN HDMI_TX2+_CONN 7 7 4 4 HDMI_TX2+_CONN
1
D
6 6 5 5 HDMI_TX1+_CONN 6 6 5 5 HDMI_TX1+_CONN HDMI_TX2-_CONN 6 6 5 5 HDMI_TX2-_CONN 2
G
3 3 3 3 3 3 S Q95
3
HDMI@
8 8 8 2N7002H_SOT23-3
YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9

A A

HDMI CONN
Document Number Rev
B 1.0
LA-9631P
1bios.ru
5 4 3 2 1
A B C D E
Mini Card for WLAN/WiMAX(Half)
1 1
+3VS 80mil +3VS_WLAN

J6
1 2
1 2 +1.5VS
JUMP_43X79
@ JWLN1
<16> PCIE_WAKE# R508 1 2 0_0402_5% PCIE_WAKE#_WLAN 1 2
3 1 2 4
5 3 4 6
<19> PCH_BT_ON# 5 6
<15> CLKREQ_WLAN# 7 8
9 7 8 10
11 9 10 12
<15> CLK_PCIE_WLAN1# 11 12
13 14
<15> CLK_PCIE_WLAN1 15 13 14 16
17 15 16 18
19 17 18 20
21 19 20 22 PCH_WL_OFF# <18>
21 22 PLT_RST# <18,23,37,42>
23 24 +3VS_WLAN
2 <15> PCIE_PRX_DTX_N2 25 23 24 26
2
<15> PCIE_PRX_DTX_P2 25 26
27 28
29 27 28 30 1 R501 2 @ 0_0402_5%
29 30 SMB_CLK_S3 <12,13,15>
31 32 1 R502 2 @ 0_0402_5%
<15> PCIE_PTX_C_DRX_N2 31 32 SMB_DATA_S3 <12,13,15>
33 34
<15> PCIE_PTX_C_DRX_P2 35 33 34 36
+3VS_WLAN 35 36 USB20_N10 <18>
37 38
39 37 38 40 USB20_P10 <18>
41 39 40 42
43 41 42 44
100_0402_1% 45 43 44 46
R505 47 45 46 48
1 2 49 47 48 50
<42,43> EC_TX 1 2 51 49 50 52
<42,43> EC_RX 51 52
R506
DVT 100_0402_1% 53 54
1 R405 2 INTEL_BT_OFF#_R GND1 GND2
<19> INTEL_BT_OFF#
1K_0402_5%
BELLW_80003-8041
2
For EC to detect ME@
R507
debug card insert. 100K_0402_5%
3 3
4 4

Mini-Card/NEW Card/SIM
Document Number Rev
1.0
LA-9631P
1bios.ru
A B C D E
5 4 3 2 1
For LAN & Green CLK +3VALW +3V_LAN

+LX
Close together
J10
LL2 LL3 SWR@
1 2 LL1 SWR@
1 2 +LX_R 1 2 +LX FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P
1000P_0402_50V7K
1 2 1 2
10U_0603_6.3V6M
+1.1_AVDDL_L +1.1_AVDDL +LX_R
.1U_0402_16V7K
4.7UH_SIA4012-4R7M_20%
JUMP_43X79
CL1
CL2
.1U_0402_16V7K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
1 1
CL4
CL5
CL6
D
Note: Place Close to LAN chip 1 1 1 D
3 1
D
2 2 LL1 DCR< 0.15 ohm
CL3
@
@ Rate current > 1A
RL3 2 2 2
QL1
G
2
LAN_PWR_ON# 2 1 LP2301ALT1G_SOT23-3
<42> LAN_PWR_ON# 10U
2
@
10K_0402_5% CL7 SWR@SWR@SWR@
1
.1U_0402_16V7K Place close to Pin34
Close to
Pin40
Vendor recommand reseve the

PU resistor close LAN chip
UL1 8172@
RL4 1 2 4.7K_0402_5% +3V_LAN
+3V_LAN
@
PLT_RST#
<18,23,36,42> PLT_RST#
QCA8172-BL3A-R
.1U_0402_16V7K
1U_0402_6.3V6K
SA000065410
S IC QCA8172-BL3A-R QFN 40P E-LAN CTRL
CL10
CL8
1 1
UL1
C
Place Close to Chip 2 2
C
CL9 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_N1 29 38 RL12 10K_0402_5%

<15> PCIE_PRX_DTX_N1 TX_N LED_0 39 2 LDO@ 1 mount RL12 if use LDO modue
CL11 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_P1 30
Atheros LED_1 23
<15> PCIE_PRX_DTX_P1 TX_P LED_2
AR8151/AR8161 Place close to Pin16
36
<15> PCIE_PTX_C_DRX_N1 RX_N 12 MDI0- @
35 TRXN0 11 MDI0- <38>
MDI0+
<15> PCIE_PTX_C_DRX_P1 RX_P TRXP0 MDI0+ <38>
15 MDI1-
TRXN1 MDI1- <38>
32 14 MDI1+
<15> CLK_PCIE_LAN# 33 REFCLK_N TRXP1 18 MDI1+ <38>
<15> CLK_PCIE_LAN REFCLK_P TRXN2 17
PLT_RST# 2 TRXP2 21
PERST# TRXN3 20
PCIE_WAKE#_R 3 TRXP3 Place Close to PIN1
RL7 1 @ 2 0_0402_5% W AKE#
<42> LAN_WAKE# +3V_LAN
25 10 LAN_RBIAS 1 2
RL9 1 2 4.7K_0402_5% 26 SMCLK RBIAS RL8 2.37K_0402_1%
+3V_LAN SMDATA
@ Place Close to PIN1
28 1 +3V_LAN
NC VDD33
CL12
CL13
CL14
CL15
CL16
27
1000P_0402_50V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
Vendor recommand reseve the
.1U_0402_16V7K
1U_0402_6.3V6K
TESTMODE 1 1 1 1
2
PU resistor close LAN chip 40 +LX
LX +LX
LAN_XTALO 7
don't @ (could be B C cost done)
1
LAN_XTALI 8 XTLO RL10 30K_0402_5% 2 2 2 2
RL11 1 @ 2 4.7K_0402_5% XTLI 5 +1.7_VDDCT 1 2
+3V_LAN VDDCT/ISOLAN +3V_LAN
4
<15> CLKREQ_LAN# CLKREQ# 24 @ @
B DVDDL/PPS 37 +LX_R B
+1.1_AVDDL 13 DVDDL_REG/DVDDL
AVDDL +2.7_AVDDH @
+1.1_AVDDL 19
+1.1_AVDDL 31 AVDDL 16 +3V_LAN
+1.1_AVDDL_L 34 AVDDL AVDDH/AVDD33 22 +2.7_AVDDH
+1.1_AVDDL 6 AVDDL AVDDH 9 +2.7_AVDDH
AVDDL_REG/AVDDL AVDDH_REG
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
1U_0402_6.3V6K
CL17
CL18
CL19
CL20
CL21
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
1 1 1 1 1
CL22
CL23
CL24
CL25
CL26
41 1 1 1 1 1
GND
AR8162-BL3A-R_QFN40_5X5
2 2 2 Near 2 2 8162@
SA000052J20 2 2 2 2 2
Pin6 IC AR8162-BL3A-R QFN 40P E-LAN CTRL
@ @
Near
Near Near Near Near @
Near
Pin9
Pin13 Pin19 Pin31 Pin22 Pin37
LAN_XTALI
A YL1 LAN_XTALO A
4 3
NC OSC
1 2
OSC NC
1 25MHZ_10PF_7V25000014 1
CL28 CL29
15P_0402_50V8J 15P_0402_50V8J
2 2
LAN-AR8162/8172
1bios.ru
Lenovo 5 Custom 1.0
LA-9631P
5 4 3 2 1
5 4 3 2 1
ESD
@
DL1
Place Close to TL1 AZC099-04S.R7G_SOT23-6 Reserve gas tube for EMI go rural solution
MDI1+ 1 4 MDI0+
I/O1 I/O3
D D
DL1 2 5
1'S PN:SC300001G00
GND VDD
For EMI
2'S PN:SC300002E00 MDI0- 3
I/O2 I/O4
6 MDI1-
RL14 CL30
1 2 1 2
CHASSIS1_GND
75_0805_5% 10P_0603_50V
2 1
TL1
DLL1
MDI0+ 1 16 MDO0+ BS4200N-C-LV_SMB-F2
<37> MDI0+ 2 TD+ TX+ 15
MDI0- MDO0- GAS@
<37> MDI0- TD- TX-
3 14 MCT
4 CT CT 13
5 NC NC 12
NC NC Place Close to TL1
1 6 11 MCT
C CT CT C
MDI1+ 7 10 MDO1+
For EMI CL31
0.01U_0402_16V7K
<37> MDI1+
<37> MDI1-
MDI1- 8 RD+
RD-
RX+
RX-
9 MDO1-
2
MHPC_NS681612A For EMI
CL63 1 2 0.1U_0603_50V7K
CL61 1 2 0.1U_0603_50V7K
CL64 1 2 0.1U_0603_50V7K
CL65 1 2 0.1U_0603_50V7K
JLAN1 ESD
MDO0+ 1
PR1+ CHASSIS1_GND
B MDO0- 2 B
PR1-
MDO1+ 3
PR2+
MCT 4
PR3+
MCT 5
PR3-
MDO1- 6
PR2-
MCT 7 9
PR4+ GND 10
MCT 8 GND
PR4-
SANTA_130456-121
ME@ CHASSIS1_GND
A A

LAN_Transformer
Document Number Rev
B 1.0
LA-9631P
1bios.ru
5 4 3 2 1
5 4 3 2 1
2 Channel
D D
+3VGS
SMSC thermal sensor
C329
2 placed near PCH
.1U_0402_16V7K
@
1
U9 Lenovo 2
1 8 EC_SMB_CK2
<24> REMOTE1+ VDD SCLK EC_SMB_CK2 <15,24,42>
1
REMOTE1+ 2 7 EC_SMB_DA2
D+ SDATA EC_SMB_DA2 <15,24,42>
C587
2200P_0402_50V7K REMOTE1- 3 6
2 D- ALERT#
<24> REMOTE1-
C +3VGS
1 R335 2 4 5 C
THERM# GND
4.7K_0402_5%
@ EMC1402-2-ACZL-TR MSOP 8P
Address is 1001100xb
REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"
B B
CPU VGA_L VGA_R HDD

@ @ @ @
H1 H2 H3 H4 H5 H18 @ @ @ @
HOLEA
1 HOLEA HOLEA HOLEA HOLEA HOLEA FD1 FD2 FD3 FD4
1
FAN1 Conn
H_3P8 H_3P8 H_3P8 H_3P3 H_3P3 H_2P8
+5VS C
@
R581 JFAN1 A B
2 1 1 R
2 1 @ @ @ @ @ @
<42> EC_TACH 2
0_0603_5%<42> EC_FAN_PWM 3 H6 H7 H8 H10 H11 @ H17
4 3 HOLEA HOLEA HOLEA HOLEA HOLEA H16 HOLEA
5 4 HOLEA
2 G5
6
C591 G6
1
1
10U_0603_6.3V6M ACES_85205-04001
1
1 ME@
H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P5X3P5N H_3P0N
A
D E F A
2P8 * 9 pcd M/B 橢橢橢 M/B 橢橢

Compal Secret Data
Fintek-Thermal IC/FAN/screw
Custom 1.0
LA-9631P
5 4 3 2 1
A B C D E F G H
SATA HDD Conn.

Near Connector JHDD1
1
0.01U_0402_16V7K 2 1 C184 SATA_ITX_DRX_P0 2 GND
<14> SATA_ITX_C_DRX_P0 RX+
<14> SATA_ITX_C_DRX_N0 0.01U_0402_16V7K 2 1 C185 SATA_ITX_DRX_N0 3
4 RX-
SATA_DTX_C_IRX_N0 C596 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N0 5 GND
<14> SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 C597 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P0 6 TX-
<14> SATA_DTX_C_IRX_P0 7 TX+
GND
1 1
8
1 2 +3V_HDD 9 3.3V
+3VS 3.3V
R551 0_0805_5% 10
@ 11 3.3V
12 GND
13 GND
14 GND
1 2 +5V_HDD 15 5V
+5VS 5V
R550 0_0805_5% 16
@ 17 5V
18 GND
Near HDD 19 Reserved
+5VS 20 GND 23
21 12V GND 24
22 12V GND
12V
1 1 1
@ SUYIN_127043FB022G278ZR
C598 C599 C602
1000P_0402_50V7K .1U_0402_16V7K 10U_0603_6.3V6M
2 2 2
ODD Power Control

2 2
J9
1 2
1 2 +5V_ODD FOR 15"
+5VALW +5VS JUMP_43X79
SATA ODD FFC Conn.
Place CAP in Sub BD
S
3 1 JODD2
DVT 1
1
1
Q99 <14> SATA_ITX_C_DRX_P2 SATA_ITX_C_DRX_P2 R401 1 15@ 2 0_0402_5% SATA_ITX_DRX_P2_15 2

LP2301ALT1G_SOT23-3 SATA_ITX_C_DRX_N2 R402 1 15@ 2 0_0402_5% SATA_ITX_DRX_N2_15 3 2
G
<14> SATA_ITX_C_DRX_N2
2
R568 @ @ 4 3
10K_0402_5% R675 SATA_DTX_C_IRX_N2 R403 1 15@ 2 0_0402_5% SATA_DTX_IRX_N2_15 5 4
@ 100K_0402_5% <14> SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 R404 1 15@ 2 0_0402_5% SATA_DTX_IRX_P2_15 6 5
2
1 2 <14> SATA_DTX_C_IRX_P2 1 2 ODD_DETECT# 7 6

R710 @ 0_0402_5% +5V_ODD 8 7
1 8
1
1 9
C608 ODD_DA# 10 9
OUT
C607 10U_0603_6.3V6M <42> ODD_DA# 10 11

2 @ GND 12
0.01U_0402_16V7K GND
2 2 @ 1 R555 2
<19> ODD_EN IN +3VS
10K_0402_5% HB_A051020-SAHR21
GND
ME@
Q100
DTC124EKAT146_SC59-3
3
3 Co-lay 3
FOR 14"
SATA ODD Conn.
Near Connector JODD1
1
SATA_ITX_C_DRX_P2 14@ C616 1 2 0.01U_0402_16V7K SATA_ITX_DRX_P2_14 2 GND
SATA_ITX_C_DRX_N2 14@ C615 1 2 0.01U_0402_16V7K SATA_ITX_DRX_N2_14 3 A+
4 A-
SATA_DTX_C_IRX_N2 14@ C614 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N2_14 5 GND
SATA_DTX_C_IRX_P2 14@ C613 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P2_14 6 B-
7 B+
GND
ODD_DETECT# 8
+5V_ODD 9 DP
10 +5V
ODD_DA# 11 +5V
12 MD 15
13 GND GND 14
GND GND
4 ALLTO_C18518-11305-L 4
ME@

Compal Secret Data
HDD/ODD/BT Connector
Custom 1.0
LA-9631P
A B C D E F G H
5 4 3 2 1
CX20751 Sense resistors must be

connected same power
High Definition Audio Codec SoC that is used for VAUX_3.3
With Integrated Class-D Stereo
RA5 1 2 5.11K_0402_1%
Amplifier. +3VS
An integrated 5 V to 3.3 V Low-dropout RA6 10K_0402_1%

mount RA6 on the Jack Sense circuit
voltage regulator (LDO). 1 2 to configure Port-C for mono MIC.
Lenovo 1
An integrated 3.3 V to 1.8V Low-dropout JSENSE RA7 1 2 20K_0402_1% Don't support LINE_IN function
voltage regulator (LDO). RA8 1 2 39.2K_0402_1% PLUG_IN
RA7 could be @
+VREF_1V65 CA3 vendor suggest For Universal jack
D change to 2.2U D
+LDO_OUT_3.3V
RA1 1 @ 2 0_0402_5% +3V_AVDD_HP
1U_0603_10V4Z
.1U_0402_16V7K
.1U_0402_16V7K
+3VLP
2.2U_0603_6.3V4Z
1 1 2 1 AVDD_3.3 pinis output of
1 2 0_0402_5%
CA1
CA2
CA4
RA2 @
.1U_0402_16V7K
internal LDO. NOT connect
4.7U_0603_6.3V6K
+3V_PCH
CA3
1 1 to external supply.
CA5
CA6
2 2 1 2
2 @ 2
+3VS
+3VS
.1U_0402_16V7K
.1U_0402_16V7K
1U_0603_10V4Z
1U_0603_10V4Z
1 1
CA8
CA9
1 1
CA15
CA10
Should be same supply rail as used for @
@ 2 2 Layout Note:Path from +5VS to LPWR_5.0
PCH HDA bus controller section 2 2
RPWR_5.0 must be very low
resistance (<0.01 ohms)
RA3
ESD +3VS 1 @ 2 0_0402_5%
.1U_0402_16V7K
4.7U_0603_6.3V6K
+3VS +5VS
+3V_PCH RA4 1 @ 2 0_0402_5% 1 1
CA16 +LDO_1.8V
CA17
.1U_0402_16V7K
4.7U_0603_6.3V6K
+5VS
1 1
CA18
CA20
10 mils
.1U_0402_16V7K
.1U_0402_16V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
@ @ 2 2
1 1 1 1
CA19
CA21
CA22
CA23
RA15 @
.1U_0402_16V7K
4.7U_0603_6.3V6K
4.7K_0402_5% 2 2
1 1
@ Combo Jack
CA24
CA25
For EMI 2 2 2 2
For EMI (Normal Open)

2
HGNDA, HGNDB 80mils
.1U_0402_16V7K
HDA_RST_AUDIO# @ 2 2 For Layout For Layout
18
29
27
28
24
C 1 C
3
7
2
CA26
1 CA7 @ UA1
@ 1 RA21 2 JHP1
FILT_1.8
VDDO_3.3
DVDD_3.3
AVDD_3.3
VDD_IO
VREF_1.65V
AVDD_5V
AVDD_HP
CA11 Please bypass caps very close to device. APPLE_MIC RA16 1 2 100_0402_1% CA28 1 2 2.2U_0402_6.3V6M HGNDB 4
.1U_0402_16V7K 22P_0402_50V8J 33_0402_5% 13 2 NOKIA_MIC RA12 1 2 100_0402_1% CA27 1 2 2.2U_0402_6.3V6M HGNDA 3
2 LPWR_5.0 16 HP_L RA13 1 2 15_0402_5% HPOUT_L 1
HDA_RST_AUDIO# 9 RPWR_5.0 11 HP_R RA14 1 2 15_0402_5% HPOUT_R 2
<14> HDA_RST_AUDIO# RESET# CLASS-D_REF
HDA_BITCLK_AUDIO 5 PLUG_IN 5
<14> HDA_BITCLK_AUDIO BIT_CLK
HDA_SYNC_AUDIO 8 38 JSENSE
<14> HDA_SYNC_AUDIO SYNC JSENSE
RA9 1 2 33_0402_5% 6 6
<14> HDA_SDIN0 SDATA_IN
HDA_SDOUT_AUDIO 4 34
<14> HDA_SDOUT_AUDIO SDATA_OUT MICBIASB 35
+MICBIASB For Universal jack SINGA_2SJ2352-000131F
MICBIASC +MICBIASC
ME@
PC_BEEP 10 32 MICB_L
39 PC_BEEP PORTB_L_LINE 33 MICB_R Lenovo 6
<42> EC_MUTE# SPKR_MUTE# PORTB_R_LINE Universal Jack
30 APPLE_MIC External MIC CA36
PORTD_A_MIC 31 NOKIA_MIC MICB_L RA17 1 2 100_0402_1% 1 2 HP_L
1 PORTD_B_MIC 25 HGNDA 2.2U_0402_6.3V6M
40 DMIC_DAT/GPIO1 HGNDA 26 HGNDB CA46
For EMI MIC_IN 36
DMIC_CLK / MUSIC_REQ/GPIO0 HGNDB
22 HP_L
MICB_R RA18 1
RA20 1
2 100_0402_1%
2 3K_0402_5%
1 2
2.2U_0402_6.3V6M
HP_R
Internal analog MIC 37 MUSIC_REQ/GPIO0/PORTC_L_MIC PORTA_L 23 HP_R

GPIO1/PORTC_R_MIC PORTA_R Headphone RA19 1 2 3K_0402_5%
+MICBIASB
CA64 1 2 .1U_0402_16V7K
SPK_L2+ 12 ESD
CA65 1 2 .1U_0402_16V7K SPK_L1- 14 LEFT+
LEFT-
Internal SPEAKER 21 HPOUT_L HPOUT_L
CA66 1 2 .1U_0402_16V7K SPK_R2+ 17 AVEE 19
SPK_R1- 15 RIGHT+ FLY_P 20 1 2 HPOUT_R HPOUT_R
.1U_0402_16V7K
2.2U_0603_6.3V4Z
RIGHT- FLY_N CA29 1U_0603_10V4Z 1 2
CA35
CA30
HGNDB HGNDB
GND
HGNDA HGNDA
B 2 1 B
CX20751-11Z_QFN40
41
2
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
For EMI
1
DA1 DA2
CA31
CA32
CA33
CA34
@ @
1
LA1 LA2
0_0603_5% 0_0603_5%
@ @
LA3 LA4
PC Beep Lenovo 3 0_0603_5% 0_0603_5%
EC Beep
wide 20MIL @ @
JSPK1
<42> BEEP# 1 2 RA492
CA37 .1U_0402_16V7K 1 2 PC_BEEP SPK_R1- LA1 1 2 FCM1608CF-121T03 0603 SPK_R1-_CONN 1
1 2 33_0402_5% SPK_R2+ LA2 1 2 FCM1608CF-121T03 0603 SPK_R2+_CONN 2 1
<14> HDA_SPKR 2
CA45 .1U_0402_16V7K SPK_L1- LA3 1 2 FCM1608CF-121T03 0603 SPK_L1-_CONN 3
ICH Beep Place colose to Codec chip SPK_L2+ LA4 1 2 FCM1608CF-121T03 0603 SPK_L2+_CONN 4 3
5 4
G5
1
6
For EMI
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
@ G6
RA22 +MICBIASC +5VS
1 1 1 1
10K_0402_5% ME@
CA38
CA39
CA40
CA43
ESD
2
DA3
RA23 2 2 2 2 SPK_R1-_CONN 6 3 SPK_L2+_CONN ACES_85205-04001
2.2K_0402_5% For EMI I/O4 I/O2
2
MIC1 CA41 1U_0603_10V4Z 5 2

A 1 MIC_IN_C 1 2 MIC_IN VDD GND A
2 GNDA
1 1
WM-64PCY_2P SPK_R2+_CONN 4 1 SPK_L1-_CONN
.1U_0402_16V7K
.1U_0402_16V7K
@ I/O3 I/O1
AZC099-04S.R7G_SOT23-6
1bios.ru
2 2
CA42
CA44
@ @
CX20751 Codec
Custom 1.0
LA-9631P
Date: Tuesday, March 05, 2013 Sheet 41 of 60
5 4 3 2 1
+3VALW +3VLP
@
R304 @ R416 3.3V
1 2 +3V_EC 1 2
Vcc Board ID / SKU ID Table for AD channel
0_0603_5% 1@ 100K +/- 1%
0_0603_5% C535
R694
100P_0402_50V8J Board ID R695 VAD_BID min V AD_BID typ VAD_BID max EC AD
L44 2
FBM-11-160808-601-T_0603
0 0 0 V 0 V 0 V 0x00 - 0x0B MP
1 1 1 1
+EC_VCCA
.1U_0402_16V7K
C653
.1U_0402_16V7K
C654
1000P_0402_50V7K
C662
1000P_0402_50V7K
C658
1 2 12K +/- 1%
+3V_EC 1 1
+EC_VCCA 1 0.347V 0.354V 0.360V 0x0C - 0x1C PVT
C659 @ 15K +/- 1%
C656 2 2 @ 2 @ 2 2 0.423V 0.430V 0.438V 0x1D - 0x26 DVT
111
125
.1U_0402_16V7K 1000P_0402_50V7K U31 20K +/- 1%
3 0.541V 0.550V 0.559V 0x27 - 0x30 EVT
22
33
96
67
9
1 2 2 ECAGND 2
L45
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
FBM-11-160808-601-T_0603
ECAGND
1 21 ADP_65
<19> GATEA20 GATEA20/GPIO00 GPIO0F ADP_65 <47>
2 23 BEEP# +3VALW
<19> KBRST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# <41>
3 26 EC_FAN_PWM
<14> SERIRQ SERIRQ GPIO12 EC_FAN_PWM <39>
4 27 ACOFF
<14> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF <48>
LPC_AD3 5
<14> LPC_AD3
2
LPC_AD2 7 LPC_AD3
<14> LPC_AD2 LPC_AD2 PWM Output
LPC_AD1 8 63 BATT_TEMP @
<14> LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP <46,47>
LPC_AD0 10 LPC & MISC 64 R694
<14> LPC_AD0 LPC_AD0 GPIO39 GPU_IMON <53>
2 1 2 1 65 +5VALW 100K_0402_1%
ADP_I/GPIO3A ADP_I <47,48>
@ C660 22P_0402_50V8J @ R589 10_0402_5% 12 AD Input 66 ADP_ID
<18> CLK_PCI_EC ADP_ID <46>
1
13 CLK_PCI_EC GPIO3B 75 BRDID BRDID R695 PVT2@
<18,23,36,37> PLT_RST# PCIRST#/GPIO05 GPIO42
1 2 EC_RST# 37 76 20K_0402_1%
+3V_EC ENBKL <17>
2
R590 47K_0402_5% EC_SCI# 20 EC_RST# IMON/GPIO43 R695 PVT@
<19> EC_SCI# EC_SCII#/GPIO0E
2 BATT_LEN# 38 R594 R695 12K_0402_1%
<47> BATT_LEN# GPIO1D 68 ADP_90 USB_ON# 1 2 100K_0402_1% R695 DVT@
DAC_BRIG/GPIO3C ADP_90 <47>
C661 70 15K_0402_1%
.1U_0402_16V7K EN_DFAN1/GPIO3D 71 10K_0402_5%
DA Output +3VALW
1
1
1 KSI0 55 IREF/GPIO3E 72
C47 KSI1 56 KSI0/GPIO30 CHGVADJ/GPIO3F @
22P_0402_50V8J KSI2 57 KSI1/GPIO31 EC_MUTE# 1 R593 2 10K_0402_5%
2
KSO[0..15] KSI3 58 KSI2/GPIO32 83 +5VS +5VS

<43> KSO[0..15] KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <41>
KSI4 59 84 USB_ON#
KSI[0..7] KSI4/GPIO34 USB_EN#/GPIO4B USB_ON# <44>
KSI5 60 85 ADP_135
<43> KSI[0..7] KSI5/GPIO35 CAP_INT#/GPIO4C ADP_135 <47>
KSI6 61 PS2 Interface 86 SYS_PWROK_R R417 1 @ 2 0_0402_5%
KSI6/GPIO36 EAPD/GPIO4D SYS_PWROK <16>
ESD KSI7 62 87 TP_CLK R603 1 2 4.7K_0402_5%
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <43>
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <43>
+3V_EC KSO1 40 TP_CLK
KSO2 41 KSO1/GPIO21
R600 KSO3 42 KSO2/GPIO22 97 EC_TS_ON# R598 1 2 4.7K_0402_5%
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 EC_TS_ON# <44>
1 2 EC_SMB_CK1 KSO4 43 98
2.2K_0402_5% KSO5 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 TP_DATA
R604 KSO6 45 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 109
ME_FLASH <14>
1 2 EC_SMB_DA1 KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 NTC_V <47>
KSO7/GPIO27 SPI Device Interface
2.2K_0402_5% KSO8 47
KSO9 48 KSO8/GPIO28 119 EC_SPI_SO BATT_TEMP 1 2
KSO9/GPIO29 SPIDI/GPIO5B EC_SPI_SO <14>
KSO10 49 120 EC_SPI_SI C663 100P_0402_50V8J
KSO10/GPIO2A SPIDO/GPIO5C EC_SPI_SI <14>
EC_SMB_DA2 KSO11 50 SPI Flash ROM 126 EC_SPI_CLK ACIN 1 2
KSO11/GPIO2B SPICLK/GPIO58 EC_SPI_CLK <14>
EC_SMB_CK2 KSO12 51 128 EC_SPI_CS# C664 100P_0402_50V8J
KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS# <14>
1 1 KSO13 52 1 2
@ @ KSO14 53 KSO13/GPIO2D R522 @ 4.7K_0402_5%
C665 C666 KSO15 54 KSO14/GPIO2E 73
KSO15/GPIO2F ENBKL/GPIO40 IMVP_IMON <54>
100P_0402_50V8J 100P_0402_50V8J KSO16 81 74
2 2 <43> KSO16 KSO16/GPIO48 PECI_KB930/GPIO41 VGATE <16,54>
KSO17 82 89
<43> KSO17 KSO17/GPIO49 FSTCHG/GPIO50 LAN_PWR_ON# <37>
90 BATT_CHG_LED#
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# <43>
91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# <43>
+3VALW EC_SMB_CK1 77 GPIO 92
<47,48> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# <43>
EC_SMB_DA1 78 93 BATT_LOW_LED#
<47,48> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# <43>
EC_SMB_CK2 79 SM Bus 95 SYSON
<15,24,39> EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <50>
EC_SMB_DA2 80 121
<15,24,39> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON <54>
127 PM_SLP_S4# <16>
1 2 LAN_WAKE# PM_SLP_S4#/GPIO59
R606 10K_0402_5% H_PROCHOT# <46,47,54,6>
6 100
<16> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# <16>
14 101 EC_LID_OUT#
<16> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <19>
1
EC_SMI# 15 102 Turbo_V D
<16,19> EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 Turbo_V <47>
16 103 PROCHOT 2 1
<33> CMOS_ON# GPIO0A H_PROCHOT#_EC/GPXIOA06 PROCHOT <47>
+3VS 17 104 MAINPWON_R R738 1 @ 2 0_0402_5% G
GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON <49>
18 GPO 105 BKOFF# Q37 S C493
<53> EC_VGA_EN BKOFF# <33>
3
ODD_DA# 19 GPIO0C BKOFF#/GPXIOA08 106 PBTN_OUT# 2N7002H_SOT23-3 47P_0402_50V8J
<40> ODD_DA# GPIO0D GPIO PBTN_OUT#/GPXIOA09 PBTN_OUT# <16> 2
25 107 PCH_PWR_EN
<46> ADP_ID_CLOSE EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 PCH_PWR_EN <20>
1 2 EC_TACH EC_TACH 28 108 SA_PGOOD <51>
<39> EC_TACH FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
R605 10K_0402_5% LAN_WAKE# 29 +3VALW
<37> LAN_WAKE# EC_PME#/GPIO15
EC_TX 30
<36,43> EC_TX EC_TX/GPIO16
EC_RX 31 110 ACIN
<36,43> EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN <16,24,46,48>
PCH_PWROK 32 112 EC_ON
<16> PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <49>
NOVO# 34 114 ON/OFF <43>
<43> NOVO# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03
36 GPI 115 LID_SW# LID_SW# 1 R618 2
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <43>
2 R608 1 NUM_LED#: NC 116 SUSP# 100K_0402_5%
SUSP#/GPXIOD05 SUSP# <45,50,52>
100K_0402_5% 117 NUVOTON_VTT
@ GPXIOD06 118 PECI_KB9012
PECI_KB9012/GPXIOD07
AGND/AGND
122
<16> SUSCLK XCLKI/GPIO5D
GND/GND
GND/GND
GND/GND
GND/GND
Share ROM 123 124 +V18R 1 2

<18,25,51,53> DGPU_PWR_EN XCLKO/GPIO5E V18R H_PECI <6>
C667
4.7U_0603_6.3V6K 1 R669 43_0402_1% +V1.05S_VCCP
1
GND0
1
@ @
R740 C93
100K_0402_5% 20P_0402_50V8 KB9012QF A3 LQFP 128P_14X14 2 NUVOTON_VTT R410 1 @ 2 0_0402_5%
2
11
24
35
94
113
69
2
ECAGND
EMC Request
SYSON
C492
.1U_0402_16V7K
SA00004OB30 1
S IC KB9012QF A4 LQFP 128P KB CONTROLLER @
1bios.ru
BIOS & EC I/O Port
Custom 1.0
LA-9631P
KSI[0..7]
KSI[0..7] <42>
JKB1 ME@
KSO[0..17] KSI1 1 JKB2 ME@
KSO[0..17] <42> 2 1 26
KSI7
KSI6 3 2 25 GND2
KSO9 4 3 GND1
KSI4 5 4 KSI1 24
JP3 KSI5 6 5 KSI7 23 24
1 KSO0 7 6 KSI6 22 23
+3VALW 1 7 22
2 KSI2 8 KSO9 21
<36,42> EC_TX 2 8 21
3 KSI3 9 KSI4 20
<36,42> EC_RX 4 3 10 9 19 20
KSO5 KSI5
4 KSO1 11 10 KSO0 18 19
ACES_85205-0400 KSI0 12 11 KSI2 17 18
12 17
ME@ +3VLP KSO2 13
13
KSI3 16
16
KSO4 14 KSO5 15
KSO7 15 14 KSO1 14 15
15 14
2
@ KSO8 16 KSI0 13
R415 KSO6 17 16 KSO2 12 13
100K_0402_5% KSO3 18 17 KSO4 11 12
KSO12 19 18 KSO7 10 11
@ KSO13 20 19 KSO8 9 10
1
1 R414 2 KSO14 21 20 KSO6 8 9
0_0402_5% KSO11 22 21 KSO3 7 8
KSO10 23 22 KSO12 6 7
23 6
+3VALW KSO15 24
24
KSO13 5
5
KSO16 25 KSO14 4
<42,43> KSO16 25 4
KSO17 26 KSO11 3
<42,43> KSO17 26 3
2
+3VLP 27 KSO10 2
R642 28 27 KSO15 1 2
100K_0402_5% 29 28 31 1
J12 29 GND
2
@ 30 32 ACES_88514-2401
1 2 30 GND
1
R701 D26 ACES_88514-3001
SHORT PADS 100K_0402_5% NOVO# 2
<42> NOVO#
1 NOVO_BTN#
1 3
ON/OFF
J11 DAN202UT106_SC70-3
@
1 2
SHORT PADS
ON/OFF +3VS
ON/OFF <42>
For EMI
LED1 14@ JCR1
1
PWR_LED# 1 2 2 14@ 1 USB20_N11 1 R687@ 2 0_0402_5% USB20_N11_R 2 1
<42> PWR_LED# +5VALW <18> USB20_N11 2
R623 649_0402_1% USB20_P11 1 R683@ 2 0_0402_5% USB20_P11_R 3
<18> USB20_P11 4 3
19-213A-T1D-CP2Q2HY-3T_WHITE 4
5
GND 6
L57 @ GND
USB20_N11 1 2 USB20_N11_R
1 2 CVILU_CF06041H0RB-NH
ME@
USB20_P11 4 3 USB20_P11_R
4 3
+5VS
LED2 14@ WCM-2012-900T_4P
BATT_LOW_LED# 1 2 2 R764 1
<42> BATT_LOW_LED# +3VALW
470_0402_5%
@ JTP1 ME@ 14@
C696 HT-191UD5_AMBER
8
.1U_0402_16V7K 7 GND
GND
6
TP_CLK 5 6
<42> TP_CLK 5
TP_DATA 4
<42> TP_DATA 4
1 1 TP_3 3
TP_2 2 3
@ C697 C698 @ TP_1 1 2 LED5 14@ +3VALW
100P_0402_50V8J 100P_0402_50V8J 1
2 2 ACES_88058-060N BATT_CHG_LED# 1 2 2 14@ 1
<42> BATT_CHG_LED# +5VALW JPWRB1
3
Lenovo 1 R765 649_0402_1%

C490
C491
.1U_0402_16V7K
.1U_0402_16V7K
1 1 1
15@ 19-213A-T1D-CP2Q2HY-3T_WHITE 2 1
2 R627 1 <42> LID_SW# 3 2
@ D15 TP_3 NOVO_BTN#
PSOT24C_SOT23-3 0_0402_5% @ @ ON/OFF 4 3
2 2 5 4
1
2 R619 1 14@ TP_1 6 5

6
2
0_0402_5%
7
8 GND
D24 GND
ESD
LED6 14@ ACES_88058-060N
L30ESD24VC3-2 3P C/A SOT23 ESD ME@
1
CAPS_LED# 1 2 2 14@ 1
L R <42> CAPS_LED#
R2 649_0402_1%
+5VS
19-213A-T1D-CP2Q2HY-3T_WHITE
SW4 14@ SW5 14@ ESD
SMT1-05_4P SMT1-05_4P
15/17" 14"
5
6
5
6
4 2 4 2
TP_3 TP_2
1 VCC 1 VCC
3 1 3 1
2 CLK 2 CLK JLED1
1
+5VALW 1
2
3 DAT 3 DAT +3VALW
3 2
+5VS 3
LID_SW# 4
5 4
SW6 15@ SW7 15@
4 GND 4 L PWR_LED# 6 5
SMT1-05_4P SMT1-05_4P BATT_LOW_LED# 7 6
7
5
6
5
6
BATT_CHG_LED# 8
4 2 4 2
5 L 5 R CAPS_LED# 9 8
TP_2 TP_1 10 9
3 1 3 1 10
GND 11
6 R 6 12 GND
GND
HB_A091020-SAHR21
ME@
For 15"

Compal Secret Data
ROM/KBD/PWR/CR/LED/TP Conn.
C 1.0
LA-9631P
5 4 3 2 1
ESD
D27 D30 D22 D31
@ @ @ @
U3RXDN1 9 10 1 1 U3RXDN1 U3RXDN2 9 10 1 1U3RXDN2 U2DN1 3 6 U2DP2 3 6
I/O2 I/O4 I/O2 I/O4
U3RXDP1 8 9 2 2 U3RXDP1 U3RXDP2 8 9 2 2U3RXDP2
U3TXDN1 7 7 4 4 U3TXDN1 U3TXDN2 7 7 4 4U3TXDN2 2 5 +5VALW 2 5 +5VALW

GND VDD GND VDD
U3TXDP1 6 6 5 5 U3TXDP1 U3TXDP2 6 6 5 5U3TXDP2
3 3 3 3 1 4 U2DP1 1 4 U2DN2
I/O1 I/O3 I/O1 I/O3
8 8
AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6
D
YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9 D
For EMI
USB3.0 Intel_PCH_USB2.0
WCM-2012HS-900T
1 2 U2DN2
<18> USB20_N1 1 2
4 3 U2DP2
<18> USB20_P1 4 USB2@ 3
L55
Ext. USB2.0 Touch Screen Left Ext.USB Conn. 2

Intel_PCH_USB3.0
+5VALW WCM-2012HS-900T +USB3_VCCA
+USB_VCCB 1 2 U3RXDN2
<18> USB3_RX2_N 1 2
RIGHT USB PORT X1 W=80mils
4 3 U3RXDP2 JUSB2
<18> USB3_RX2_P 4
U36 USB3@ 3 U3TXDP2 9
1 8 L54 1 SSTX+
2 GND VOUT 7 U3TXDN2 8 VBUS
3 VIN VOUT 6 U2DP2 3 SSTX-
4 VIN VOUT 5 JTS1 7 D+
<42,44> USB_ON# EN FLG USB_OC4# <18> GND
8 U2DN2 2 10
G547I2P81U_MSOP8 7 GND U3RXDP2 6 D- GND 11
6 GND C850USB3@ 4 SSRX+ GND 12
C +3VS_TS 6 WCM-2012HS-900T GND GND 13 C
5 .1U_0402_16V7K U3RXDN2 5
4 5 1 2 U3TXDN2_L 1 2 U3TXDN2 SSRX- GND
<18> USB20_N2 4 <18> USB3_TX2_N 1 2
3 TAITW_PUBAU1-09FNLSCNN4H0
<18> USB20_P2 3
2 ME@
EC_TS_ON# R726 1 TS@ 2 0_0402_5% TS_RST# 1 2 1 2 U3TXDP2_L 4 3 U3TXDP2
1 <18> USB3_TX2_P 4 USB3@ 3 Near HDMI Conn.
ACES_50208-00601-P01 C848 USB3@ L53
ME@ .1U_0402_16V7K USB Debug Port
Right Ext.USB Conn.

JUSB3 ME@
+3VS +3VS_TS
Intel_PCH_USB2.0
8
+USB_VCCB 7 GND WCM-2012HS-900T
W=80mils GND 1 2 U2DN1
<18> USB20_N0 1 2
6 1 TS@ 2
+USB_VCCB 5 6 R5583 0_0402_5%
4 5 4 3 U2DP1
1 4 <18> USB20_P0 4 3
1 USB20_N9 R868 2 @ 1 0_0402_5% USB20_N9_C 3 USB2@
+ <18> USB20_N9 3 L51
R869 2 1 0_0402_5% 2 3 1
D
C714 @ USB20_P9 @ USB20_P9_C
<18> USB20_P9 2
220U_6.3V_M C715 1
470P_0402_50V7K 1
2
2 2 @ @ ACES_88058-060N R5581 @ Q156
G
Left Ext.USB Conn. 1
2
R503 R504 100K_0402_5% LP2301ALT1G_SOT23-3
.1U_0402_16V7K
10_0402_5% 10_0402_5% 1 2 @ Intel_PCH_USB3.0
<42> EC_TS_ON#
C1322
USB20_N9 4 3 USB20_N9_C 1 2
4 3 WCM-2012HS-900T +USB3_VCCA
1
C1331 1 2 U3RXDN1
<18> USB3_RX1_N 1 2
USB20_P9 1 2 USB20_P9_C 1 1 .1U_0402_16V7K TS@ W=80mils
1 2 @ @ 2 1
L66 @
WCM-2012HS-900T C1 C2 4 3 U3RXDP1 JUSB1
<18> USB3_RX1_P 4 3
1.2P_0402_50V8C 1.2P_0402_50V8C USB3@ U3TXDP1 9
2 2 L50 1 SSTX+
B VBUS B
U3TXDN1 8
For EMI U2DP1
U2DN1
3
7
2
SSTX-
D+
GND 10
U3RXDP1 6 D- GND 11
C849USB3@ 4 SSRX+ GND 12
.1U_0402_16V7K WCM-2012HS-900T U3RXDN1 5 GND GND 13
1 2 U3TXDN1_L 1 2 U3TXDN1 SSRX- GND
<18> USB3_TX1_N 1 2 TAITW_PUBAU1-09FNLSCNN4H0
ME@
1 2 U3TXDP1_L 4 3 U3TXDP1
<18> USB3_TX1_P 4 3
USB3@ Near Audio Jack
C847USB3@ L49
.1U_0402_16V7K
Place TX AC coupling Cap (C843~C850). Close to connector
2A/Active Low
+5VALW +USB3_VCCA
U35 W=80mils
1 8
2 GND VOUT 7
3 VIN VOUT 6
USB_ON# 4 VIN VOUT 5
<42,44> USB_ON# EN FLG USB_OC0# <18>
G547I2P81U_MSOP8
1
1
+ @
A
C736 C735 A
220U_6.3V_M 470P_0402_50V7K
2 2

2011/06/15 2012/07/11 Title
USB3.0/Left USB Ports
Custom 1.0
5 4 3 2 1
1bios.ru
A B C D E
+5VALW to +5VS
+3VALW to +3VS
+5VALW +5VS +3VALW +3VS
U38
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
U39
DMN3030LSS-13_SOP8L-8 DMN3030LSS-13_SOP8L-8
8 1 8 1
C720
C721
C723
C724
1 1 7 2 1 1 1 7 2 1 1 1
1
6 3 @ 6 3 @
5 C722 5 C725
@ 1U_0603_10V4Z R644 1U_0603_10V4Z R645
2 @ 2 2 470_0603_5% 2@ 2 @ 2 470_0603_5%
4
@ @
1 2
1 2
B+ B+
D D
2 SUSP 2 SUSP
1
1
G G
R646 S Q107 S Q108
3
150K_0402_5% 2N7002H_SOT23-3 R647 2N7002H_SOT23-3
@ 470K_0402_1% @
2
2
5VS_GATE2 R649 15VS_GATE_R
2
DVT DVT
1
1
D D R650
SUSP 2 Q110 82K_0402_5% C726 SUSP 2 Q111 C727
0_0402_5%
G 2N7002H_SOT23-3 2200P_0402_25V7K G 2N7002H_SOT23-3 2200P_0402_25V7K
2
S S @
3
1
2 2
+1.5V to +1.5VS
+V1.05S_VCCP +0.75VS
+1.5V Q8 +1.5VS
1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
LP2301ALT1G_SOT23-3
3 1
D
R659 R658
C717
C718
470_0603_5% 22_0603_5% 1 1 1
1
@
1 2
1 2
@ C719
G
2
D D @ 1U_0603_10V4Z R643
2 SUSP 2 SUSP 2 2 2 470_0603_5%
G G DVT @
2
S Q116 S Q115
3
2N7002H_SOT23-3 2N7002H_SOT23-3
1
@ +3VALW D
2 SUSP
G
1
S Q109
3
2N7002H_SOT23-3
100K_0402_5% @
R648
R651
.1U_0402_16V7K
1 2 1.5VS_GATE
+RTCVCC +3VLP
C729
Q112 1
1
D 0_0402_5%
3 3
SUSP# 2 @
2
@ G
R652 R653 2N7002H_SOT23-3 S 2
3
220K_0402_5% 220K_0402_5%
1
SUSP
<10> SUSP
Q117
1
DTC124EKAT146_SC59-3
OUT
2
<42,50,52> SUSP# IN
GND
1
R1110 @
100K_0402_5%
2
4 4

Compal Secret Data
DC Interface
Custom 1.0
LA-9631P
A B C D E
5 4 3 2 1
VIN
PF101
7A_24VDC_429007.WRML PL101
JDCIN1 SMB3025500YA_2P
1 APDIN 1 2 APDIN1 1 2
1 2
D 2 3 D
3
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
4
4 5
5
1
PC101
PC102
PC103
PC104
ACES_50312-00541-001
@
2
PQ102A
PR102 2N7002KDW-2N_SOT363-6
1 2 6 1
+3VALW ADP_ID <42>
750_0402_1%
680P_0402_50V7K
0.1U_0402_16V7K
2
PR110
1
1
PC108
PC109
1 2
C VIN C
2
2
100K_0402_1%
3
2
2N7002KDW-2N_SOT363-6
PQ102B
PR111
100K_0402_1% 5
ADP_ID_CLOSE <42>
1
+5VS
+3VALW
47K_0402_1%
<42,47,54,6> H_PROCHOT# @
PR106
@
10K_0402_1%
2N7002KDW-2N_SOT363-6
PU101A
PR108
AS393MTR-E1 SO 8P OP
+CHGRTC
8
@
B @ PC105 3 BATT_TEMP <42,47> B
P
+
PQ101A
2 2 1 1
1N4148WS-7-F_SOD323-2
PR103
1
1K_0603_5% O 2
-
G
1.5M_0402_5%
1 2 0.022U_0402_16V7K
+3VLP
1
100K_0402_1%
100P_0402_50V8J
PD101
1
PR104
S SCH DIO BAS40CW SOT-323 @ @
+CHGRTC_R
PD105
PR109
2 @
PC107
+RTCBATT 1
2
3 PR101 2 @
1
1K_0603_5% JRTC1 @
1 2 1 @ +5VS
2 1
3 2
4 GND
GND
H_PROCHOT#
RTC Battery
47K_0402_1%
ACES_50271-0020N-001
@
PR107
2N7002KDW-2N_SOT363-6
3
8
PC106 5
P
+
PQ101B
5 2 1 7
O 6 ACIN <16,24,42,48>
1N4148WS-7-F_SOD323-2
G
0.022U_0402_16V7K
4
1.5M_0402_5%
@ PU101B
4
@ AS393MTR-E1 SO 8P OP
PD104
PR105
@
2
A A

Compal Secret Data
PWR DCIN / RTC Battery
Custom 1.0
Gx00
5 4 3 2 1
5 4 3 2 1
VMB2 90W(DIS) : 6.65K 100W active 90W recovery

@ PF201
VMB
PL201 JBATT1 ---> 15" PH201 under CPU botten side :
65W(UMA): 1.65K 70W active 65W recovery
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
CPU thermal protection at 93 +-3 degree C
SUYIN_200082GR007M229ZR
1 1 2 1 2
1 2 BATT+
2 3
3 4
EC_SMCA JBATT2 ---> 14" Recovery at 56 +-3 degree C 20120314
Change to +EC_VCCA from +3VLP
EC_SMDA
4 5
5 6
6 7
1
7 8
1
100_0402_1%
100_0402_1%
GND 9 PC201 PC203
GND 1000P_0402_50V7K 0.01U_0402_25V7K
2
PR201
PR204
D D
2
<42,48> ADP_I
+EC_VCCA
+3VS
2
8.45K_0402_1%
EC_SMB_CK1 <42,48>
1
PR221
12.7K_0402_1%
EC_SMB_DA1 <42,48>
100K_0402_1%
PR226
JBATT2
SUYIN_200082GR007M229ZR
1
PR215
@ @
1 <42> Turbo_V
<42,46,54,6> H_PROCHOT#
2
1 2 @
2 3 1 2
+3VLP
1
3 4 PR209 PQ201 <42> NTC_V
4
2
D
100K_0402_1%_TSM0B104F4251RZ
@
25.5K_0402_1%
9.31K_0402_1%
5.9K_0402_1%
5 6.49K_0402_1%
5
2
6 @ 2 ADP_OCP_1 PR229
6
PR225
PR227
PR228
7 G 100K_0402_1%
7 8 1 2 PR222
+3VALW S
3
GND
1
9 PR206 2N7002KW_SOT323-3 100K_0402_1%
1
GND
PH201
6.49K_0402_1%
1
2N7002KW_SOT323-3
PR216
1 2 0_0402_5%
BATT_TEMP <42,46,47> <42,47> PROCHOT 1 2 <42,47> PROCHOT
PR207
2
1
D
PQ206
10K_0402_5%
A/D @
2N7002KW_SOT323-3
2
<42> ADP_65 G
S
2N7002KW_SOT323-3
1
D
+3VALW
PQ208
2
<42> ADP_90 G
PQ207
C C
S
3
VL
1
D
2
2
<42> ADP_135 G
VL PR214 S
3
2
PC202 PR211 100K_0402_1%
1
6 1
1
0.01U_0402_25V7K 100K_0402_1%
BATT_OUT <48>
PR202 PR210
2
1
2
75K_0402_1% 47K_0402_1% ECAGND

PQ202A
2 2N7002KDW-2N_SOT363-6
2
3
PC208
1
1
8
<42,46,47> BATT_TEMP 0.068U_0402_16V7K~N

3 PQ202B
P
+ 1 1 2 5 2N7002KDW-2N_SOT363-6
2 O
1N4148WS-7-F_SOD323-2
-
G
PU201A
4
2
4
2
PD201
PR213 PR205
1
100K_0402_1%
PC207 1.5M_0402_5%
1
100P_0402_50V8J
1
+3VLP
2
PR220
B B
100K_0402_1%
VMB +3V_LDO VL
1
1
D
2 PQ205
<42> BATT_LEN#
G 2N7002KW_SOT323-3
75K_0402_1%
3
2
1
@ PR208
@ PR218
1
D @
47K_0402_1% 2 PQ209
8
G 2N7002KW_SOT323-3
1
5 S
P
+ 7 1 2
6 O
-
G
1N4148WS-7-F_SOD323-2
@ PC210
2
100K_0402_1%
100P_0402_50V8J
0.068U_0402_16V7K~N
4
1
PU201B
@ PR217
PD203
@ PC213
@ PR223
1
1.5M_0402_5% @
1
+5VALW
22U_0603_6.3V6M
@ PU202
1
@ PC212
1 5
A IN OUT +3V_LDO A
2
2
GND
2
1bios.ru
3 4 PC209
SHDN# BYP
4.7U_0402_6.3V6M
1
G9191-330T1U_SOT23-5
1
@ PC211
2
1U_0402_16V6K 2011/06/15 2012/07/11 Title

PWR-BATTERY CONN/OTP
Custom 1.0
Gx00-CR
5 4 3 2 1
5 4 3 2 1
P3
B+
P2
PQ301 PQ302
AO4407AL_SO8 AO4423L_SO8
8 1 1 8 PR301
VIN 7 2 2 7 0.01_1206_1% CHG_B+
6 3 3 6
5 5 1 4 1 2 PQ312
PL301 AO4407AL_SO8
2 3 1UH_PCMB061H-1R0MS_7A_20% 1 8
4
2 7
3 6
@ 10U_0805_25V6K
@ 10U_0805_25V6K
2200P_0402_50V7K
PQ304 5
10U_0805_25V6K
10U_0805_25V6K
D D
47K_0402_5%
1
2
200K_0402_1%
0.1U_0603_25V7K
PC319
4
1
PR302
PC310
PC313
PC315
PC316
DTA144EUA_SC70-3 DISCHG_G
PC302
PR304
1
1 2 PR322
200K_0402_1%
2
2
2 PC301 1 2
2
5600P_0402_25V7K ACN VIN
2ACOFF-1
1SS355_SOD323-2
2
1
ACP PR321
1DISCHG_G-1
47K_0402_1%
1
2
PD302
P2-1 PR325
0.1U_0402_25V6
1
2 200K_0402_1%
PQ303 PQ311
1
PC307 PC311 DTC115EUA_SC70-3
1
DTC115EUA_SC70-3
PR306 <48> ACPRN 1 2 2 1
3
20K_0402_1%
1 2 0.1U_0402_25V6 2 1 2
6
PQ306
1
D 2N7002KW _SOT323-3 PC308 PD303 PQ313

150K_0402_1%
2
PR305
PQ307A 1SS355_SOD323-2
2 BATT_OUT <47,48>
2N7002KDW -2N_SOT363-6 G 0.1U_0402_25V6 P2 2N7002KW _SOT323-3
1
D
0.1U_0402_25V6
S
3
2 1 2 PACIN
1
1
PC324
VIN G
S
3
392K_0402_1%
2
1
P2-2
10_1206_5%
S TR MDS1525URH 1N SO8
2
5
6
7
8
C C
PR309
2N7002KDW-2N_SOT363-6
PQ309
PR319
3
PQ307B
ACOK
CMPIN
CMPOUT
ACP
ACN
PR303 PR308 <42,47> ADP_I
2
47K_0402_1% 64.9K_0402_1% 21
1
PACIN 1 2 5 1 2 6 TP 4
PACIN ACDET PC314
PC303 PC304 20 BQ24737VCC 1 2
4
1 2 1 2 7 VCC
ACON IOUT PL302 PR324
3
2
1
1U_0603_25V6K
1
PQ305 0.1U_0402_25V6 100P_0402_50V8J 19 10UH_PCMB104T-100MS_6A_20% 0.01_1206_1%

PHASE
DTC115EUA_SC70-3
<42,47> EC_SMB_DA1
8
SDA
PU301
1 2
BATT+
BQ24727RGRR_VQFN20_3P5X3P5 LX_CHG CHG1 4
18 DH_CHG
HIDRV
5
6
7
8
1 2ACOFF-12 9 2 3
<42> ACOFF SCL
1
<42,47> EC_SMB_CK1
PQ310
PR315 PR320 PC317
4.7_1206_5%
S TR MDS1521URH 1N SO8
PR323
PR326 316K_0402_1% 2.2_0603_5% 0.047U_0603_16V7K
10K_0402_5% 1 2 10 17 BST_CHG 1 2 2 1 SRP SRN
10U_0805_25V6K
10U_0805_25V6K
124737_SN
ILIM BTST
+3VALW PD301
3
4 @
LODRV
1
16 2 1
PC322
PC323
PQ314 PR316
2N7002KW_SOT323-3
GND
SRN
SRP
REGN
BM
100K_0402_1%
1
2
2 RB751V-40_SOD323-2
680P_0603_50V7K
<47,48> BATT_OUT
2
11
12
13
14
15
3
2
1
1
PC320
G
2
PC312 BQ24737VDD
6.8_0402_5%
S
3
10_0402_5%
1U_0603_25V6K
2
PR317
PR318
@
DL_CHG
2
2
B PC306 B
2 1
0.1U_0402_25V6
1
PC305 1 PC309
0.1U_0402_25V6 0.1U_0402_25V6
2
BQ24737VDD
PR314
10K_0402_1%
1
1 2
ACIN <16,24,42,46>
PR310
PR307 10K_0402_1%
47K_0402_1%
PACIN
2
PQ308
2N7002KW_SOT323-3
1
ACPRN <48> D PR312

2
G 12K_0402_1%
2
S
3
A A

Compal Secret Data
CHARGER
1.0
Gx00-CR
Date: W ednesday, February 27, 2013 Sheet 48 of 60
5 4 3 2 1
A B C D E
PR411
3V5V_EN_R 1 2 3V5V_EN
10K_0402_5%
2
PC432
0.047U_0402_25V7K
1
1 PR414 1
0_0402_5% PR402
499K_0402_1%
2 1 ENLDO_3V5V 2 1
B+
1
150K_0402_1%
1U_0603_25V6K
1
PR403
@ PR415
2 1
PC407
2
0_0402_5%
2
PU401
B+ PL401 7 1 3V5V_EN_R
HCB2012KF-121T50_0805 IN EN1 PC439 PR416
1 2 3V_VIN 8 3 1 2 2 1
IN EN2
2200P_0402_50V7K
68P_0402_50V8J
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
PC402
6 BST_3V 2 1 1 2 0.01U_0402_25V7K 1K_0402_5%
BS
PC401
PC403
1
1
PC404
PC405
PC406
PR401 0.1U_0603_25V7K
0_0603_5% PL402
@ @ 10 LX_3V 1 2
+3VALWP
2
2
@ LX
9 4 1.5UH_PCMC063T-1R5MN_9A_20%
GND OUT
470P_0402_50V8J
470P_0402_50V8J
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
PC434
PC435
4.7_1206_5%
2 5
SPOK PG LDO +3VLP
PC408
PC409
PC410
PC411
PC412
PC413
1
PR404
S IC SY8208BQNC QFN 10P PWM
2
PC414
1 3V_SN
4.7U_0603_6.3V6M @ @
680P_0603_50V7K
1 ENLDO_3V5V
PC415
2 2
2
@
PR412
0_0402_5%
B+ PL403
HCB2012KF-121T50_0805
2
1 2 5V_VIN
PC436 PR413
1 2 2 1
6800P_0402_25V7K 1K_0402_5%
2200P_0402_50V7K
68P_0402_50V8J
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
PU402
8 1 3V5V_EN
IN EN1
1
1
PC419
PC420
PC416
PC417
PC418
3 PC421
EN2 0.1U_0603_25V7K
6 BST_5V 2 1 1 2
2
@ @ BS
PR405
0_0603_5% PL404
9 10 LX_5V 1 2 +5VALWP
GND LX
5V_VCC 5 4
150U_D2_6.3VY_R15M
1.5UH_PCMC063T-1R5MN_9A_20% 1
VCC OUT
470P_0402_50V8J
470P_0402_50V8J
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
PC433
PC437
PC438
+
4.7_1206_5%
2 7
PG LDO VL
1
PC422
PC423
PC424
PC425
PC426
PC427
PC428
4.7U_0603_6.3V6M
PR406
S IC SY8208CQNC QFN 10P PWM
2
2@
2
5V_SN
PC430
4.7U_0603_6.3V6M
@
2
3 3
2
680P_0603_50V7K
1
PC429
2
PR407
2.2K_0402_5% @ PJ401
EC_ON 2 1 +3VALWP 1 2 +3VALW
<42> EC_ON 1 2
JUMP_43X118
MAINPWON 2 1
<42> MAINPWON
PR408
0_0402_5%
@ PJ402
3V5V_EN +5VALWP 1 2 +5VALW
1 2
1M_0402_1%
4.7U_0402_6.3V6M
JUMP_43X118
1
1
PR409
PC431
2
2
4 4

Compal Secret Data
+1.05VS_VCCP
Custom 1.0
Gx00-CR
A B C D E
A B C D
PL502
1.5V_B+ 1 2 B+
HCB2012KF-121T50_0805
2200P_0402_50V7K
STATE S3 S5 1.5VP VTT_REFP 0.75VSP
10U_0805_25V6K
0.1U_0402_25V6
4.7U_0805_25V6-K
MDU1516URH_POWERDFN56-8-5
1
PC501
PC520
PC509
PC513
S0 Hi Hi On On On
5
Off
2
@ @
S3 Lo Hi On On (Hi-Z) +1.5VP
PQ501
UG_1.5V 4
S4/S5 Lo Lo Off Off Off
1
1 1
PR503 LX_1.5V
3
2
1
Note: S3 - sleep ; S5 - power off 0_0603_5%
2
PR501 PC512 PL501
2.2_0603_5% 0.1U_0603_25V7K 1UH_PCMB104T-1R0MH_18A_20%
BST_1.5V 1 2 BST_1.5V-1 1 2 2 1
+0.75VSP +1.5VP
10U_0805_25V6K
10U_0805_25V6K
1
MDU1511RH_POWERDFN56-8-5
5
@
20
19
18
17
16
1
1
PC504
PC505
PU501 PR515
4.7_1206_5% @
VTT
VLDOIN
BOOT
UGATE
PHASE
21 1 1
2
PAD
PQ502
1 15 LG_1.5V 4 + +
VTTGND LGATE PC521 PC522
1
@
2 14 PC517 330U_2.5V_M 2 2 220U_6.3V_M
VTTSNS PGND PR511 680P_0603_50V7K
3
2
1
2
6.65K_0402_1%
3 13 2 1
GND RT8207MZQW _W QFN20_3X3 CS
4 12
+VTT_REFP VTTREF VDDP
5 11 2 1
+1.5VP VDDQ VDD
+5VALW
1
PGOOD
PR514
PC506 +3VALW 5.1_0603_5%
+1.5VP
1U_0603_10V6K
TON
0.033U_0402_16V7K OCP min 20A
FB
S3
S5
2
2 2
1
OVP min 1.65V
PC510
10K_0402_5%
PC511
10
PR510
1U_0603_10V6K
S3_1.5V
2
PR502
S5_1.5V
64.9K_0402_1% @
2
<42,45,50,52> SUSP# 1 2 PGOOD_1.5V
PR509
887K_0402_1%
<42> SYSON 1 2 2 1 1.5V_B+
PR505 PR507 PJ504

1
PC503 0_0402_5% 5.9K_0402_1% 2 1

0.1U_0402_16V6K 2 1 2 1
@ JUMP_43X118
2
@ PC508
1
0.1U_0402_16V7K PJ505
1 2 +1.5VP 2 1 +1.5V
2
PR506 2 1
@ JUMP_43X118
5.76K_0402_1% PC526
2
0.1U_0402_16V6K
@
PJ506
2 1
+0.75VSP 2 1 +0.75VS
JUMP_43X79
@
3 3
PU502
SY8033BDBC_DFN10_3X3
PL503
4
PJ502 1UH_PH041H-1R0MS_3.8A_20%
2 1 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
+3VALW
PG
2 1 PVIN LX +1.8VSP
@ JUMP_43X79 9 3
4.7_1206_5%
PVIN LX
1
1
8
PR508
PC502
22U_0805_6.3VAM SVIN
68P_0402_50V8J
1
6 FB=0.6Volt
2200P_0402_50V7K
68P_0402_50V8J
0.1U_0402_25V6
2
FB
1
5 @ PC525
22U_0805_6.3VAM
22U_0805_6.3VAM
1 2
EN
1
PC518
PC519
NC
NC
PR512
TP
PC514
PC515
PC516
20K_0402_1% PJ507
680P_0603_50V7K
2
2 1
PC523
+1.8VSP +1.8VS
11
2
2 1
PR516
2
<42,45,50,52> SUSP# @ @ @ JUMP_43X79

1 2 EN_1.8VSP @ @
1
0_0402_5% PC524
0.1U_0402_10V7K
2
PC507 @
0.1U_0402_10V7K
2
1
PR504 1.8VSP_FB
1M_0402_5%
1
2
1
PR513
10K_0402_1%
4 4
2

+1.5VP/+1.8VSP
Custom 1.0
Gx00-CR
A B C D
5 4 3 2 1
VID [0] VID[1] VCCSA Vout

0 0 0.9V
0 1 0.8V +VCCSAP 2
PJ601
2 1
1 +VCCSA
1 0 0.725V @ JUMP_43X118
1 1 0.675V PR613
1 2 +VCCSA
D
output voltage adjustable network +V1.05S_VCCP D
0.005_1206_1%
SY8037BDCC_DFN12_3X3
PL601
PJ602
PU601 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
+3VALW 1
1 2
2 +VCCSA_PWR_SRC 12
PVIN LX
1 +VCCSA_PHASE 1 2 +VCCSAP
11 2
22U_0805_6.3V6M
22U_0805_6.3V6M
JUMP_43X79 PVIN LX SA_PGOOD <42>
1
@
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PC602 10 3 PR601 PR602
SVIN LX
2
2
68P_0402_50V8J 100K_0402_5% 4.7_0603_5%
PC608
PC601
PC603
PC604
PC607
PC609
2 1FB_VCCSA_IC 9 4 1 2
FB PG +3VS
1
1 2
1
8 5
VOUT EN 2 1 @ PC605
GND
7 6 680P_0402_50V7K
VID1 VID0 @ PR614
2
0_0402_5%
13
2 1
+V1.05S_VCCP_PWRGOOD <52>
1
PR603
2
PR608 0_0402_5%
1M_0402_5%
1
@ PC606
2
.1U_0402_16V7K
H_VCCSA_VID0 <10>
PR604
C FB_VCCSA 1K_0402_5% C
2 1 The 1k PD on the VCCSA VIDs are empty.
PR605 These should be stuffed to ensure that
1K_0402_5% VCCSA VID is 00 prior to VCCIO stability.
2 1
H_VCCSA_VID1 <10>
PR606
100_0402_1%
2 1
2 1
+VCCSA_SENSE <10>
PR607
0_0402_5%
B B
PR612
82.5K_0402_1%
2 1
DGPU_PWR_EN <18,25,42,53>
2
1M_0402_1%
0.1U_0402_25V6
1
PR616
PC637
2
1
+0.95VGSP PJ606
@ PR610 @ PC634 2 1
2 1 +0.95VGS
4.7_1206_5% 680P_0603_50V7K
PL606 1 2SNB_0.95V 1 2 @ JUMP_43X118
HCB2012KF-121T50_0805 PU604
1 2 B+_0.95V 8 1 PC632
B+ IN EN 0.1U_0603_25V7K
10U_0805_25V6K
6 1 2 PL605
0.1U_0402_25V6
2200P_0402_50V7K
BS
1
1UH_PCMB063T-1R0MS_12A_20%
PC627
PC636 @
9 10 1 2
+0.95VGSP
PC621
GND LX
2
78.7K_0402_1%
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0805_6.3VAM
22U_0805_6.3VAM
1
220P_0402_50V7K
1
1
+3VS 4
PR611
FB
PC635
PC629
PC633
PC631
PC622
ILMT_0.95V3 7
+3VALW
2
2
ILMT BYP
1
@
4.7U_0603_6.3V6K
1 2 PGD_0.95V 2 5 @
4.7U_0603_6.3V6K
+3VS PG LDO
1
@ PR618
PC628
1
PR617 SY8208DQNC_QFN10_3X3
PC630
0_0402_5%
100K_0402_5%
2
ILMT_0.95V
2
PR615
1
A A
133K_0402_1%
PR609
2
1bios.ru
1M_0402_5%
2

+VCCSAP
C 1.0
Gx00-CR
5 4 3 2 1
5 4 3 2 1
D D
PJ701
PR701 2 1
<42,45,50> SUSP# 60.4K_0402_1% 2 1
1 2 @ JUMP_43X118
+1.05VS_VCCPP PJ703 +V1.05S_VCCP
@ 10K_0402_1%
2
2 1
.1U_0402_16V7K
+3VS 2 1
1
PR706
@ JUMP_43X118
PC701
100K_0402_1%
2
1
2
PR710
100K_0402_1%
PL702
1
C HCB2012KF-121T50_0805 C
2
<51> +V1.05S_VCCP_PW RGOOD 1.05VS_B+ 2 1
PR712
B+
2200P_0402_50V7K
10U_0805_25V6K
4.7U_0805_25V6-K
PQ701
0.1U_0402_25V6
S TR MDU1516URH 1N POW ERDFN56-8
1
PR713 PC707
PC712
PC713
1
2.2_0603_5% 0.1U_0603_25V7K
PC711
PC715
1
BST_1.05VS_VCCP 2 1 2
2
@
@
17
16
15
14
13
PU701 4
10.7K_0402_1%~N
PAD
PGOOD
EN
MODE
BST
2
PR704
1 12 LX_1.05VS_VCCP PL701
0.1U_0402_25V6
3
2
1
VREF SW 1UH_PCMB104T-1R0MH_18A_20%
+1.05VS_VCCPP
1
2 1
12K_0402_1%
1
PC702
2 11 DH_1.05VS_VCCP
2
REFIN DH
2
1
PR705
1000P_0603_50V7K 4.7_1206_5%
5
PC703
TPS51219RTER_QFN16_3X3
PR714
PR702 0.01UF_0402_25V7K
1
3 10 DL_1.05VS_VCCP PC714 1
2 1 GSNS DL
1
2
@ +
0_0402_5% 4
S TR MDU1511RH 1N POWERDFN56-8
4 9 330U_6.3V_M
VSNS V5 +5VALW 2
COMP
1
PGND
PQ702
TRIP
GND
B B
3
2
1
1
<9> VSSIO_SENSE_L
PC709
2
PC706 PC708
5
<9> VCCIO_SENSE 1U_0603_10V6K
2
1 2 @
PR703
1 2 0.01UF_0402_25V7K
75K_0402_1%
1
10_0402_1%
+1.05VP
2
OCP min 20A

PR711
PC704
2
1000P_0402_50V7K OVP min 1.24V

1
PR709
1 2
10_0402_1%
2
PC705
1000P_0402_50V7K
1
A A

Compal Secret Data
+1.05VS_VCCP
Custom 1.0
Gx00-CR
5 4 3 2 1
A B C D
+3VGS
10K_0402_1%
10K_0402_1%
PR803 @ 10K_0402_1%
10K_0402_1%
PR805 @ 10K_0402_1%
PR806 @ 10K_0402_1%
PR807 @ 10K_0402_1%
PR808 @ 10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
Mars XT = 0.85V (1 1 0 1 0 0)
2
+VGA_B+
@ Sun Pro = 0.9V (1 1 0 0 0 0) PL801
HCB4532KF-800T90_1812
1 2
PR801
PR802
PR804
PR809
PR810
PR811
PR812
B+
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
PC801 @
1
@
PC803
PC804
PR813
PC802
1 1
147K_0402_1%
2
1 2VRON_VGA
<18,25,42,51> DGPU_PWR_EN
PR820
0_0402_5%
2
2 1
<42> EC_VGA_EN PR814
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
<24>
<24>
<24>
<24>
<24>
0_0402_5%
@ PR816
2.2K_0402_1% PC805 @ PR817 PC806 PQ801
1
1
1 2 1 2 2.2_0603_5% 0.22U_0603_10V7K CSD87351Q5D_SON8-7
+3VGS
BOOT2_VGA 2 1 BOOT2_2_VGA 1 2 2 PL802
PR818 @ 100P_0402_25V8K
<24,53> GPU_GPIO0 1 2 UGATE2_VGA 0.22UH_PCME064T-R22MS_28A_20% +VGA_CORE
7
0_0402_5% PHASE2_VGA 3 6 SW2_VGA 1 4
PR819 5
1 2 DPRSLPVR_VGA-1 4 LF2_VGA 2 3 V2N_VGA
1 1 1 1
3.65K_0402_1%
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
1
1
2.2K_0402_1%
4.7_1206_5%
10K_0402_1%
1
PR826 @
+3VGS + + + +
PR827
PC807
PC808
PC809
PC810
1_0402_1%
10K_0402_1%
GPU_VID6
@ PR830
PR828
PR837
PR829
8
1 2 CLK_ENABLE#_VGA
LGATE2_VGA 2 2 2 2
1.91K_0402_1%
2
1
1.91K_0402_1%
2
SNUB2_VGA
PR831
PR832
0_0402_5%
2
2 1
VSUM+_VGA
PR833
ISEN2_VGA
2.2K_0402_1% ISEN1_VGA
VSUM-_VGA
+3VGS 1 2
680P_0402_50V7K
9> DGPU_PWROK
PC811 @
1
1 PR834 2
<24,53> GPU_GPIO0 0_0402_5%
PR835
2
@ 1 2
PSI#_VGA
2 2
2.2K_0402_1%
2 1
RBIAS_VGA
PC812
PR836 1U_0603_10V6K +VGA_CORE
40
39
38
37
36
35
34
33
32
31
147K_0402_1% PU801 1 2
CLK_EN#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON
30
BOOT2 29
1 UGATE2 28
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2 PGOOD PHASE2 27
PSI# VSSP2
1
3 26
PC824
PC825
PC826
PC827
PC828
PC829
PC830
PC831
PC832
PC833
PC834
PC835
PC836
PC837
PC838
PC839
4 RBIAS LGATE2 25
5 VR_TT# VCCP 24 +5VS
2
VW_VGA 6 NTC PWM3 23
COMP_VGA 7 VW LGATE1 22
FB_VGA 8 COMP VSSP1 21
1 2ISEN3_VGA 9 FB PHASE1
5.9K_0402_1%
1000P_0402_50V7K
ISEN3
1
UGATE1
10 PC872
BOOT1
ISUM+
ISEN2
1
ISEN1
ISUM-
VSEN
IMON
PC871 1U_0603_10V6K
PC873
VDD
RTN
VIN
22P_0402_50V8J 41
PR841
249K_0402_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
2
AGND
2
PR840 @
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2
ISL62883CHRTZ-T_TQFN40_5X5
11
12
13
14
15
16
17
18
19
20
1
PR842 PR864
PC840
PC841
PC842
PC843
PC844
PC845
PC846
PC851
PC852
PC853
PC854
PC855
PC856
PC857
2
499_0402_1% PC874 0_0402_5%

1 2FB1_VGA1 2 1 2
ISUM-_VGA
1
2
VDD_VGA
RTN_VGA
@
390P_0402_50V7K
PC847 PR843 PR844 @ 0_0402_5%
33P_0402_50V8J 1.69K_0402_1% 1 2
+5VS
1 2 1 2 PR863 VSEN_VGA PR845
0_0402_5% For 15W one phase 0_0402_5%
11K_0402_1%
0.047U_0402_16V7-K
2
1 2 VIN_VGA 2 1 GPU_IMON <42>

1
PC849
PR847
+5VS +VGA_B+
@
1 2FB2_VGA1 2 PR848
ISEN2_VGA
1_0402_5%
2
3
PC848 PR846 1 2 +VGA_B+ 3
ISEN1_VGA
1
150P_0402_50V8J 221K_0402_1% +5VS

1
1
PC876
PC877
1U_0603_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0603_25V7K
VSSSENSE_VGA <27,53>
1
PR849
PC850
PC875
2200P_0402_50V7K
2
30K_0402_1%
BOOT1_VGA
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2
PC878 @
1
PC879
PC880
PC881
VSUM-_VGA
2
VSUM+_VGA UGATE1_VGA
1 2 PQ802
82.5_0402_5%
+VGA_CORE
PR851 @
PR852 PC858 CSD87351Q5D_SON8-7

1
1
PR850 2.2_0603_5% 0.22U_0603_10V7K
1
10_0402_1% 2 1 BOOT1_1_VGA 1 2 2 PL803

2.61K_0402_1%
PR853
0.22UH_PCME064T-R22MS_28A_20%
1 2 7
<27> VCCSENSE_VGA
2
PHASE1_VGA 3 6 SW1_VGA 1 4
+VGA_CORE
2
PR854 5
VSUM_VGA_N001
0.22U_0603_10V7K
0.033U_0603_25V7K
1
0_0402_5% 4 2 3 V1N_VGA
1NTC_VGA
PC859 LF1_VGA
1
1
330P_0402_50V7K
PC860
PC861
10K_0402_1%
3.65K_0402_1%
2
1
PR856
1_0402_1%
4.7_1206_5%
10K_0402_1%
PR855 @
PR858
2
8
@
PR857
PR838
0.01U_0402_25V7K
PC864 @
PH802 LGATE1_VGA
330P_0402_50V7K
2
1
PC863 @
10K_0402_1%_TSM0A103F34D1RZ
11K_0402_1%
2
1
PC862
PR859
1000P_0402_50V7K
PR860
2
1 SNUB1_VGA
2
1 2
<27,53> VSSSENSE_VGA
2
ISEN2_VGA
Layout Note:
VSUM-_VGA
0_0402_5%
Place near Phase1 Choke
VSUM+_VGA
PR862
ISEN1_VGA
680P_0402_50V7K
PC865 @
953_0402_1%
4
1 2 1 2 4
VSUM-_VGA
PR861
1bios.ru
2
10_0402_1%
1
PC866
0.1U_0402_16V7K
2

PWR-CPU_CORE
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C Gx00-CR 1.0
A B C D
5 4 3 2 1
PR915,PR946=200K(setting 113 degreeC)

PR915,PR946=8.25K(setting 93 degreeC)
PC902
1200P_0402_50V7K
470P_0402_50V7K
1 PR901 2 FBA3 1 2 PC901 1 2
D PUT COLSE D
75K_0402_1%
10_0402_1% 680P_0402_50V7K .1U_0402_16V7K
TO GT
1
PR903 1 PR904 2
PC903
PC904
PR905
TRBSTA# 1 PR902 2 FBA1 1 2 PH901 Inductor
2P: 24K 24.9K_0402_1% PR906 PC906
1
1
1.21K_0402_1% 10.7K_0402_1% 220K_0402_5%_ERTJ0EV224J CSCOMPA 1 2 DROOPA 1 2 CSREFA
PC905 1P: 24.9K
2
PR908 PC907 PC908 2 1 NTC_PH203 1K_0402_1% 1000P_0402_50V7K
2
4700P_0402_25V7K 1 2 FBA2 1 2 1 2
10_0402_1% PR907 2P: 1.65K
680P_0402_50V7K PR910 10P_0402_50V8J PC909 165K_0402_1%
1 PR909 2 1 2 COMPA11 2 1P: 1K TSENSEA
1K_0402_1% 6.04K_0402_1% 2200P_0402_50V7K CSREFA
1_0402_5%
PC910
2
1 PR912 2 SWN1A 0.047U_0402_16V7K
PR916
2P: 21.5K 63.4K_0603_1%
1
PR937 CSP1A 1 2
1P: 15.8K SWN1A <55>
2
2
2
15.8K_0402_1%
0_0402_5%
CSCOMPA
2 1 PC911 PR913
<10> VCC_AXG_SENSE
1PR914
1000P_0402_50V7K 5.6K_0402_1% @
1
PR954 PC912
2
200K_0402_1%
0_0402_5% 1000P_0402_50V7K
CSREFA <55>
1
2 1 PH904
<10> VSS_AXG_SENSE
PR915
PC914
1 2 100K_0402_1%_TSM0B104F4251RZ
CSP2A
CSP1A
CSSUMA
1
TRBSTA#
DROOPA
.1U_0402_16V7K
TSENSEA
ILIMA
COMPA
+V1.05S_VCCP
IMONA
FBA
DIFFA
Switching Frequency = 450KHz PR918 2P: 36K
1 2
26.1K_0402_1% 1P: 26.1K
+5VS 1 PR919 2 PUT COLSE
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
C C
2_0603_5% PU901
PC915
6132_PWMA TO V_GT
VSNA
VSPA
DIFFA
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
PAD
TRBSTA#
1 2 6132_VCC HOT SPOT
.1U_0402_16V7K
2.2U_0603_10V7K 1 45 PR921 PC918

VCC PWMA +5VS
130_0402_1%
54.9_0402_1%
PC916 @ PR920 2 44 BSTA1 1 2 BSTA1_1

1 2
VDDBP BSTA SW1A <55>
1
PR922 2
.1U_0402_16V7K 2 1VR_ON_CPU 3 43 2.2_0603_5% 0.22U_0603_25V7K

<42> VR_ON VRDYA HGA HG1A <55>
PR923
PC917 4 42
0_0402_5% VR_SVID_DAT1 5 EN SWA 41 PC919
LG1A <55> 2Phase: @
2
SDIO LGA
1
PR926 PR925 VR_SVID_ALRT# 6 40 BST2 1 PR9242 BST2_1
1 2
ALERT# BST2 SW2 <55> 1Phase: install
0_0402_5% PR927 1 2 VR_SVID_CLK7 39 2.2_0603_5% 0.22U_0603_25V7K Option for PR928
HG2 <55>
1
2 1VR_SVID_DAT1 60.4K_0402_1% 10K_0402_1% VBOOT 8 SCLK HG2 38

<9> VR_SVID_DAT 1 phase GFX 0_0402_5%
1 2 ROSC_CPU 9 VBOOT NCP6132AMNR2G_QFN60_7X7 SW2 37 PC920
<9> VR_SVID_ALRT# ROSC LG2 LG2 <55>
VRMP 10 36 6132P_VCCP 2 1 PR930 1 2
<9> VR_SVID_CLK VRMP PVCC
2
CPU_B+ 1 2 H_PROCHOT# 11 35 2.2U_0603_10V7K
VGATE 12 VRHOT# PGND 34 0_0402_5% CSP2A
+V1.05S_VCCP VRDY LG1 LG1 <55> +5VS
0.01U_0402_25V7K
PR929 1K_0402_1% 13 33
+3VS VSN SW1 SW1 <55>
1
14 32 PC922
VSP HG1 HG1 <55>
PC921 DIFF_CPU 15 31 BST1 1 PR931 2 BST1_1 1 2
CSCOMP
DIFF BST1
1
TRBST#
@ 0.22U_0603_25V7K
DROOP
CSSUM
DRVEN
CSREF
2
1
COMP
TSNS
PR932 2.2_0603_5%
CSP3
CSP2
CSP1
PWM
IOUT
ILIM
75_0402_1% PR933 +5VS
FB
10K_0402_5%
<42,46,47,6> H_PROCHOT#
3P: 73.2K
2
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
1 PR934 2
2P: 41.2K
2
PR936 41.2K_0402_1% Option for PR935 3Phase: @

<16,42> VGATE
0_0402_5%
TRBST#
COMP_CPU 0_0402_5%
FB_CPU
2 phase CPU
DROOP
TSENSE
2Phase: install
2 ILIM_CPU
2 1 VSN 3P: 22p
<9> VSSSENSE 6132_PWM
1
IMON
2P: 10p
2
PR938 PC923
IMON
0_0402_5% 1000P_0402_50V7K CSP3

2
2 1 VSP PC924
<9> VCCSENSE
PR939 12.4K_0402_1%
1 2
.1U_0402_16V7K
IMVP_IMON
B PR941 B
PC926 CSP1 5.62K_0402_1%
3P: 330p 1 PR940 2 2 1 CSP2 CSP2 1 2
SWN2 <55>
1
2
1K_0402_1% CSP3 PC927 TSENSE
2P: 1000p
1
22P_0402_50V8J 0.047U_0402_16V7K @
PR960
1
CSCOMP
1_0402_5%
PR942 PC928 PR943 PC929 3P: 21K 6.98K_0402_1%
2
1 2FB_CPU1 1 2 2 1COMP_CPU1 2 1 CSREF
2P: 12.4K
PR917
PR944 PC930 49.9_0402_1% 6.04K_0402_1% PR945
1 2FB_CPU3 1 2 680P_0402_50V7K 1500P_0402_50V7K CSP1 1 2
SWN1 <55>
2
10_0402_1% 3P: 6.04K CSREF <55>
2
2
1
0.033U_0402_16V7K PC931 5.62K_0402_1%
PR947 PR948 2P: 4.32K PC932 @
TRBST# 1 2 FB_CPU2 1 2 1000P_0402_50V7K 3P: 1500p0.047U_0402_16V7K PR961
1
2
0.033U_0402_16V7K
CSREF 6.98K_0402_1%
2P: 1200p
1
1
8.06K_0402_1% 806_0402_1% 3P: 2200p

PC933 @
2P: 3300p
200K_0402_1%
CSSUM
2
PR946 1
2
3P: 348 3P: 3.65K PC934 PR949
1 2 100K_0603_1% PH902
2P: 1.21K 2P: 9.53K 1000P_0402_50V7K 1 2 SWN1
24.9K_0402_1%
100K_0402_1%_TSM0B104F4251RZ
2
.1U_0402_16V7K
1
PC935
3P: 23.7K 1 2 PC936 1 2 SWN2

220P_0402_50V7K
PR950
2P: 24.9K
1
PR951
1 PR952 2NTC_PH201 1 PR953 2 100K_0603_1%
1
75K_0402_1%
PR955 PC937 165K_0402_1%
CSCOMP 1 2 DROOP 1 2 CSREF PH903 PUT COLSE
PUT COLSE TO VCORE
1K_0402_1% 1000P_0402_50V7K 2 1
3P: 806 TO VCORE HOT SPOT
2P: 1K Phase 1 220K_0402_5%_ERTJ0EV224J
A Inductor A
1bios.ru
<42> IMVP_IMON
2011/06/15
Compal Secret Data
2012/07/11 Title
PWR-CPU_CORE
Custom Gx00-CR 1.0
5 4 3 2 1
5 4 3 2 1
CPU_B+ CPU_B+
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
B+
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_25V7K
2200P_0402_25V7K
5
5
PL901
HCB4532KF-800T90_1812
1
1 2
PC938
PC939
PC940
PC941
PC942
PC943
PC944
PC946
CPU_B+
1
2
4 4
<54> HG1 + PC947 <54> HG2
PQ901
+VCC_CORE 220U_25V_M PQ902 +VCC_CORE
PL902 2
S TR MDU1516URH 1N POWERDFN56-8 S TR MDU1516URH 1N POWERDFN56-8
3
2
1
3
2
1
D D
S COIL 0.22UH +-20% PCMB104T-R22MS 35A PL903
S COIL 0.22UH +-20% PCMB104T-R22MS 35A
1 4 1 4
<54> SW1 <54> SW2
1
2 3 2 3
5
PR956 PR957
4.7_1206_5% 4.7_1206_5%
2
PR958
4 V1N_CPU 2 1 4 V2N_CPU 2 PR959 1 CSREF
<54> LG1 CSREF <54> <54> LG2
1SNUB_CPU1
SNUB_CPU2
10_0402_1%
10_0402_1%
PQ903
PQ904
SWN1 <54> SWN2 <54>
3
2
1
3
2
1
PC948 S TR MDU1511RH 1N POWERDFN56-8
680P_0603_50V7K
1
PC949
2
680P_0603_50V7K
2
C C
QC 45W CPU DC 35W CPU

VID1=0.9V VID1=1.05V
IccMax=94A IccMax=53A
Icc_Dyn=66A Icc_Dyn=43A
Icc_TDC=52A Icc_TDC=36A
R_LL=1.9m ohm R_LL=1.9m ohm
OCP~110A OCP~65A
CPU_B+
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_25V7K
B B
1
1
PC957
PC958
PC959
PC960
2
2
5
4
<54> HG1A
PL905
PQ907
S TR MDU1516URH 1N POWERDFN56-8
+VCC_GFXCORE_AXG
3
2
1
S COIL 0.22UH +-20% PCMB104T-R22MS 35A
1 4
<54> SW1A
1
2 3
5
PR967
V1N_GFX
4.7_1206_5%
2
4
<54> LG1A
SNUB_GFX1
PQ909
2 PR971 1
CSREFA <54>
3
2
1
10_0402_1%
1
PC968
680P_0603_50V7K SWN1A <54>
2
A A
1bios.ru QC 45W GT2

VID1=1.23V
IccMax=46A
Icc_Dyn=37A
DC 35W GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A Security Classification Compal Secret Data Compal Electronics, Inc.
Icc_TDC=38A Icc_TDC=21.5A Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
R_LL=3.9m ohm R_LL=3.9m ohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE
OCP~55A OCP~40A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Gx00-CR
5 4 3 2 1
5 4 3 2 1
+VCC_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.

+VCC_CORE +VCC_GFXCORE_AXG
1 1 1 1 1
5 x 22 µF (0805)
PC1
PC2 PC3 PC4 PC5
Socket Bottom 5 x (0805) no-stuff
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM +VCC_GFXCORE_AXG sites
D
7 x 22 µF (0805) D
Socket Top 2 x (0805) no-stuff
sites
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1
PC13
PC15
PC17
PC18
PC19
PC6 PC7 PC8 PC9 PC10
10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM
2 2 2 2 2 2 2 2 2 2 @ +V1.05S_VCCP
+VCC_CORE +V1.05S_VCCP
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1
PC27
PC28
PC29
PC30
PC31
PC32
PC33
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2
PC36
PC38
PC39
PC40
PC41
PC42
PC43
2 2 @ 2 2 2 2 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1
1 1 1 1 1
PC50
PC51
PC52
PC53
PC56
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2
2 2 2 2 2
330U_D2_2V_Y
330U_D2_2V_Y
1 1
PC58
PC59
+ +
C C
2 2
330U_D2_2V_Y
330U_D2_2V_Y
1 1
1 1 1 1
PC66
PC67
+ +
PC61 PC62 PC63 PC64 @
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2
1 1
@ @
PC71 PC72
22U_0805_6.3V6M 22U_0805_6.3V6M
2 2
+VCC_CORE
1 1 1
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
+ + +
PC73
PC74
PC76
B 2 2 2 B
1 1
330U_D2_2V_Y
330U_D2_2V_Y
+ +
PC77
PC78
2 2@
A A

Compal Secret Data
PWR - PROCESSOR DECOUPLING

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9631P 1.0
5 4 3 2 1
5 4 3 2 1
VIWGP/R PWR PIR List

Item Page MODIFICATION LIST PURPOSE
EVT TO DVT
1 P.46 Add PR102,PC108,PC109 For ADP_ID pin detect
D 2 P.47 Add PR225,PR227,PR228,PQ206,PQ207,PQ208 For protect adapter function D
3 P.49 Add PR410,PC433 For 3VALWP/5VALWP sequence

4 P.49 Add PC434,PC435,PC436,PC437 For EMI solution
5 P.49 Add PC432 and change PL404 from 1.5uH to 3.3uH For improve output voltage ripple
6 P.50 Change PR502 from 49.9k to 64.9k For +0.75VSP sequence
7 P.51 Add PC637 For +0.95VGSP sequence
8 P.54 Change PC907,PR912,PR927,PC928 For CPU Transient Compensation
PVT TO PVT2
9 P.48 Add PR326 and PQ314 For battery health function
10 P.49 Add PR411,PC432 To delay +3VALW enable. PR411 change to 10K and PC432 change to 0.047uF
11 P.49 Change PC439 from 4700P to 10nF ,PC436 from 47nF to 6.8nF Adjust +3VALW and +5VALW rising time.
C C
12 P.51 Add PR614 For Celeron CPU SA_PGOOD

13
14
15
16
17
18
19
20
21
B 22 B
23
A A

Compal Secret Data
HW-PIR1
Custom 1.0
LA-9631P
5 4 3 2 1
5 4 3 2 1
COMPAL CONFIDENTIAL
MODEL NAME: Power Sequence Block Diagram
PCB NAME: LA-9631P
D REVISION: D
DATE: 2011/07/13 10
PCH_PWROK
AC A1
MODE VIN +3V_PCH
V V
A2 A3 B5 +5V_PCH
VV
PU301 A5 3
V
PU401
V
B+
+3VALW B7 3 3
BATT BATT V 10
+5VALW
MODE
B1
B2
B+ B4 V PCH_PWROK
V SYS_PWROK 15 14 VGATE
V
EC 4
PQ2 11
PCH_RSMRST#_R PM_DRAM_PWRGD
V
V V PCH
B3 A5 B7 5 12
PBTN_OUT# H_CPUPWRGD
CPU
V V
13 SVID
V
C C
51ON# EC_ON
PM_SLP_S3#
PM_SLP_S4# PLT_RST# 16
PM_SLP_S5#
A4 B6 PM_SLP_SUS# 6
DGPU_PWROK
V
V
ON/OFF
SYSON 7 SYSON#
V
+1.5V
PU501
DGPU_PWR_EN
SUSP#,SUSP 8
(DIS)
V
PU601 U38
8b
B +VCC_SA +5VS B
(DIS)
V
V
PU702 U39
8a
+V1.05S +3VS DGPU
V
V
V
PU602 Q8
+V1.05S_VCCP +1.5VS
PU701
V
SA_PGOOD 8a +0.75VS
13 SVID
VR_ON 9 PU901
V
+VCC_CORE
A A
14 VGATE

Compal Secret Data
Power sequence
Custom 1.0
LA-9631P
5 4 3 2 1
5 4 3 2 1
VIWGP/R HW PIR List

EVT TO DVT
1 P.46 Change C726, C727 to 2.2nF For Sequence
D 2 P.36 Add R405 For Intel Combo Card D
3 P.35 Delete RP19. Add RP26, RP27 Because ME modify MIC location
4 P.14 Add R406, R407, R408, R409 Reserve for improvement factory processes
5 P.42 Add EC_SPI_SO, EC_SPI_SI, EC_SPI_CLK, EC_SPI_CS# to EC Reserve for improvement factory processes
6 P.42 Add PCH_PWR_EN to EC Pin.107 Reserve for improvement factory processes
7 P.42 Reserve R410 Reserve Pull-high for GPIO
8 P.5~32 Change footprint of JCPU1, U4, UV1, UV5, UV6, UV7, UV8, UV9, UV10, UV11, UV12 For Lenovo rule
9 P.25 Change RV41 to 240K. Change CV53 to 0.1uF For VGA sequence
10 P.21 Add Q21, R40, C237, R225, C243 Reserve for power consumption
11 P.34 Add R411, R412, C411, C412 Reserve for EMI
12 P.25 Change CV36, CV37 to 8.2pF For Crystal fine-tune
C
13 P.42 Add ADP_65 to EC Pin.21 For adapter protection C
14 P.42 Add ADP_90 to EC Pin.68 For adapter protection

15 P.42 Add ADP_135 to EC Pin.85 For adapter protection
16 P.42 Change EC_FAN_PWM from EC Pin.34 to EC Pin.26 For common design
17 P.42 Change NOVO# from EC Pin.26 to EC Pin.34 For common design
18 P.42 Add ADP_ID to EC Pin.66 For adapter
19 P.42 Change PCH_ENBKL from EC Pin.73 to EC Pin.76 For common design
20 P.42 Change IMVP_IMON from EC Pin.76 to EC Pin.73 For common design
21 P.42 Add VGATE to EC Pin.74 Reserve for sequence
22 P.42 Add SYS_PWROK to EC Pin.86 Reserve for sequence
23 P.42 Change EC_TS_ON# from EC Pin.85 to EC Pin.97 For common design
B B
24 P.42 Change DGPU_PWR_EN from EC Pin.107 to EC Pin.123 For common design

25 P.42 Change SUSCLK from EC Pin.123 to EC Pin.122 For common design
A A

Compal Secret Data
HW-PIR1
Custom 1.0
LA-9631P
5 4 3 2 1
5 4 3 2 1
VIWGP/R HW PIR List

DVT TO PVT
1 P.40 Delete R416, Add J9 No need Zero ODD Function
D 2 P.36 Reserve R508 For leakage current issue of Atheros WLAN D
3 P.33 Add R509 protect BKOFF# damage

4 P.42 Reserve R416 Reserve +3VLP power rail to EC
5 P.42 Change EC_RST# power rail to +3V_EC Using power rail which the same with EC.
6 P.42 Change EC_SMB_CK1 & EC_SMB_DA1 power rail to +3V_EC Using power rail which the same with EC.
7 P.14 Change U5 from 4MB to 8MB ROM Follow common design
8 P.14 Delete R266, R221, U6 It is for 2MB ROM, we don't need it
1 P.41 Reserve resistance to +3VLP and +3VALW. For Speaker Noise in S5
2 P.42 Reserve resistance in EC for share ROM. Follow common design
3 P.51 Reserve +V1.05S_VCCP_PWRGOOD of +V.05S_VCCP to connect to SA_PGOOD For Celeron CPU
C C
B B
A A

Compal Secret Data
HW-PIR2
Custom 1.0
LA-9631P
5 4 3 2 1

Compal Confidential: Gx00/Gx00 DIS M/B Schematics Document

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1bios.ru Security Classification

2 LVDS Conn. Left USB3.0 x2 Right USB2.0 Int. Camera

HDMI Conn. USB20 x6 Touch Screen Card Reader

WLAN Audio Codec

Int. MIC Conn. Int. Speaker Conn. Audio Combo Jacks

USB/B ODD/B Thermal Sensor Touch Pad Int. KBD

Voltage Rails BOARD ID Table

+5VALW +1.5V +VCC_CORE

12 VGA is Mars XT Mars@

Sun PRO VRAM STRAP

ZZZ9 ZZZ10 ZZZ11 ZZZ12 ZZZ13 ZZZ14 ZZZ16

Samsung_2G Micron_2G Hynix_2G Samsung_1G Micron_1G Hynix_1G Hynix_1G

Security Classification Compal Secret Data Compal Electronics, Inc.

ZZZ1 14@ ZZZ2 15@

PEG_ICOMPI and RCOMPO signals should be

PCI EXPRESS* - GRAPHICS

<16> FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_C_N5 C11 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N5

PEG_TX#[14] E25 PCIE_CTX_GRX_C_N0 C16 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N0

1bios.ru Security Classification

T48 H_CATERR# AL33

JTAG & BPM

R29 AL35 XDP_DBRESET# R28 2 1 1K_0402_5%

2 BPM#[1] AR30 XDP_BPM#2 47P_0402_50V8J

Buffered reset to CPU

1bios.ru Security Classification

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY A

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

CFG Straps for Processor

Interl request AH26 short GND

1: Normal Operation; Lane # definition matches

@ Display Port Presence Strap

R82 1 @ 2 100_0402_1% VSS_AXG_VAL_SENSE AH31 VAXG_VAL_SENSE RSVD39 G16

@ @ F23 1K_0402_1% 1K_0402_1%

D23 RSVD14 RSVD_NCTF9 C35

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

1bios.ru Security Classification

JCPU1F POWER +V1.05S_VCCP

PEG AND DDR

V33 VCC62 VIDALERT# AJ30 VR_SVID_ALRT# <54>

TYCO_2013620-2_IVY BRIDGE Security Classification Compal Secret Data

DDR3 -1.5V RAILS

VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <51>

A IVY Bridge drives VCCIO_SEL low A

Security Classification Compal Secret Data

ME@ Security Classification CompalME@

+VREF_DQ_DIMMA +1.5V +1.5V

A 201 202 SMB_CLK_S3 A

1 1 203 204 +0.75VS

ME@ Security Classification Compal Secret Data Compal Electronics, Inc.

A 1 2 201 202 SMB_CLK_S3 A

1 1 R97 10K_0402_5% 203 204 +0.75VS

ME@ Security Classification Compal Secret Data Compal Electronics, Inc.

Q10 AB13 SATA3_COMP 1 2

6 3 SPI_CLK SATA3RBIAS R115