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Mask Summary: The Masks Encountered For Well Specification May Include N-Well

This document discusses CMOS processing technology and transistor rules. It describes how wells are specified using n-well, p-well and deep n-well masks. Transistors are generally defined using active, n-select, p-select and polysilicon masks. The active mask defines diffusion and gate areas, and select masks define diffusion types. Polysilicon must cross active completely to avoid shorts, and active must extend beyond polysilicon for source and drain regions. Contact rules allow connection of metal to n-diffusion and p-diffusion areas.

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Carlos Saavedra
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108 views1 page

Mask Summary: The Masks Encountered For Well Specification May Include N-Well

This document discusses CMOS processing technology and transistor rules. It describes how wells are specified using n-well, p-well and deep n-well masks. Transistors are generally defined using active, n-select, p-select and polysilicon masks. The active mask defines diffusion and gate areas, and select masks define diffusion types. Polysilicon must cross active completely to avoid shorts, and active must extend beyond polysilicon for source and drain regions. Contact rules allow connection of metal to n-diffusion and p-diffusion areas.

Uploaded by

Carlos Saavedra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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114 Chapter 3 CMOS Processing Technology

across the well boundary. Processes that use STI may permit zero inside clearance. In
older LOCOS processes, problems such as the bird’s beak effect usually force substantial
clearances. Being able to place nMOS and pMOS transistors closer together can signifi-
cantly reduce the size of SRAM cells.
Because the n-well sheet resistance can be several k< per square, it is necessary to
ground the well thoroughly by providing a sufficient number of well taps. This will prevent
excessive voltage drops due to well currents. Guidelines on well and substrate taps are
given in Section 7.3.6. Where wells are connected to different potentials (say in analog
circuits), the spacing rules may differ from equipotential wells (all wells at the same volt-
age––the normal case in digital logic).
Mask Summary: The masks encountered for well specification may include n-well,
p-well, and deep n-well. These are used to specify where the various wells are to be placed.
Often only one well is specified in a twin-well process (i.e., n-well) and by default the
p-well is in areas where the n-well isn’t (i.e., p-well equals the logical NOT of the n-well).

3.3.1.2 Transistor Rules CMOS transistors are generally defined by at least four physical
masks. These are active (also called diffusion, diff, thinox, OD, or RX), n-select (also called
n-implant, nimp, or nplus), p-select (also called p-implant, pimp, or pplus) and polysilicon
(also called poly, polyg, PO, or PC). The active mask defines all areas where either n- or p-
type diffusion is to be placed or where the gates of transistors are to be placed. The gates of
transistors are defined by the logical AND of the polysilicon mask and the active mask, i.e.,
where polysilicon crosses diffusion. The select layers define what type of diffusion is
required. n-select surrounds active regions where n-type diffusion is required. p-select sur-
rounds areas where p-type diffusion is required. n-diffusion areas inside p-well regions
define nMOS transistors (or n-diffusion wires). n-diffusion areas inside n-well regions
define n-well contacts. Likewise, p-diffusion areas inside n-wells define pMOS transistors
(or p-diffusion wires). p-diffusion areas inside p-wells define substrate contacts (or p-well
contacts). Frequently, design systems will define only n-diffusion (ndiff ) and p-diffusion
(pdiff ) to reduce the complexity of the process. The appropriate selects are generated auto-
matically. That is, ndiff will be converted automatically into active with an overlapping
rectangle or polygon of n-select.
It is essential for the poly to cross active completely; otherwise the transistor that has
been created will be shorted by a diffusion path between source and drain. Hence, poly is
required to extend beyond the edges of the active area. This is often termed the gate exten-
sion. Active must extend beyond the poly gate so that diffused source and drain regions exist
to carry charge into and out of the channel. Poly and active regions that should not form a
transistor must be kept separated; this results in a spacing rule from active to polysilicon.
Figure 3.15(a) shows the mask construction for the final structures that appear in
Figure 3.15(b).
Mask Summary: The basic masks (in addition to well masks) used to define transistors,
diffusion interconnect (possibly resistors), and gate interconnect are active, n-select, p-select,
and polysilicon. These may be called different names in some processes. Sometimes
n-diffusion (ndiff ) and p-diffusion (pdiff ) masks are used in place of active to alleviate
designer confusion.

3.3.1.3 Contact Rules There are several generally available contacts:


 Metal to p-active (p-diffusion)
 Metal to n-active (n-diffusion)

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