Exercises: V L T I I I I I

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Exercises 95

Even when the gate voltage is low, the transistor is not completely OFF. Subthreshold
current through the channel drops off exponentially for Vgs < Vt , but is nonnegligible
for transistors with low thresholds. Junction leakage currents flow through the reverse-biased
p–n junctions. Tunneling current flows through the insulating gate when the oxide becomes
thin enough.
We can derive the DC transfer characteristics and noise margins of logic gates using
either analytical expressions or a graphical load line analysis or simulation. Static CMOS
gates have excellent noise margins.
Unlike ideal switches, MOS transistors pass some voltage levels better than others.
An nMOS transistor passes 0s well, but only pulls up to VDD – Vtn when passing 1s. The
pMOS passes 1s well, but only pulls down to |Vtp| when passing 0s. This threshold drop is
exacerbated by the body effect, which increases the threshold voltage when the source is at
a different potential than the body.
There are too many parameters in a modern BSIM model for a designer to deal with
intuitively. Instead, CMOS transistors are usually characterized by the following basic fig-
ures of merit:
 VDD Target supply voltage
 Lgate / Lpoly Effective channel length (< feature size)
 tox Effective oxide thickness (a.k.a. EOT)
 Idsat Ids @ Vgs = Vds = VDD
 Ioff Ids @ Vgs = 0, Vds = VDD
 Ig Gate leakage @ Vgs = VDD
[Muller03] and [Tsividis99] offer comprehensive treatments of device physics at a
more advanced level. [Gray01] describes MOSFET models in more detail from the ana-
log designer’s point of view.

Exercises
2.1 Consider an nMOS transistor in a 0.6 Rm process with W/L = 4/2 Q (i.e., 1.2/0.6
Rm). In this process, the gate oxide thickness is 100 Å and the mobility of electrons
is 350 cm2/V· s. The threshold voltage is 0.7 V. Plot Ids vs. Vds for Vgs = 0, 1, 2, 3, 4,
and 5 V.
2.2 Show that the current through two transistors in series is equal to the current through
a single transistor of twice the length if the transistors are well described by the Shock-
ley model. Specifically, show that IDS1 =
IDS2 in Figure 2.32 when the transistors are IDS1 IDS2
in their linear region: VDS < VDD – Vt , VDD W/L
> Vt (this is also true in saturation). Hint: V1
Express the currents of the series transis- W/2L W/L
tors in terms of V1 and solve for V1.
VDD VDS VDD VDS
2.3 In Exercise 2.2, the body effect was
ignored. If the body effect is considered, (a) (b)
will IDS2 be equal to, greater than, or less
than IDS1? Explain. FIGURE 2.32 Current in series transistors

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