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C C C C C C C C: TABLE 2.1 Parameter Cutoff Linear Saturation

The document discusses gate capacitance in MOS transistors. It notes that there are intrinsic gate capacitances between the gate and source (Cgs), gate and drain (Cgd), and gate and body (Cgb). However, real devices also have additional overlap capacitances (Cgsol and Cgdol) due to the gate overlapping the source and drain. These overlap capacitances are proportional to the width of the transistor. The effective total gate capacitance can vary depending on whether the source, drain, or both are switching. For delay calculations in digital circuits, the gate capacitance is typically approximated as Cg = Cgs + Cgd + Cgb ~ C0 + 2CgolW

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13 views1 page

C C C C C C C C: TABLE 2.1 Parameter Cutoff Linear Saturation

The document discusses gate capacitance in MOS transistors. It notes that there are intrinsic gate capacitances between the gate and source (Cgs), gate and drain (Cgd), and gate and body (Cgb). However, real devices also have additional overlap capacitances (Cgsol and Cgdol) due to the gate overlapping the source and drain. These overlap capacitances are proportional to the width of the transistor. The effective total gate capacitance can vary depending on whether the source, drain, or both are switching. For delay calculations in digital circuits, the gate capacitance is typically approximated as Cg = Cgs + Cgd + Cgb ~ C0 + 2CgolW

Uploaded by

Carlos Saavedra
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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2.

3 C-V Characteristics 71

TABLE 2.1 Approximation for intrinsic MOS gate capacitance


Parameter Cutoff Linear Saturation
Cgb f C0 0 0
Cgs 0 C0/2 2/3 C0
Source Gate Drain
Cgd 0 C0/2 0
Cg = Cgs + Cgd + Cgb C0 C0 2/3 C0 Cgsol Cgdol

The gate overlaps the source and drain in a real device and also has fring- n+ n+
ing fields terminating on the source and drain. This leads to additional overlap p
capacitances, as shown in Figure 2.10. These capacitances are proportional to
the width of the transistor. Typical values are Cgsol = Cgdol = 0.2 – 0.4 f F /Rm.
FIGURE 2.10 Overlap capacitance
They should be added to the intrinsic gate capacitance to find the total.

C gsol ( overlap ) = C gsolW


(2.15)
C gdol ( overlap ) = C gdolW

It is convenient to view the gate capacitance as a single-terminal capacitor attached to


the gate (with the other side not switching). Because the source and drain actually form
second terminals, the effective gate capacitance varies with the switching activity of the
source and drain. Figure 2.11 shows the effective gate capacitance in a 0.35 Rm process for
seven different combinations of source and drain behavior [Bailey98].
More accurate modeling of the gate capacitance may be achieved by using a charge-
based model [Cheng99]. For the purpose of delay calculation of digital circuits, we usually
approximate Cg = Cgs + Cgd + Cgb ~ C0 + 2CgolW or use an effective capacitance extracted

Case 1

Case 2 Cg /C0
0
0
Case 3 1.3 Case 1
0
1.1 Case 2
1
Case 4 1.0 Case 3
0
.80 Case 4
1
Case 5
1
1 .42 Case 5
Case 6
.31 Case 6
.13 Case 7
Case 7

FIGURE 2.11 Data-dependent gate capacitance

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