Microprocessors and

Microcontrollers
Focus Areas: CONTROL ENGINEERING &
COMMUNICATION ENGINEERING

COMPILED BY: TIGABU Y.

UNIVERSITY OF GONDAR
INSTITUTE OF TECHNOLOGY

@2019
 Microprocessor
• Microprocessor (µP) is the “brain” of a computer
that has been implemented on one
semiconductor chip.
• The word comes from the combination micro and
processor.
• Processor means a device that processes
whatever(binary numbers, 0’s and 1’s)
 To process means to manipulate. It describes all
manipulation.
 Micro - > extremely small

2
 Definition of a Microprocessor.
The microprocessor is a
programmable device that takes in numbers,
performs on them arithmetic or logical
operations according to the program stored in
memory and then produces other numbers as
a result.

3
 Microprocessor ?

A microprocessor is multi
programmable clock driven
register based semiconductor
device that is used to fetch ,
process & execute a data
within fraction of seconds.
4
 Applications
• Calculators
• Accounting system
• Games machine
• Instrumentation
• Traffic light Control
• Multi user, multi-function environments
• Military applications
• Communication systems

5
 Evolution of Microprocessor
First Generation ( 1939 -1954)
Vacuum Tubes
Second Generation ( 1954 -1959)
Transistor
Third Generation ( 1999 -1971)
Integrated Circuit (IC)
Fourth Generation ( 1971 -Present)
Microprocessor
Microprocessor is scaling from 4004 to Pentium 4.
Microprocessor is identified with word size of data
6
MICROPROCESSOR HISTORY

7
 DIFFERENT PROCESSORS AVAILABLE

Socket
Pinless
Processor

Processor Slot
Processor

ProcessorSl
ot

8
 Development of Intel Microprocessors

• 8086 - 1979
• 286 - 1982
• 386 - 1985
• 486 - 1989
• Pentium - 1993
• Pentium Pro - 1995
• Pentium MMX -1997
• Pentium II - 1997
• Pentium II Celeron - 1998
• Pentium II Zeon - 1998
• Pentium III - 1999
• Pentium III Zeon - 1999
• Pentium IV - 2000
• Pentium IV Zeon - 2001

9
GENERATION OF PROCESSORS
Processor Bits Speed

8080 8 2 MHz

8086 16 4.5 – 10
MHz
8088 16 4.5 – 10
MHz
80286 16 10 – 20
MHz
80386 32 20 – 40
MHz
80486 32 40 – 133
MHz

10
GENERATION OF PROCESSORS

Processor Bits Speed

Pentium 32 60 – 233
MHz
Pentium 32 150 – 200
Pro MHz
Pentium II, 32 233 – 450
Celeron , MHz
Xeon
Pentium 32 450 MHz –
III, Celeron 1.4 GHz
, Xeon
Pentium IV, 32 1.3 GHz –
Celeron , 3.8 GHz
Xeon
Itanium 64 800 MHz –
3.0 GHz
11
Intel 4004
 Introduced in 1971.

 It was the first microprocessor

by Intel.

 It was a 4-bit µP.

 Its clock speed was 740KHz.

 It had 2,300 transistors.

 It could execute around

60,000 instructions per
second.

12
Intel 4040
Introduced in 1971.
It was also 4-bit µP.

13
8-bit Microprocessors

14
Intel 8008
Introduced in 1972.
It was first 8-bit µP.
Its clock speed was
500 KHz.
Could execute
50,000 instructions
per second.

15
Intel 8080
Introduced in 1974.
It was also 8-bit µP.
Its clock speed was
2 MHz.
It had 6,000
transistors.

16
 Introduced in 1976.
Intel 8085
It was also 8-bit µP.
Its clock speed was 3 MHz.
Its data bus is 8-bit and
address bus is 16-bit.
It had 6,500 transistors.
Could execute 7,69,230
instructions per second.
It could access 64 KB of
memory.
It had 246 instructions.

17
16-bit Microprocessors

18
  Introduced in 1978.

INTEL 8086  It was first 16-bit µP.

 Its clock speed is 4.77 MHz, 8 MHz

and 10 MHz, depending on the
version.

 Its data bus is 16-bit and address

bus is 20-bit.

 It had 29,000 transistors.

 Could execute 2.5 million

instructions per second.

 It could access 1 MB of memory.

 It had 22,000 instructions.

 It had Multiply and Divide

instructions.
INTEL 8088
 Introduced in 1979.

 It was also 16-bit µP.

 It was created as a
cheaper version of
Intel’s 8086.

 It was a 16-bit processor

with an 8-bit external
bus.
19
INTEL 80186 & 80188
 Introduced in 1982.
 They were 16-bit µPs.
 Clock speed was 6 MHz.
 80188 was a cheaper
version of 80186 with an
8-bit external data bus.
INTEL 80286
 Introduced in 1982.
 It was 16-bit µP.
 Its clock speed was 8
MHz.
 Its data bus is 16-bit
and address bus is 24-
bit.
 It could address 16 MB
of memory.
 It had 1,34,000 21
transistors.
32-BIT MICROPROCESSORS
  Introduced in 1986.

INTEL 80386  It was first 32-bit µP.

 Its data bus is 32-bit
and address bus is 32-
bit.
 It could address 4 GB of
memory.
 It had 2,75,000
transistors.
 Its clock speed varied
from 16 MHz to 33 MHz
depending upon the
23
various versions.
  Introduced in 1989.
INTEL 80486
 It was also 32-bit µP.
 It had 1.2 million
transistors.
 Its clock speed varied
from 16 MHz to 100
MHz depending upon
the various versions.
 8 KB of cache memory
was introduced.

25
  Introduced in 1993.
INTEL PENTIUM
 It was also 32-bit µP.

 It was originally named

80586.

 Its clock speed was 66

MHz.

 Its data bus is 32-bit

and address bus is 32-
bit.

26
INTEL PENTIUM PRO
 Introduced in 1995.
 It was also 32-bit µP.
 It had 21 million
transistors.
 Cache memory:
 8 KB for instructions.

 8 KB for data.

27
INTEL PENTIUM II
 Introduced in 1997.
 It was also 32-bit µP.
 Its clock speed was 233
MHz to 500 MHz.
 Could execute 333
million instructions per
second.

28
INTEL PENTIUM II XEON
 Introduced in 1998.

 It was also 32-bit µP.

 It was designed for

servers.

 Its clock speed was 400

MHz to 450 MHz.

29
INTEL PENTIUM III
 Introduced in 1999.
 It was also 32-bit µP.
 Its clock speed varied
from 500 MHz to 1.4
GHz.
 It had 9.5 million
transistors.
INTEL PENTIUM IV
 Introduced in 2000.

 It was also 32-bit µP.

 Its clock speed was from

1.3 GHz to 3.8 GHz.

 It had 42 million
transistors.
  Introduced in 2006.
INTEL DUAL CORE
 It is 32-bit or 64-bit µP.
64-BIT MICROPROCESSORS
Intel Core 2 Intel Core i3
INTEL CORE I5 INTEL CORE I7
 Basic Terms
• Bit: A digit of the binary number { 0 or 1 }
• Nibble: 4 bit Byte: 8 bit word: 16 bit
• Double word: 32 bit
• Data: binary number/code operated by an
instruction
• Address: Identification number for memory
locations
• Clock: square wave used to synchronize various
devices in µP
• Memory Capacity = 2^n ,
n->no. of address lines
37
 BUS CONCEPT
• BUS: a collection of wires through which data is
transmitted
• Data: data, address or control signals
• The size of bus (its width) is how many bits it
can transfer at a time.
CLASSIFICATION OF BUSES:
1. Address Bus: sends a memory address along bus
from the CPU to the memory. To fetch/write
data, the CPU needs to tell the RAM the address
2. ADDRESS BUS: sends the actual data to and
from the memory
3. CONTROL BUS: carries commands from the
CPU and status messages from other
hardware devices 38
 BUS CONCEPT
• BUS: Group of conducting lines that carries data ,
address & control signals.
CLASSIFICATION OF BUSES:
1. DATA BUS: group of conducting lines that carries
data.
2. ADDRESS BUS: group of conducting lines that
carries address.
3. CONTROL BUS: group of conducting lines that
carries control signals {RD, WR etc}
CPU BUS: group of conducting lines that directly
connected to µP
SYSTEM BUS: group of conducting lines that carries
data , address & control signals in a µP system
39
Microcomputer CONCEPT

40
 TRISTATE LOGIC
3 logic levels are:
• High State (logic 1)
• Low state (logic 0)
• High Impedance state

High Impedance: output is not being driven to any defined logic level
by the output circuit.

41
 Basic Microprocessors System
Central Processing Unit
Arithmetic-
Control
Logic
Unit
ProcessingUnit
Input Data into Output
Devices Information
Primary Storage Devices
Unit
Keyboard, Monitor
Mouse Printer
etc

Disks, Tapes, Optical Disks

Secondary Storage Devices 39

 UNIT

2
THE 8086 MICROPROCESSOR

43
 UNIT 2 Syllabus
• Introduction to 8086 – Features
• Memory and Memory Segmentations
• Microprocessor architecture
 Bus Interface Unit  Execution Unit
 Instruction Queue  Instruction Decoder
 Segment Registers  Control System
 Instruction Pointer  Arithmetic Logic Unit
 Address Adder ( Address  General Purpose
Summing Block Registers
 Flag Register
 Pointer & Index registers
44
 8086 Microprocessor-features
 INTEL launched 8086 in 1978
 8086 is a 16-bit microprocessor.
 8086 has a 20 bit address bus can access
up to 𝟐𝟐𝟎 = 10,48,576 bytes memory
locations (1 MB).
 It provides 14, 16 -bit registers.
 Word size is 16 bits.
 It requires single phase clock with 33% duty
cycle to provide internal timing.
 It can support upto 64K I/O ports
45
 8086 Microprocessor-features cont’d
 8086 is designed to operate in two modes,
Minimum and Maximum.
 It can prefetches up to 6 instruction bytes from
memory and queues them in order to speed up
instruction execution.
 It requires +5V power supply.
 A 40 pin dual in line package.
 Address ranges from 00000H to FFFFFH
 Memory is byte addressable - Every byte has a
separate address.
46
 8086 Microprocessor-features cont’d
8086 is a 16-bit microprocessor with
 16-bit Data Bus {D0-D15}
 20-bit Address Bus {A0-A19} [can access
up to [𝟐𝟐𝟎 = 1,048,576 bytes = 1 MB
memory locations] .
It has multiplexed address and data
bus AD0-AD15 and A16–A19.

47
 8086 Microprocessor
8086 requires one phase clock with a
33% duty cycle to provide optimized
internal timing.
 Range of clock:
• 5 MHz for 8086
• 8Mhz for 8086-2
• 10Mhz for 8086-1

48
 Memory (RAM)
 In memory, data is stored as bytes.
 Each byte has a specific address.
 Intel 8086 has 20 lines address bus.
 With 20 address lines, the memory that can
be addressed is 𝟐𝟐𝟎 bytes.
 𝟐𝟐𝟎 = 1,048,576 bytes (1 MB).
 8086 can access memory with address
ranging from 00000 H to FFFFF H.

49
 Memory Segmentation
 Segmentation is the process in which the
main memory of the computer is logically
divided into different segments and each
segment has its own base address.
 The total memory size is divided into
segments of various sizes.
 Segment is just an area in memory.
 The process of dividing memory this way is
called Segmentation.

50
 Memory Segmentation
 8086 has a 20-bit address bus
 So it can address a maximum of 1MB of
memory
 8086 can work with only four 64KB segments
at a time within this 1MB range
 These four memory segments are called
• Code segment
• Stack segment
• Data segment
• Extra segment

51
 Memory
64KB Memory 1
00000H
2
Segment
3
4
4
5
Only 4 such segments can be 6
addressed at a time 7

8
1MB
9 Address
10 Range
11

12

13

14

15

16
FFFFFH
52
 Code Segment
 That part of memory from where BIU is
currently fetching instruction code bytes

Stack Segment
 A section of memory set aside to store
addresses and data while a subprogram
executes

Data & Extra Segments

 Used for storing data values to be used in
the program

53
 Memory
Code Segment 1
00000H
2

4
Data & Extra 5

Segments 6

8
1MB
9 Address
10 Range
11

12

13

14

15

Stack Segment 16 FFFFFH

54
 8086 Internal Architecture
 8086 employs parallel processing
 8086 CPU has two parts which operate at the
same time
• Bus Interface Unit 8086 CPU
• Execution Unit
 CPU functions Bus Interface
Unit (BIU)
1. Fetch

2. Decode Execution Unit

(EU)
3. Execute

55
 8086 Internal Architecture
 8086 has two blocks BIU and EU.
 The BIU handles all transactions of data and
addresses on the buses for EU.
 The BIU performs all bus operations such as
instruction fetching, reading and writing
operands from/to memory and calculating the
addresses of the memory operands. The
instruction bytes are transferred to the
instruction queue.
 EU executes instructions from the instruction
system byte queue.
56
 Bus Interface Unit
Sends out addresses for memory locations
Fetches Instructions from memory
Reads/Writes data to memory
Sends out addresses for I/O ports
Reads/Writes data from/to Input/Output
ports

57
 Execution Unit
Tells BIU (addresses) from where to
fetch instructions or data, decodes
& Executes instructions

Dividing the work between BIU & EU

speeds up processing

58
Architecture Diagram of 8086

59
Instruction Decoder

Control System

49
 Execution Unit
Main components are
• Instruction Decoder
• Control System
• Arithmetic Logic Unit
• General Purpose Registers
• Flag Register
• Pointer & Index registers

61
Execution Unit

62
 Instruction Decoder
 Translates instructions fetched from memory
into a series of actions which EU carries out

Control System
 Generates timing and control signals to
perform the internal operations of the
microprocessor (Directs the internal operations)

Arithmetic Logic Unit

 EU has a 16-bit ALU which can ADD,
SUBTRACT, AND, OR, increment, decrement,
complement or shift binary numbers
63
Registers
Registers
 General Purpose Registers
 EU has 8 general
purpose registers
 are used to store
temporary data in the time
of different operations in
microprocessor.
 AL register is also called
Accumulator
 Two registers can also be
combined to form 16-bit
registers
 The valid register pairs are
– AX, BX, CX, DX
 General Purpose Registers
 AX - the accumulator register (divided into
AH / AL):
 Accumulator Register
 Preferred register to use in arithmetic, logic and
data transfer instructions because it generates
the shortest Machine Language Code
 Must be used in multiplication and division
operations
 Must also be used in I/O operations
 BX - the base address register (divided into
BH / BL). Also serves as an address Reg. 67
 General Purpose Registers
 CX - the count register (divided into CH /
CL): Counter Register
 Iterative code segments using the LOOP
instruction
 Repetitive operations on strings with the REP
command
 Count (in CL) of bits to shift and rotate
 DX - the data register (divided into DH / DL):
 DX:AX concatenated into 32-bit register for some
MUL and DIV operations
 Also used in I/O operations. 68
 Pointers and Index Registers
 Used to Keep offset addresses.
 Used in various forms of memory addressing.

 The index registers (SI & DI) and the BX

generally default to the Data segment register
(DS).
69
 Pointers and Index Registers
 SI - source index register:
 Can be used for pointer addressing of data
 Used as source in some string processing
instructions
 Offset address relative to DS
 DI - destination index register:
 Can be used for pointer addressing of data
 Used as destination in some string processing
instructions
 Offset address relative to ES
70
 Pointers and Index Registers
 SI - source index register:
 is required for some string operations
 When string operations are performed, the SI register points
to memory locations in the data segment which is
addressed by the DS register. Thus, SI is associated with
the DS in string operations.

 DI - destination index register:

 is also required for some string operations.
 When string operations are performed, the DI register
points to memory locations in the data segment which is
addressed by the ES register. Thus, DI is associated with
the ES in string operations.
 The SI and the DI registers may also be used to access data
stored in arrays 71
 Pointers and Index Registers
 BP - base pointer:
 Primarily used to access parameters (data)
passed via the stack
 Offset address relative to SS
 Can be used to access data in other segments
 SP - stack pointer:
 Always points to top item on the stack
 Offset address relative to SS
 Always points to word (byte at even address)
 An empty stack will had SP = FFFEh
72
 Flag Register
A flag register a flip-flop which indicates
some condition produced by the execution
of instruction or controls certain
operations of the EU (Execution Unit)
8086 has a 16-bit flag register
Contains 9 active flags

73
 Flag Register
8086 has a 16-bit flag register
Contains 9 active flags
There are two types of flags in 8086
• Conditional flags – six flags, set or reset
by EU on the basis of results of some
arithmetic operations
• Control flags – three flags, used to control
certain operations of the processor

74
 Flag Register
U U U U OF DF IF TF SF ZF U AF U PF U CF

1. CF CARRY FLAG
Conditional Flags
2. PF PARITY FLAG
(Compatible with 8085,
3. AF AUXILIARY CARRY
except OF)
4. ZF ZERO FLAG
5. SF SIGN FLAG

6. OF OVERFLOW FLAG
7. TF TRAP FLAG
Control Flags
8. IF INTERRUPT FLAG
9. DF DIRECTION FLAG
75
 Flag Register
Auxiliary Carry Flag
Carry Flag
This is set, if there is a carry from the
lowest nibble, i.e, bit three during This flag is set, when there is
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number of
zero 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag If this flag is set, it will work in a
This flag is set, if an overflow occurs, i.e, if the result of a signed single step mode. After each
operation is large enough to accommodate in a destination instruction, one internal interrupt
register. The result is of more than 7-bits in size in case of 8-bit is generated. It helps to execute
signed operation and more than 15-bits in size in case of 16-bit some program instruction by
sign operations, then the overflow will be set. instruction.
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest If IF = 1, then MPU will recognize
address to the highest address, i.e., auto incrementing mode. the interrupts from peripherals. For
Otherwise, the string is processed from the highest address IF = 0, the interrupts will be 54
ignored
towards the lowest address, i.e., auto incrementing mode.
 Flag Register
 Six of the flags are status indicators reflecting
properties of the last arithmetic or logical instruction.
 For example, if register AL = 7Fh and the instruction
ADD AL,1 is executed then the following happen
 AL = 80h
 CF = 0; there is no carry out of bit 7
 PF = 0; 80h has an odd number of ones
 AF = 1; there is a carry out of bit 3 into bit 4
 ZF = 0; the result is not zero
 SF = 1; bit seven is one
 OF = 1; the sign bit has changed 77
 Registers, Flag

8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

into 4 groups OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

1 General purpose 16 bit AX, BX, CX, DX
register
8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

55
 Registers and Special Functions

Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic

operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic

operations

BX Base register Used to hold base value in base addressing mode

to access memory data

CX Count Register Used to hold the count value in SHIFT, ROTATE

and LOOP instructions

DX Data Register Used to hold data for multiplication and division

operations

SP Stack Pointer Used to hold the offset address of top stack

memory

BP Base Pointer Used to hold the base value in base addressing

using SS register to access data from stack
memory

SI Source Index Used to hold index value of source operand (data)

for string instructions

DI Data Index Used to hold the index value of destination

operand (data) for string operations 56
Bus Interface Unit

80
 Bus Interface Unit

Main Components are

• Instruction Queue
• Segment Registers
• Instruction Pointer
• Address Adder ( Address Summing Block

81
 Instruction Queue
 8086 employs parallel processing
 When EU is busy decoding or executing current
instruction, the buses of 8086 may not be in use.
 At that time, BIU can use buses to fetch upto six
instruction bytes for the following instructions
 BIU stores these pre-fetched bytes in a FIFO
register called Instruction Queue
 So that the execution unit gets the instructions
for execution in the order they are fetched.
 When EU is ready for its next instruction, it simply
reads the instruction from the queue in BIU

82
 Pipelining
EU of 8086 does not have to wait in
between for BIU to fetch next
instruction byte from memory
So the presence of a queue in 8086
speeds up the processing
Feature of fetching the next instruction
while the current instruction executes
is called pipelining
83
 Memory Segmentation
 Segmentation is the process in which the
main memory of the computer is logically
divided into different segments and each
segment has its own base address. It is
basically used to enhance the speed of
execution of the computer system, so that
the processor is able to fetch and execute
the data from the memory easily and fast.

84
 Memory Segmentation
 8086 has a 20-bit address bus
 So it can address a maximum of 1MB of
memory
 8086 can work with only four 64KB segments
at a time within this 1MB range
 These four memory segments are called
• Code segment
• Stack segment
• Data segment
• Extra segment

85
 Memory
64KB Memory 1
00000H
2
Segment
3
4
4
5
Only 4 such segments can be 6
addressed at a time 7

8
1MB
9 Address
10 Range
11

12

13

14

15

16
FFFFFH
86
 Code Segment
 That part of memory from where BIU is
currently fetching instruction code bytes

Stack Segment
 A section of memory set aside to store
addresses and data while a subprogram
executes

Data & Extra Segments

 Used for storing data values to be used in
the program

87
 Memory
Code Segment 1
00000H
2

4
Data & Extra 5

Segments 6

8
1MB
9 Address
10 Range
11

12

13

14

15

Stack Segment 16 FFFFFH

88
 Segment Registers

Physical address of 8086 is 20 Bit wide (To

access 1 Mb memory locations)
BUT- But the registers and memory
locations which contains logical address
are 16 Bit
Hence segmentation is required

89
 Segment Registers
hold the upper 16-bits of the starting
address for each of the segments
The four segment registers are
• CS (Code Segment register)
• DS (Data Segment register)
• SS (Stack Segment register)
• ES (Extra Segment register)

90
Segment Registers and Segmentation

91
 Memory
1 00000H
CS 1000 0H Code Segment
3

DS 4000 0H Data Segment

ES 5000 0H Extra Segment

7

Starting Addresses
8
1MB
9
of Segments Address
10
Range
11

12

13

14

15

SS F000 0H Stack Segment

FFFFFH 92
 Max. size of Segment
All offsets are limited to 16-bits.
It means that the maximum size
possible for segment is 𝟐𝟏𝟔 -1 = 65,535
bytes (64 KB).
 The offset of the first location within the
segment is 0000 H.
The offset of the last location in the
segment is FFFF H.

93
Max. size of Segment

94
95
Address of a segment is of 20-bits
A segment register stores only upper 16-
bits
BIU always inserts zeros for the lowest 4-
bits of the 20-bit starting address.
E.g. if CS = 348AH, then the code
segment will start at 348A0H
A 64-KB segment can be located
anywhere in the memory, but will start at
an address with zeros in the lowest 4-bits
96
Physical Address Generation
In order to calculate the physical
address, we need to master the
concept of:
 Memory Segmentation and the
Segments
 Segment Registers
 Index and pointer Registers

97
 Instruction Pointer and summing block
 Instruction Pointer (IP) Register
 a 16-bit register
 Holds 16-bit offset, of instruction in the
code segment that is to be executed
next.
 The IP always references the Code
segment register (CS).
 BIU uses IP and CS registers to
generate the 20-bit address of the
instruction to be fetched from memory.
98
 Instruction Pointer and summing block
 The value contained in the instruction pointer
is called as an offset because this value must
be added to the base address of the code
segment, which is available in the CS register
to find the 20-bit physical address.
 The value of the instruction pointer is
incremented after executing every instruction.
 To form a 20bit address of the next instruction,
the 16 bit address of the IP is added (by the
address summing block) to the address
contained in the CS , which has been shifted
four bits to the left. 99
Physical Address Generation
The BIU has a dedicated adder for
determining physical memory addresses

10
0
Physical Address Generation
Example:
 If the data segment starts at location
1000h and a data reference contains
the address 29h where is the actual
data?
Offset: 0000000000101001

Segment: 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0

Address: 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 01 0 0 1

10
1
Physical Address Generation

 Logical Address is specified as segment: offset

 Physical address is obtained by shifting the
segment address 4 bits to the left and adding the
offset address
 Thus the physical address of the logical address
A4FB:4872 is
A4FB0
+ 4872
A9822
102
Physical Address Generation

103
 Physical Address Calculation Memory
Start of Code Segment 1 00000H
348A0H Data
Segment
IP = 4214H 3

4
Code Byte 38AB4H MOV AL, BL
Code
Segment
Extra
Segment
7 1MB
8 Address
9
Range
CS 348A0 H 10

11
IP + 4214 H 12
Physical Address 38AB4 H 13

14

15

Stack
68
Segment FFFFF H
 Stack Segment (SS) Register
Stack Pointer (SP) Register
Upper 16-bits of the starting address of
stack segment is stored in SS register
It is located in BIU
SP register holds a 16-bit offset from the
start of stack segment to the top of the
stack
It is located in EU

10
5
Other Pointer & Index Registers
Base Pointer (BP) register
Source Index (SI) register
Destination Index (DI) register
Can be used for temporary storage of data
Main use is to hold a 16-bit offset of a data
word in one of the segments

10
6
Segment and Address register
combination
CS:IP
SS:SP SS:BP
DS:BX DS:SI
DS:DI (for other than string operations)
ES:DI (for string operations)

10
7
Summary of Registers & Pipeline of
8086 µP

10
8
Where to Look for the Offset

10
9
Question

11
0
Solution

11
1