IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 17, NO.

4, APRIL 1999 539

Analog-to-Digital Converter Survey and Analysis

Robert H. Walden, Member, IEEE

Abstract—Analog-to-digital converters (ADC’s) are ubiquitous, also important for ADC’s to be used in receivers. Fig. 1
critical components of software radio and other signal processing shows ADC resolution, as stated by the manufacturer versus
systems. This paper surveys the state-of-the-art of ADC’s, includ- sampling rate, Over 150 converters (listed in Appendix
ing experimental converters and commercially available parts.
The distribution of resolution versus sampling rate provides I), including experimental systems and commercially available
insight into ADC performance limitations. At sampling rates parts, are represented in the graph. Strictly speaking, this data
below 2 million samples per second (Ms/s), resolution appears does not represent measured performance. It does, however,
to be limited by thermal noise. At sampling rates ranging from show two important features. First, approximately one bit of
2 Ms/s to 4 giga samples per second (Gs/s), resolution falls off
by 1 bit for every doubling of the sampling rate. This behavior
resolution is lost for every doubling of the sampling rate.
may be attributed to uncertainty in the sampling instant due This is indicated by the state-of-the-art line on the graph.
to aperture jitter. For ADC’s operating at multi-Gs/s rates, the Second, the highest Nyquist sampling rate attained is 8 giga
speed of the device technology is also a limiting factor due to samples per second (Gs/s) [5]. An analysis of SNR shows that
comparator ambiguity. Many ADC architectures and integrated the 1-bit per octave slope is related to the sample-to-sample
circuit technologies have been proposed and implemented to push variation of the instant in time at which sampling occurs. This
back these limits. The recent trend toward single-chip ADC’s
brings lower power dissipation. However, technological progress variation is called aperture jitter or aperture uncertainty.1 In
as measured by the product of the ADC resolution (bits) times addition, the speed of sampling is limited by the ability of
the sampling rate is slow. Average improvement is only 1.5 bits the comparator(s) to make an unambiguous decision regarding
for any given sampling frequency over the last six–eight years. the relative amplitude of the input voltage due to comparator
Index Terms—Analog-to-digital converters, aperture jitter, ambiguity. This is related to the speed of the device technology
comparator ambiguity, input-referred noise, signal-to-noise ratio, used to fabricate the ADC. Device speed is measured as the
spurious-free dynamic range. frequency at which there is unity current gain.
Section II of this paper discusses how ADC’s are evaluated,
I. INTRODUCTION then Section III deals with the performancae limitations in
more detail. ADC architectures that are presently under in-

D URING the past two decades, the rapid evolution of

digital integrated circuit technologies has led to ever
more sophisticated signal processing systems. These systems
vestigation are presented in Sections IV and V. Performance
trends are discussed in Section VI.
operate on a wide variety of continuous-time signals including
II. ADC CHARACTERIZATION
speech, medical imaging, sonar, radar, electronic warfare, in-
strumentation, consumer electronics, and telecommunications There are a number of ways to measure and compare ADC
(terrestrial and satellite). One of the keys to the success performance. This paper focuses on determining the resolution
of these systems has been the advance in analog-to-digital in bits for a given sampling rate. In an increasing number of
converters (ADC’s) which convert the continuous-time signals applications, the power consumption is also important. Reso-
to discrete-time, binary-coded form. As an example, in the lution can be determined both quasistatically and dynamically.
telecommunications arena, advances in software radio devel- Quasi-static measures include differential nonlinearity (DNL)
opment [1]–[3] have provided impetus for ADC performance and integral nonlinearity (INL). Dynamic measures include
improvements, especially for sampling rates of approximately SNR, SFDR, and noise power ratio (NPR). These quantities are
100 million samples per second (Ms/s). More generally, the determined from spectral analysis, usually in the form of a fast
large number of signal types to be digitized has led to a Fourier transform (FFT) of a sequence of ADC output samples.
diverse selection of data converters in terms of architectures, This study focuses on SNR and SFDR because dynamic
resolution, and sampling rates. performance is most important for high-speed applications and
Despite the variety in ADC’s, their performances can be SNR and SFDR provide a more accurate measure of ADC
summarized by a relatively small number of parameters: performance than the stated-number-of-bits. In addition, SNR
stated resolution (number of bits per sample), signal-to-noise and SFDR are universally accepted performance measures.
ratio (SNR), spurious-free dynamic range (SFDR), and power SNR is the ratio of the root-mean-square (rms) signal
dissipation [4]. Two-tone intermodulation distortion is amplitude to the square-root of the integral of the noise power
1 In this paper, the terms aperture jitter and aperture uncertainty are
Manuscript received November 17, 1997; revised June 3, 1998 and August synonymous. Another term, aperture time, relates to the fact that sampling
9, 1998. is, in fact, not instantaneous, but is actually the result of a weighted averaging
The author is with HRL Laboratories LLC, Malibu, CA 90265 USA of the sample over a period of time. This effect does not limit SNR to the
(e-mail: [email protected]). degree that aperture jitter does, however variations in aperture time can be
Publisher Item Identifier S 0733-8716(99)02983-2. thought of as being included in the jitter effect.

0733–8716/99$10.00  1999 IEEE

540 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 17, NO. 4, APRIL 1999

Fig. 1. Survey of ADC’s.

Fig. 2. Example of quantization error. VFS is the full-scale voltage range, Fig. 3. Random approximation for quantization error. All errors within the
and Q is the size of the LSB. 6
range Q=2 are equally likely. The resulting SNR is linear in the number
of bits of resolution N:

spectrum over the frequency band of interest. For a Nyquist

content due to the simultaneity of complicated signals and
converter the frequency band of interest ranges from 0 to
noise. In this situation, the quantization error is approximately
Hz. The noise spectrum contains contributions from
random. The common white noise approximation is to assume
all the error mechanisms present. These include quantiza-
that the probabilities of quantization errors are equal. This
tion noise, circuit noise, aperture uncertainty, and comparator
random error process is described in Fig. 3 with the equations
ambiguity.
of SNR due solely to quantization noise. the sampling
The only error mechanism present in an ideal ADC is
interval, equals is the resolution of the converter
quantization. This error arises because the analog input signal
in bits. The SNR (in dB) of an ideal ADC is shown in the
may assume any value within the input range of the ADC while
lower portion of the figure It can be
the output data is a sequence of finite precision samples [6].
improved only by increasing
The example of Fig. 2 compares a sinusoidal waveform and its
In physical ADC devices, additional error mechanisms are
(reconstructed) digitized representation. The difference is the
present. Some of these other errors may also be characterized
quantization error. is the size of the elementary quantization
as white noise with the same expression for SNR as in Fig. 3,
step, which is the least significant bit (LSB) of a binary
except that represents an effective number of bits. The
representation of that value. In this case, the quantization error
notation SNR-bits refers to SNR-bits is given by
waveform and the analog waveform are strongly correlated.
In a more typical case, the analog input contains frequency (1)
WALDEN: ADC SURVEY AND ANALYSIS 541

of Fig. 4(a). There are many reasons for such a wide variation.
The design emphasis may render SNR more important in
some cases and SFDR more important in others. Other factors
include how well the design overcomes noise, aperture jitter,
comparator ambiguity, and the nonlinearity of the transistors.
A complete characterization of an ADC includes the values
of SNR and SFDR as a function of frequency with
as a parameter. For low values of the SNR is constant. It
decreases as increases. The value of at which the
SNR decreases to 3 dB below the low-frequency value is
the effective resolution bandwidth (ERBW). This important
characteristic implies the range of frequencies over which the
converter may be used. If then the ADC is
a Nyquist converter, which is the design goal of many ADC’s.
The characterization of an ADC includes the highest value of
for which Nyquist operation is sustained.
Not all widely published reports on ADC’s include the
conditions for Nyquist conversion. However, some still
achieve noteworthy sampling speed, SNR or SFDR. To
include these, the criterion for inclusion in this study is that
(a)
Furthermore, the low-frequency values
of SNR and SFDR are used.
a universal measure of ADC performance, is the prod-
uct of the effective number of quantization levels,
times the sample rate
(3)

a figure of merit that includes power dissipation [4], is

(4)

This figure of merit emphasizes efficiency with respect to

dissipated power, SNR, SFDR, and are used
subsequently to quantify ADC performance.
Two-tone intermodulation distortion (IMD) of ADC’s is
particularly relevant to receiver applications. One excites an
ADC with two sinusoids of equal amplitude but with different
frequencies, and observing spurious tones in the FFT
spectrum of the ADC output. The strongest such tone is
usually either second- or third-order
or Unfortunately, IMD data reported in the
(b)
literature is minimal. In addition, there is no standard set of
Fig. 4. Comparisons of stated bits (number of output leads) with (a) conditions for IMD evaluation, making comparisons between
SNR-bits and with (b) SFDR-bits.
ADC’s more difficult. Hence, IMD’s must be evaluated by the
prospective user for the intended application.
The difference between stated resolution and SNR bits for
a given ADC indicates the degradation in SNR due to all III. PERFORMANCE ANALYSIS
other error sources. Fig. 4(a) exhibits this difference with a
degradation of approximately 1.5 bits for a given sampling For a better understanding of ADC performance limits, it
rate, with scatter in the data. is helpful to plot the effective resolution as determined from
The effective number of bits associated with SFDR is SFDR and SNR. Fig. 5 shows the reported SFDR (where
available). Comparing Figs. 1 and 5 indicates that the effective
(2) resolution expressed as SFDR-bits is roughly the same as the
SFDR is the ratio of the single-tone signal amplitude to the stated resolution for the population is taken as a whole.
largest nonsignal component within the spectrum of interest. This is somewhat misleading because the difference Stated-
Fig. 4(b) shows the difference between stated resolution and bits minus SFDR-bits [see Fig. 4(b)], for a given converter is
SFDR-bits. Although the average difference is less than .5 3 bits, a wide variation.2
LSB, there is more scatter in this plot than for the SNR data 2 The terms stated bits and stated resolution are synonymous.
542 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 17, NO. 4, APRIL 1999

Fig. 5. Spur-free dynamic range expressed as effective number of bits according to SFDR-bits = SFDR(dBc)/6.02.

Fig. 6. Signal-to-noise ratio expressed as effective number of bits according to SNR-bits = (SNR(dB) 0 1.76)/6.02. The two values of P bracket
the current state of the art.

A similar graph of SNR-bits versus sample rate is shown maximum achievable resolutions, in SNR-bits, are
in Fig. 6. Comparing with Fig. 1 shows that the distribution
of ADC’s in the SNR-bits plane is approximately 1.5 to 2
bits lower than the distribution of stated resolutions. This thermal noise (referred to the input:
conclusion is consistent with Fig. 4(a). From the figure, the
(5)
state-of-the-art corresponds to the range
aperture uncertainty:
The data of Fig. 6 reveal global performance factors for
the ADC population. Many factors and loss mechanisms (6)
affect ADC performance. Aside from quantization noise, three
mechanisms limit achieved SNR: input-referred circuit noise comparator ambiguity:
(equivalent thermal noise), aperture uncertainty, and com- (7)
parator ambiguity. The equations that calculate the associated
WALDEN: ADC SURVEY AND ANALYSIS 543

= 0
Fig. 7. Signal-to-noise ratio according to SNR-bits (SNR(dB) 1.76)/6.02. Three sets of curves show performance limiters due to thermal noise, aperture
uncertainty, and comparator ambiguity. The Heisenberg limit is also displayed.

The derivations of these three equations are given in Ap-

pendix II. To summarize, and were derived
by developing expressions for the noise voltages associated
with thermal noise and aperture jitter, respectively and then
equating each with the equivalent quantization noise
The equivalent thermal noise resistance is denoted as
The rms aperture jitter is denoted as The expression
for reflects the probability that the comparator
will make an ambiguous decision [7], treating the result
as additive noise to the otherwise ideal quantization noise.
The ambiguity probability is related to the regeneration time
constant of the comparator. This is related to the unity-
current-gain frequency of the transistors employed in the
circuit. An analysis of the flash ADC in [5] indicated that Fig. 8. Applying the Heisenberg uncertainty principle to ADC performance
[8]. indicates that the ultimate limit in the resolution–sampling rate product is
From these expressions SNR curves are calculated for approximately four orders of magnitude beyond the current state of the art.
values of input-referred thermal noise, aperture jitter, and
which measures comparator ambiguity. Assume
tainty and/or technologies with GHz. Experimental
V, K for the thermal noise curves. Aperture jitter
HBT and HEMT IC technologies have been reported that have
is calculated for Nyquist sampling, i.e.,
devices with and ranging from 150 GHz to 260
Comparator ambiguity is determined from the regeneration GHz [9]–[11]. Hence, one can envision an eventual increase in
time constant of the IC technology. These are included in sampling rates of a factor of two to about four beyond today’s
Fig. 7, which contains the same SNR data as Fig. 6. The 8 Gs/s.
current state-of-the-art is limited by the equivalent of thermal The ultimate limit to the ADC resolution-sampling rate
noise associated with a 2 k resistor for sampling rates product may be estimated using the Heisenberg uncertainty
under 2 Ms/s. Aperture jitter, in the range 0.5 ps to 2 ps, principle. Let where is the energy of
limits SNR for the sampling frequency range of 2 Ms/s to the smallest resolvable signal, equivalent to .5 LSB, is
4 Gs/s. Comparator ambiguity is limited via the regeneration .5 sampling period and J-s is
time constant corresponding to a value of GHz for Planck’s constant. The analysis is summarized in Fig. 8. For
ADC’s at the highest sampling rates. The 3-bit, 8 Gs/s Nyquist 50 impedance and a 1 V peak-to-peak input signal, that limit
ADC [5] was fabricated with an GHz InP process. is approximately four orders of magnitude beyond the state-of-
The aperture uncertainty results in the bit/octave slope; this the-art, which is aperture jitter limited (see the curve labeled
is the dominant factor because the range of affected Heisenberg in Fig. 7). There are probably other limiting factors
values is so large. between aperture jitter and the uncertainty principle. Although
To continue to advance the state-of-the-art requires low- these are worthy of study, it is more urgent to develop a
noise designs that achieve less than 0.5 ps of aperture uncer- thorough understanding of aperture jitter.
544 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 17, NO. 4, APRIL 1999

Fig. 9. Histogram of the figure of merit F: The most power-efficient ADC’s have been reported within the past six years.

IV. HIGH-PERFORMANCE ADC ARCHITECTURES a rate which is many times the Nyquist output rate. Integration
The ADC’s of the preceding figures include architectures and feedback suppress the quantization noise in the lower
ranging from flash, a parallel technique, which is the fastest, portions of the spectrum relative to the delta–sigma clock
through integrating which is probably the most accurate but frequency. This technique requires few analog components.
The challenge is that a high speed IC technology is needed
which also is the slowest. Most of the converters have been
for RF applications. Recently, near ideal performance was
fabricated in silicon, while a few have been realized in gallium
reported with an InP HBT second-order modulator with
arsenide (GaAs) and indium phosphide (InP).
a sampling rate of 3.2 Gs/s and an over-sampling ratio of 32
The flash architecture uses comparators, where is
for a Nyquist rate of 100 Ms/s [19]. This converter technology
the stated resolution. Flash converters often include one or two
has GHz and GHz.
additional comparators to measure overflow conditions. All
Delta–sigma modulators may be designed with a bandpass
comparators sample the analog input voltage simultaneously. characteristic [20]–[22]. This is useful when a relatively nar-
This ADC is thus inherently fast. The fastest ADC reported is row band of intermediate frequencies contains the signal to be
the 3-bit, 8 Gs/s Nyquist flash converter [5] cited above. This digitized. Furthermore, the center frequency of the converter
ADC had a maximum sampling rate of 14 Gs/s. is tunable. Finally, in receiver applications, down conversion
The parallelism of the flash architecture has drawbacks stages are eliminated. Recently two bandpass delta–sigma
for high-resolution applications. The number of comparators modulators were reported with a 60 MHz center frequency [21]
grows exponentially with In addition, the separation of and an 800 MHz center frequency [22]. Both of these sample
adjacent reference voltages grows smaller exponentially. Con- at 4 GHz. These are the fastest bandpass modulators
sequently, this architecture requires very large IC’s. It has yet built. Further discussion of bandpass sampling for RF
high power dissipation. It is difficult to match components applications can be found in [2].
in the parallel comparator channels. Finally, increasingly large
input capacitance reduces analog input bandwidth. Most flash
converters available today have 8-bit resolution. In order to V. LOW-POWER ADC ARCHITECTURES
overcome these problems, variations on the flash architecture Another facet of ADC performance is power dissipation
have been developed which use relatively few comparators Generally the highest performing converters also dissi-
yet retain good speed. Examples capable of Gs/s rates are pate the most power. A convenient way to include in
the folded-flash [12]–[14]; and pipelined [15], [16] architec- the performance comparison is to use the figure of merit,
tures. defined above. Fig. 9 shows a histogram of for the ADC
Another approach to high-speed conversion is to time- population under study. Most of the ADC’s have values of
interleave two or more converters [17]. The reported ADC (the mean).
achieves ps aperture jitter, but requires two hybrids, each Two fictitious examples of converter specifications that
with five LSI chips. The total is 40 W, roughly an order would correspond approximately to this value of are: 1)
of magnitude larger than single-chip converters. 13 SNR-bits, 10 Ms/s, 1.1 W, and 2) 7 SNR-bits, 1 Gs/s, 1.75
An architecture that trades speed for resolution combines W. These two examples would represent present-day state-of-
delta–sigma modulation with digital decimation filtering the-art performance and correspond to an aperture jitter of
[18]. Delta–sigma converters sample the analog input signal at ps (see Fig. 7).
WALDEN: ADC SURVEY AND ANALYSIS 545

Fig. 10. Trend in SNR bits over time.

There are a few ADC’s with values significantly above derived from each value of using the relation
7.9 10 and some of these are pointed out in the figure.
These power-efficient converters utilize four architectures:
flash (low resolution only) [23], [24], folded-flash [12], [25],
pipelined [26]–[29], and modulation [30]–[33]. These Using this relation a graph of as a function of time
particular modulators, in contrast to the GHz circuits (year) can be generated and is shown in Fig. 11. In this figure
mentioned above, were designed in CMOS using switched- only the best results ps) are shown and the very
capacitors and are oriented toward lower frequency applica- best aperture jitter values achieved in each year are connected
tions. In addition, the accompanying digital decimation filters by a line. The scatter in the data emphasizes the sporadic
for these modulators have not been included in the power nature of improvement in however, a least squares fit
dissipation, so the actual complete ADC’s will have somewhat through the logs of the very best yearly data values indicates
lower values for The highest value of is 6.6 10 , and a gradual improvement over time. It can be conjectured that
corresponds to a superconducting (denoted by S.C. in Fig. 1) there may be an aperture uncertainty barrier of 0.5 ps.
ADC [34]. The refrigeration overhead was not included in the Some other reasons for the stagnation in ADC performance
determination of for this circuit. Most of these very efficient improvement may be: 1) that much of the recent research
converters have been reported within the last six years. has been aimed at monolithic, and therefore, power-efficient
ADC’s (c.f. Fig. 9); 2) a recent and general de-emphasis on
VI. ADC PERFORMANCE OVER TIME research and development; and 3) few application drivers
that push the state-of-the-art. Although software radios 100
It is revealing to examine the trends in ADC performances
Ms/s) and satellite communications Gs/s) may provide
during recent years. As an example, the data in Fig. 9 show
the incentives for a breakthrough.
that excellent progress has been made recently in developing
power-efficient designs. However, the same is not true for
the advancement of the resolution-speed product To show VII. SUMMARY
this, the SNR data in Fig. 6 were sorted according to the year The state-of-the-art for ADC’s has been reviewed and ana-
in which the ADC’s were reported. The results are given in lyzed. Data for SNR and SFDR as functions of has been
Fig. 10, and it is evident that relatively little improvement discussed. The SNR data show that converter performance
has been made over the last six–eight years or so. From the is limited by input-referred noise, aperture uncertainty and
scatter in the data it is also evident that the improvement is comparator ambiguity. The best results have been achieved
quite sporadic. A similar lack of advancement for SFDR-bits for flash, folded-flash, pipelined, and time-interleaved archi-
also holds. tectures.
If it is assumed that aperture uncertainty is the performance It is clear from the data presented above, that in order to
limiter for the best converters and if it is further assumed that improve upon the present state-of-the-art in ADC performance,
all of the ADC’s represented in Fig. 10 are Nyquist converters significant technical challenges must be met. Specifically 1) a
(optimistic) then, for each converter a value of can be reduction in aperture uncertainty to well below 1 ps, 2) an
546 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 17, NO. 4, APRIL 1999

Fig. 11. Derived aperture jitter for the best ADC performances as a function of the year of introduction. Converter performances are gradually improving,
although actual progress is sporadic.

increase in the maximum sampling frequency to beyond 8 thermal noise, shot noise, noise, and input-referred noise.
Gs/s, and 3) accomplishing both 1) and 2) while maintaining The thermal and shot components are white while the
low power consumption, e.g., 5 W. and input-referred components are frequency dependent. The
With respect to aperture uncertainty, only about 1.5 bits of resulting input-referred noise voltage is obtained by integrating
overall improvement has been achieved over the last six–eight these spectra over the full-Nyquist band and can be
years in SNR (and only one bit in SFDR). The best effort was expressed as
the time-interleaved ADC which achieved ps [17]. In
addition, while significant progress has been made in achieving
power-efficient ADC designs (high ), none of these efforts
has gone below 0.5–2 ps of aperture jitter.
where is Boltzmann’s constant J/K,
temperature in K (assumed 300 K in Fig. 7), and
APPENDIX I is an effective thermal resistance which lumps together the
See Table I. effects of all noises. The equivalent quantization noise voltage
is given by
APPENDIX II
This appendix contains the derivation of the three equations
which calculate the maximum ADC resolutions in SNR-bits
for input-referred thermal noise, aperture uncertainty, and,
where is the maximum resolution in SNR-bits (for
comparator ambiguity. The first two equations are obtained
a given value of Equating these two expressions leads
by developing expressions for the noise voltage due to each
directly to the desired result
mechanism and then equating to an equivalent quantization
noise. The ambiguity equation is developed by generating
an expression for the probability that an ambiguous decision
will be made by a particular comparator, then summing the
probabilities for all comparators, then adding the resulting
noise to an otherwise ideal quantization noise voltage. All three Aperture Uncertainty Derivation: This effect comes about
equations are developed as if each error (thermal, aperture, because an ADC does not sample the input signal at precisely
ambiguity) is acting alone. equal time-intervals, Instead the sampling
Thermal Noise Derivation: The spectral noise density seen process can be characterized by a mean and a standard
at the ADC input consists of various contributions such as deviation with regard to the location in time of when sampling
WALDEN: ADC SURVEY AND ANALYSIS 547

TABLE I

(a)

occurs. The mean is the average position of the sampling time error will occur when attempting to sample the sinusoid at its
and the standard deviation is a measure of the variation of zero-crossing, and is given by the product of the maximum
the sampling point and is defined as the rms aperture jitter, slope of the wave and the aperture uncertainty
Assuming that is known, an expression for the voltage
error due to can be derived. The worst case situation
corresponds to sampling a sinusoidal waveform with the
highest frequency in the Nyquist band, which is i.e., Equating this to the square root of the expression for
The maximum rms voltage given above (here is replaced by leads to
548 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 17, NO. 4, APRIL 1999

TABLE I (Continued.)

(b)

the desired relation for is given by [7]

where clock period regeneration

Comparator Ambiguity Derivation: This effect is due to the time constant [8], comparator gain, and
finite speed with which the transistors in the comparators is the effective LSB voltage Making the
are able to respond to a (small) voltage difference .5 implied substitutions yields
LSB). The probability that the th comparator will produce an
ambiguous decision as to whether the input signal is above or
below the reference voltage associated with said comparator
WALDEN: ADC SURVEY AND ANALYSIS 549

TABLE I (Continued.)

(c)

An equation for the quantization noise plus the contribu- REFERENCES

tions from all comparators due to the ambiguity probabilities
[1] J. Mitola, “The software radio architecture,” IEEE Commun. Mag., vol.
is [7] 33, pp. 26–38, May 1995.
[2] J. A. Wepman, “Analog-to-digital converters and their applications in
radio receivers,” IEEE Commun. Mag., vol. 33, pp. 39–45, May 1995.
[3] R. Baines, “The DSP bottleneck,” IEEE Commun. Mag., vol. 33, pp.
46–54, May 1995.
[4] R. H. Walden, “Analog-to-digital converter technology comparison,” in
IEEE GaAs IC Symp. Tech. Dig., Oct. 1994, pp. 217–219.
where is the number of comparators in the ADC which [5] C. Baringer, J. F. Jensen, L. Burns, and R. H. Walden, “A 3-bit, 8
holds for a flash converter with one overflow comparator (this GSPS flash ADC,” in Proc. Indium Phos. Rel. Mater. Conf., Apr. 1996,
pp. 64–67.
is the fastest architecture). Substituting for and defining the [6] A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing.
quantity gives Englewood Cliffs, NJ: Prentice-Hall, ch. 3, p. 114.
[7] L. E. Larson, “High-speed analog-to-digital conversion with GaAs
technology: Prospects, trends, and obstacles,” presented at the 14th
European Solid-State Circuits Conf., Manchester, England, Sept. 1988.
[8] J. F. Jensen, private communication.
[9] Y. Matsuoka and E. Sano, “High-speed AlGaAs/GaAs HBT’s and their
applications to 40-Gbit/s-class IC’s,” in IEEE GaAs IC Symp. Tech. Dig.,
Oct. 1994, vol. 16, pp. 185–188.
The second term in the parentheses can be considered as [10] T. Enoki, T. Kobayashi, and Y. Ishii, “Device technologies for InP-
an excess noise and can be equated with a fraction, of the based HEMT’s and their application to IC’s,” in IEEE GaAs IC Symp.
quantization noise, i.e., Tech. Dig., Oct. 1994, vol. 16, pp. 337–340.
[11] S. Yamahata et al., “Ultra-high fmax and fT InP/InGaAs double-
heterojunction bipolar transistors with step-graded InGaAsP collectors,”
in IEEE GaAs IC Symp. Tech. Dig., Oct. 1994, vol. 16, pp. 345–348.
[12] J. van Valberg and R. J. van de Plassche, “An 8-bit 650 MHz folding
ADC,” IEEE J. Solid-State Circuits, vol. 27, pp. 1662–1666, Dec. 1992.
[13] K. Poulton, K. L. Knudsen, J. Corcoran, K.-C. Wang, R. B. Nubling, R.
L. Pierson, M.-C. F. Chang, and P. M. Asbeck, “A 6-bit, 4 Gsa/s ADC
Solving for yields the following: fabricated in a GaAs HBT process,” in GaAs IC Symp. Tech. Dig., Oct.
1994, vol. 16, pp. 240–243.
[14] K. Nary, R. Nubling, S. Beccue, W. Colleran, J. Penney, and K. Wang,
“An 8-bit, 2 gigasample per second analog to digital converter,” in GaAs
IC Symp. Tech. Dig., Oct. 1995, vol. 17, pp. 303–246.
[15] K. Sone, N. Naotoshi, Y. Nishida, M. Ishida, Y. Sekine, and M.
Yotsuyanagi, “A 10b 100 Ms/s pipelined subranging BiCMOS ADC,”
If the following assumptions are made: 1) the additive term in IEEE ISSCC Dig. Tech. Papers, Feb. 1993, vol. 36, pp. 66–67.
[16] W. T. Colleran, T. H. Phan, and A. A. Abidi, “A 10b 100 Ms/s pipelined
should be no more than .5 LSB, then 2) a value for A/D converter,” in IEEE ISSCC Dig. Tech. Papers, Feb. 1993, vol. 36,
[5], and 3) [see Fig. 4(a)], then the final pp. 68–69.
expression for is obtained [17] C. Schiller and P. Byrne, “A 4-GHz 8-b ADC system,” IEEE J. Solid-
State Circuits, vol. 26, pp. 1781–1789, Dec. 1991.
[18] J. C. Candy and G. C. Temes, Eds., “Oversampling Delta-Sigma Data
Converters. New York: IEEE Press, 1992 (see Introduction).
[19] J. F. Jensen, G. Raghavan, A. E. Cosand, and R. H. Walden, “A 3.2 GHz
2nd order delta-sigma modulator implemented in InP HBT technology,”
550 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 17, NO. 4, APRIL 1999

IEEE J. Solid-State Circuits, vol. 30, pp. 1119–1127, Oct. 1995. [31] E. van der Zwan, “A 2.3 mW CMOS SD modulator for audio ap-
[20] F. W. Singor and W. M. Snelgrove, “Switched capacitor bandpass delta- plications,” IEEE ISSCC Dig. Tech. Papers, Feb. 1997, vol. 40, pp.
sigma A/D modulation at 10.7 MHz,” IEEE J. Solid-State Circuits, vol. 220–221.
30, pp. 184–192, Mar. 1995. [32] G. Yin and W. Sansen, “A high-frequency and high-resolution fourth-
[21] G. Raghavan, J. F. Jensen, R. H. Walden, and W. P. Posey, “A bandpass order SD A/D converter in BiCMOS technology,” IEEE J. Solid-State
16 modulator with 92 dB SNR and center frequency continuously Circuits, vol. 29, pp. 857–865, Aug. 1994.
programmable from 0 to 70 MHz,” in ISSCC Tech. Dig., Feb. 1997, [33] S. Rabii and B. A. Wooley, “A 1.8 V digital-audio sigma-delta modulator
vol. 40, pp. 214–215. in 0.8 mm CMOS,” IEEE J. Solid-State Circuits, vol. 32, pp. 783–796,
[22] A. Jayaraman et al., “Bandpass delta-sigma modulator with 800 MHz June 1997.
center frequency,” in IEEE GaAs IC Symp. Tech. Dig., Oct. 1997, vol. [34] E. Stebbins and P. Bradley, “Hypres flash ADC program report,”
19, pp. 95–98. Hypres, Inc., 1993.
[23] R. H. Walden, A. E. Schmitz, A. R. Kramer, L. E. Larson, and J.
Pasiecznik, “A deep-submicrometer analog-to-digital converter using
focused-ion-beam implants,” IEEE J. Solid-State Circuits, vol. 25, pp.
562–571, Apr. 1990.
[24] T. Ducourant, M. Binet, J.-C. Baelde, Ch. Rocher, and J.-M. Gibereau,
“3 GHz 150 mW, 4-bit GaAs analog to digital converter,” IEEE GaAs Robert H. Walden (S’62–M’63) received the
IC Symp. Tech. Dig., Oct. 1986, p. 209. B.E.S., M.E.E., and Ph.D. degrees, all from New
[25] P. Vorenkamp and R. Roovers, “A 12b 50Msample/s cascaded folding York University, Bronx, NY.
and interpolating ADC,” in IEEE ISSCC Dig. Tech. Papers, Feb. 1997, He joined Bell Telephone Laboratories in 1966,
vol. 40, pp. 134–135. where he was engaged in solid-state device and
[26] S.-U. Kwak, B.-S. Song, and K. Bacrania, “A 15b 5M sample/s low- circuit research, including charge-coupled devices
spurious CMOS ADC,” in IEEE ISSCC Dig. Tech. Papers, Feb. 1997, and a variety of integrated circuit designs. He then
vol. 40, pp. 146–147. joined Hughes in 1978, and participated in several
[27] T. B. Cho and P. R. Gray, “A 10b, 20 Msample/s, 35 mW pipeline A/D silicon integrated circuit designs. He has been at
converter,” IEEE J. Solid-State Circuits, vol. 30, pp. 166–172, Mar. the HRL Laboratories, LLC, Malibu, CA, since
1995. 1985 and is presently a Principal Research Scientist
[28] K. Kusumoto, A. Matsuzawa, and K. Murata, “A 10-b, 20-MHz, 30 in the Microelectronics Laboratory. He is studying exploratory analog-to-
mW pipelined interpolating CMOS ADC,” IEEE J. Solid-State Circuits, digital conversion techniques, as well as high-speed optical receivers. He
vol. 28, pp. 1200–1206, Dec. 1993. has authored or coauthored over 50 technical publications and holds 15 U.S.
[29] Analog Devices, Inc., part number AD6640, 12-bit, 65 Msps ADC, patents.
1997. Dr. Walden is a member of Eta Kappa Nu and the Optical Society of
[30] F. Chen and B. Leung, “A 0.25-mW low-pass passive sigma-delta America. He has won a Hughes Research Labs Outstanding Achievement
modulator with built-in mixer for a 10-MHz IF input,” IEEE J. Solid- Award, and was a corecipient of a Hughes Research Labs Outstanding Paper
State Circuits, vol. 32, pp. 774–782, June 1997. of the Year Award and an R&D 100 Award.