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NAME: Fuldeore Srushti Vinod Subject: Coa ID: 201071908 BRANCH: Computer

This document contains an assignment submission for the subject COA. It includes 4 questions and their detailed solutions regarding instruction formats, differences between pipeline and non-pipeline processors, instruction cycles, and types of registers used in a CPU. The student provides explanations of zero address, one address, two address, and three address instruction formats. They also compare pipeline and non-pipeline processors in terms of performance, and explain the phases of an instruction cycle in detail. Finally, they list and describe different types of registers, including general purpose, data, address, condition code, control and status registers.

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54 views7 pages

NAME: Fuldeore Srushti Vinod Subject: Coa ID: 201071908 BRANCH: Computer

This document contains an assignment submission for the subject COA. It includes 4 questions and their detailed solutions regarding instruction formats, differences between pipeline and non-pipeline processors, instruction cycles, and types of registers used in a CPU. The student provides explanations of zero address, one address, two address, and three address instruction formats. They also compare pipeline and non-pipeline processors in terms of performance, and explain the phases of an instruction cycle in detail. Finally, they list and describe different types of registers, including general purpose, data, address, condition code, control and status registers.

Uploaded by

Srushti vinod Fuldeore
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Assignment 02

NAME: Fuldeore Srushti Vinod SUBJECT: COA


ID: 201071908 BRANCH: Computer

Q.1 What is an instruction format? Explain different types of instruction formats


in detail.
Solution:-
 An instruction format defines the layout of the bits of an instruction, in terms of
its constituent fields
 An instruction format must include an opcode and, the addressing mode for each
operator
 The instruction format defines the layout fields in the instruction. Instruction
format design is a complex undertaking, including such consideration as
instruction length, fixed or variable length, number of bits assigned to opcode
and each operand reference, and how addressing mode is determined.

Fig.A simple instruction format


 Opcodes are represented by abbreviations, called mnemonics, that indicate the
operation. Common examples include
ADD Add
SUB Subtract
MUL Multiply
DIV Divide
Types of Instruction formats:
1. Zero Address Instructions –
A stack based computer do not use address field in instruction. To evaluate a
expression first it is converted to revere Polish Notation i.e. Post fix Notation.
Expression: X = (A+B)*(C+D)
Postfixed : X = AB+CD+*
TOP means top of stack
M[X] is any memory location

PUSH A TOP = A

PUSH B TOP = B

ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

2. One Address Instructions –

This use a implied ACCUMULATOR register for data manipulation. One operand
is in accumulator and other is in register or memory location. Implied means that
the CPU already know that one operand is in accumulator so there is no need to
specify it.

Expression: X = (A+B)*(C+D)
AC is accumulator
M[] is any memory location
M[T] is temporary location
LOAD A AC = M[A]

ADD B AC = AC + M[B]

STORE T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC

3. Two Address Instructions –

This is common in commercial computers. Here two address can be specified in


the instruction. Unlike earlier in one address instruction the result was stored in
accumulator here result cab be stored at different location rather than just
accumulator, but require more number of bit to represent address.

Here destination address can also contain operand.


Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

MOV R2, C R2 = C

ADD R2, D R2 = R2 + D

MUL R1, R2 R1 = R1 * R2
MOV X, R1 M[X] = R1
4. Three Address Instructions –

This has three address field to specify a register or a memory location. Program
created are much short in size but number of bits per instruction increase. These
instructions make creation of program much easier but it does not mean that
program will run much faster because now instruction only contain more
information but each micro operation (changing content of register, loading
address in address bus etc.) will be performed in one cycle only.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]

MUL X, R1, R2 M[X] = R1 * R2

Q.2 Differentiate between pipeline and non-pipeline processor based on their


performance.
Solution:-
Pipeline processor Non-pipeline processor
In pipelining system, multiple In a Non-Pipelining system, processes
instructions are overlapped during like decoding, fetching, execution and
execution. writing memory are merged into a single
unit or a single step.
Many instructions are executed at the Only one instruction is executed at the
same time same time
The efficiency of the pipelining system In a Non-Pipelining system, The CPU
depends upon the effectiveness of CPU scheduler chooses the instruction from
scheduler. the pool of waiting instructions, when an
execution unit gives a signal that it is
free. The efficiency is not dependent on
the CPU scheduler.
Execution time is comparatively less and Execution takes more time or more
execution is done in fewer cycles number of cycles comparatively
The efficiency of pipelining system It is not dependent on CPU scheduler.
depends upon the effectiveness of CPU
scheduler.

Q.3 What is instruction cycle? Explain in detail.


Solution:-
 The processing required for a single instruction is called an instruction cycle.
 A program residing in the memory unit of a computer consists of a sequence of
instructions. These instructions are executed by the processor by going through a
cycle for each instruction.
 Each instruction cycle consists of the following phases:

Fig. Instruction Cycle with Indirect

1. Fetch: Read the next instruction from memory into the processor.
2. Execute: Interpret the opcode and perform the indicated operation.
3. Interrupt: If interrupts are enabled and an interrupt has occurred, save the
current process state and service the interrupt.
4. Indirect Cycle: May require memory access to fetch operands Indirect.
Addressing requires more memory accesses can be thought of as additional
instruction sub cycle.

 The execution cycle for a particular instruction may involve more than one
reference to memory. Also, instead of memory references, an instruction may
specify an I/O operation. For any given instruction cycle, some states may be
null and others may be visited more than once.
The states can be described as follows:
 Instruction address calculation (iac): Determine the address of the next
instruction to be executed. Usually, this involves adding a fixed number to the
address of the previous instruction

Fig. Instruction Cycle state diagram


 Instruction fetch (if): Read instruction from its memory location into the
processor
 Instruction operation decoding (iod): Analyze instruction to determine type
of operation to be performed and operand(s) to be used.
 Operand address calculation (oac): If the operation involves reference to an
operand in memory or available via I/O, then determine the address of the
operand
 Operand fetch (of): Fetch the operand from memory or read it in from I/O
 Operand store (os): Write the result into memory or out to I/O.

Q4. Enlist the types of registers used in CPU.


Solution:-

 Registers are a type of computer memory used to quickly accept, store, and
transfer data and instructions that are being used immediately by the CPU. The
registers used by the CPU are often termed as Processor registers.
 A processor register may hold an instruction, a storage address, or any data (such
as bit sequence or individual characters).
 The computer needs processor registers for manipulating data and a register for
holding a memory address. The register holding the memory location is used to
calculate the address of the next instruction after the execution of the current
instruction is completed.
 Types of Registers:

1. User-visible registers: A user-visible register is one that may be


referenced by means of the machine language that the processor executes.

We can characterize these in the following categories:

i. General purpose - General-purpose registers can be assigned to a


variety of functions by the programmer. Sometimes their use
within the instruction set is orthogonal to the operation. That is,
any general-purpose register can contain the operand for any
opcode
ii. Data - used only to hold data and cannot be employed in the
calculation of an operand address.
iii. Address – are somewhat general purpose, or they may be devoted
to a particular addressing mode

Examples include the following:

 Segment pointers: In a machine with segmented


addressing a segment register holds the address of the base
of the segment.
 Index registers: These are used for indexed addressing and
may be auto indexed.
 Stack pointer: If there is user-visible stack addressing, then
typically there is a dedicated register that points to the top
of the stack.

iv. Condition codes - Condition codes are bits set by the processor
hardware as the result of operations

2. Control and status registers: Used by the control unit to control the
operation of the processor and by privileged, operating system programs
to control the execution of programs.

i. Program counter (PC): Contains the address of an instruction to


be fetched
ii. Instruction register (IR): Contains the instruction most recently
fetched
iii. Memory address register (MAR): Contains the address of a
location in memory
iv. Memory buffer register (MBR): Contains a word of data to be
written to memory or the word most recently read

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