SED1330F/1335F/1336F

LCD Controller ICs

Technical Manual

S-MOS Systems, Inc.

September, 1995
Version 0.4

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 1
 THIS PAGE INTENTIONALLY BLANK

2 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
Table of Contents SED1330F/1335F/1336F
CONTENTS

1.0 Overview ............................................................................................................. 9

1.1 Description .................................................................................................................................. 11
1.2 Features ...................................................................................................................................... 11
1.3 Block Diagram ............................................................................................................................. 12
1.4 Pinouts ........................................................................................................................................ 14
1.4.1 SED1330FBA, 1335FBB and SED1336F0A Pinouts ............................................. 14
1.4.2 SED1330FBA and SED1335F0A Pinouts .............................................................. 14
1.5 Package Dimensions ................................................................................................................... 15

2.0 Pin Description ................................................................................................. 17

2.1 SED1330FBA/BB Pin Summary .................................................................................................. 18
2.2 SED1330F/1335F0A/0B Pin Summary ....................................................................................... 19
2.3 SED1336F0A Pin Summary ........................................................................................................ 20
2.4 Pin Functions ............................................................................................................................... 21
2.4.1 Power Supply .......................................................................................................... 21
2.4.2 Oscillator ................................................................................................................. 21
2.4.3 Microprocessor Interface ........................................................................................ 21
2.4.4 Display Memory Control ......................................................................................... 23
2.4.5 LCD Drive Signals .................................................................................................. 23

3.0 Command Description ..................................................................................... 25

3.1 The Command Set ...................................................................................................................... 27
3.2 System Control Commands ........................................................................................................ 28
3.2.1 SYSTEM SET ......................................................................................................... 28
3.2.1.1 C ........................................................................................................ 29
3.2.1.2 M0 ...................................................................................................... 29
3.2.1.3 M1 ...................................................................................................... 29
3.2.1.4 M2 ...................................................................................................... 29
3.2.1.5 W/S .................................................................................................... 29
3.2.1.6 IV ........................................................................................................ 32
3.2.1.7 T/L ...................................................................................................... 32
3.2.1.8 DR ...................................................................................................... 32
3.2.1.9 FX ...................................................................................................... 32
3.2.1.10 WF ................................................................................................... 33
3.2.1.11 FY ..................................................................................................... 33
3.2.1.12 C/R .................................................................................................... 34
3.2.1.13 TC/R ................................................................................................. 34
3.2.1.14 L/F .................................................................................................... 35
3.2.1.15 AP .................................................................................................... 35
3.2.2 SLEEP IN................................................................................................................ 36

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 3
SED1330F/1335F/1336F Table of Contents
3.3 Display Control Commands ......................................................................................................... 36
3.3.1 DISP ON/OFF ......................................................................................................... 36
3.3.1.1 D ........................................................................................................ 37
3.3.1.2 FC ...................................................................................................... 37
3.3.1.3 FP ...................................................................................................... 37
3.3.2 SCROLL ................................................................................................................. 37
3.3.2.1 C ........................................................................................................ 37
3.3.2.2 SL1, SL2 ............................................................................................ 38
3.3.3 CSRFORM.............................................................................................................. 42
3.3.3.1 CRX ................................................................................................... 42
3.3.3.2 CRY .................................................................................................... 42
3.3.3.3 CM ..................................................................................................... 43
3.3.4 CSRDIR .................................................................................................................. 43
3.3.5 OVLAY .................................................................................................................... 43
3.3.5.1 MX0, MX1 .......................................................................................... 43
3.3.5.2 DM1, DM2 .......................................................................................... 45
3.3.5.3 OV ...................................................................................................... 45
3.3.6 CGRAM ADR .......................................................................................................... 45
3.3.7 HDOT SCR ............................................................................................................. 45
3.3.7.1 D0 to D2 ............................................................................................. 45
3.4 Drawing Control Commands ....................................................................................................... 46
3.4.1 CSRW ..................................................................................................................... 46
3.4.2 CSRR ...................................................................................................................... 46
3.5 Memory Control Commands ....................................................................................................... 47
3.5.1 MWRITE ................................................................................................................. 47
3.5.2 MREAD ................................................................................................................... 47

4.0 Specifications ................................................................................................... 49

4.1 Absolute Maximum Ratings ......................................................................................................... 51
4.1.1 SED1330 ................................................................................................................ 51
4.1.2 SED1335/SED1336 ................................................................................................ 51
4.2 SED 1330 Electrical Characteristics............................................................................................ 52
4.3 SED1335/1336 Electrical Characteristics.................................................................................... 53
4.4 SED1330 Timing Diagrams ......................................................................................................... 54
4.4.1 System bus READ/WRITE timing I (8080) ............................................................. 54
4.4.1.1 SED1330F ......................................................................................... 54
4.4.2 System bus READ/WRITE timing II (6800) ............................................................ 55
4.4.2.1 SED1330F ......................................................................................... 55
4.4.3 Display memory READ timing ................................................................................ 56
4.4.3.1 SED1330F ......................................................................................... 56
4.4.4 Display memory WRITE timing ............................................................................... 57
4.4.4.1 SED1330F ......................................................................................... 57
4.4.5 LCD control timing .................................................................................................. 58
4.4.5.1 SED1330F ......................................................................................... 59

4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
Table of Contents SED1330F/1335F/1336F
4.4.6 Oscillator timing ...................................................................................................... 60
4.4.6.1 SED1330F ......................................................................................... 60
4.4.7 Measurement circuit ............................................................................................... 61
4.5 SED1335/SED1336 AC Timing Diagrams ................................................................................... 62
4.5.1 8080 family Interface Timing ................................................................................... 62
4.5.1.1 SED1335F ......................................................................................... 62
4.5.1.2 SED1336F ......................................................................................... 63
4.5.2 6800 family Interface Timing ................................................................................... 64
4.5.2.1 SED1335F ......................................................................................... 65
4.5.2.2 SED1336F ......................................................................................... 65
4.5.3 Display Memory Read Timing ................................................................................. 66
4.5.3.1 SED1335F ......................................................................................... 66
4.5.3.2 SED1336F ......................................................................................... 67
4.5.4 Display Memory Write Timing ................................................................................. 68
4.5.4.1 SED1335F ......................................................................................... 69
4.5.4.2 SED1336F ......................................................................................... 70
4.5.5 SLEEP IN Command Timing .................................................................................. 71
4.5.5.1 SED1335F ......................................................................................... 71
4.5.5.2 SED1336F ......................................................................................... 71
4.5.6 External Oscillator Signal Timing ............................................................................ 72
4.5.6.1 SED1335F ......................................................................................... 72
4.5.6.2 SED1336F ......................................................................................... 72
4.5.7 E-1330 LCD Controller IC ........................................................................................................ 73
4.5.7.1 SED1335F ......................................................................................... 75
4.5.7.2 SED1336F ......................................................................................... 75

5.0 Display Control Functions .............................................................................. 77

5.1 Character Configuration .............................................................................................................. 79
5.2 Screen Configuration ................................................................................................................... 81
5.2.1 Screen Configuration .............................................................................................. 81
5.2.2 Display Address Scanning ...................................................................................... 81
5.2.3 Display Scan Timing ............................................................................................... 84
5.3 Cursor Control ............................................................................................................................. 85
5.3.1 Cursor Register Function ........................................................................................ 85
5.3.2 Cursor Movement ................................................................................................... 85
5.3.3 Cursor Display Layers ............................................................................................ 85
5.4 Memory to Display Relationship .................................................................................................. 87
5.5 Scrolling ....................................................................................................................................... 90
5.5.1 On-page Scrolling ................................................................................................... 90
5.5.2 Inter-page Scrolling ................................................................................................. 91
5.5.3 Horizontal Scrolling ................................................................................................. 92
5.5.4 Bidirectional Scrolling ............................................................................................. 93
5.5.5 Scroll Units.............................................................................................................. 93

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 5
SED1330F/1335F/1336F Table of Contents
6.0 Character Generator ........................................................................................ 95
6.1 CG Characteristics ...................................................................................................................... 97
6.1.1 Internal Character Generator .................................................................................. 97
6.1.2 External Character Generator ROM ....................................................................... 97
6.1.3 Character Generator RAM ...................................................................................... 97
6.2 CG Memory Allocation................................................................................................................. 98
6.3 Setting the Character Generator Address ................................................................................... 99
6.3.1 M1 = 1 ................................................................................................................... 100
6.3.2 CG RAM Addressing Example .............................................................................. 100
6.4 Character Codes ....................................................................................................................... 101

7.0 TV Mode (SED1336F only) ............................................................................. 103

7.1 Sync Generator Circuit Timing .................................................................................................. 105

8.0 Description of Circuit Blocks ........................................................................ 109

8.1 Microprocessor Interface ........................................................................................................... 111
8.1.1 System Bus Interface............................................................................................ 111
8.1.1.1 8080 series ...................................................................................... 111
8.1.1.2 6800 series ...................................................................................... 111
8.1.2 Microprocessor Synchronization........................................................................... 111
8.1.2.1 Display Status Indication Output For SED1336F only...................... 111
8.1.2.2 Internal Register Access .................................................................. 111
8.1.2.3 Display Memory Access ................................................................... 111
8.1.3 Interface Examples ............................................................................................... 113
8.1.3.1 Z80® to SED1330F/1335F/1336F Interface .................................... 113
8.1.3.2 6802 to SED1330F/1335F/1336F Interface ..................................... 114
8.2 Display Memory Interface .......................................................................................................... 115
8.2.1 Static RAM ............................................................................................................ 115
8.2.2 Supply Current during Display Memory Access .................................................... 115
8.3 Oscillator Circuit ........................................................................................................................ 116
8.4 Status Flag ................................................................................................................................ 116
8.5 Reset ......................................................................................................................................... 117

9.0 Application Notes ........................................................................................... 119

9.1 Initialization Parameters ............................................................................................................ 121
9.1.1 SYSTEM SET Instruction and Parameters ........................................................... 121
9.1.2 Initialization Example ............................................................................................ 122
9.1.3 Display Mode Setting Example 1: Combining Text and Graphics ......................... 128
9.1.4 Display Mode Setting Example 2: Combining Graphics and Graphics ................. 129
9.1.5 Display Mode Setting Example 3: Combining Three Graphics Layers ................. 130
9.2 System Overview ...................................................................................................................... 132

6 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
Table of Contents SED1330F/1335F/1336F

9.3 System Interconnection ............................................................................................................. 133

9.3.1 SED1330F/1335F ................................................................................................. 133
9.3.2 SED1336F ............................................................................................................ 134
9.4 Smooth Horizontal Scrolling ...................................................................................................... 135
9.5 Layered Display Attributes ......................................................................................................... 137
9.5.1 Inverse Display ..................................................................................................... 137
9.5.2 Half-tone Display .................................................................................................. 137
9.5.2.1 Menu Pad Display ............................................................................ 137
9.5.2.2 Graph Display .................................................................................. 138
9.5.3 Flashing Areas ...................................................................................................... 138
9.5.3.1 Small Area ........................................................................................ 138
9.5.3.2 Large Area ....................................................................................... 138
9.6 16 × 16-dot Graphic Display ...................................................................................................... 139
9.6.1 Command Usage .................................................................................................. 139
9.6.2 Kanji Character Display ........................................................................................ 139

10.0 Internal Character Generator Font ............................................................. 141

11.0 Glossary of Terms ........................................................................................ 145

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 7
SED1330F/1335F/1336F Table of Contents

THIS PAGE INTENTIONALLY BLANK

8 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
 1.0
Overview

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 9
 THIS PAGE INTENTIONALLY BLANK

10 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
1.0 – 1.2 1.0 Overview
1.0 Overview

1.1 Description 1.2 Features

The SED1330/1335F/1336F is a family of versatile • Text, graphics and combined text/graphics dis-
LCD controller ICs that can display text and graphics play modes
on a medium size LCD panel. The software is • Three overlapping screens in graphics mode
compatible among all three chips. S-MOS recom-
• 640 × 256 pixel LCD panel display resolution
mends new designs use the SED1335 since the
SED1330 will gradually be replaced by the SED1335. • Programmable cursor control
• Smooth horizontal and vertical scrolling of all or
The SED1336F incorporates a TV sync generator part of the display
circuit that is compatible with both NTSC and PAL • 1/2-duty to 1/256-duty LCD drive
systems. The 256 × 200 pixel TV display comprises
three superimposed layers, and is identical to the • Up to 64 Kbytes of external static RAM frame
simultaneous LCD panel display. When driving an buffer memory
LCD only, up to 3 overlapping layers can be displayed • Internal character generator
on LCD panels up to 640 × 256 pixels in size. The • 160, 5 × 7 pixel characters in internal mask-
SED1330/1335F does not incorporate a TV controller. programmed character generator ROM
• Up to 64, 8 × 16 pixel characters in external
The SED1330/1335F/1336F can display layered text
character generator RAM
and graphics, scroll the display in any direction and
partition the display into multiple screens. • Up to 256, 8 × 16 pixel characters in external
character generator ROM
The SED1330/1335F/1336F stores text, character • 6800 and 8080 family microprocessor inter-
codes and bit-mapped graphics data in external frame faces
buffer memory. Display controller functions include
• NTSC and PAL systems compatible
transferring data from the controlling microprocessor
(SED1336F only)
to the buffer memory, reading memory data, convert-
ing data to display pixels and generating timing sig- • 256 × 200 pixel TV monitor display resolution
nals for the buffer memory, TV monitor and LCD (SED1336F only)
panel. • Low power consumption—3.5 mA operating
current (VDD = 3.5V), 0.05 µA standby current
The SED1330/1335F/1336F has an internal charac- • 4.5 to 5.5V (SED1330F)
ter generator with 160, 5 × 7 pixel characters in
internal mask ROM. The character generators sup- • 2.7 to 5.5V (SED1330F/1335F)
port up to 64, 8 × 16 pixel characters in external • 3.0 to 5.5V (SED1336F)
character generator RAM and up to 256, 8 × 16 pixel • Available in 60-pin QFPs
characters in external character generator ROM.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 11
1.0 Overview 1.3
1.3 Block Diagram

Video RAM Character

Character LCD
Generator ROM
Generator RAM

YSCL,YD,YDIS
VA0 to VA15

VR/W

XSCL, XECL

XD0 to XD3
VD0 to VD7

LP, WF
VCE

Input/Output
Video RAM Interface Register LCD Controller

Cursor Display Character

Address Address Refresh Dot Counter Generator Layered
Controller Controller Counter ROM Controller

Microprocessor Interface Oscillator

SEL1
SEL0

RES

RD, WR

A0, CS

D0 to D7

OSC1 OSC2

Figure 1. SED1330F block diagram

12 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
1.3 1.0 Overview
1.3 Block Diagram

Video RAM Character

TV LCD
Character Generator ROM
Generator RAM

YSCL, YD, YDIS

VA0 to VA15

XSCL, XECL

XD0 to XD3
VD0 to VD7

LP, WF
SNC
VSD
VRD,
VCE,

VWR

VWR
VRD

Input/Output TV
Video RAM Interface LCD Controller
Register Controller*

Cursor Display Character

Refresh Layered
Address Address Dot Counter Generator
Counter Controller
Controller Controller ROM

Microprocessor Interface Oscillator

SEL1
SEL0

RES

RD, WR

A0, CS

D0 to D7

XG XD

*SED1336F only

Figure 2. SED1335F/1336F block diagram

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 13
1.0 Overview 1.4 – 1.4.2
1.4 Pinouts

SEL1
SEL2

YSCL

XSCL
XECL
VWR

YDIS
RES

VCE

VA0
VA1
VA2
VA3
VA4
VA5
VA6
VA7

VD4
VD5
VD6
VD7

XD0
XD1
XD2
WR
XG

RD
NC
NC

NC

WF

VSS
YD

LP
45 31
VD3 46 30 XD3
XD 55 50 45 40 VA8 VD2 D7
CS VA9
VA10
VD1 D6
A0
VDD VA11 VD0 D5
D0 VA12 VA15 D4
D1 60 SED1330FBA 30 VA13 VA14 D3
VA13 SED1330FBB D2
1 Index VA12 D1
D2 29 NC
D3 VA14 VA11 D0
D4 VA15 Index VDD
VA10
D5 VD0 VA9 A0
D6 5 VD1 VA8 CS
6 10 15 20 VD2
VA7 OSC2
VA6 OSC1
60 16
NC 1 15 SEL 1
D7
XD3
XD2
XD1
XD0
XECL
XSCL
VSS
LP
WF
YDIS
YD
YSCL
VD7
VD6
VD5
VD4
VD3

VA5
VA4
VA3
VA2
VA1
VA0
VR/W
VCE
NC
RES
NC
NC
RD
WR
SEL 2
YSCL(SNC)

XECL(VSD)
XSCL
YDIS
VD4
VD5
VD6
VD7

XD0
XD1
XD2
WF

VSS
SEL1
SEL2

YD
VWR

LP
VRD
RES

VCE

VA0
VA1
VA2
VA3
VA4
VA5
VA6
VA7
WR
XG

RD
NC
NC

45 31
VD3 46 30 XD3
VD2 D7
XD 55 50 45 40 VA8 VD1 D6
CS VA9 VD0 D5
A0 VA10 VA15 D4
VDD VA11
D0 VA12
VA14 SED1335F0B D3
SED1335FOA VA13 (SED1336F0A) D2
D1 60 30 VA13
VA12 D1
1 Index VA11 D0
D2 29 NC Index
D3 VA14 VA10 VDD
D4 VA15 VA9 A0
D5 VD0 VA8 CS
D6 5 VD1 VA7 XD
6 10 15 20 VD2 VA6 XG
60 16
NC 1 15 SEL1
D7
XD3
XD2
XD1
XD0
XECL
XSCL
VSS
LP
WF
YDIS
YD
YSCL
VD7
VD6
VD5
VD4
VD3

VA5
VA4
VA3
VA2
VA1
VA0
VWR
VCE
VRD
RES
NC
NC(CLO)
RD
WR
SEL 2(NT/PL)

Figure 3. SED1330F and SED1335F pinouts

14 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
1.4 – 1.4.2 1.0 Overview
1.5 Package Dimensions

QFP5 25.6 ± 0.4 Unit: mm

20.0 ± 0.1
54 36

55 35

14.0 ± 0.1

19.6 ± 0.4
60 30
1 Index
29

5
24

6 23
1.0 ± 0.1 0.35 ± 0.1
0.15 ± 0.05

2.7 ± 0.1

0 ~ 12°
1.5 ± 0.3

2.8

Figure 4. SED1330FBA and 1335F0A package dimensions

QFP6 17.6 ± 0.4 Unit: mm

14.0 ± 0.2
45 31

46 30
14.0 ± 0.2

17.6 ± 0.4

Index

60 16

1 15
0.15 ± 0.05

2.7 ± 0.1

0.8 ± 0.15 0.35 ± 0.15

0 ~ 12°
0.8 ± 0.3

1.8

Figure 5. SED1330FBB , 1335F0B and SED1336F0A

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 15
 THIS PAGE INTENTIONALLY BLANK

16 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
 2.0
Pin Description

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 17
2.0 Pin Description 2.0 – 2.1
2.0 Pin Description

2.1 SED1330FBA/BB Pin Summary

Number
Name Type Description
SED1330F0A SED1330FBB
27 to 28 50 to 59
VA0 to VA15 Output VRAM address bus
30 to 43 1 to 6
VR/W 44 7 Output VRAM write signal
VCE 45 8 Output Memory control signal
RES 47 10 Input Reset
NC 29, 46, 48, 49 9, 11, 12, 60 — No connection
8080 family: Read signal
RD 50 13 Input
6800 family: Enable clock (E)
8080 family: Write signal
WR 51 14 Input
6800 family: R/W signal
8080 or 6800 family interface
SEL2 52 15 Input
select
8080 or 6800 family interface
SEL1 53 16 Input
select
OSC1 54 17 Input Oscillator connection
OSC2 55 18 Output Oscillator connection
CS 56 19 Input Chip select
A0 57 20 Input Data type select
VDD 58 21 Supply 4.5 to 5.5V supply
59 to 60
D0 to D7 22 to 29 Input/output Data bus
1 to 6
XD0 to XD3 10 to 7 33 to 30 Output X-driver data
XECL 11 34 Output X-driver enable chain clock
XSCL 12 35 Output X-driver data shift clock
VSS 13 36 Supply Ground
LP 14 37 Output Latch pulse
WF 15 38 Output Frame signal
Power-down signal when display is
YDIS 16 39 Output
blanked
YD 17 40 Output Scan start pulse
YSCL 18 41 Output Y-driver shift clock
VD0 to VD7 26 to 19 49 to 42 Input/output VRAM data bus

18 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
2.0 – 2.2 2.0 Pin Description
2.0 Pin Description

2.2 SED1330F/1335F0A/0B Pin Summary

Number
Name Type Description
SED1335F0A SED1335F0B
27 to 28 50 to 59
VA0 to VA15 Output VRAM address bus
30 to 43 1 to 6
VWR 44 7 Output VRAM write signal
VCE 45 8 Output Memory control signal
VRD 46 9 Output VRAM read signal
RES 47 10 Input Reset
NC 29, 48, 49 11, 12, 60 — No connection
8080 family: Read signal
RD 50 13 Input
6800 family: Enable clock (E)
8080 family: Write signal
WR 51 14 Input
6800 family: R/W signal
8080 or 6800 family interface
SEL2 52 15 Input
select
8080 or 6800 family interface
SEL1 53 16 Input
select
XG 54 17 Input Oscillator connection
XD 55 18 Output Oscillator connection
CS 56 19 Input Chip select
A0 57 20 Input Data type select
VDD 58 21 Supply 2.7 to 5.5V supply
59 to 60
D0 to D7 22 to 29 Input/output Data bus
1 to 6
XD0 to XD3 10 to 7 33 to 30 Output X-driver data
XECL 11 34 Output X-driver enable chain clock
XSCL 12 35 Output X-driver data shift clock
VSS 13 36 Supply Ground
LP 14 37 Output Latch pulse
WF 15 38 Output Frame signal
Power-down signal when display is
YDIS 16 39 Output
blanked
YD 17 40 Output Scan start pulse
YSCL 18 41 Output Y-driver shift clock
VD0 to VD7 26 to 19 49 to 42 Input/output VRAM data bus

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 19
2.0 Pin Description 2.3
2.3 SED1336F0A Pin Summary

Name Number Type Description

1 to 6
VA0 to VA15 Output VRAM address bus
50 to 59
VWR 7 Output VRAM write signal
VCE 8 Output Memory control signal
VRD 9 Output VRAM read signal
RES 10 Input Reset
NC 11, 60 — No connection
CLO 12 Output Clock output
8080 family: Read signal
RD 13 Input
6800 family: Enable clock (E)
8080 family: Write signal
WR 14 Input
6800 family: R/W signal
NT/PL 15 Input NTSC or PAL TV mode select
SEL1 16 Input 8080 or 6800 family interface select
OSC1 17 Input Oscillator connection
OSC2 18 Output Oscillator connection
CS 19 Input Chip select
A0 20 Input Data type select
VDD 21 Supply 3.0 to 5.5V supply
D0 to D7 22 to 29 Input/output Data bus
XD0 to XD3 30 to 33 Output X-driver data
VSD 34 Output Video data
XSCL 35 Output Data shift clock
VSS 36 Supply Ground
LP 37 Output Latch pulse
WF 38 Output Frame signal
Power-down signal when display is
YDIS 39 Output
blanked
YD 40 Output Scan start pulse
SNC 41 Output TV sync signal
VD0 to VD7 42 to 49 Input/output VRAM data bus

20 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
2.4 – 2.4.3 2.0 Pin Description
2.4 Pin Functions

2.4.1 Power Supply

Pin Name Function

4.5 to 5.5V (SED1330F), 3.0 to 5.5V (SED1336F) or 2.7 to 5.5V (SED1330F/1335F) supply.
VDD
This may be the same supply as the controlling microprocessor.
VSS Ground
Note: The peak supply current drawn by the SED1330F/1335F/1336F may be up to ten times the average supply current. The power
supply impedance must be kept as low as possible by ensuring that supply lines are sufficiently wide and by placing 0.47 µF
decoupling capacitors that have good high-frequency response near the device’s supply pins.

2.4.2 Oscillator

Pin Name Function

Crystal connection for internal oscillator (see Section 8.3). This pin can be driven by an external
(OSC) XG
clock source that satisfies the timing specifications of the EXT φ0 signal (see Section 4.3.6).
Crystal connection for internal oscillator. Leave this pin open when using an external clock
(OSC2) XD
source.
Clock output (SED1336F only). Same phase as XG. Clock is output when system command
CLO
P1 is executed. Output stops during system reset.

2.4.3 Microprocessor Interface

Pin Name Function

D0 to D7 Tristate input/output pins. Connect these pins to an 8- or 16-bit microprocessor bus.
Microprocessor interface select pin. The SED1336F supports both 8080 family processors
(such as the 8085 and Z80®) and 6800 family processors (such as the 6802 and 6809).

SEL1* SEL2 Interface A0 RD WR CS

SEL1, SEL2
0 0 8080 family A0 RD WR CS
1 0 6800 family A0 E R/W CS
* SED1330F and SED1335F only

Note: SEL1 should be tied directly to VDD or V SS to prevent noise. If noise does appear on SEL1, decouple it to ground using a
capacitor placed as close to the pin as possible.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 21
2.0 Pin Description 2.4.3

Pin Name Function

A0, in conjunction with the RD and WR or R/W and E signals, controls the type of access to
the SED1336F, as shown below.
8080 family interface
A0 RD WR Function
0 0 1 Status flag read
1 0 1 Display data and cursor address read
0 1 0 Display data and parameter write
1 1 0 Command write
A0

6800 family interface

A0 R/W E Function
0 1 1 Status flag read
1 1 1 Display data and cursor address read
0 0 1 Display data and parameter write
1 0 1 Command write

When the 8080 family interface is selected, this signal acts as the active-LOW read strobe. The
SED1330F/1335F/1336F’s output buffers are enabled when this signal is active.
RD or E
When the 6800 family interface is selected, this signal acts as the active-HIGH enable clock.
Data is read from or written to the SED1330F/1335F/1336F when this clock goes HIGH.
When the 8080 family interface is selected, this signal acts as the active-LOW write strobe. The
bus data is latched on the rising edge of this signal.
WR or R/W When the 6800 family interface is selected, this signal acts as the read/write control signal. Data
is read from the SED1330F/1335F/1336F if this signal is HIGH, and written to the SED1330F/
1335F/1336F if it is LOW.
Chip select. This active-LOW input enables the SED1330F/1335F/1336F. It is usually
CS connected to the output of an address decoder device that maps the SED1330F/1335F/1336F
into the memory space of the controlling microprocessor.
This active-LOW input performs a hardware reset on the SED1330F/1335F/1336F. It is a
RES Schmitt-trigger input for enhanced noise immunity; however, care should be taken to ensure
that it is not triggered if the supply voltage is lowered.

22 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
2.4.4 – 2.4.5 2.0 Pin Description
2.4.4 Display Memory Control

The SED1330F/1335F/1336F can directly access static these two types of memory to achieve an optimum
RAM and PROM. The designer may use a mixture of trade-off between low cost and low power consumption.

Pin Name Function

16-bit display memory address. When accessing character generator RAM or ROM, VA0 to
VA0 to VA15
VA3, reflect the lower 4 bits of the row counter.
VD0 to VD7 8-bit tristate display memory data bus. These pins are enabled when VR/W is LOW.
VR/W Active-LOW display memory write control output (SED1330).
VRD Active-LOW display memory read control output (SED1335/6).
VCE Active-LOW static memory standby control signal. VCE can be used with CS.
VWR Active-LOW display memory write control output (SED1335/6).

2.4.5 LCD Drive Signals

In order to provide effective low-power drive for LCD

matrixes, the SED1330F/1335F/1336F can directly
control both the X- and Y-drivers using an enable
chain.
Pin Name Function
4-bit X-driver (column drive) data outputs. Connect these outputs to the inputs of the X-driver
XD0 to XD3
chips.
The falling edge of XSCL latches the data on XD0 to XD3 into the input shift registers of the
XSCL X-drivers. To conserve power, this clock halts between LP and the start of the following display
line (see Section 4.3.7).
The falling edge of XECL (SED1330F/1335F only) triggers the enable chain cascade for the
XECL
X-drivers (SED1600/SED1180). Every 16th clock pulse is output to the next X-driver.
LP latches the signal in the X-driver shift registers into the output data latches. LP is a falling-
LP edge triggered signal, and pulses once every display line.
Connect LP to the Y-driver shift clock on modules that use the SED1600 and SED1610 drivers.
LCD panel AC drive output. The WF period is selected to be one of two values with SYSTEM
WF
SET command.
The falling edge of YSCL (SED1330F/1335F only) latches the data on YD into the input shift
YSCL registers of the Y-drivers. YSCL is not used with the SED1600, SED1610 or other driver ICs
which use LP as the Y-driver shift clock.
YD is the data pulse output for the Y drivers. It is active during the last line of each frame, and
YD is shifted through the Y drivers one by one (by YSCL), to scan the display’s common
connections.
Power-down output signal. YDIS is HIGH while the display drive outputs are active.
YDIS goes LOW one or two frames after the sleep command is written to the SED1330F/
YDIS 1335F/1336F. All Y-driver outputs are forced to an intermediate level (de-selecting the display
segments) to blank the display. In order to implement power-down operation in the LCD unit,
the LCD power drive supplies must also be disabled when the display is disabled by YDIS.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 23
1.0 Overview 1.3

THIS PAGE INTENTIONALLY BLANK

24 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
1.3 – 1.4 1.0 Overview

3.0
Command Description

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 25
 THIS PAGE INTENTIONALLY BLANK

26 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
3.0 – 3.1 3.0 Command Description
3.0 Command Description

3.1 The Command Set

Table 1. The Command Set

Command
Code Read
Class Command Hex Command Description Parameters
No. of Sec-
RD WR A0 D7 D6 D5 D4 D3 D2 D1 D0
Bytes tion
Initialize device and dis-
System SYSTEM SET 1 0 1 0 1 0 0 0 0 0 0 40 8 3.2.1
play
control
SLEEP IN 1 0 1 0 1 0 1 0 0 1 1 53 Enter standby mode 0 3.2.2
58, Enable and disable dis-
DISP ON/OFF 1 0 1 0 1 0 1 1 0 0 D 1 3.3.1
59 play and display flashing
Set display start address
SCROLL 1 0 1 0 1 0 0 0 1 0 0 44 10 3.3.2
and display regions
CSRFORM 1 0 1 0 1 0 1 1 1 0 1 5D Set cursor type 2 3.3.3
Set start address of char-
Display CGRAM ADR 1 0 1 0 1 0 1 1 1 0 0 5C 2 3.3.6
acter generator RAM
control
4C
CD CD Set direction of cursor
CSRDIR 1 0 1 0 1 0 0 1 1 to 0 3.3.4
1 0 movement
4F
Set horizontal scroll pos-
HDOT SCR 1 0 1 0 1 0 1 1 0 1 0 5A 1 3.3.7
ition
Set display overlay for-
OVLAY 1 0 1 0 1 0 1 1 0 1 1 5B 1 3.3.5
mat
Drawing CSRW 1 0 1 0 1 0 0 0 1 1 0 46 Set cursor address 2 3.4.1
control CSRR 1 0 1 0 1 0 0 0 1 1 1 47 Read cursor address 2 3.4.2
MWRITE 1 0 1 0 1 0 0 0 0 1 0 42 Write to display memory — 3.5.1
Memory
control Read from display mem-
MREAD 1 0 1 0 1 0 0 0 0 1 1 43 — 3.5.2
ory
Notes:
1. In general, the internal registers of the SED1330F/1335F/1336F are modified as each command parameter is input. However,
the microprocessor does not have to set all the parameters of a command and may send a new command before all parameters
have been input. The internal registers for the parameters that have been input will have been changed but the remaining
parameter registers are unchanged.
2-byte parameters (where two bytes are treated as one data item) are handled as follows:
a. CSRW, CSRR: Each byte is processed individually. The microprocessor may read or write just the low byte of the cursor
address.
b. SYSTEM SET, SCROLL, CGRAM ADR: Both parameter bytes are processed together. If the command is changed after
half of the parameter has been input, the single byte is ignored.
2. APL and APH are 2-byte parameters, but are treated as two 1-byte parameters.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 27
3.0 Command Description 3.2 – 3.2.1
3.2 System Control Commands

3.2.1 SYSTEM SET

Initializes the device, sets the window sizes, and 1335F/1336F, an incorrect SYSTEM SET command
selects the LCD interface format. Since the command may cause other commands to operate incorrectly.
sets the basic operating parameters of the SED1330F/

MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0 A0 WR RD

C 0 1 0 0 0 0 0 0 1 0 1

P1 DR T/L IV 1 W/S M2 M1 M0 0 0 1

P2 WF 0 0 0 0 FX 0 0 1

P3 0 0 0 0 FY 0 0 1

P4 C/R 0 0 1

P5 TC/R 0 0 1

P6 L/F 0 0 1

P7 APL 0 0 1

P8 APH 0 0 1

Figure 7. SYSTEM SET instruction

28 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
3.2.1.1 – 3.2.1.5 3.0 Command Description
3.2.1.1 C as character generator RAM, and the CG RAM2
address space is treated as character generator ROM.
This control byte performs the following:
M1 = 1: 64 char CG RAM + CG RAM2
1. Resets the internal timing generator
2. Disables the display The CG RAM1 and CG RAM2 address spaces are
3. Cancels sleep mode contiguous and are both treated as character genera-
tor RAM.
Parameters following P1 are not needed if only can-
celing sleep mode.

3.2.1.4 M2

Selects the height of the character defined in external

3.2.1.2 M0 CG ROM and CG RAM. Characters more than 16 pix-
els high can be displayed by creating a bitmap for
Selects the internal or external character generator
each portion of each character and using the
ROM. The internal character generator ROM con-
SED1330F/1335F/1336F’s graphics mode to reposi-
tains 160, 5 × 7 pixel characters. These characters are
tion them.
fixed at fabrication by the metalization mask. The
external character generator ROM can contain up to M2 = 0: 8-pixel character height (2716 or
256 user-defined characters. equivalent ROM)
M0 = 0: Internal CG ROM M2 = 1: 16-pixel character height (2732
or equivalent ROM)
M0 = 1: External CG ROM

Note that if the CG ROM address space overlaps the

display memory address space, that portion of the
display memory cannot be written to. 3.2.1.5 W/S

Selects the LCD drive method.

W/S = 0: Single-panel drive

W/S = 1: Dual-panel drive
3.2.1.3 M1

Selects the CG RAM area for user-definable charac-

ters. The CG RAM codes are selected from the 64
codes shown in Figure 59.

M1 = 0: CG RAM1; 32 char

The CG RAM1 and CG RAM2 address spaces are not

contiguous, the CG RAM1 address space is treated

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 29
3.0 Command Description 3.2.1.5

EI X driver X driver

YD

Y driver LCD

Figure 8. Single-panel display

EI X driver X driver

YD

Upper Panel
Y driver
Lower Panel

X driver X driver

Figure 9. Dual-panel display

30 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
3.2.1.5 3.0 Command Description

EI X driver X driver X driver X driver

YD

Y driver
Left Panel Right Panel

Note: There are no Seiko-Epson LCD units in the configuration shown in Figure 10.

Figure 10. Left-and-right two-panel display

Table 3. LCD parameters

W/S = 0 W/S = 1
Parameter
IV = 1 IV = 0 IV = 1 IV = 0
C/R C/R C/R C/R C/R
TC/R TC/R TC/R (see note 1) TC/R TC/R
L/F L/F L/F L/F L/F
00H to L/F + 1
SL1 00H to L/F (L/F) / 2 (L/F) / 2
(see note 2)
00H to L/F + 1
SL2 00H to L/F (L/F) / 2 (L/F) / 2
(see note 2)
SAD1 First screen block First screen block First screen block First screen block
SAD2 Second screen block Second screen block Second screen block Second screen block
SAD3 Third screen block Third screen block Third screen block Third screen block
SAD4 Invalid Invalid Fourth screen block Fourth screen block
Cursor move- Above-and-below configuration:
Continuous movement over whole screen
ment range continuousmovement over whole screen
Notes:
1. See table 31 (page 105) for further details on setting the C/R and TC/R parameters when using the HDOT SCR command.
2. The value of SL when IV = 0 is equal to the value of SL when IV = 1, plus one.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 31
3.0 Command Description 3.2.1.6 – 3.2.1.9
3.2.1.6 IV 3.2.1.7 T/L

Screen origin compensation for inverse display. IV is Selects TV or LCD mode. When TV mode is selected,
usually set to 1. the TV sync generator circuit is ON.

The best way of displaying inverted characters is to T/L = 0: LCD mode

Exclusive-OR the text layer with the graphics back- T/L = 1: TV mode
ground layer. However, inverted characters at the top
or left of the screen are difficult to read as the charac-
ter origin is at the top-left of its bitmap and there are no
background pixels either above or to the left of these 3.2.1.8 DR
characters.
Selects output of an additional shift-clock cycle for
The IV flag causes the SED1330F/1335F/1336F to every 64 pixels. The extra cycles are required for
offset the text screen against the graphics back layer correct operation of the enable chain when using a
by one vertical pixel. Use the horizontal pixel scroll two-panel display.
function (HDOT SCR) to shift the text screen 1 to 7
DR = 0: Normal operation
pixels to the right. All characters will then have the
necessary surrounding background pixels that en- DR = 1: Additional shift-clock cycles
sure easy reading of the inverted characters.

See Section 5.5 for information on scrolling.

3.2.1.9 FX
IV = 0: Screen top-line correction
Sets the width, in pixels, of the character field. The
IV = 1: No screen top-line correction (no character width in pixels is equal to FX + 1, where FX
offset) can range from 00 to 07H inclusive. If data bit 3 is set
(FX is in the range 08 to 0FH) and an 8-pixel font is
used, a space is inserted between characters. Note
Display start point
IV that the maximum character width in TV mode is eight
Back layer pixels.
1 dot

HDOT SCR
Table 4. Horizontal character size selection

Character FX [FX] character width

HEX D3 D2 D1 D0 (pixels)
00 0 0 0 0 1
01 0 0 0 1 2
Dots 1 to 7 ↓ ↓ ↓ ↓ ↓ ↓
07 0 1 1 1 8
Figure 11. IV and HDOT SCR adjustment
Since the SED1330F/1335F/1336F handles display
data in 8-bit units, characters larger than 8 pixels wide
must be formed from 8-pixel segments. As Figure 12
shows, the remainder of the second eight bits are not
displayed. This also applies to the second screen layer.

In graphics mode, the normal character field is also

eight pixels. If a wider character field is used, any
remainder in the second eight bits is not displayed.
32 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
3.2.1.10 – 3.2.1.11 3.0 Command Description

FX

FX

FY
8 bits 8 bits
FY
8 bits 8 bits

Address A Address B Non-display area

Figure 12. FX and FY display addresses

3.2.1.10 WF 3.2.1.11 FY

Selects the AC frame drive waveform period. WF is Sets the height, in pixels, of the character. The height
usually set to 1. in pixels is equal to FY + 1.

WF = 0: 16-line AC drive FY can range from 00 to 0FH inclusive.

WF = 1: two-frame AC drive
Set FY to zero (vertical size equals one) when in
graphics mode.
In two-frame AC drive, the WF period is twice the
frame period. Table 5. Vertical character size selection
In 16-line AC drive, WF inverts every 16 lines. FY [FY] character
HEX D3 D2 D1 D0 height (pixels)
Although 16-line AC drive gives a more readable
display, horizontal lines may appear when using high 00 0 0 0 0 1
LCD drive voltages or at high viewing angles. 01 0 0 0 1 2
↓ ↓ ↓ ↓ ↓ ↓
07 0 1 1 1 8
↓ ↓ ↓ ↓ ↓ ↓
0E 1 1 1 0 15
0F 1 1 1 1 16

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 33
3.0 Command Description 3.2.1.12 – 3.2.1.13
3.2.1.12 C/R

Sets the address range covered by one display line, characters, less 2. See Section 9.1.1 for the calcula-
that is, the number of characters less one, multiplied tion of C/R.
by the number of horizontal bytes per character.
[C/R] cannot be set to a value greater than the
C/R can range from 0 to 239. address range. It can, however, be set smaller than
the address range, in which case the excess display
For example, if the character width is 10 pixels, then area is blank. The number of excess pixels must not
the address range is equal to twice the number of exceed 64.

Table 6. Display line address range

C/R
[C/R] bytes per display line
HEX D7 D6 D5 D4 D3 D2 D1 D0
00 0 0 0 0 0 0 0 0 1
01 0 0 0 0 0 0 0 1 2
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
4F 0 1 0 0 1 1 1 1 80
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
EE 1 1 1 0 1 1 1 0 239
EF 1 1 1 0 1 1 1 1 240

3.2.1.13 TC/R

Sets the length, including horizontal blanking, of one according to the equation given in section 9.1.1 in
line. The line length is equal to TC/R + 1, where TC/ order to hold the frame period constant and minimize
R can range from 0 to 255. jitter for any given main oscillator frequency, fOSC.

TC/R must be greater than or equal to C/R + 4.

Provided this condition is satisfied, [TC/R] can be set

Table 7. Line length selection

TC/R
[TC/R] line length (bytes)
HEX D7 D6 D5 D4 D3 D2 D1 D0
00 0 0 0 0 0 0 0 0 1
01 0 0 0 0 0 0 0 1 2
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
52 0 1 0 1 0 0 1 0 83
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
FE 1 1 1 1 1 1 1 0 255
FF 1 1 1 1 1 1 1 1 256

34 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
3.2.1.14 – 3.2.1.15 3.0 Command Description
3.2.1.14 L/F

Sets the height, in lines, of a frame. The height in lines If W/S is set to 1, selecting two-screen display, the
is equal to L/F + 1, where L/F can range from 0 to 255. number of lines must be even and L/F must, therefore,
be an odd number.

Table 8. Frame height selection

L/F
[L/F] lines per frame
HEX D7 D6 D5 D4 D3 D2 D1 D0
00 0 0 0 0 0 0 0 0 1
01 0 0 0 0 0 0 0 1 2
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
7F 0 1 1 1 1 1 1 1 128
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
FE 1 1 1 1 1 1 1 0 255
FF 1 1 1 1 1 1 1 1 256

Table 9. Frame heights and compatible LCD units Table 10. Horizontal address range

Number of lines [LF] Panel Duty Cycle Hex code [AP] addresses
APH APL per line
64 1/64
0 0 0 0 0
0 0 0 1 1
128 1/64
↓ ↓ ↓ ↓ ↓
0 0 5 0 80
↓ ↓ ↓ ↓ ↓
F F F E 16
2 –2
3.2.1.15 AP
F F F F 216 – 1
Defines the horizontal address range of the virtual
screen. APL is the least significant byte of the ad-
dress.

APL AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0

APH AP15 AP14 AP13 AP12 AP11 AP10 AP9 AP8

Figure 13. AP parameters

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 35
3.0 Command Description 3.2.1.15 – 3.3.1
1. The YDIS signal goes LOW between one
and two frames after the SLEEP IN com-
mand is received. Since YDIS forces all
display driver outputs to go to the dese-
lected output voltage, YDIS can be used as
Display area a power-down signal for the LCD unit. This
can be done by having YDIS turn off the
relatively high-power LCD drive supplies at
C/R
the same time as it blanks the display.

2. Since all internal clocks in the SED1330F/

1335F/1336F are halted while in the sleep
Display memory limit state, a DC voltage will be applied to the LCD
panel if the LCD drive supplies remain on.

AP
If reliability is a prime consideration, turn off
the LCD drive supplies before issuing the
Figure 14. AP and C/R relationship SLEEP IN command.

3. Note that, although the bus lines become

3.2.2 SLEEP IN high impedance in the sleep state, pull-up
or pull-down resistors on the bus line will
Places the system in standby mode. This command force these lines to a known state.
has no parameter bytes. At least one blank frame after
receiving this command, the SED1330F/1335F/1336F
halts all internal operations, including the oscillator,
and enters the sleep mode. Blank data is sent to the
X-drivers, and the Y-drivers have their bias supplies 3.3 Display Control Commands
turned off by the YDIS signal. Using the YDIS signal
to disable the Y-drivers guards against any spurious 3.3.1 DISP ON/OFF
displays.
Turns the whole display on or off. The single-byte
The internal registers of the SED1330F/1335/1336F parameter enables and disables the cursor and lay-
maintain their values during the sleep mode. The ered screens, and sets the cursor and screen flash
display memory control pins maintain their logic levels rates. The cursor can be set to flash over one charac-
to ensure that the display memory is not corrupted. ter or over a whole line.

The SED1330F/1335F/1336F can be removed from

the sleep state by sending the SYSTEM SET com- MSB LSB
mand with only the P1 parameter. The DISP ON
C 0 1 0 1 1 0 0 0
command should be sent next to enable the display.
P1 FP5 FP4 FP3 FP2 FP1 FP0 FC1 FC0
MSB LSB

C 0 1 0 1 0 0 1 1 Figure 16. DISP ON/OFF parameters

Figure 15. SLEEP IN instruction

36 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
3.3.1.1 – 3.3.2.1 3.0 Command Description
3.3.1.1 D Note: If SAD4 is enabled by setting W/S to 1, FP3 and FP2
control both SAD2 and SAD4. The attributes of SAD2
and SAD4 cannot be set independently.
Turns the display ON or OFF. The D bit takes prece-
dence over the FP bits in the parameter.

D = 0: Display OFF
3.3.2 SCROLL
D = 1: Display ON
3.3.2.1 C

Sets the scroll start address and the number of lines

3.3.1.2 FC per scroll block. Parameters P1 to P10 can be omitted
if not required. The parameters must be entered
Enables/disables the cursor and sets the flash rate. sequentially as shown in Figure 17.
The cursor flashes with a 70% duty cycle (ON/OFF).

Table 11. Cursor flash rate selection

MSB LSB
FC1 FC0 Cursor display
C 0 1 0 0 0 1 0 0
0 0 OFF (blank)
0 1 No flashing P1 A7 A6 A5 A4 A3 A2 A1 A0 (SAD 1L)
Flash at fFR/32 Hz
1 0 ON (approx. 2 Hz) P2 A15 A14 A13 A12 A11 A10 A9 A8 (SAD 1H)
Flash at fFR/64 Hz
1 1
(approx. 1 Hz) P3 L7 L6 L5 L4 L3 L2 L1 L0 (SL 1)
Note: As the MWRITE command always enables the cursor,
the cursor position can be checked even when perform-
ing consecutive writes to display memory while the P4 A7 A6 A5 A4 A3 A2 A1 A0 (SAD 2 L)
cursor is flashing.
P5 A15 A14 A13 A12 A11 A10 A9 A8 (SAD 2H)

P6 L7 L6 L5 L4 L3 L2 L1 L0 (SL 2)
3.3.1.3 FP

Each pair of bits in FP sets the attributes of one screen P7 A7 A6 A5 A4 A3 A2 A1 A0 (SAD 3L)
block, as follows.
P8 A15 A14 A13 A12 A11 A10 A9 A8 (SAD 3H)
Table 12. Screen block attribute selection
P9 A7 A6 A5 A4 A3 A2 A1 A0 (SAD 4L)
FP1 FP0 First screen block (SAD1)
Second screen block (SAD2,
FP3 FP2 P10 A15 A14 A13 A12 A11 A10 A9 A8 (SAD 4H)
SAD4). See note.
FP5 FP4 Third screen block (SAD3)
Note: Set parameters P9 and P10 only if both two-screen
0 0 OFF (blank) drive (W/S = 1) and two-layer configuration are se-
0 1 No flashing lected. SAD4 is the fourth screen block display start
address.
Flash at fFR/32 Hz
1 0 ON (approx. 2 Hz)
Flash at fFR/4 Hz Figure 17. SCROLL instruction parameters
1 1
(approx. 16 Hz)

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 37
3.0 Command Description 3.3.2.1 – 3.3.2.2
Table 13. Screen block start address selection

SL1, SL2
[SL] screen lines
HEX L7 L6 L5 L4 L3 L2 L1 L0
00 0 0 0 0 0 0 0 0 1
01 0 0 0 0 0 0 0 1 2
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
7F 0 1 1 1 1 1 1 1 128
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
FE 1 1 1 1 1 1 1 0 255
FF 1 1 1 1 1 1 1 1 256

3.3.2.2 SL1, SL2

SL1 and SL2 set the number of lines per scrolling The relationship between SAD, SL and the display
screen. The number of lines is SL1 or SL2 plus one. mode is described below.

Table 14. Text display mode

W/S Screen First Layer Second Layer

First screen block SAD1 SAD2
Second screen block SL1 SL2
SAD3 (see note 1)
Third screen block (partitioned screen) Set both SL1 and SL2 to L/F + 1
if not using a partitioned screen.
Screen configuration example:

SAD2

SAD1
0 SL2

Graphics display page 2

SL1 Character display page 1

SAD3

Character display page 3

Layer 2

Layer 1

(continued)

38 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
3.3.2.2 3.0 Command Description
Table 14. Text display mode (continued)

W/S Screen First Layer Second Layer

SAD1 SAD2
Upper screen
SL1 SL2
SAD3 SAD4
Lower screen
(see note 2) (see note 2)
Set both SL1 and SL2 to ((L/F) / 2 + 1)
Screen configuration example:

SAD2

SAD1

1 Graphics display page 2

SL1 Character display page 1

SAD3
Graphics display page 4
(SAD4)
Character display page 3

Layer 1 Layer 2

Notes:
1. SAD3 has the same value as either SAD1 or SAD2, whichever has the least number of lines (set by SL1 and SL2).
2. Since the parameters corresponding to SL3 and SL4 are fixed by L/F, they do not have to be set in this mode.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 39
3.0 Command Description 3.3.2.2
Table 15. Graphics display mode

W/S Screen First Layer Second Layer Third Layer

SAD1 SAD2
Two-layer composition
SL1 SL2
SAD3 (see note 3)
Set both SL1 and SL2 to
Upper screen
L/F + 1 if not using a
partitioned screen
Screen configuration example:

SAD2

SAD1
SL2
0
Graphics display page 2
SL1 Character display page 1

SAD3

Character display page 3

Layer 1 Layer 2

SAD1 SAD2 SAD3

Three-layer configuration
SL1 = L/F + 1 SL2 = L/F + 1 —
Screen configuration example:

SAD3
Graphics display page 3
SAD2
SAD1

SL2
SL1
0 Graphics display page 2

Graphics display page 1

Layer 3
Layer 1 Layer 2

40 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
3.3.2.2 3.0 Command Description
Table 15. Graphics display mode (continued)

W/S Screen First Layer Second Layer Third Layer

SAD1 SAD2
Upper screen —
SL1 SL2
SAD3 SAD4
Lower screen —
(see note 2) (see note 2)
Set both SL1 and SL2 to ((L/F) / 2 + 1)
Screen configuration example (see note 3):

SAD2

SAD1

1
Graphics display page 2
SL1 Graphics display page 1

SAD3
Graphics display page 4

Graphics display page 3

Layer 1 Layer 2

Notes:
1. SAD3 has the same value as either SAD1 or SAD2, whichever has the least number of lines (set by SL1 and SL2).
2. Since the parameters corresponding to SL3 and SL4 are fixed by L/F, they do not have to be set.
3. If, and only if, W/S = 1, the differences between SL1 and (L/F + 1) / 2, and between SL2 and (L/F + 1) / 2, are blanked.

SL1
Upper Panel

L
Graphics
L/2 Lower Panel

Figure 18. Two-panel display height

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 41
3.0 Command Description 3.3.3 – 3.3.3.2
3.3.3 CSRFORM 3.3.3.2 CRY

Sets the cursor size and display mode. Although the Sets the location of an underscored cursor in lines,
cursor is normally only used in text displays, it may from the character origin. When using a block cursor,
also be used in graphics displays when displaying CRY sets the vertical size of the cursor from the
special characters. character origin. CRY is equal to the number of lines
less one.

MSB LSB Table 17. Cursor height selection

C 0 1 0 1 1 1 0 1 CRY [CRY] cursor

HEX Y3 Y2 Y1 Y0 height (lines)
CRX
P1 0 0 0 0 X3 X2 X1 X0 0 0 0 0 0 illegal
1 0 0 0 1 2
CRY
P2 CM 0 0 0 Y3 Y2 Y1 Y0 ↓ ↓ ↓ ↓ ↓ ↓
8 1 0 0 0 9
Figure 19. CSRFORM parameter bytes ↓ ↓ ↓ ↓ ↓ ↓
E 1 1 1 0 15
F 1 1 1 1 16

3.3.3.1 CRX

Sets the horizontal size of the cursor from the charac-

ter origin. CRX is equal to the cursor size less one.
Character start point
CRX must be less than or equal to FX.
0 1 2 3 4 5 6 • • •
0
Table 16. Horizontal cursor size selection
1
CRX [CRX] cursor width
2
HEX X3 X2 X1 X0 (pixels)
3
0 0 0 0 0 1
4
1 0 0 0 1 2
↓ ↓ ↓ ↓ ↓ ↓ 5

8 1 0 0 0 9 6

↓ ↓ ↓ ↓ ↓ ↓ 7
E 1 1 1 0 15 8
F 1 1 1 1 16 9
CRX = 5 dots
CRY = 9 dots
CM = 0

Figure 20. Cursor size and position

42 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
3.3.3.3 – 3.3.5.1 3.0 Command Description
3.3.3.3 CM Table 18. Cursor shift direction

Sets the cursor display mode. Always set CM to 1 C CD1 CD0 Shift direction
when in graphics mode. 4CH 0 0 Right
4DH 0 1 Left
CM = 0: Underline cursor
4EH 1 0 Up
CM = 1: Block cursor
4FH 1 1 Down
Note: Since the cursor moves in address units even if FX ≥ 9,
the cursor address increment must be preset for move-
ment in character units. See Section 5.3.
3.3.4 CSRDIR

Sets the direction of automatic cursor increment. The

cursor can move left or right one character, or up or
down by the number of bytes specified by the address
3.3.5 OVLAY
pitch, AP. Selects layered screen composition and screen text/
When reading from and writing to display memory, graphics mode.
this automatic cursor increment controls the display
memory address increment on each read or write.
MSB LSB

C 0 1 0 1 1 0 1 1
MSB LSB

C 0 1 0 0 1 1 CD1 CD2 P1 0 0 0 OV DM2 DM1 MX1 MX0

Figure 21. CSRDIR parameters Figure 23. OVLAY parameter

3.3.5.1 MX0, MX1

MX0 and MX1 set the layered screen composition

10
method, which can be either OR, AND, Exclusive-OR
–AP or Priority-OR. Since the screen composition is orga-
nized in layers and not by screen blocks, when using
a layer divided into two screen blocks, different com-
–1 +1
01 00
position methods cannot be specified for the indi-
vidual screen blocks.

The Priority-OR mode is the same as the OR mode

+AP unless flashing of individual screens is used.
11

Figure 22. Cursor direction

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 43
3.0 Command Description 3.3.5.1
Table 19. Composition method selection

MX1 MX0 Function Composition Method Applications

0 0 L1 ∪ L2 ∪ L3 OR Underlining, rules, mixed text and graphics
Inverted characters, flashing regions, un-
0 1 (L1 ⊕ L2) ∪ L3 Exclusive-OR
derlining
1 0 (L1 ∩ L2) ∪ L3 AND Simple animation, three-dimensional ap-
1 1 L1 > L2 > L3 Priority-OR pearance
Notes:
L1: First layer (text or graphics). If text is selected, layer L3 cannot be used.
L2: Second layer (graphics only)
L3: Third layer (graphics only)

Layer 1 Layer 2 Layer 3 Visible display

1 EPSON EPSON OR

2 EPSON EPSON Exclusive OR

3 EPSON SON AND

4 EPSON EPSON Prioritized OR

Notes:
L1: Not flashing
L2: Flashing at 1 Hz
L3: Flashing at 2 Hz

Figure 24. Combined layer display

44 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
3.3.5.2 – 3.3.7.1 3.0 Command Description
3.3.5.2 DM1, DM2 3.3.7 HDOT SCR

DM1 and DM2 specify the display mode of screen While the scroll command only allows scrolling by
blocks 1 and 3, respectively. characters, HDOT SCR allows the screen to be scrolled
horizontally by pixels. HDOT SCR cannot be used on
DM1/2 = 0: Text mode individual layers.
DM1/2 = 1: Graphics mode
Note 1: Screen blocks 2 and 4 can only display graphics.
MSB LSB
Note 2: DM1 and DM2 must be the same, regardless of the
setting of W/S. C 0 1 0 1 1 0 1 0

P1 0 0 0 0 0 D2 D1 D0

3.3.5.3 OV

Specifies two- or three-layer composition in graphics Figure 26. HDOT SCR parameters
mode.

OV = 0: Two-layer composition
OV = 1: Three-layer composition 3.3.7.1 D0 to D2

Specifies the number of pixels to scroll. The C/R

Set OV to 0 for mixed text and graphics mode. parameter has to be set to one more than the number
of horizontal characters before using HDOT SCR.
Smooth scrolling can be simulated if the controlling
microprocessor repeatedly issues the HDOT SCR
command to the SED1330F/1335F/1336F. See Sec-
3.3.6 CGRAM ADR
tion 5.5 for more information on scrolling the display.
Specifies the CG RAM start address.
Table 20. Scroll step selection

P1 Number of pixels
MSB LSB
HEX D2 D1 D0 to scroll
C 0 1 0 1 1 1 0 0
00 0 0 0 0
01 0 0 1 1
P1 A7 A6 A5 A4 A3 A2 A1 A0 (SAGL)
02 0 1 0 2
P2 A15 A14 A13 A12 A11 A10 A9 A8 (SAGH) ↓ ↓ ↓ ↓ ↓
06 1 1 0 6
07 1 1 1 7
Figure 25. CGRAM ADR parameters

Note: See Section 6 for information on the SAG parameters.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 45
3.0 Command Description 3.4 – 3.4.2
Note that the microprocessor cannot directly access
the display memory.
M

The MREAD and MWRITE commands use the ad-

A B X Y dress in this register.

M=0 The cursor address register can only be modified by

Z A B X Y
N=0 the CSRW command, and by the automatic incre-
ment after an MREAD or MWRITE command. It is not
affected by display scrolling.
Z A B X Y

If a new address is not set, display memory accesses

Display width N
will be from the last set address or the address after
M/N is the number of bits (dots) that parameter 1 (P1)
is incremented/decremented by. previous automatic increments.

Figure 27. Horizontal scrolling

3.4.2 CSRR

Reads from the cursor address register. After issuing

the command, the data read address is read twice, for
3.4 Drawing Control Commands the low byte and then the high byte of the register.
3.4.1 CSRW
MSB LSB
The 16-bit cursor address register contains the dis-
play memory of the data at the cursor position as C 0 1 0 0 0 1 1 1
shown in Figure 28.
P1 A7 A6 A5 A4 A3 A2 A1 A0 (CSRL)

MSB LSB
P2 A15 A14 A13 A12 A11 A10 A9 A8 (CSRH)
C 0 1 0 0 0 1 1 0

P1 A7 A6 A5 A4 A3 A2 A1 A0 (CSRL) Figure 29. CSRR parameters

P2 A15 A14 A13 A12 A11 A10 A9 A8 (CSRH)

Figure 28. CSRW parameters

46 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
3.5 – 3.5.2 3.0 Command Description
3.5 Memory Control Commands 3.5.2 MREAD

3.5.1 MWRITE Puts the SED1330F/1335F/1336F into the data out-

put state. On the MREAD command, the display
The microprocessor may write a sequence of data memory data at the cursor address is read into a
bytes to display memory by issuing the MREAD buffer in the SED1330F/1335F/1336F.
command and then writing the bytes to the SED1330F/
1335F/1336F. There is no need for further MWRITE Each time the microprocessor reads the buffer, the
commands or for the microprocessor to update the cursor address is incremented by the amount set by
cursor address register after each byte as the cursor CSRDIR and the next data byte fetched from memory,
address is automatically incremented by the amount set so a sequence of data bytes may be read without
with CSRDIR, in preparation for the next data write. further MREAD commands or by updating the cursor
address register.

MSB LSB If the cursor is displayed, the read data will be from two
positions ahead of the cursor.
C 0 1 0 0 0 0 1 0

P1 MSB LSB

C 0 1 0 0 0 0 1 1
P2

P1

Pn n≥1
P2
Note:
P1, P2, ..., Pn: display data.
Pn n≥1

Figure 30. MWRITE parameters

Figure 31. MREAD parameters

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 47
1.0 Overview 1.3

THIS PAGE INTENTIONALLY BLANK

48 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
3.3.2.2 3.0 Command Description

4.0
Specifications

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 49
 THIS PAGE INTENTIONALLY BLANK

50 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.0 – 4.1 4.0 Specifications
4.0 Specifications

4.1 Absolute Maximum Ratings

4.1.1 SED1330

Parameter Symbol Rating Unit

Supply voltage range VDD –0.3 to 7.0 V
Input voltage range VIN –0.5 to VDD + 0.5 V
Power dissipation PD 300 mW
Operating temperature range Topr –20 to 75 °C
Storage temperature range Tstg –65 to 150 °C
Soldering temperature (10 seconds). See note 1. Tsolder 260 °C

4.1.2 SED1335/SED1336

Parameter Symbol Rating Unit

Supply voltage range VDD –0.3 to 7.0 V
Input voltage range VIN –0.3 to VDD + 0.3 V
Power dissipation PD 300 mW
Operating temperature range Topr –20 to 75 °C
Storage temperature range Tstg –65 to 150 °C
Soldering temperature (10 seconds). See note 1. Tsolder 260 °C

Notes:
1. The humidity resistance of the flat package may be reduced if the package is immersed in solder. Use a soldering technique
that does not heatstress the package.
2. If the power supply has a high impedance, a large voltage differential can occur between the input and supply voltages. Take
appropriate care with the power supply and the layout of the supply lines. (See Section 2.3.)
3. All supply voltages are referenced to VSS = 0V.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 51
4.0 Specifications 4.2
4.2 SED 1330 Electrical Characteristics
VDD = 5V ±10%, VSS = 0V, Ta = –20 to 75°C
Rating
Parameter Symbol Condition Unit
min typ max
Supply voltage VDD 4.5 5.0 5.5 V
Register data retention voltage VOH 2.0 — 5.5 V
Input leakage current ILI VI = VDD. — 0.05 2.0 µA
Output leakage current ILO VI = VSS. — 0.10 5.0 µA
Operating supply current Iopr See note 4. — 8 12 mA

Quiescent supply current IQ VOSC1 = VCS = VRD = VDD — 0.05 20.0 µA

Oscillator frequency fOSC 1.0 — 10.0 MHz

External clock frequency fCL Measured at OSC1 — — 10.0 MHz
Oscillator feedback resistance Rf 0.5 1.0 5.0 MΩ
TTL
HIGH-level input voltage VIHT See note 1. 2.2 — VDD + 0.3 V
LOW-level input voltage VILT See note 1. –0.3 — 0.8 V
IOH = –5.0 mA.
HIGH-level output voltage VOHT 2.4 — — V
See note 1.
LOW-level output voltage VOLT IOL = 5.0 mA. See note 1. — — 0.4 V
CMOS
HIGH-level input voltage VIHC See note 2. 0.8V DD — — V
LOW-level input voltage VILC See note 2. — — 0.2V DD V
HIGH-level output voltage VOHC IOH = –1.6 mA. See note 2.VDD – 0.4 — — V
LOW-level output voltage VOLC IOH = 1.6 mA. See note 2. — — 0.4 V
Schmitt-trigger
Rising-edge threshold voltage VT+ See note 3. 0.5V DD 0.7V DD 0.8V DD V
Falling-edge threshold voltage VT– See note 3. 0.2V DD 0.3V DD 0.5V DD V

Notes:
1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15,
VR/W and VCE are TTL-level inputs.
2. SEL1, SEL2 and OSC1 are CMOS-level inputs. YD,
XD0 to XD3, XSCL, YECL, LP, WF, YSCL, YDIS and
CLO are CMOS-level outputs.
3. RES is a Schmitt-trigger input. The pulsewidth on RES
must be at least 200 µs. Note that pulses of more than
a few seconds will cause DC voltages to be applied to
the LCD panel.
4. fOSC = 10 MHz, no load (no display memory), internal
character generator, 256 × 200 pixel display. The
operating supply current can be reduced by approxi-
mately 1 mA by setting both CLO and the display OFF.

52 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.3 4.0 Specifications
4.3 SED1335/1336 Electrical Characteristics
VDD = 4.5 to 5.5V, VSS = 0V, Ta = –20 to 75°C
Rating
Parameter Symbol Condition Unit
min typ max
Supply voltage VDD 4.5 5.0 5.5 V
Register data retention voltage VOH 2.0 — 6.0 V
Input leakage current I LI VI = VDD. See note 6. — 0.05 2.0 µA
Output leakage current ILO VI = VSS. See note 6. — 0.10 5.0 µA
Operating supply current Iopr See note 4. — 11 15 mA
Sleep mode,
Quiescent supply current IQ — 0.05 20.0 µA
VOSC1 = VCS = VRD = VDD
Oscillator frequency f OSC Measured at crystal, 1.0 — 10.0 MHz
External clock frequency f CL 47.5% duty cycle. 1.0 — 10.0 MHz
Oscillator feedback resistance Rf See note 7. 0.5 1.0 3.0 MΩ
TTL
HIGH-level input voltage VIHT See note 1. 0.5V DD — VDD V
LOW-level input voltage VILT See note 1. VSS — 0.2V DD V
IOH = –5.0 mA.
HIGH-level output voltage VOHT 2.4 — — V
See note 1.
LOW-level output voltage VOLT IOL = 5.0 mA. See note 1. — — VSS + 0.4 V
CMOS
HIGH-level input voltage VIHC See note 2. 0.8V DD — VDD V
LOW-level input voltage VILC See note 2. VSS — 0.2V DD V
HIGH-level output voltage VOHC IOH = –2.0 mA. See note 2. VDD – 0.4 — — V
LOW-level output voltage VOLC IOH = 1.6 mA. See note 2. — — VSS + 0.4 V
Open-drain
LOW-level output voltage VOLN IOL = 6.0 mA. See note 5. — — VSS + 0.4 V
Schmitt-trigger
Rising-edge threshold voltage VT+ See note 3. 0.5V DD 0.7V DD 0.8V DD V
Falling-edge threshold voltage VT– See note 3. 0.2V DD 0.3V DD 0.5V DD V
Notes:
1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15,
VRD, VWR and VCE are TTL-level inputs.
2. SEL1 and NT/PL are CMOS-level inputs. YD, XD0 to
XD3, XSCL, XECL, LP, WF, YSCL, YDIS and CLO are
CMOS-level outputs.
3. RES is a Schmitt-trigger input. The pulsewidth on RES
must be at least 200 µs. Note that pulses of more than
a few seconds will cause DC voltages to be applied to
the LCD panel.
4. fOSC = 10 MHz, no load (no display memory), internal
character generator, 256 × 200 pixel display. The
operating supply current can be reduced by approxi-
mately 1 mA by setting both CLO and the display OFF.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 53
4.0 Specifications 4.4 – 4.4.1
4.4 SED1330 Timing Diagrams

4.4.1 System bus READ/WRITE timing I (8080)

tAH8

A0, CS
tAW8
tCYC
tCC
WR, RD
tDS8
tDH8
D0~D7
(WRITE)
tACC8 tOH8

D0~D7
(READ)

Figure 32. System bus READ/WRITE timing I (8080)

4.4.1.1 SED1330F
Ta = –20 to 75°C
Rating
Signal Symbol Parameter Unit Condition
min max
tAH8 Address hold time 10 — ns
A0, CS
tAW8 Address setup time 30 — ns
tCYC System cycle time (1) — ns
WR, RD
tCC Strobe pulsewidth 220 — ns CL = 100
tDS8 Data setup time 120 — ns pF
tDH8 Data hold time 10 — ns
D0 to D7
tACC8 RD access time — 120 ns
tOH8 Output disable time 10 50 ns
Note: tCYC = 2tC + tCC + tCEA + 75 > tACV + 245:
memory control/movement control commands:
= 4tC + tCC + 30:
all other commands:

54 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.4.2 – 4.4.2.1 4.0 Specifications
4.4 SED1330 Timing Diagrams

4.4.2 System bus READ/WRITE timing II (6800)

tCYC6

E
tAW6 tEW

R/W

tAH6

A0, CS
tDS6
tDH6
D0~D7
(WRITE)
tACC6 tOH6
D0~D7
(READ)

Figure 33. System bus READ/WRITE timing II (6800)

4.4.2.1 SED1330F
Ta = –20 to 75°C
Rating
Signal Symbol Parameter Unit Condition
min max
t AH6 Address hold time 10 — ns
A0, CS
t AW6 Address setup time 30 — ns
R/W
tCYC6 System cycle time (1) — ns
CL=100pF+1TTL
t DS6 Data setup time 120 — ns
pF
tDH6 Data hold time 10 — ns
D0 to D7
tACC6 Access time — 120 ns
t OH6 Output disable time 10 50 ns
E t EW Enable pulse width 220 — ns

Note: (1) tCYC6 = 2tC + tEW + tCEA + 75 > tACV + 245:

memory control/movement control commands:
= 4tC + tEW + 30:
all other commands:
1. tCYC6 means a cycle of (CS.E) not E alone.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 55
4.0 Specifications 4.4.3 – 4.4.3.1
4.4 SED1330 Timing Diagrams

4.4.3 Display memory READ timing

tC

EXTφO
tW tCE tW

VCE
tCYR

VA0~VA15
tASC tAHC tRCH

VR/W tRCS tCE3

tCEA
tOH2
tACY

VD0~VD7

Figure 34. Display memory READ timing

4.4.3.1 SED1330F
Ta = –20 to 75°C
Rating
Signal Symbol Parameter Unit Condition
min max
EXT Ø0 tC Clock cycle 100 — ns
tW VCE high level pulse width tc–40 — ns
VCE
tCE VCE low level pulse width 2tc–40 — ns
tCYR Read cycle time (1) — ns
VA0
tASC VCE address setup time (fall) tc–45 — ns CL = 100pF
to VA15
tAHC VCE address hold time (fall) 2tc–40 — ns +1TTL
tRCS VCE read cycle setup time (fall) tc–45 — ns
VR/W
tRCH VCE read cycle hold time (fall) tc/2–35 — ns
tACV Address access time — (2) ns
VD0 tCEA VCE access time — (3) ns
to VD7 tOH2 Output data hold time 0 — ns
tCE2 VCE data off time 0 — ns

Note: 1. tCYR = 3tC

2. tACV = 3tC –120
3. tCEA = 2tC –120

56 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.4.4 – 4.4.4.1 4.0 Specifications
4.4 SED1330 Timing Diagrams

4.4.4 Display memory WRITE timing

tC

EXTφO
tW tCE

VCE
tASC tCA
tAHC

VA0~VA15
tCYW
tAS tWSC
tWHC tAH2

VWR
tOSC tOH2
tOHC

VD0~VD7

Figure 35. Display memory WRITE timing

4.4.4.1 SED1330F
Ta = –20 to 75°C
Rating
Signal Symbol Parameter Unit Condition
min max
EXT Ø0 tC Clock cycle 100 — ns
tW VCE high level pulse width tc–40 — ns
VCE
t CE VCE low level pulse width 2tc–40 — ns
tCYW Write cycle time 3tc — ns
tAHC VCE address hold time (fall) 2tc–40 — ns
VA0 t ASC VCE address setup time (fall) tc–55 — ns CL = 100pF
to VA15 t CA VCE address hold time (rise) 5 — ns +1TTL
tAS VR/W address setup time (fall) 0 — ns
t AH2 VR/W address hold time (rise) 15 — ns
tWSC VCE write setup time (fall) tc–55 — ns
VR/W
t WHC VCE write hold time (fall) tc2–40 — ns
tDSC VCE data input setup time (fall) twsc–10 — ns
VD0
t DHC VCE data input hold time (fall) 2tc–30 — ns
to VD7
tDH2 VR/W data hold time (rise) 10* 50 ns

* Lines VD0 to VD7 are latched.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 57
4.0 Specifications 4.4.5
4.4 SED1330 Timing Diagrams

4.4.5 LCD control timing

ROW NO

LP
1 frame period
YD

WF
YSCL

WF 1 line period
YSCL
ROW64 ROW1 ROW2

LP
XSCL

XD0~XD3

XECL
tr tWX tf tCX

XSCL
tDS tDH

XD0~XD3
tWL

tL1 tL2
LP
tS2 tS1
XECL tWXE

WF(B)
YD
tDf
YSCL
tLD
tDHY

tWY

Figure 36. LCD control timing

58 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.4.5.1 4.0 Specifications
4.4 SED1330 Timing Diagrams

4.4.5.1 SED1330F
Ta = –20 to 75°C
Rating
Signal Symbol Parameter Unit Condition
min max
EXT Ø0 tC Clock cycle 100 — ns
tr VCE high level pulse width — 35 ns
tf VCE low level pulse width — 35 ns
t CX Shift clock cycle time 4tc — ns
XSCL
t WX XSCL clock pulse width t CX2–80 — ns
XD0 tDH X-data hold time t CX2–100 — ns VDD = 5.0V
to XD3 t DS X-data setup time t CX2–100 — ns ±10%
tLS Latch data setup time t CX2–100 — ns CL=150F
LP
t WL LP signal pulse width t CX4–80 — ns
tL1 XECL setup time t CX3–100 — ns
tL2 XECL data hold time t C–30 — ns
XECL tS1 Enable setup time t C–30 — ns
tS1 Enable delay time t C–30 — ns
t WXE XECL clock pulse width t CX3–80 — ns
WF tDF Time allowance of WF delay — 100 ns
t LD LP delay time against YSCL t CX4–100 — ns
YSCL
t WY YSCL clock pulse width t CX4–80 — ns
YD tDHY Y-data hold time t CX6–100 — ns

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 59
4.0 Specifications 4.4 .6– 4.4.6.1
4.4 SED1330 Timing Diagrams

4.4.6 Oscillator timing

VDD
tOSP

CLO

tOSS

YDIS
Power ON Sleep period

tRCL tFCL

EXT 0O
tWL tWH
tCL

Figure 37. Oscillator timing

4.4.6.1 SED1330F
Ta = –20 to 75°C
Rating
Signal Symbol Parameter Unit Condition
min max
tOSP Time to stable CLO output after power ON — 3 ms RES = H
CLO
tOSS Time to stable CLO output after sleep OFF — 1 ms 20 pF
tRCL External clock rise time — 15 ns
tFCL External clock fall time — 15 ns
EXTø0 tWH External clock high-pulse width Note 1 Note 2 ns
tWL External clock low-pulse width Note 1 Note 2 ns
tCL External clock cycle 100 — ns

1. (tC – tRCL – tFCL) X 475/1000 < tWH, tWL

2. (tC – tRCL – tFCL) X 525/1000 > tWH, tWL

60 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.4.7 4.0 Specifications
4.4 SED1330 Timing Diagrams

4.4.7 Measurement circuit

VDD

2.1 KΩ

Measurement
Terminal

C = 100 pF 24 KΩ
IN 916
COMPATABLE

VSS

* C includes probe capacitance.

Figure 38. Measurement circuit

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 61
4.0 Specifications 4.5 – 4.5.1.1
4.5 SED1335/SED1336 AC Timing Diagrams

4.5.1 8080 family Interface Timing

AO, CS

tAW8 tAH8
tCYC
WR, RD

tCC
tDH8
tDS8
D0 to D7
(Write)

tACC8 tOH8

D0 to D7
(Read)

Figure 39. 8080 family interface timing

4.5.1.1 SED1335F
Ta = –20 to 75°C
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal Symbol Parameter Unit Condition
min max min max
tAH8 Address hold time 10 — 10 — ns
A0, CS
tAW8 Address setup time 0 — 0 — ns
tCYC System cycle time See note — See note — ns
WR, RD
tCC Strobe pulsewidth 120 — 150 — ns CL = 100
tDS8 Data setup time 120 — 120 — ns pF
tDH8 Data hold time 5 — 5 — ns
D0 to D7
tACC8 RD access time — 50 — 80 ns
tOH8 Output disable time 10 50 10 55 ns
Note: For memory control and system control commands:
tCYC8 = 2tC + tCC + tCEA + 75 > tACV + 245
For all other commands:
tCYC8 = 4tC + tCC + 30

62 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.5.1.2 4.0 Specifications
4.5.1.2 SED1336F
Ta = –20 to 75°C
VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V
Signal Symbol Parameter Unit Condition
min max min max
t AH8 Address hold time 10 — 10 — ns
A0, CS
t AW8 Address setup time 0 — 0 — ns
tCYC System cycle time See note — See note — ns
WR, RD
tCC Strobe pulsewidth 120 — 140 — ns CL = 100
t DS8 Data setup time 120 — 120 — ns pF
tDH8 Data hold time 5 — 5 — ns
D0 to D7
tACC8 RD access time — 50 — 70 ns
t OH8 Output disable time 10 50 10 50 ns
Note: For memory control and system control commands:
tCYC8 = 2tC + tCC + tCEA + 75 > tACV + 245
For all other commands:
tCYC8 = 4tC + tCC + 30

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 63
4.0 Specifications 4.5.2
4.5.2 6800 family Interface Timing

tCYC
tAW6 tEW
R/W

tAH6

AO, CS

tDH6
tDS6

D0 to D7
(Write)

tACC6 tOH6

D0 to D7
(Read)

Note: tCYC6 indicates the interval during which CS is LOW and E is HIGH.

Figure 40. 6800 family interface timing

64 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.5.2.1 – 4.5.2.2 4.0 Specifications
4.5.2.1 SED1335F
Ta = –20 to 75°C
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal Symbol Parameter Unit Condition
min max min max
A0, tCYC6 System cycle time See note — See note — ns
CS, t AW6 Address setup time 0 — 10 — ns
R/W t AH6 Address hold time 0 — 0 — ns
t DS6 Data setup time 100 — 120 — ns CL =
tDH6 Data hold time 0 — 0 — ns 100 pF
D0 to D7
t OH6 Output disable time 10 50 10 75 ns
tACC6 Access time — 85 — 130 ns
E t EW Enable pulsewidth 120 — 150 — ns
Note: For memory control and system control commands:
tCYC6 = 2tC + tEW + tCEA + 75 > tACV + 245
For all other commands:
tCYC6 = 4tC + tEW + 30

4.5.2.2 SED1336F
Ta = –20 to 75°C
VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V
Signal Symbol Parameter Unit Condition
min max min max
A0, tCYC6 System cycle time See note — See note — ns
CS, t AW6 Address setup time 0 — 10 — ns
R/W t AH6 Address hold time 0 — 0 — ns
t DS6 Data setup time 100 — 120 — ns CL =
tDH6 Data hold time 0 — 0 — ns 100 pF
D0 to D7
t OH6 Output disable time 10 50 10 70 ns
tACC6 Access time — 85 — 120 ns
E t EW Enable pulsewidth 120 — 140 — ns
Note: For memory control and system control commands:
tCYC6 = 2tC + tEW + tCEA + 75 > tACV + 245
For all other commands:
tCYC6 = 4tC + tEW + 30

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 65
4.0 Specifications 4.5.3 – 4.5.3.1
4.5.3 Display Memory Read Timing

EXTΦ0
tC
tW tCE tW

VCE

tCYR

VA0 to VA15

tASC tAHC
tRCH

VRD
tRCS tCEA tCE3
tACV tOH2

VD0 to VD7
(SED1335F)

Figure 41. Display memory read timing

4.5.3.1 SED1335F
Ta = –20 to 75°C
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal Symbol Parameter Unit Condition
min max min max
EXT φ0 tC Clock period 100 — 125 — ns
VCE HIGH-level pulse-
tW tC – 50 — tC – 50 — ns
width
VCE
VCE LOW-level pulse-
tCE 2tC – 30 — 2tC – 30 — ns
width
tCYR Read cycle time 3tC — 3t C — ns
Address setup time to
VA0 to tASC tC – 70 — tC – 100 — ns
falling edge of VCE
VA15 CL = 100
Address hold time from
tAHC 2tC – 30 — 2tC – 40 — ns pF
falling edge of VCE
Read cycle setup time to
tRCS tC – 45 — tC – 60 — ns
falling edge of VCE
VRD
Read cycle hold time
tRCH 0.5tC — 0.5tC — ns
from rising edge of VCE
tACV Address access time — 3tC – 100 — 3tC – 115 ns
VD0 to tCEA VCE access time — 2tC – 80 — 2tC – 90 ns
VD7 tOH2 Output data hold time 0 — 0 — ns
tCE3 VCE to data off time 0 — 0 — ns

66 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.5.3.2 4.0 Specifications
4.5.3.2 SED1336F
Ta = –20 to 75°C
VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V
Signal Symbol Parameter Unit Condition
min max min max
EXT φ0 tC Clock period 100 — 125 — ns
VCE HIGH-level pulse-
tW tC – 50 — tC – 50 — ns
width
VCE
VCE LOW-level pulse-
t CE 2tC – 30 — 2tC – 30 — ns
width
tCYR Read cycle time 3tC — 3t C — ns
Address setup time to
VA0 to t ASC tC – 70 — tC – 100 — ns
falling edge of VCE
VA15 CL = 100
Address hold time from
tAHC 2tC – 30 — 2tC – 40 — ns pF
falling edge of VCE
Read cycle setup time to
tRCS tC – 45 — tC – 55 — ns
falling edge of VCE
VRD
Read cycle hold time
t RCH 0.5tC — 0.5tC — ns
from rising egde of VCE
t ACV Address access time — 3tC – 100 — 3tC – 110 ns
VD0 to t CEA VCE access time — 2tC – 80 — 2tC – 85 ns
VD7 t OH2 Output data hold time 0 — 0 — ns
t CE3 VCE to data off time 0 — 0 — ns

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 67
4.0 Specifications 4.5.4
4.5.4 Display Memory Write Timing

tC

EXTφO
tW tCE

VCE
tASC tCA
tAHC

VA0~VA15
tCYW
tAS tWSC
tWHC tAH2

VWR
tOSC tOH2
tOHC

VD0~VD7

Figure 42. Display memory write timing

68 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.5.4.1 4.0 Specifications
4.5.4.1 SED1335F
Ta = –20 to 75°C
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal Symbol Parameter Unit Condition
min max min max
EXT φ0 tC Clock period 100 — 125 — ns
VCE HIGH-level pulse-
tW tC – 50 — tC – 50 — ns
width
VCE
VCE LOW-level pulse-
t CE 2tC – 30 — 2tC – 30 — ns
width
tCYW Write cycle time 3tC — 3t C — ns
Address hold time from
tAHC 2tC – 30 — 2tC – 40 — ns
falling edge of VCE
Address setup time to
t ASC tC – 70 — tC – 110 — ns
falling edge of VCE
VA0 to
Address hold time from
VA15 t CA 0 — 0 — ns CL = 100
rising edge of VCE
Address setup time to pF
tAS 0 — 0 — ns
falling edge of VWR
Address hold time from
t AH2 10 — 10 — ns
rising edge of VWR
Write setup time to falling
tWSC tC – 80 — tC – 115 — ns
edge of VCE
VWR
Write hold time from fall-
t WHC 2tC – 20 — 2tC – 20 — ns
ing edge of VCE
Data input setup time to
tDSC tC – 85 — tC – 125 — ns
falling edge of VCE
VD0 to Data input hold time
t DHC 2tC – 30 — 2tC – 30 — ns
VD7 from falling edge of VCE
Data hold time from
tDH2 5 50 5 50 ns
rising edge of VWR
Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read
from the memory is placed on the bus.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 69
4.0 Specifications 4.5.4.2
4.5.4.2 SED1336F
Ta = –20 to 75°C
VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V
Signal Symbol Parameter Unit Condition
min max min max
EXT φ0 tC Clock period 100 — 125 — ns
VCE HIGH-level pulse-
tW tC – 50 — tC – 50 — ns
width
VCE
VCE LOW-level pulse-
tCE 2tC – 30 — 2tC – 30 — ns
width
tCYW Write cycle time 3tC — 3t C — ns
Address hold time from
tAHC 2tC – 30 — 2tC – 40 — ns
falling edge of VCE
Address setup time to
tASC tC – 70 — tC – 100 — ns
falling edge of VCE
VA0 to
Address hold time from
VA15 tCA 0 — 0 — ns CL = 100
rising edge of VCE
Address setup time to pF
tAS 0 — 0 — ns
falling edge of VWR
Address hold time from
tAH2 10 — 10 — ns
rising edge of VWR
Write setup time to falling
tWSC tC – 80 — tC – 110 — ns
edge of VCE
VWR
Write hold time from fall-
tWHC 2tC – 20 — 2tC – 20 — ns
ing edge of VCE
Data input setup time to
tDSC tC – 85 — tC – 120 — ns
falling edge of VCE
VD0 to Data input hold time
tDHC 2tC – 30 — 2tC – 30 — ns
VD7 from falling edge of VCE
Data hold time from
tDH2 5 50 5 50 ns
rising edge of VWR
Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read
from the memory is placed on the bus.

70 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.5.5 – 4.5.5.2 4.0 Specifications
4.5.5 SLEEP IN Command Timing

VCE SLEEP IN write SYSTEM SET write

tWRL tWRD

WR
(command input)

YDIS

Figure 43. SLEEP IN command timing

4.5.5.1 SED1335F
Ta = –20 to 75°C
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal Symbol Parameter Unit Condition
min max min max
VCE falling-edge delay
t WRD See note 1 — See note 1 — ns
time CL = 100
WR
YDIS falling-edge delay pF
tWRL — See note 2 — See note 2 ns
time
Notes:
1. tWRD = 18tC + tOSS + 40 (tOSS is the time delay from the sleep state until stable operation)
2. tWRL = 36tC × [TC/R] × [L/F] + 70

4.5.5.2 SED1336F
Ta = –20 to 75°C
VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V
Signal Symbol Parameter Unit Condition
min max min max
VCE falling-edge delay
t WRD See note 1 — See note 1 — ns
time CL = 100
WR
YDIS falling-edge delay pF
tWRL — See note 2 — See note 2 ns
time
Notes:
1. tWRD = 18tC + tOSS + 40 (tOSS is the time delay from the sleep state until stable operation)
2. tWRL = 36tC × [TC/R] × [L/F] + 70

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 71
4.0 Specifications 4.5.6 – 4.5.6.2
4.5.6 External Oscillator Signal Timing

tRCL tFCL

EXTφ0

tWL tWH
tCL

Figure 44. External oscillator signal timing

4.5.6.1 SED1335F
Ta = –20 to 75°C
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal Symbol Parameter Unit Condition
min max min max
tRCL External clock rise time — 15 — 15 ns
tFCL External clock fall time — 15 — 15 ns
External clock
EXT φ0 tWH
HIGH-level pulsewidth
See note 1 See note 2 See note 1 See note 2 ns

External clock
tWL See note 1 See note 2 See note 1 See note 2 ns
LOW-level pulsewidth
tC External clock period 100 — 125 — ns
Notes:
1. 475
(tC – tRCL – tFCL) × < tWH, tWL
1000
2. 525
(tC – tRCL – tFCL) × > tWH, tWL
1000

4.5.6.2 SED1336F
Ta = –20 to 75°C
VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V
Signal Symbol Parameter Unit Condition
min max min max
tRCL External clock rise time — 15 — 15 ns
tFCL External clock fall time — 15 — 15 ns
External clock
EXT φ0 tWH
HIGH-level pulsewidth
See note 1 See note 2 See note 1 See note 2 ns

External clock
tWL See note 1 See note 2 See note 1 See note 2 ns
LOW-level pulsewidth
tC External clock period 100 — 125 — ns
Notes:
1. 475
(tC – tRCL – tFCL) × < tWH, tWL
1000
2. 525
(tC – tRCL – tFCL) × > tWH, tWL
1000

72 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.5.7 4.0 Specifications
4.5.7 LCD Output Timing

The following characteristics are for a 1/64 duty cycle.

ROW 62 63 64 1 2 3 4 60 61 62 63 64

LP

1 frame period
YD

WF

YSCL

WF
1 line period

YSCL ROW64 ROW1 ROW2

LP

XSCL

XD0~XD3

XECL

tr tWX tf tCX

XSCL
tDS tDH

XD0~XD3
tWL

LP tL2
tL1
tS2 tS1

XECL
tWXE
tDf

WF(B)
tLD

YD
tDHY

tWY
YSCL

Figure 45. LCD output timing

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 73
4.0 Specifications 4.5.7
4.5.7.1 SED1330F
Ta = –20 to 75°C
Rating
Signal Symbol Parameter Unit Condition
min max
tr VCE high level pulse width — 35 ns
tf VCE low level pulse width — 35 ns
tCX Shift clock cycle time 4tc–70 — ns
XSCL
tWX XSCL clock pulse width 2t C–80 — ns
XD0 tDH X-data hold time 2t C–100 — ns VDD = 5.0V
to XD3 tDS X-data setup time 2t C–100 — ns ±10%
tLS Latch data setup time 2tC–100 — ns CL=150F
LP
tWL LP signal pulse width 4t C–80 — ns
tL1 XECL setup time 3tC–100 — ns
tL2 XECL data hold time tC–30 — ns
XECL tS1 Enable setup time tC–30 — ns
tS1 Enable delay time tC–30 — ns
tWXE XECL clock pulse width 3t C–80 — ns
WF tDF Time allowance of WF delay — 100 ns
tLD LP delay time against YSCL 4tC–100 — ns
YSCL
tWY YSCL clock pulse width 4t C–80 — ns
YD tDHY Y-data hold time 6t C–100 — ns

Notes:
1. The E-1330 reads display memory data from the address of the top left corner of the display screen, then scans horizontally until
it reaches the address for the bottom right corner of the display screen. Therefore, each line of X-driver data is sent starting from
the left side of the display line.
2. The E-1330 uses nine cycles of ø0 as the basic cycle (tc). The XSCL waveform is shown in the following figure.

ø0

4 tC 5 tC

XSCL

74 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
4.5.7.2 – 4.5.7.3 4.0 Specifications
4.5.7.2 SED1335F
Ta = –20 to 75°C
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal Symbol Parameter Unit Condition
min max min max
tr Rise time — 30 — 40 ns
tf Fall time — 30 — 40 ns
t CX Shift clock cycle time 4tC — 4t C — ns
XSCL
t WX XSCL clock pulsewidth 2tC – 60 — 2tC – 60 — ns
XD0 to tDH X data hold time 2tC – 50 — 2tC – 50 — ns CL =
XD3 t DS X data setup time 2tC – 100 — 2tC – 105 — ns 100 pF
tLS Latch data setup time 2tC – 50 — 2tC – 50 — ns
LP t WL LP pulsewidth 4tC – 80 — 4tC – 120 — ns
t LD LP delay time from XSCL 0 — 0 — ns
WF tDF Permitted WF delay — 50 — 50 ns
YD tDHY Y data hold time 2tC – 20 — 2tC – 20 — ns

4.5.7.3 SED1336F
Ta = –20 to 75°C
VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V
Signal Symbol Parameter Unit Condition
min max min max
tr Rise time — 30 — 35 ns
tf Fall time — 30 — 35 ns
t CX Shift clock cycle time 4tC — 4t C — ns
XSCL
t WX XSCL clock pulsewidth 2tC – 60 — 2tC – 60 — ns
XD0 to tDH X data hold time 2tC – 50 — 2tC – 50 — ns CL =
XD3 t DS X data setup time 2tC – 100 — 2tC – 100 — ns 100 pF
tLS Latch data setup time 2tC – 50 — 2tC – 50 — ns
LP t WL LP pulsewidth 4tC – 80 — 4tC – 100 — ns
t LD LP delay time from XSCL 0 — 0 — ns
WF tDF Permitted WF delay — 50 — 50 ns
YD tDHY Y data hold time 2tC – 20 — 2tC – 20 — ns
Note: The SED1335F/1336F reads display memory data from the address of the top left corner of the display screen, then scans
horizontally until it reaches the address for the bottom right corner of the display screen. Therefore, each line of X-driver data
is sent starting from the left side of the display line.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 75
 THIS PAGE INTENTIONALLY BLANK

76 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
 5.0
Display Control Functions

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 77
 THIS PAGE INTENTIONALLY BLANK

78 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
5.0 – 5.1 5.0 Display Control Functions
5.0 Display Control Functions

5.1 Character Configuration

The origin of each character bitmap is in the top left If the area outside the character bitmap contains only
corner as shown in Figure 38. Adjacent bits in each zeros, the displayed character size can easily be
byte are horizontally adjacent in the corresponding increased by increasing FX and FY, as the zeros
character image. ensure that the extra space between displayed char-
acters is blank.
Although the size of the bitmap is fixed by the charac-
ter generator, the actual displayed size of the charac- The displayed character width can be set to any value
ter field can be varied in both dimensions. up to 16 even if each horizontal row of the bitmap is
two bytes wide.

Character starting point

FX D7 to D0

R0 0 1 1 1 0 0 0 0

R1 1 0 0 0 1 0 0 0

R2 1 0 0 0 1 0 0 0

R3 1 0 0 0 1 0 0 0
Character
height R4 1 1 1 1 1 0 0 0

R5 1 0 0 0 1 0 0 0

R6 1 0 0 0 1 0 0 0

R7 0 0 0 0 0 0 0 0
FY
R8 0 0 0 0 0 0 0 0

R9 0 0 0 0 0 0 0 0

R10 0 0 0 0 0 0 0 0

R11 0 0 0 0 0 0 0 0 Space
Space
data
R12 0 0 0 0 0 0 0 0

R13 0 0 0 0 0 0 0 0

R14 0 0 0 0 0 0 0 0

R15 0 0 0 0 0 0 0 0
Space
Character width Space
data

Figure 46. Example of character display ([FX] ≤ 8) and generator bitmap

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 79
5.0 Display Control Functions 5.1

Horizontal
FX non-display
area

Character
Height

FY

16 dots
Space

Vertical
non-display
area

8 dots 8 dots

Character width Space

Note: The SED1330F/1335F/1336F does not automatically insert spaces between characters. If the displayed character size is
8 pixels or less and the space between character origins is nine pixels or more, the bitmap must use two bytes per row,
even though the character image requires only one.

Figure 47. Character width greater than one byte wide ([FX] = 9)

80 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
5.2 – 5.2.2 5.0 Display Control Functions
5.2 Screen Configuration

5.2.1 Screen Configuration

The basic screen configuration of the SED1330F/ Figure 40 shows the relationship between the virtual
1335F/1336F is as a single text screen or as overlap- screens and the physical screen.
ping text and graphics screens. The graphics screen
uses eight times as much display memory as the text
screen.

A/P
C/R
0000H

Character
memory area
0800H

07FFH
Graphics
memory area

Display 47FFH
memory
window (0,YM)
(XW,YM)

Y (XM,YM)

(0,0)

(XM,0)

Figure 48. Virtual and physical screen relationship

5.2.2 Display Address Scanning

The SED1330F/1335F/1336F scans the display memory In text mode, the address counter is set to the same
in the same way as a raster scan CRT screen. Each row start address, and the same character data is read, for
is scanned from left to right until the address range each row in the character bitmap. However, a new row
equals C/R. Rows are scanned from top to bottom. of the character generator output is used each time.
Once all the rows in the character bitmap have been
In graphics mode, at the start of each line, the address displayed, the address counter is set to the start
counter is set to the address at the start of the previous address plus AP and the next line of text is displayed.
line plus the address pitch, AP.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 81
5.0 Display Control Functions 5.2.2

1
• SAD SAD + 1 SAD + 2 SAD + C/R
•
•
8
9
• SAD + AP SAD + AP SAD + AP SAD + AP
• +1 +2 + C/R
•
16
17 SAD + 2AP
•
•
•
24
•
•
•
•

C/R
W/S = 0, FX = 8, FY = 8

Note: One byte of display memory corresponds to one character.

Figure 49. Character position parameters

1 SAD SAD +1 SAD + 2 SAD + C/R

2 SAD + AP SAD + AP SAD + AP SAD + AP

SAD
+1 +2 + C/R
SAD +1
3 SAD + 2AP SAD + 2
Line 1
• AP
•
• SAD + C/R
•
•
• SAD + AP
• SAD + AP + 1
• Line 2
AP

SAD + AP + C/R

SAD + 2AP
Line 3

C/R

W/S = 0, FX = 8

Note: One bit of display memory corresponds to one pixel.

Figure 50. Character parameters vs. memory

82 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
5.2.2 5.0 Display Control Functions

1
SAD1 SAD1 + 1 SAD1 + 2 SAD1 + C/R
•
•
•
8
9 SAD1 + AP SAD1 + AP SAD1 + AP SAD1 + AP
+1 +2 + C/R
•
•
•
16
17
SAD1 + 2AP
•
•
•

24
25
•
•

•
(L/F)/2 = β
β+1 SAD3 + 1 SAD3 + 2 SAD3 + C/R
•
•
•
β+8
β+9 SAD3 + AP SAD3 + AP SAD3 + AP SAD3 + AP
+1 +2 + C/R
•
•
•
β + 16
β + 17 SAD3 + 2AP
•
•
•
β + 24
β + 25
•
•
•
•

(L/F)

C/R
W/S = 1, FX = 8, FY = 8

Note: In two-panel drive, the SED1330F/1335F/1336F reads line 1 and line β + 1 as one cycle. The upper and lower panels are
thus read alternately, one line at a time.

Figure 51. Two-panel display address indexing

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 83
5.0 Display Control Functions 5.2.3
5.2.3 Display Scan Timing

Figure 44 shows the basic timing of the SED1330F/ cycles, though the LCD drive signals are still gener-
1335F/1336F. One display memory read cycle takes ated. TC/R may be set to any value within the con-
nine periods of the system clock, φ0 (f OSC). This cycle straints imposed by C/R, fOSC, fFR, and the size of the
repeats (C/R + 1) times per display line. LCD panel, and it may be used to fine tune the frame
frequency. The microprocessor may also use this
When reading, the display memory pauses at the end pause to access the display memory data.
of each line for (TC/R – C/R) display memory read

φ0
T0 T1 T2
Display read cycle interval

VCE
Graphics generator
Character read interval Graphics read interval read interval
VA

Figure 52. Display memory basic read cycle

Display period Divider frequency

period
TC/R
C/R

Line 1 O R

2 O R

3 O R
Frame
period •
•
•
•
•
(L/F) O R

LP

Note: The divider adjustment interval (R) applies to both the upper and lower screens even if W/S = 1. In this case, LP is active
only at the end of the lower screen’s display interval.

Figure 53. Relationship between TC/R and C/R

84 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
5.3 – 5.3.3 5.0 Display Control Functions
5.3 Cursor Control

5.3.1 Cursor Register Function the cursor layer moved within the display memory if it
is necessary to display the cursor on a layer other than
The SED1330F/1335F/1336F cursor address regis- the present cursor layer.
ter functions as both the displayed cursor position
address register and the display memory access Although the cursor is normally displayed for charac-
address register. When accessing display memory ter data, the SED1330F/1335F/1336F may also dis-
outside the actual screen memory, the address regis- play a dummy cursor for graphical characters. This is
ter must be saved before accessing the memory and only possible if the graphics screen is displayed, the
restored after memory access is complete. text screen is turned off and the microprocessor
generates the cursor control address.

Cursor display
address register
Cursor register D=1

Address pointer

FC1 = 0
Figure 54. Cursor addressing Cursor ON
FC0 = 1

Note that the cursor may disappear from the display

if the cursor address remains outside the displayed
screen memory for more than a few hundred millisec- FP1 = 0
Block screen 1 (character
onds. FP0 = 0
screen) OFF

5.3.2 Cursor Movement FP3 = 0

Block screen 2 (graphics
On each memory access, the cursor address register screen) ON
FP2 = 1
changes by the amount previously specified with
CSRDIR, automatically moving the cursor to the de-
sired location.
Figure 55. Cursor display layers

5.3.3 Cursor Display Layers

Consider the example of displaying Chinese charac-
Although the SED1330F/1335F/1336F can display ters on a graphics screen. To write the display data,
up to three layers, the cursor is displayed in only one the cursor address is set to the second screen block,
of these layers: but the cursor is not displayed. To display the cursor,
the cursor address is set to an address within the
Two-layer configuration: First layer (L1) blank text screen block.
Three-layer configuration: Third layer (L3)
Since the automatic cursor increment is in address
units, not character units, the controlling microproces-
The cursor will not be displayed if it is moved outside sor must set the cursor address register when moving
the memory for its layer. Layers may be swapped or the cursor over the graphical characters.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 85
5.0 Display Control Functions 5.3.3

8 dots 8 dots 8 dots 8 dots

Block cursor

18 dots

Auto shift Auto shift

Auto shift

Cursor address preset

Figure 56. Cursor movement

If no text screen is displayed, only a bar cursor can be SED1330F/1335F/1336F automatically decides which
displayed at the cursor address. cursor shape to display. On the text screen it displays
a block cursor, and on the graphics screen, a bar
If the first layer is a mixed text and graphics screen cursor.
and the cursor shape is set to a block cursor, the

86 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
5.4 5.0 Display Control Functions
5.4 Memory to Display Relationship

The SED1330F/1335F/1336F supports virtual blocks, with each block able to display a different
screens that are larger than the physical size of the portion of the virtual screen.
LCD panel address range, C/R. A layer of the
SED1330F/1335F/1336F can be considered as a This enables, for example, one block to dynamically
window in the larger virtual screen held in display scroll through a data area while the other acts as a
memory. This window can be divided into two status message display area. See Figure 49 and 50.

AP
C/R
SAD1
W/S = 0 W/S = 1
Character page 1 SAD1
SAD3
Character page 3 SAD3 Display page 1
Display page 1 Display page 3
SAD2
Character page 2 SAD2 Layer 1
Layer 1 SAD4
Character page 2 SAD4 Display page 2
Display page 2 C/R Display page 4

Layer 2
Layer 2
CG RAM

SAD1 C/R
Character page 1
SAD1
Display page 1 C/R
SAD3
Display page 3 SAD3 Character page 3

Layer 1
SAD2 C/R
SAD2
Display page 2
Graphics page 2

Layer 2

C/R
SAD3
Graphics page 3

SAD3 C/R
SAD2 Display page 3 SAD2 Graphics page 2
SAD1 Display page 2
Display page 1
C/R
SAD1
Graphics page 1
Layer 1 Layer 2
Layer 3

Figure 57. Display layers of memory

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 87
5.0 Display Control Functions 5.4

AP
0000H

FX
SAD1

FY CRY

CSRA CRX
Display
L/F window

Virtual display
memory limit

CRX

FX = Horizontal character field ≤ 16 dots

FY = Vertical character field ≤ 16 dots
CRX = Horizontal cursor size ≤ 16 dots
CRY = Vertical cursor size ≤ 16 dots
C/R = Characters per row ≤ 240 bytes
L/F = Lines per frame ≤ 256 bytes
AP = Address pitch ≤ 64 Kbytes

FFFFH

Figure 58. Display window and memory

88 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
 5.4

D7 to D0 D7 to D0
SAD1
0000
A (Code) 0000
SL1 Page 1 ABC
Character B
code 0300
0400
C
Page 2
XY

0800 Display
SAD2 X
Page 1
SL2 Y 02FF
2000 α β
2800 α 0080
Back layer
β (MSB) (LSB)(MSB) (LSB)
D7 D0 D7 D0
Page 2
γ

4440
SAG
4800
χ 1FFF
Character generator
RAM
4A00
HEX D7 D0
Not used

F000 70 01110000 #4800

88 10001000 1
88 10001000 2

Figure 59. Memory map and magnified characters

Character generator Magnified image
88 10001000 3
ROM
F8 11111000 4
88 10001000 5
88 10001000 6
00 00000000 #4807

Example of character A

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238
89
5.0 Display Control Functions
5.0 Display Control Functions 5.5 – 5.5.1
5.5 Scrolling 5.5.1 On-page Scrolling

The controlling microprocessor can set the SED1330F/ The normal method of scrolling within a page is to
1335F/1336F scrolling modes by overwriting the scroll move the whole display up one line and erase the
address registers SAD1 to SAD4, and by directly bottom line. Since the SED1330F/1335F/1336F does
setting the scrolling mode and scrolling rate. not automatically erase the bottom line, it must be
erased with blanking data when changing the scroll
address register.

Display memory

AP

C/R

ABC SAD1 ABC

Before scrolling
WXYZ 789 WXYZ 789

SAD3 Blank

After scrolling WXYZ 789

SAD1

WXYZ 789

Blank

Figure 60. On-page scrolling

90 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
5.5.2 5.0 Display Control Functions
5.5.2 Inter-page Scrolling

Scrolling between pages and page switching can be

performed only if the display memory capacity is
greater than one screen.

Display memory
AP
C/R

ABC SAD1 ABC

Before scrolling
WXYZ 789 WXYZ 789

WXYZ 789 ABC

After scrolling SAD1

WXYZ 789

Figure 61. Inter-page scrolling

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 91
5.0 Display Control Functions 5.5.3
5.5.3 Horizontal Scrolling

The display can be scrolled horizontally in one-

character units, regardless of the display memory
capacity.

Display Display memory

ABC XYZ ABC XYZ

Before scrolling SAD1
123 123

AP
C/R

After scrolling BC XYZ1 ABC XYZ

SAD1
23 123

Figure 62. Horizontal wraparound scrolling

Refer to Section 9.4 for application notes.

92 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
5.5.4 – 5.5.5 5.0 Display Control Functions
5.5.4 Bidirectional Scrolling

Bidirectional scrolling can be performed only if the SCR command can be used to scroll horizontally in
display memory is larger than the physical screen pixel units. Single-pixel scrolling both horizontally and
both horizontally and vertically. Although scrolling is vertically can be performed by using the SCROLL and
normally done in single-character units, the HDOT HDOT SCR commands. See Section 9.4

Display memory

AP
BC
Before scrolling EFG
TUV A BC
12 EFG
TUV

12 34
567
C/R 89

ABC
E FG
FG TUV
After scrolling TUV

1234
56
1234
56 7
89

Figure 63. Bidirectional scrolling

5.5.5 Scroll Units

Table 21. Scroll units

Mode Vertical Horizontal

Pixels or
Text Characters
characters
Graphics Pixels Pixels
Note that in a divided screen, each block cannot be indepen-
dently scrolled horizontally in pixel units.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 93
 THIS PAGE INTENTIONALLY BLANK

94 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
 6.0
Character Generator

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 95
 THIS PAGE INTENTIONALLY BLANK

96 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
6.0 – 6.1.3 6.0 Character Generator
6.0 Character Generator

6.1 CG Characteristics

6.1.1 Internal Character Generator • Mapped into the display memory address space
at F000H to F7FFH (M2 = 0) or F000H to
The internal character generator is recommended for FFFFH (M2 = 1)
minimum system configurations containing a • Characters can be up to 8 × 16-pixels; how-
SEDSED1330F/1335F/1336F, display RAM, LCD ever, excess bits must be set to zero.
panel, single-chip microprocessor and power supply.
Since the internal character generator uses a CMOS
mask ROM, it is also recommended for low-power
applications.
6.1.3 Character Generator RAM
• 5 × 7-pixel font (See Section 10)
The user can freely use the character generator RAM
• 160 JIS standard characters
for storing graphics characters. The character gen-
• Can be mixed with character generator RAM erator RAM can be mapped by the microprocessor
(maximum of 64 CG RAM characters) anywhere in display memory, allowing effective use of
• Can be automatically spaced out up to 8 × 16 unused address space.
pixels
• Up to 8 × 8-pixel characters (M2 = 0) or 8 × 16
characters (M2 = 1)
• Up to 256 characters if mapped at F000H to
6.1.2 External Character Generator ROM FFFFH (64 if used together with character
generator ROM)
The external CG ROM can be used when fonts other • Can be mapped anywhere in display memory
than those in the internal ROM are needed. Data is address space if used with the character gen-
stored in the external ROM in the same format used erator ROM
in the internal ROM. (See Section 6.3.) • Mapped into the display memory address space
at F000H to F7FFH if not used with the charac-
• Up to 8 × 8-pixel characters (M2 = 0) or 8 × 16-
ter generator ROM (more than 64 characters
pixel characters (M2 = 1)
are in the CG RAM). Set SAG0 to F000H and
• Up to 256 characters (192 if used together with M1 to zero when defining characters number
the internal ROM) 193 upwards.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 97
6.0 Character Generator 6.2
6.2 CG Memory Allocation

Since the SED1335F/1336F uses 8-bit character required, character generator memory can be bank-
codes, it can handle no more than 256 characters at switched using the CGRAM ADR command.
a time. However, if a wider range of characters is

Built–in CG ROM
(160 characters,
5 × 7 pixels max.) CG RAM n
CG RAM 2

CG RAM SAG CG RAM 1

M0 = 1
(64 characters max, 8 × 16 pixels max)

Basic CG space
(256 characters,
8 × 16 pixels max.) 256 characters max.
CG RAM M1 = 0

CG ROM
M0 = 1 256 characters max.
Built-in CG ROM
(160 characters, M1 = 0
5 × 7 pixels max.)
CG RAM n
CG RAM 2
CG RAM
CG ROM CG RAM 1
ADR
(64 characters max, 8 × 16 pixels max)

Note that there can be no more than 64 characters per bank.

Figure 64. Internal and external character mapping

98 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
6.2 – 6.3 6.0 Character Generator
Table 22. Character mapping
Item Parameter Remarks
Internal/external character generator selection M0
1 to 8 pixels M2 = 0
Character field height 9 to 16 pixels M2 = 1
Greater than 16 pixels Graphics mode (8 bits × 1 line)
Internal CG ROM/RAM select Determined by the
Automatic
External CG ROM/RAM select character code
CG RAM bit 6 correction M1
Specified with CG RAM ADR Can be moved anywhere in the
CG RAM data storage address
command display memory address space
192 characters or less Other than the area of Figure 58
External CG ROM
address Set SAG to F000H and overly
More than 192 characters
SAG and the CG ROM table.

6.3 Setting the Character Generator Address

The CG RAM addresses in the VRAM address space address calculated from SAG + character code +
are not mapped directly from the address in the SAG ROW select address. This mapping is shown in Tables
register. The data to be displayed is at a CG RAM 23 and 24.

Table 23. Character fonts, number of lines ≤ 8 (M2 = 0, M1 = 0)

SAG A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Character code 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0
+ROW select address 0 0 0 0 0 0 0 0 0 0 0 0 0 R2 R1 R0
CG RAM address VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0

Table 24. Character fonts, 9 ≤ number of lines ≤ 16 (M2 = 1, M1 = 0)

SAG A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Character code 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0
+ROW select address 0 0 0 0 0 0 0 0 0 0 0 0 R3 R2 R1 R0
CG RAM address VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 99
6.0 Character Generator 6.3 – 6.3.2
As the character code table in Figure 58 shows, codes
80H to 9FH and E0H to FFH are allocated to the CG
Row R3 R2 R1 R0 RAM and can be used as desired. 80H is thus the first
Row 0 0 0 0 0
code for CG RAM. As characters cannot be used if
only using graphics mode, there is no need to set the
Row 1 0 0 0 1 CG RAM data.
Row 2 0 0 1 0
Line 1 Table 25. Character data example

CGRAM ADR 5CH Reverse the CG RAM ad-

Line 2
Row 7 0 1 1 1 P1 00H dress calculation to cal-
P2 40H culate SAG
Row 8 1 0 0 0
Set cursor shift direction
CSRDIR 4CH
to right
CSRW 46H
Row 14 1 1 1 0 CG RAM start address is
P1 00H
4800H
Row 15 1 1 1 1 P2 48H
MWRITE 42H
Note: Lines = 1: lines in the character bitmap ≤ 8 P 70H Write ROW 0 data
Lines = 2: lines in the character bitmap ≥ 9 P2 88H Write ROW 1 data
P3 88H Write ROW 2 data
Figure 65. Row select address P4 88H Write ROW 3 data
P5 F8H Write ROW 4 data
P6 88H Write ROW 5 data
6.3.1 M1 = 1 P7 88H Write ROW 6 data
P8 00H Write ROW 7 data
The SED1335F/1336F automatically converts all bits P8 00H Write ROW 8 data
set in bit 6 of character code for CG RAM 2 to zero.
Because of this, the CG RAM data areas become ↓ ↓ ↓
contiguous in display memory. P16 00H Write ROW 15 data

When writing data to CG RAM:

• Calculate the address as for M1 = 0.

• Change bit 6 of the character code from “1” to
“0”.

6.3.2 CG RAM Addressing Example

• Define a pattern for the “A” in Figure 38.

• The CG RAM table start address is 4800H.
• The character code for the defined pattern is
80H (the first character code in the CG RAM
area).

100 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
6.4 6.0 Character Generator
6.4 Character Codes

The following figure shows the character codes and

the codes allocated to CG RAM. All codes can be
used by the CG RAM if not using the internal ROM.

Upper 4 bits
Lower 4 bits 0 1 2 3 4 5 6 7 8 8 A B C D E F
0 0 @ P ' p
1 ! 1 A Q a q
2 " 2 B R b r
3 # 3 C S c s
4 $ 4 D T d t
5 % 5 E U e u
6 & 6 F V f v
7 ' 7 G W g w
8 ( 8 H X h x
9 ) 9 I Y i y
A * : J Z j z
B + ; K [ k {
C , < L ¥ l |
D . + M ] m }
E - \> N ^ n →
F / ? O _ o ←

Figure 66. On-chip character codes

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 101
 THIS PAGE INTENTIONALLY BLANK

102 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
 7.0
TV Mode
(SED1336F only)

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 103
 THIS PAGE INTENTIONALLY BLANK

104 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
7.0 – 7.1 7.0 TV Mode (SED1336F only)
7.0 TV Mode (SED1336F only)

When used with an external video mixer circuit, the The TV and LCD display register parameters which
SED1336F can show the same display on a television are determined by hardware constraints are shown in
as on the LCD panel. In addition, the changeover from Table 26.
LCD-only to TV-and-LCD display is instantaneous
with the changing of the T/L register using the System
Set instruction.

Table 26. Register parameters

Clock Cycles Oscillator

System TC/R (Hex) C/R (Hex) L/F (Hex) per Frequency, T/L
Horizontal Line fO (MHz)
NTSC 2A 1F C7 388 6.1050 1
PAL 2A 1F C7 388 6.0625 1
6.0625 or
LCD ≥ 2A 1F C7 ≥ 388 0
6.1050

7.1 Sync Generator Circuit Timing

The NTSC and PAL vertical sync signal waveforms vertical sync timing parameters and VSD output states
are shown in Figure 59 and 60, respectively. The are shown in Table 27.

21H Color field I vertical blanking interval 21H

1.5 ± 0.1µs TI
3H 3H 3H 11H
1 2 3 4 5 6 7 8 9 10 19 20

Pre-blanking Start of
H H H H
interval field I Equalizing Vertical serration 0.5H
Horizontal pulse interval pulse interval
sync interval
Reference Post-
Display Interval before Vertical Sync Interval after Display
subcarrier phase blanking
interval equalizing pulses pulse interval equalizing pulses color field I interval interval

9-line vertical interval

Figure 67. NTSC vertical sync waveform

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 105
7.0 TV Mode (SED1336 only) 7.1

Field blanking (25H + a) (a = 11-line blanking interval)

42H 2.5H 2.5H 2.5H 17.5H 45H

311 312 313 314 315 316 317 318 319 320 335

Reference Post-
Display Pre-blanking Interval before Vertical sync Interval after subcarrier phase blanking Display
period interval equalizing pulses pulse interval equalizing pulses interval
color field I interval

Figure 68. PAL vertical sync waveform

Table 27. Vertical sync timing characteristics

Interval Interval Reference Vertical
Pre- Vertical Post- Equalizing
before after Subcarrier Display Serration
Parameter blanking Sync Pulse blanking Pulse
Equalizing Equalizing Phase Color Interval Pulse
Interval Interval Interval Interval
Pulse Pulse Field I Interval
NTSC
system 21H 3H 3H 3H 11H 21H 200H 15CK 27CK
timing
PAL
system 42H 2.5H 2.5H 2.5H 17.5H 45H 200H 15CK 27CK
timing
VSD LOW or
High High
output LOW LOW LOW LOW high — —
impedance impedance
level impedance
Notes:
1. The NTSC system uses 262 lines per screen, and the PAL system, 312.
2. H = Horizontal line period
CK = Oscillator period

106 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
7.1 7.0 TV Mode (SED1336 only)
The horizontal sync signal waveforms are shown in states, in Table 28. Note that SNC and VSD are both
Figure 61, and the timing parameters and VSD output high-impedance when in LCD mode.

SNC High High

impedance impedance

VSD High Low or high

impedance impedance

Pre- Horizontal Post-

Display Display
blanking sync Back porch blanking
interval Front interval
interval pulse interval
porch

Figure 69. Horizontal sync waveforms

Table 28. Horizontal sync characteristics

Pre-blanking Horizontal Post-blanking Display

Parameter Front Porch Back Porch
Interval Sync Pulse Interval Interval
NTSC
29CK 10CK 29CK 28CK 36CK 256CK
system timing
PAL
29CK 10CK 29CK 34CK 30CK 256CK
system timing
VSD High High LOW or High
LOW LOW LOW
output level impedance impedance impedance

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 107
 THIS PAGE INTENTIONALLY BLANK

108 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
 8.0
Description of Circuit Blocks

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 109
 THIS PAGE INTENTIONALLY BLANK

110 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
8.0 – 8.1.2.3 8.0 Description of Circuit Blocks
8.0 Description of Circuit Blocks

8.1 Microprocessor Interface

8.1.1 System Bus Interface 8.1.2 Microprocessor Synchronization

SEL1, SEL2 (SED1330F and SED1335F only), A0, The SED1330F/1335F/1336F interface operates at
RD, WR and CS are used as control signals for the full bus speed, completing the execution of each
microprocessor data bus. A0 is normally connected to command within the cycle time, tCYC. The controlling
the lowest bit of the system address bus. SEL1 and micro-processor’s performance is thus not hampered
SEL2 change the operation of the RD and WR pins to by polling or handshaking when accessing the
enable interfacing to either an 8080 or 6800 family SED1330F/1335F/1336F.
bus, and should have either a pull-up or a pull-down
resistor. Display flicker may occur if there is more than one
consecutive access that cannot be ignored within a
With microprocessors using an 8080 family interface, frame. The microprocessor can minimize this either
the SED1330F/1335F/1336F is normally mapped into by performing these accesses intermittently, or by
the I/O address space. continuously checking the status flag (D6) and waiting
for it to become HIGH.
8.1.1.1 8080 series

Table 29. 8080 series interface signals 8.1.2.1 Display Status Indication Output
A0 RD WR Function (For SED1336 only)
0 0 1 Status flag read When CS, A0 and RD are LOW, D6 functions as the
Display data and cursor address display status indication output. It is HIGH during the
1 0 1
read TV-mode vertical retrace period or the LCD-mode
0 1 0 Display data and parameter write horizontal retrace period, and LOW, during the period
the controller is writing to the display. By monitoring
1 1 0 Command write
D6 and writing to the data memory only during retrace
periods, the display can be updated without causing
screen flicker.
8.1.1.2 6800 series

Table 30. 6800 series interface signals 8.1.2.2 Internal Register Access
A0 RD WR Function
The SYSTEM SET and SLEEP IN commands can be
0 1 1 Status flag read used to perform input/output to the SED1330F/1335F/
Display data and cursor address 1336F independently of the system clock frequency.
1 1 1
read These are the only commands that can be used while
0 0 1 Display data and parameter write the SED1330F/1335F/1336F is in sleep mode.
1 0 1 Command write
8.1.2.3 Display Memory Access

The SED1330F/1335F/1336F supports a form of

pipelined processing, in which the microprocessor

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 111
8.0 Description of Circuit Blocks 8.1.2.3
synchronizes its processing to the SED1330F/1335F/ When reading, the microprocessor first issues the
1336F’s timing. When writing, the microprocessor MREAD command, which causes the SED1330F/
first issues the MWRITE command. It then repeatedly 1335F/1336F to load the first read data into its output
writes display data to the SED1336F using the sys- buffer. The microprocessor then reads data from the
tem bus timing. This ensures that the microprocessor SED1330F/1335F/1336F using the system bus tim-
is not slowed down even if the display memory ing. With each read, the SED1330F/1335F/1336F
access times are slower than the system bus access reads the next data item from the display memory
times. See Figure 70. ready for the next read access. See Figure 71.

tCYC

WR

Microprocessor Command write Data write Data write

D0 to D7

WR/W

Display memory

VD0 to VD7

Figure 70. Display memory write cycle

WR

tCYC
Command write

Microprocessor RD

Data read Data read

D0 to D7

WR/W

Display memory

VD0 to VD7

Figure 71. Display memory read cycle

Note: A possible problem with the display memory read cycle is that the system bus access time, tACC, does not depend on the display
memory access time, tACV. The microprocessor may only make repeated reads if the read loop time exceeds the SED1330F/
1335F/1336F cycle time, tCYC. If it does not, NOP instructions may be inserted in the program loop. tACC, tACV and tCYC limits
are given in Section 4.3.

112 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
8.1.3 – 8.1.3.1 8.0 Description of Circuit Blocks
8.1.3 Interface Examples

8.1.3.1 Z80® to SED1330F/1335F/1336F Interface

IORQ
A0 A0

A1
to Decoder CS
A15

SED1335F/
Z80® D0 D0
to to 1336F
D7 D7

RD RD SEL 1
WR WR SEL 2
RESET RES

RESET

Note: Z80® is a registered trademark of Zilog Corporation.

Figure 72. Z80® to SED1330F/1335F/1336F* interface

Note: *For SED1336F: SEL 2 is open..

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 113
8.0 Description of Circuit Blocks 8.1.3.2
8.1.3.2 6802 to SED1330F/1335F/1336F Interface

VMA
A0 A0

A1
to Decoder CS
A15
SED1335F/
6802
D0 D0 1336F
to to VDD
D7 D7

E RD SEL 1
R/W WR SEL 2
RESET RES

RESET

Figure 73. 6802 to SED1330F/1335F/1336F interface

Note: *For SED1336F: SEL 2 is open..

114 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
8.2 – 8.2.2 8.0 Description of Circuit Blocks
8.2 Display Memory Interface

8.2.1 Static RAM

The figure below shows the interface between an 8K Note that bus buffers are required if the bus is heavily
× 8 static RAM and the SED1330F/1335F/1336F. loaded.

VA0 to VA12 A0 to A12

HC138
A
VA13 to VA15 to Y CE1
C VDD
VCE
CE2
SED1335F/ 6264 SRAM
1336F
OE

VR/W R/W
I/O1 to I/O8 I/O1 to I/O8

Figure 74. Static RAM interface

8.2.2 Supply Current during Display Memory Access

The 24 address and data lines of the SED1330F/ If VOPR = 5.0V, f = 1.0 MHz, and the display memory
1335F/1336F cycle at one-third of the oscillator fre- bus capacitance is 1.0 pF per line:
quency, fOSC. The charge and discharge current on
these pins, IVOP, is given by the equation below. IVOP ≤ 120 µA / MHz × pF
When IVOP exceeds I OPR, it can be estimated by:
To reduce current flow during display memory ac-
IVOP ∝ C V f cesses, it is important to use low-power memory, and
to minimize both the number of devices and the
where C is the capacitance of the display memory parasitic capacitance.
bus, V is the operating voltage, and f is the operating
frequency.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 115
8.0 Description of Circuit Blocks 8.3 – 8.4
8.3 Oscillator Circuit 8.4 Status Flag

The SED1330F/1335F/1336F incorporates an oscil- The SED1330F/1335F/1336F has a single bit status
lator circuit. A stable oscillator can be constructed flag.
simply by connecting an AT-cut crystal and two ca-
pacitors to OSC1 and OSC2, as shown in the figure D6: X line standby
below. If the oscillator frequency is increased, CD and
CG should be decreased proportionally. D7 D0

Note that the circuit board lines to OSC1 and OSC2 X D6 X X X X X X X: Don’t care
must be as short as possible to prevent wiring capaci-
tance from changing the oscillator frequency or in-
creasing the power consumption. Figure 76. Status flag

SED1335F/1336F The D6 status flag is LOW (0) for the TC/R - C/R cycles
at the end of each line where the SED1330F/1335F/
1336F is not reading the display memory. The micro-
processor may use this period to update display
memory without affecting the display; however, it is
OSC1 OSC2
CD = 3 to 20 pF
recommended that the display be turned off when
refreshing the whole display.
CG CD CG = 2 to 18 pF

Load impedance = 700 Ω (max)

Figure 75. Crystal oscillator

LP

tTC/R
tm tC/R

XSCL

Figure 77. C/R to TC/R time difference

116 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
8.4 – 8.5 8.0 Description of Circuit Blocks
8.5 Reset

The SED1330F requires a reset pulse at least 1 ms

long after power-on in order to re-initialize its internal
Read Status Flag state. The SED1335F/1336F requires a minimum
reset pulse of 200µs.

No During reset, the LCD drive signals XD, LP and FR are

D6 = 1? halted.

For maximum reliability, it is not recommended to

Yes
apply a DC voltage to the LCD panel while the
Data Input SED1330F/1335F/1336F is reset. Turn off the LCD
power supplies for at least one frame period after the
start of the reset pulse.
No
Data Input ? The SED1330F/1335F/1336F cannot receive com-
mands while it is reset. Commands to initialize the
internal registers should be issued soon after a reset.
Yes
A delay of 3 ms (maximum) is required following the
rising edges of both RES and VDD to allow for system
stabilization.
Figure 78. Flowchart for busy flag checking

VDD

200µs reset pulse

RES 0.7 VDD
0.3 VDD

Figure 79. Reset timing

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 117
 THIS PAGE INTENTIONALLY BLANK

118 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
 9.0
Application Notes

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 119
 THIS PAGE INTENTIONALLY BLANK

120 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
9.0 – 9.1.1 9.0 Application Notes
9.0 Application Notes

9.1 Initialization Parameters • TC/R

TC/R must satisfy the condition [TC/R] ≥ [C/R]
The parameters for the initialization commands must + 4.
be determined first. Square brackets around a param-
eter name indicate the number represented by the
parameter, rather than the value written to the param- • fOSC and fFR
eter register. For example, [FX] = FX + 1. Once TC/R has been set, the frame frequency,
fFR, and lines per frame [L/F] will also have
9.1.1 SYSTEM SET Instruction and Param- been set. The lower limit on the oscillator
eters frequency fOSC is given by:

• FX fOSC ≥ ([TC/R] × 9 + 1) × [L/F] × fFR

The horizontal character field size is deter-
mined from the horizontal display size in pixels • If no standard crystal close to the calculated
[VD] and the number of characters per line value of fOSC exists, a higher frequency crystal
[VC]. can be used and the value of TC/R revised
[VD] / [VC] ≤ [FX] using the above equation.
VD: # of X-directional dots
VC: # of X-directional characters • Symptoms of an incorrect TC/R setting are
listed below. If any of these appears, check the
• C/R value of TC/R and modify it if necessary.
C/R can be determined from VC and FX. • Vertical scanning halts and a high-con-
trast horizontal line appears.
[C/R] = RND([FX] / 8) × [VC]
• All pixels are on or off.
where RND(x) denotes x rounded up to the • The LP output signal is absent or cor-
next highest integer. [C/R] is the number of rupted.
bytes per line, not the number of characters.
• The display is unstable.

Table 31. Epson LCD unit example parameters (SED1335F only)

fOSC (MHz)
Resolution (X × Y) [FX] [FY] [C/R] TC/R
See Note 2
[FX] = 6 pixels: [C/R] = 42 = 2AH bytes:
8 or 16, depending
256 × 64 256 / 6 = 42 remainder 4 C/R = 29H. When using HDOT 2DH 1.85
on the screen
= 4 blank pixels SCR, [C/R] = 43 bytes
[FX] = 6 pixels: [C/R] = 85 = 55H bytes:
8 or 16, depending
512 × 64 512 / 6 = 85 remainder 2 C/R = 54H. When using HDOT 58H 3.59
on the screen
= 2 blank pixels SCR, [C/R] = 86 bytes
[FX] = 8 pixels: [C/R] = 32 = 20H bytes:
8 or 16, depending
256 × 128 256 / 8 = 32 remainder 0 C/R = 19H. When using HDOT 22H 2.90
on the screen
= no blank pixels SCR, [C/R] = 33 bytes
[FX] = 10 pixels: [C/R] = 102 = 66H bytes:
8 or 16, depending
512 × 128 512 / 10 = 51 remainder C/R = 65H. When using HDOT 69H 8.55
on the screen
2 = 2 blank pixels SCR, [C/R] = 103 bytes
Notes:
1. The remainder pixels on the right-hand side of the display are automatically blanked by the SED1335F. There is no need to
zero the display memory corresponding to these pixels.
2. Assuming a frame frequency of 60 Hz.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 121
9.0 Application Notes 9.1.2
9.1.2 Initialization Example

The initialization example shown in Figure 80 is for a sor interface bus display unit (512 × 128 pixels).
SED1330F/1335F/1336F with an 8-bit microproces-

Clear first
Start
memory layer

Clear second
Supply on
memory layer

SYSTEM SET CSRW

SCROLL CSR FORM

HDOT SCR DISP ON

Output display
OVLAY data

DISP OFF

Note: Set the cursor address to the start of each screen’s layer memory, and use MWRITE to fill the memory with space
characters, 20H (text screen only) or 00H (graphics screen only). Determining which memory to clear is explained in section
9.1.3.

Figure 80. Initialization procedure

122 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
9.1.2 9.0 Application Notes
Table 32. Initialization procedure

No. Command Operation

1 Power-up
2 Supply Wait for at least 3 ms after reset with VDD ≥ 4.5V
3 SYSTEM SET initialization.
C = 40H
P1 = 38H M0: Internal CG ROM
M1: CG RAM is 32 characters maximum
M2: 8 lines per character
W/S: Two-panel drive
IV: No top-line compensation
P2 = 87H FX: Horizontal character size = 8 pixels
WF: Two-frame AC drive
P3 = 07H FY: Vertical character size = 8 pixels
P4 = 3FH C/R: 64 display addresses per line
P5 = 49H TC/R: Total address range per line = 90
fOSC = 6.0 MHz, fFR = 70 Hz
P6 = 7FH L/F: 128 display lines
P7 = 80H AP: Virtual screen horizontal size is 128 addresses
P8 = 00H
4 SCROLL
C = 44H
P1 = 00H First screen block start address
P2 = 00H Set to 0000H
P3 = 40H Display lines in first screen block = 64
P4 = 00H Second screen block start address
P5 = 10H Set to 1000H
P6 = 40H Display lines in second screen block = 64
P7 = 00H Third screen block start address
P8 = 04H Set to 0400H
(continued)

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 123
9.0 Application Notes 9.1.2
Table 32. Initialization procedure (continued)

No. Command Operation

P9 = 00H Fourth screen block start address
P10 = 30H Set to 3000H

Display memory

(SAD1) 0000H 1st display memory page

(SAD3) 0400H
2nd display memory page
0800H
(SAD2) 1000H

3rd display memory page

(SAD4) 3000H

4th display memory page

5000H

5 HDOT SCR
C = 5AH
P1 = 00H Set horizontal pixel shift to zero
6 OVLAY
C = 5BH
P1 = 01H MX 1, MX 0: Inverse video superposition
DM 1: First screen block is text mode
DM 2: Third screen block is text mode
7 DISP ON/OFF
C = 58H D: Display OFF
P1 = 56H FC1, FC0: Flash cursor at 2 Hz
FP1, FP0: First screen block ON
FP3, FP2: Second and fourth screen blocks ON
FP5, FP4: Third screen block ON
8 Clear data in first layer Fill first screen layer memory with 20H (space character)
(continued)

124 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
9.1.2 9.0 Application Notes
Table 32. Initialization procedure (continued)

No. Command Operation

9 Clear data in second layer Fill second screen layer memory with 00H (blank data)

Display
Character code in every position

1st layer
Blank code in every position

2nd layer

10 CSRW
C = 46H
P1 = 00H Set cursor to start of first screen block
P2 = 00H
11 CSR FORM
C = 5DH
P1 = 04H CRX: Horizontal cursor size = 5 pixels
P2 = 86H CRY: Vertical cursor size = 7 pixels
CM: Block cursor
12 DISP ON/OFF
C = 59H Display ON

Display

13 CSR DIR
C = 4CH Set cursor shift direction to right
(continued)

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 125
9.0 Application Notes 9.1.2
Table 32. Initialization procedure (continued)

No. Command Operation

14 MWRITE
C = 42H
P1 = 20H ‘’
P2 = 45H ‘E’
P3 = 50H ‘P’
P4 = 53H ‘S’
P5 = 4FH ‘O’
P6 = 4EH ‘N’

EPSON

15 CSRW
C = 46H
P1 = 00H Set cursor to start of second screen block
P2 = 10H
16 CSR DIR
C = 4FH Set cursor shift direction to down
17 MWRITE
C = 42H
P1 = FFH Fill in a square to the left of the ‘E’
↓
P9 = FFH
EPSON

18 CSRW
C = 46H
P1 = 01H Set cursor address to 1001H
P2 = 10H
19 MWRITE
C = 42H
(continued)

126 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
9.1.2 9.0 Application Notes
Table 32. Initialization procedure (continued)

No. Command Operation

P1 = FFH Fill in the second screen block in the second column of line
1
↓
P9 = FFH
20 CSRW Repeat operations 18 and 19 to fill in the background under
‘EPSON’
↓
Inverse display
29 MWRITE
EPSON

30 CSRW
C = 46H
P1 = 00H Set cursor to line three of the first screen block
P2 = 01H
31 CSR DIR
C = 4CH Set cursor shift direction to right
32 MWRITE
C = 42H
P1 = 44H ‘D’
P2 = 6FH ‘o’
P3 = 74H ‘t’ Inverse display
P4 = 20H ‘’
P5 = 4DH ‘M’
P6 = 61H ‘a’ EPSON
P7 = 74H ‘t’
P8 = 72H ‘r’
P9 = 69H ‘i’ Dot matrix LCD
P10 = 78H ‘x’
P11 = 20H ‘’
P12 = 4CH ‘L’
P13 = 43H ‘C’
P14 = 44H ‘D’

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 127
9.0 Application Notes 9.1.3
9.1.3 Display Mode Setting Example 1: Combining Text and Graphics

• Conditions • Display memory allocation

• 320 × 200 pixels, single-panel drive (1/ • First layer (text): 320/8 = 40 characters
200 duty cycle) per line, 200/8 = 25 lines. Required
• First layer: text display memory size = 40 × 25 = 1000 bytes.
• Second layer: graphics display • Second layer (graphics): 320/8 = 40 char-
acters per line, 200/1 = 200 lines. Re-
• 8 × 8-pixel character font
quired memory size = 40 × 200 = 8000
• CG RAM not required bytes.

03E8H
2nd graphics layer
(8000 bytes)

0000H
1st character layer 2327H
(1000 bytes)

03E7H

Figure 81. Character over graphics layers

• Register setup procedure

SYSTEM SET TC/R calculation SCROLL
C= 40H C= 44H
P1 = 30H fOSC = 6 MHz P1 = 00H
P2 = 87H fFR = 70 Hz P2 = 00H
P3 = 07H P3 = C8H
P4 = 27H (1/6) × 9 × [TC/R] × 200 = 1/70 P4 = E8H
P5 = 2FH [TC/R] = 48, so TC/R = 2FH P5 = 03H
P6 = C7H P6 = C8H
P7 = 28H P7 = XH
P8 = 00H P8 = XH
P9 = XH
P10 = XH

128 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
9.1.3 – 9.1.4 9.0 Application Notes
CSR FORM OVLAY
C= 5DH C= 5BH
P1 = 04H P1 = 00H
P2 = 86H
DISP ON/OFF
HDOT SCR C= 59H
C= 5AH P1 = 16H
P1 = 00H

X = Don’t care

9.1.4 Display Mode Setting Example 2: Combining Graphics and Graphics

• Conditions • Display memory allocation

• 320 × 200 pixels, single-panel drive (1/ • First layer (graphics): 320/8 = 40 charac-
200 duty cycle) ters per line, 200/1 = 200 lines. Required
• First layer: graphics display memory size = 40 × 200 = 8000 bytes.
• Second layer: graphics display • Second layer (graphics): 320/8 = 40 char-
acters per line, 200/1 = 200 lines. Re-
quired memory size = 8000 bytes.

1F40H
2nd graphics layer
(8000 bytes)

0000H
1st graphics layer 3E7FH
(8000 bytes)

1F3FH

Figure 82. Two-layer graphics

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 129
9.0 Application Notes 9.1.4 –9.1.5
• Register setup procedure CSR FORM

SYSTEM SET TC/R calculation C= 5DH

C= 40H P1 = 07H
P1 = 30H fOSC = 6 MHz P2 = 87H
P2 = 87H fFR = 70 Hz
P3 = 07H HDOT SCR

P4 = 27H (1/6) × 9 × [TC/R] × 200 = 1/70 C= 5AH

P5 = 2FH [TC/R] = 48, so TC/R = 2FH P1 = 00H

P6 = C7H
P7 = 28H OVLAY

P8 = 00H C= 5BH
P1 = 0CH

SCROLL
C= 44H DISP ON/OFF
P1 = 00H C= 59H

P2 = 00H P1 = 16H

P3 = C8H
P4 = 40H X = Don’t care
P5 = 1FH
P6 = C8H
P7 = XH
P8 = XH
P9 = XH
P10 = XH

9.1.5 Display Mode Setting Example 3: Combining Three Graphics Layers

• Conditions • Display memory allocation

• 320 × 200 pixels, single-panel drive (1/ • All layers (graphics): 320/8 = 40 charac-
200 duty cycle) ters per line, 200/1 = 200 lines. Required
• First layer: graphics display memory size = 40 × 200 = 8000 bytes.
• Second layer: graphics display
• Third layer: graphics display

130 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
9.1.5 9.0 Application Notes

3E80H
3rd graphics layer
(8000 bytes)

1F40H
2nd graphics layer 5DBFH
(8000 bytes)

0000H
1st graphics layer 3E7FH
(8000 bytes)

1F3FH

Figure 83. Three-layer graphics

• Register setup procedure

SYSTEM SET TC/R calculation SCROLL
C= 40H C= 44H
P1 = 30H fOSC = 6 MHz P1 = 00H
P2 = 87H fFR = 70 Hz P2 = 00H
P3 = 07H P3 = C8H
P4 = 27H (1/6) × 9 × [TC/R] × 200 = 1/70 P4 = 40H
P5 = 2FH [TC/R] = 48, so TC/R = 2FH P5 = 1FH
P6 = C7H P6 = C8H
P7 = 28H P7 = 80H
P8 = 00H P8 = 3EH
P9 = XH
P10 = XH

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 131
9.0 Application Notes 9.1.5 – 9.2
CSR FORM OVLAY
C= 5DH C= 5BH
P1 = 07H P1 = 1CH
P2 = 87H
DISP ON/OFF
HDOT SCR C= 59H
C= 5AH P1 = 16H
P1 = 00H

X = Don’t care

9.2 System Overview

Figure 84 shows the SED1330F/1335F/1336F in a Since all of the LCD control circuits are integrated
typical system. The microprocessor issues instruc- onto the SED1330F/1335F/1336F, few external com-
tions to the 1330F/SED1335F/1336F, and the ponents are required to construct a complete me-
SED1330F/1335F/1336F drives the LCD panel and dium-resolution liquid crystal display.
may have up to 64Kbytes of display memory.

SED1335F/1336F

Character Display memory External character

generator address bus generator memory
Micro-
processor
Display memory
Display
address
control Display memory
data bus

Driver LCD unit

control Driver bus

Main
memory TV
X driver X driver X driver
control*

Data bus
Address bus Composite LCD panel
Y driver
signal
Control bus

TV
* SED1336F only

Figure 84. System block diagram

132 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
9.3 – 9.3.1 9.0 Application Notes
9.3 System Interconnection

9.3.1 SED1330F/1335F

10MHz crystal
HC138
OSC1 OSC2 CS7
Y7
CS6
A0 A0 VA13 A Y6
to B to
to
VA15 C CS0
A1 Y0
VCE
to VR/W
A7 Decoder CS
VA0 VA12
IORQ to
VA12
Micro-
processor A0 to A12 WE A0 to A12 WE A0 to A11
D0 D0 SED1335F SRM2064 CS1 SRM2064 CS1 2732 OE
to to (RAM1) CS2 (RAM2) CS2 (CGROM)
D7 D7
D0 to D7 OE D0 to D7 OE D0 to D7 CE
RD RD
WR WR
RES RES VD0
XD0 to
to VD7
RESET
XD3
XECL
XSCL

YSCL
YDIS
WF

YD
LP

LAT
DI
INH LCD
FR
YSCL

POFF SED1630F

V1 SED1600F SED1600F SED1600F

Power FR FR FR
supply V2
EI E0 EI E0 EI
E1 E0
XSCL

XSCL

XSCL
converter
ECL

ECL

ECL
V3
DO

DO

DO
D3

D3

D3
LP

LP

LP
to

to

to
V4
VREG V5

LCD UNIT

Notes:
1. The recommended common drivers are the SED1743, SED1635.
2. The recommended segment drivers are the SED1742 and SED1606.

Figure 85. System interconnection diagram

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 133
9.0 Application Notes 9.3.2
9.3.2 SED1336F

10MHz crystal
HC138
OSC1 OSC2 CS7
Y7
CS6
A0 A0 VA13 A Y6
to B to
to
VA15 C CS0
A1 Y0
VCE
to VR/W
A7 Decoder CS
VA0 VA12
IORQ to
VA12
Micro-
processor A0 to A12 WE A0 to A12 WE A0 to A11
D0 D0 SED1336F SRM2064 CS1 SRM2064 CS1 2732 OE
to to (RAM1) CS2 (RAM2) CS2 (CGROM)
D7 D7
D0 to D7 OE D0 to D7 OE D0 to D7 CE
RD RD
WR WR
RES RES VD0
XD0 to
to VD7
RESET
XD3
XSCL

YDIS
WF

YD
LP

DI
INH LCD
FR
YSCL

POFF SED1630F

V1 SED1600F SED1600F SED1600F

Power FR FR FR
supply V2
EI E0 EI E0 EI
E1 E0
XSCL

XSCL

XSCL
converter

ECL
V3
DO

DO

DO
D3

D3

D3
LP

LP

LP
to

to

to
V4
VREG V5

LCD UNIT

Notes:
1. The recommended common drivers are the SED1743, SED1635.
2. The recommended segment drivers are the SED1742 and SED1606.

Figure 86. System interconnection diagram

The SED1330F/1335F/1336F’s layered screens and • Character code table

flexible scrolling facilities support a range of display • Contains character codes for text display
functions and reduces the load on the controlling
• Each character requires 8 bits
microprocessor when displaying underlining, inverse
display, text overlaid on graphics or simple animation. • Table mapping can be changed by using
the scroll start function
These facilities are supported by the SED1330F/
1335F/1336F’s ability to divide display memory into
up to four different areas.

134 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
9.3.2 – 9.4 9.0 Application Notes
• Graphics data table 9.4 Smooth Horizontal Scrolling
• Contains graphics bitmaps
Figure 87 illustrates smooth display scrolling to the
• Word length is 8 bits left. When scrolling left, the screen is effectively
• Table mapping can be changed moving to the right, over the larger virtual screen.

Instead of changing the display start address SAD

• CG RAM table
and shifting the display by eight pixels, smooth scroll-
• Character generator memory can be ing is achieved by repeatedly changing the pixel-shift
modified by the external microprocessor parameter of the HDOT SCR command. When the
• Character sizes up to 8 × 16 pixels (16 display has been scrolled seven pixels, the HDOT
bytes per character) SCR pixel-shift parameter is reset to zero and SAD
• Maximum of 64 characters incremented by one. Repeating this operation at a
suitable rate gives the appearance of smooth scroll-
• Table mapping can be changed
ing.

• CG ROM table To scroll the display to the right, the reverse proce-
• Used when the internal character genera- dure is followed.
tor is not adequate When the edge of the virtual screen is reached, the
• Can be used in conjunction with the inter- microprocessor must take appropriate steps so that
nal character generator and external char- the display is not corrupted. The scroll must be stopped
acter generator RAM or the display modified.
• Character sizes up to 8 × 16-pixels (16
bytes per character) Note that the HDOT SCR command cannot be used
to scroll individual layers.
• Maximum of 256 characters
• Fixed mapping at F000H to FFFFH

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 135
9.0 Application Notes 9.4

HDOT SCR SAD SAD + 1 SAD + 2

parameter

P1 = 00H Magnified

AP

P1 = 01H

SAD = SAD
P1 = 02H

Display

P1 = 03H C/R

Virtual screen

P1 = 07H

P1 = 00H
SAD = SAD + 1

Not visible Visible

Note: The response time of LCD panels changes considerably at low temperatures. Smooth scrolling under these conditions may
make the display difficult to read.

Figure 87. HDOT SCR example

136 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
9.5 – 9.5.2.1 9.0 Application Notes
9.5 Layered Display Attributes

SED1330F/1335F/1336F incorporates a number of A number of means can be used to achieve these

functions for enhanced displays using monochrome effects, depending on the display configuration. These
LCD panels. It allows the display of inverse charac- are listed below. Note, however, that not all of these
ters, half-intensity menu pads and flashing of selected can be used in the one layer at the same time.
screen areas. These functions are controlled by the
OVLAY and DISP ON/OFF commands.

Attribute MX1 MX0 Combined layer display 1st layer display 2ndt layer display

0 1
Reverse IV EPSON IV EPSON
1 1

0 0
Half-tone ME Yes, No ME Yes, No
1 1

0 0
Local flashing BL Error BL Error
0 1

0 0
Ruled line RL LINE RL LINE
0 1
LINE LINE
1 1

Figure 88. Layer synthesis

9.5.1 Inverse Display 9.5.2 Half-tone Display

The first layer is text, the second layer is graphics. The FP parameter can be used to generate half-
intensity display by flashing the display at 17 Hz. Note
1. CSRW, CSDIR, MWRITE that this mode of operation may cause flicker prob-
Write 1s into the graphics screen at the area to lems with certain LCD panels.
be inverted.
2. OVLAY: MX0 = 1, MX1 = 0
Set the combination of the two layers to 9.5.2.1 Menu Pad Display
Exclusive-OR.
Turn flashing off for the first layer, on at 17 Hz for the
3. DISP ON/OFF: FP0 = FP1 = 1, FP1 = FP3 = second layer, and combine the screens using the OR
0. function.
Turn on layers 1 and 2.
1. OVLAY: P1 = 00H
2. DISP ON/OFF: P1 = 34H

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 137
9.0 Application Notes 9.5.2.1 – 9.5.3.2

SAD1 SAD2 Half-tone

AB AB

1st layer 2nd layer Combined layer display

Figure 89. Half-tone character and graphics

9.5.2.2 Graph Display 9.5.3 Flashing Areas

To present two overlaid graphs on the screen, config- 9.5.3.1 Small Area
ure the display as for the menu bar display and put one
graph on each screen layer. The difference in contrast To flash selected characters, the MPU can alternately
between the half- and full-intensity displays will make write the characters as character codes and blank
it easy to distinguish between the two graphs and help characters at intervals of 0.5 to 1.0 seconds.
create an attractive display.

1. OVLAY: P1 = 00H
9.5.3.2 Large Area
2. DISP ON/OFF: P1 = 34H
Divide both layer 1 and layer 2 into two screen blocks
each, layer 2 being divided into the area to be flashed
and the remainder of the screen. Flash the layer 2
screen block at 2 Hz for the area to be flashed and
combine the layers using the OR function.

ABC ABC

XYZ XYZ

Figure 90. Localized flashing

138 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
9.6 – 9.6.2 9.0 Application Notes
9.6 16 × 16-dot Graphic Display

9.6.1 Command Usage 9.6.2 Kanji Character Display

This example shows how to display 16 × 16-pixel The program for writing large characters operates as
characters. The command sequence is as follows: follows:

CSRW Set the cursor address. 1. The microprocessor reads the character data
CSRDIR Set the cursor auto-increment di- from its ROM.
rection. 2. The microprocessor sets the display address
MWRITE Write to the display memory. and writes to the VRAM. The flowchart is
shown in Figure 91.

A0 = 0 A0 = 1
O8 O7 O6 O5 O4 O3 O2 O1 O8 O7 O6 O5 O4 O3 O2 O1 CG ROM output
0H (1) (2)
1H (3) (4)
2H (5) (6)
(n) shows the CG ROM data
3H (7) (8) readout order
4H (9) (10)
5H (11) (12)
6H (13) (14)
7H (15) (16)
8H (17) (18)
9H (19) (20)
AH (21) (22)
BH (23) (24)
CH (25) (26)
DH (27) (28)
EH (29) (30)
FH (31) (32) (Kanji ROM pattern)
1st column 2nd column
Scan address A1 to A4

(6)
(4)
(2)

2nd column (4)

(19)
memory area (2)
(17)
(15)
(13)
(11)
(9)
1st column (3)
(7)
memory area (1)
(5)
(3)
(1)

Data held in the microprocessor memory Data written into the SED1330 display memory

Figure 91. Graphics address indexing

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 139
9.0 Application Notes 9.6 – 9.6.2

320 dots

Direction of cursor movement

(1) (2)
(3) (4)
(5) (6) 240 dots
(7) (8)
(9) (10)
(11) (12)
(13) (14)
(15) (16)
(17) (18)
(19) (20)
(21) (22)
(23) (24)
(25) (26)
(27) (28)
(29) (30)
(31) (32)

Figure 92. Graphics bit map

Using an external character generator ROM, and 8 ×

Start
16-pixel font can be used, allowing a 16 × 16-pixel
character to be displayed in two segments. The exter-
nal CG ROM EPROM data format is described in
Enable cursor downwards movement Section 5.1. This will allow the display of up to 128, 16
× 16-pixel characters. If CG RAM is also used, 96 fixed
characters and 32 bank-switchable characters can
Set column 1 cursor address also be supported.

Write data

Set column 2 cursor address

Write data

End

Figure 93. 16 × 16-dot display flowchart

140 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
 10.0
Internal Character
Generator Font

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 141
 THIS PAGE INTENTIONALLY BLANK

142 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
10.0 10.0 Internal Character Generator Font
10.0 Internal Character Generator Font

Character code bits 0 to 3

0 1 2 3 4 5 6 7 8 9 A B C D E F

5
Character code bits 4 to 7

Figure 94. On-chip character set

Note: The shaded positions indicate characters that have the whole 6 × 8 bitmap blackened.

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 143
 THIS PAGE INTENTIONALLY BLANK

144 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
 11.0
Glossary of Terms

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 145
 THIS PAGE INTENTIONALLY BLANK

146 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4
11.0 11.0 Glossary of Terms
11.0 Glossary of Terms

A Address

AP Address pitch parameter

C Character display mode

CD Cursor direction of movement parameter

CG Character generator

CGRAM ADR Character generator memory address

CM Cursor display shape parameter

C/R Characters per row parameter

CRX Horizontal cursor size parameter

CRY Vertical cursor size parameter

CSR DIR Cursor direction of movement instruction

CSR FORM Cursor size, position and type instruction

CSRR Read cursor address register instruction

CSRW Write cursor address register instruction

DM Display mode parameter

FC Flashing cursor parameter

fFR Frame frequency

fOSC Oscillator frequency

FP Screen flashing parameter

FX Horizontal character size parameter

FY Vertical character size parameter

G Graphics display mode

GLC Graphic line control unit

HDOT SCR Horizontal scrolling by pixels instruction

IV Screen origin compensation for inverse display

L/F Lines per frame instruction

268-0.4 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 147
11.0 Glossary of Terms 11.0
MREAD Display memory read instruction

MWRITE Display memory write instruction

MX Screen composition mode

OV Graphics layer select parameter

OVLAY Screen layer mode instruction

P Parameter

R Row

RAM Random access memory

ROM Read only memory

SAD Display scrolling start address parameter

SL Display scrolling length parameter

TC/R Length, including horizontal blanking, of one screen line

VRAM Display memory

WF Display drive waveform parameter

W/S Windows per screen parameter

S-MOS assumes no responsibility or liability for (1) any errors or inaccuracies contained in the
information herein and (2) the use of the information or a portion thereof in any application,
including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or
consequential damages. There are no warranties extended or granted by this document. The
information herein is subject to change without notice from S-MOS.
September 1995 © Copyright 1995 S-MOS Systems, Inc. Printed in U.S.A. 268-0.4

148 S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: (408) 922-0200 • Fax: (408) 922-0238 268-0.4