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Example: A Simple MIPS Microprocessor

The document describes a simple 8-bit subset of the MIPS microprocessor architecture including the instruction set and encoding formats. It includes a table listing the supported instructions, their functions, and encoding. The architecture uses 32-bit instruction encodings but only eight 8-bit general purpose registers and an 8-bit program counter. It supports common arithmetic and logical instructions as well as branches and jumps.

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Carlos Saavedra
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41 views1 page

Example: A Simple MIPS Microprocessor

The document describes a simple 8-bit subset of the MIPS microprocessor architecture including the instruction set and encoding formats. It includes a table listing the supported instructions, their functions, and encoding. The architecture uses 32-bit instruction encodings but only eight 8-bit general purpose registers and an 8-bit program counter. It supports common arithmetic and logical instructions as well as branches and jumps.

Uploaded by

Carlos Saavedra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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1.

7 Example: A Simple MIPS Microprocessor 33

1.7 Example: A Simple MIPS Microprocessor


We consider an 8-bit subset of the MIPS microprocessor architecture [Patterson04,
Harris07] because it is widely studied and is relatively simple, yet still large enough to
illustrate hierarchical design. This section describes the architecture and the multicycle
microarchitecture we will be implementing. If you are not familiar with computer archi-
tecture, you can regard the MIPS processor as a black box and skip to Section 1.8.
A set of laboratory exercises is available at www.cmosvlsi.com in which you can
learn VLSI design by building the microprocessor yourself using a free open-source CAD
tool called Electric or with commercial design tools from Cadence and Synopsys.

1.7.1 MIPS Architecture


The MIPS32 architecture is a simple 32-bit RISC architecture with relatively few idiosyn-
crasies. Our subset of the architecture uses 32-bit instruction encodings but only eight
8-bit general-purpose registers named $0–$7. We also use an 8-bit program counter
(PC). Register $0 is hardwired to contain the number 0. The instructions are ADD, SUB,
AND, OR, SLT, ADDI, BEQ, J, LB, and SB.
The function and encoding of each instruction is given in Table 1.7. Each instruction
is encoded using one of three templates: R, I, and J. R-type instructions (register-based)
are used for arithmetic and specify two source registers and a destination register. I-type
instructions are used when a 16-bit constant (also known as an immediate) and two regis-
ters must be specified. J-type instructions ( jumps) dedicate most of the instruction word to
a 26-bit jump destination. The format of each encoding is defined in Figure 1.49. The six
most significant bits of all formats are the operation code (op). R-type instructions all
share op = 000000 and use six more funct bits to differentiate the functions.

TABLE 1.7 MIPS instruction set (subset supported)


Instruction Function Encoding op funct
add $1, $2, $3 addition: $1 <- $2 + $3 R 000000 100000
sub $1, $2, $3 subtraction: $1 <- $2 – $3 R 000000 100010
and $1, $2, $3 bitwise and: $1 <- $2 and $3 R 000000 100100
or $1, $2, $3 bitwise or: $1 <- $2 or $3 R 000000 100101
slt $1, $2, $3 set less than: $1 <- 1 if $2 < $3 R 000000 101010
$1 <- 0 otherwise
addi $1, $2, imm add immediate: $1 <- $2 + imm I 001000 n/a
beq $1, $2, imm branch if equal: PC <- PC + imm × 4a I 000100 n/a

j destination jump: PC <- destinationa J 000010 n/a


lb $1, imm($2) load byte: $1 <- mem[$2 + imm] I 100000 n/a
sb $1, imm($2) store byte: mem[$2 + imm] <- $1 I 101000 n/a

a.Technically, MIPS addresses specify bytes. Instructions require a 4-byte word and must begin at addresses that are a mul-
tiple of four. To most effectively use instruction bits in the full 32-bit MIPS architecture, branch and jump constants are
specified in words and must be multiplied by four (shifted left 2 bits) to be converted to byte addresses.

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