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    Stick Diagrams: Chapter 1 Introduction

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    Carlos Saavedra
    This document discusses stick diagrams, which are simplified schematic representations used by circuit designers to plan layouts before committing to a full design. It provides stick diagrams of an inverter and 3-input NAND gate as examples. The document explains that stick diagrams allow designers to estimate the area of a layout even though the diagrams are not drawn to scale, with area usually determined by the number and pitch of metal routing tracks required.

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    © All Rights Reserved
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    Stick Diagrams: Chapter 1 Introduction

    Uploaded by

    Carlos Saavedra
    41 views1 page
    This document discusses stick diagrams, which are simplified schematic representations used by circuit designers to plan layouts before committing to a full design. It provides stick diagrams of an inverter and 3-input NAND gate as examples. The document explains that stick diagrams allow designers to estimate the area of a layout even though the diagrams are not drawn to scale, with area usually determined by the number and pitch of metal routing tracks required.

    Original Title

    CMOS-VLSI-design-55

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    This document discusses stick diagrams, which are simplified schematic representations used by circuit designers to plan layouts before committing to a full design. It provides stick diagrams of an inverter and 3-input NAND gate as examples. The document explains that stick diagrams allow designers to estimate the area of a layout even though the diagrams are not drawn to scale, with area usually determined by the number and pitch of metal routing tracks required.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    41 views1 page

    Stick Diagrams: Chapter 1 Introduction

    Uploaded by

    Carlos Saavedra
    This document discusses stick diagrams, which are simplified schematic representations used by circuit designers to plan layouts before committing to a full design. It provides stick diagrams of an inverter and 3-input NAND gate as examples. The document explains that stick diagrams allow designers to estimate the area of a layout even though the diagrams are not drawn to scale, with area usually determined by the number and pitch of metal routing tracks required.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 1

    28 Chapter 1 Introduction

    VDD VDD Contact


    A A B C

    Metal1

    Y Y pdiff

    ndiff

    GND GND Polysilicon

    (a) (b)
    FIGURE 1.43 Stick diagrams of inverter and 3-input NAND gate. Color version on inside front cover.

    to each gate. While this increases the size of the cell, it allows free access to all terminals
    on metal routing layers.

    1.5.5 Stick Diagrams


    Because layout is time-consuming, designers need fast ways
    to plan cells and estimate area before committing to a full
    layout. Stick diagrams are easy to draw because they do not
    4h 4h need to be drawn to scale. Figure 1.43 and the inside front
    cover show stick diagrams for an inverter and a 3-input
    4h 4h
    NAND gate. While this book uses stipple patterns, layout
    designers use dry-erase markers or colored pencils.
    With practice, it is easy to estimate the area of a layout
    (b)
    from the corresponding stick diagram even though the dia-
    4h gram is not to scale. Although schematics focus on transis-
    4h tors, layout area is usually determined by the metal wires.
    Transistors are merely widgets that fit under the wires. We
    define a routing track as enough space to place a wire and the
    (a) required spacing to the next wire. If our wires have a width
    FIGURE 1.44 Pitch of routing tracks of 4 Q and a spacing of 4 Q to the next wire, the track pitch is
    8 Q, as shown in Figure 1.44(a). This pitch also leaves room
    for a transistor to be placed between the wires (Figure
    1.44(b)). Therefore, it is reasonable to estimate the height
    and width of a cell by counting the number of metal tracks
    and multiplying by 8 Q. A slight complication is the required
    spacing of 12 Q between nMOS and pMOS transistors set
    4h by the well, as shown in Figure 1.45(a). This space can be
    occupied by an additional track of wire, shown in Figure
    12 h 4h 12 h 1.45(b). Therefore, an extra track must be allocated between
    4h nMOS and pMOS transistors regardless of whether wire is
    actually used in that track. Figure 1.46 shows how to count
    tracks to estimate the size of a 3-input NAND. There are
    four vertical wire tracks, multiplied by 8 Q per track to give a
    (a) (b) cell width of 32 Q. There are five horizontal tracks, giving a
    cell height of 40 Q. Even though the horizontal tracks are
    FIGURE 1.45 Spacing between nMOS and pMOS transistors
    not drawn to scale, they are still easy to count. Figure 1.42

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