Scribd
Upload
16 views1 page

CMOS Fabrication and Layout: Inverter Cross-Section

This document discusses CMOS fabrication and layout. It begins by explaining that transistors are fabricated on silicon wafers which serve as both a mechanical support and electrical common point called the substrate. It then describes how the layout of transistors can be viewed from a top view looking down on the wafer or a cross-sectional view by slicing through the wafer. The document provides details on the cross-sectional view of a CMOS inverter, showing the p-type substrate and n-well region for the pMOS transistor. Fabrication is controlled through masks that define the size of transistors and wires based on the manufacturing process resolution.

Uploaded by

Carlos Saavedra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
16 views1 page

CMOS Fabrication and Layout: Inverter Cross-Section

This document discusses CMOS fabrication and layout. It begins by explaining that transistors are fabricated on silicon wafers which serve as both a mechanical support and electrical common point called the substrate. It then describes how the layout of transistors can be viewed from a top view looking down on the wafer or a cross-sectional view by slicing through the wafer. The document provides details on the cross-sectional view of a CMOS inverter, showing the p-type substrate and n-well region for the pMOS transistor. Fabrication is controlled through masks that define the size of transistors and wires based on the manufacturing process resolution.

Uploaded by

Carlos Saavedra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

1.

5 CMOS Fabrication and Layout 19

constructed. A collection of D flip-flops sharing a common clock input is called a register.


A register is often drawn as a flip-flop with multi-bit D and Q busses.
In Section 10.2.5 we will see that flip-flops may experience hold-time failures if the
system has too much clock skew, i.e., if one flip-flop triggers early and another triggers late
because of variations in clock arrival times. In industrial designs, a great deal of effort is
devoted to timing simulations to catch hold-time problems. When design time is more
important (e.g., in class projects), hold-time problems can be avoided altogether by dis-
tributing a two-phase nonoverlapping clock. Figure 1.33 shows the flip-flop clocked with
two nonoverlapping phases. As long as the phases never overlap, at least one latch will be
opaque at any given time and hold-time problems cannot occur.

1.5 CMOS Fabrication and Layout


Now that we can design logic gates and registers from transistors, let us consider how the
transistors are built. Designers need to understand the physical implementation of circuits
because it has a major impact on performance, power, and cost.
Transistors are fabricated on thin silicon wafers that serve as both a mechanical sup-
port and an electrical common point called the substrate. We can examine the physical lay-
out of transistors from two perspectives. One is the top view, obtained by looking down on
a wafer. The other is the cross-section, obtained by slicing the wafer through the middle of
a transistor and looking at it edgewise. We begin by looking at the cross-section of a com-
plete CMOS inverter. We then look at the top view of the same inverter and define a set
of masks used to manufacture the different parts of the inverter. The size of the transistors
and wires is set by the mask dimensions and is limited by the resolution of the manufac-
turing process. Continual advancements in this resolution have fueled the exponential
growth of the semiconductor industry.

1.5.1 Inverter Cross-Section


Figure 1.34 shows a cross-section and corresponding schematic of an inverter. (See the
inside front cover for a color cross-section.) In this diagram, the inverter is built on a
p-type substrate. The pMOS transistor requires an n-type body region, so an n-well is dif-
fused into the substrate in its vicinity. As described in Section 1.3, the nMOS transistor

φ2 φ1
QM
D Q
φ2 φ1
φ2 φ1

φ2 φ1

φ1

φ2

FIGURE 1.33 CMOS flip-flop with two-phase nonoverlapping clocks

You might also like