Scribd
Upload
67 views1 page

1.4.9.1 Latches: D Input While The Slave Positive-Level-Sensitive Latch Holds The Previous Value (Figure

This document summarizes latches and flip-flops in CMOS logic. It describes how a D latch uses a multiplexer and inverters to become transparent and pass the input when the clock is high, holding the state when the clock is low. A flip-flop combines two latches, a negative-level sensitive master latch and positive-level sensitive slave latch, to sample the input only on the rising clock edge and output the result.

Uploaded by

Carlos Saavedra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
67 views1 page

1.4.9.1 Latches: D Input While The Slave Positive-Level-Sensitive Latch Holds The Previous Value (Figure

This document summarizes latches and flip-flops in CMOS logic. It describes how a D latch uses a multiplexer and inverters to become transparent and pass the input when the clock is high, holding the state when the clock is low. A flip-flop combines two latches, a negative-level sensitive master latch and positive-level sensitive slave latch, to sample the input only on the rising clock edge and output the result.

Uploaded by

Carlos Saavedra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

1.

4 CMOS Logic 17

1.4.9.1 Latches A D latch built from a 2-input multiplexer and two inverters is shown in
Figure 1.31(a). The multiplexer can be built from a pair of transmission gates, shown in
Figure 1.31(b), because the inverters are restoring. This latch also produces a complemen-
tary output, Q. When CLK = 1, the latch is transparent and D flows through to Q (Figure
1.31(c)). When CLK falls to 0, the latch becomes opaque. A feedback path around the
inverter pair is established (Figure 1.31(d)) to hold the current state of Q indefinitely.
The D latch is also known as a level-sensitive latch because the state of the output is
dependent on the level of the clock signal, as shown in Figure 1.31(e). The latch shown is
a positive-level-sensitive latch, represented by the symbol in Figure 1.31(f ). By inverting
the control connections to the multiplexer, the latch becomes negative-level-sensitive.

1.4.9.2 Flip-Flops By combining two level-sensitive latches, one negative-sensitive and


one positive-sensitive, we construct the edge-triggered flip-flop shown in Figure 1.32(a–
b). The first latch stage is called the master and the second is called the slave.
While CLK is low, the master negative-level-sensitive latch output (QM) follows the
D input while the slave positive-level-sensitive latch holds the previous value (Figure
1.32(c)). When the clock transitions from 0 to 1, the master latch becomes opaque and
holds the D value at the time of the clock transition. The slave latch becomes transparent,
passing the stored master value (QM) to the output of the slave latch (Q). The D input is
blocked from affecting the output because the master is disconnected from the D input
(Figure 1.32(d)). When the clock transitions from 1 to 0, the slave latch holds its value
and the master starts sampling the input again.
While we have shown a transmission gate multiplexer as the input stage, good design
practice would buffer the input and output with inverters, as shown in Figure 1.32(e), to

CLK
CLK
Q Q
D 1
Q D Q
0
CLK CLK

(a) (b)

CLK

Q Q
D Q D Q

CLK = 1 CLK = 0

(c) (d)

CLK

CLK
D
Latch

D Q
Q
(e) (f)

FIGURE 1.31 CMOS positive-level-sensitive D latch

You might also like