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Cmos Vlsi Design 21

This document is an appendix about hardware description languages. It discusses topics such as modules, simulation and synthesis, combinational and sequential logic, finite state machines, and type idiosyncrasies. The appendix covers concepts like bitwise operators, comments, reduction operators, conditional assignment, internal variables, precedence, numbers, unknown and high-impedance values, bit swizzling, delays, registers, counters, latch, always/process statements, case statements, if statements, blocking and nonblocking assignments, and state enumeration in finite state machines.

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Carlos Saavedra
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56 views1 page

Cmos Vlsi Design 21

This document is an appendix about hardware description languages. It discusses topics such as modules, simulation and synthesis, combinational and sequential logic, finite state machines, and type idiosyncrasies. The appendix covers concepts like bitwise operators, comments, reduction operators, conditional assignment, internal variables, precedence, numbers, unknown and high-impedance values, bit swizzling, delays, registers, counters, latch, always/process statements, case statements, if statements, blocking and nonblocking assignments, and state enumeration in finite state machines.

Uploaded by

Carlos Saavedra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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xx Contents

WEB
ENHANCED 15.7 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
15.8 Testing in a University Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
15.9 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
Summary 697
Exercises 697

Appendix A Hardware Description Languages


A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
A.1.1 Modules 700
A.1.2 Simulation and Synthesis 701
A.2 Combinational Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
A.2.1 Bitwise Operators 702
A.2.2 Comments and White Space 703
A.2.3 Reduction Operators 703
A.2.4 Conditional Assignment 704
A.2.5 Internal Variables 706
A.2.6 Precedence and Other Operators 708
A.2.7 Numbers 708
A.2.8 Zs and Xs 709
A.2.9 Bit Swizzling 711
A.2.10 Delays 712
A.3 Structural Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
A.4 Sequential Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
A.4.1 Registers 717
A.4.2 Resettable Registers 718
A.4.3 Enabled Registers 719
A.4.4 Multiple Registers 720
A.4.5 Latches 721
A.4.6 Counters 722
A.4.7 Shift Registers 724
A.5 Combinational Logic with Always / Process Statements . . . . . . . . . . . . . . 724
A.5.1 Case Statements 726
A.5.2 If Statements 729
A.5.3 SystemVerilog Casez 731
A.5.4 Blocking and Nonblocking Assignments 731
A.6 Finite State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
A.6.1 FSM Example 735
A.6.2 State Enumeration 736
A.6.3 FSM with Inputs 738
A.7 Type Idiosyncracies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740

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