PlanAhead User

Guide

UG632 (v 12.4) December 21, 2010

Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development
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Included in the PlanAhead™ software code is source code for the following programs:
Centerpoint XML
The initial developer of the Original Code is CenterPoint - Connective Software Engineering GmbH. Portions created by CenterPoint
- Connective Software Engineering GmbH. Copyright © Copyright IBM Corp. 1998 1998-2000 CenterPoint
- Connective Software Engineering GmbH. All Rights Reserved. Source Code for CenterPoint is available at http://www.cpointc.com/XML/
NLView Schematic Engine
Copyright © Copyright IBM Corp. 1998 Concept Engineering.
Static Timing Engine by Parallax Software Inc.
Copyright © Copyright IBM Corp. 1998 Parallax Software Inc.
Java Standard Edition
Copyright © Copyright IBM Corp. 1998 1995 - 2006 Sun Microsystems
Includes portions of software from RSA Security, Inc. and some portions licensed from IBM are available at
http://oss.software.ibm.com/icu4j/.

PlanAhead User Guide www.xilinx.com UG632 (v 12.4)

Libconfig (v1.3.2) License
libconfig - A library for processing structured configuration files
Copyright (C) 2005-2009 Mark A Lindner
This file is part of libconfig.
This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published
by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details.
You should have received a copy of the GNU Library General Public License along with this library; if not, see http://www.gnu.org/licenses/.
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This is the Entire License for all of our Free IP Cores.
Copyright (C) 2000-2003, ASICs World Services, LTD., AUTHORS
All rights reserved.
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-Neither the name of ASICS World Services, the Authors and/or the names of its contributors may be used to endorse or promote products
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© 2010 Xilinx, Inc.
This RTL Design is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as
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This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details.
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UG632 (v 12.4) www.xilinx.com PlanAhead User Guide

PlanAhead User Guide www.xilinx.com UG632 (v 12.4)
 Guide Contents

Preface

About This Guide

This document provides detailed information about the PlanAhead™ software, including
an interface overview, and instructions for using the design and software capabilities.
This chapter contains the following sections:
• Guide Contents
• Additional Resources
• Document Conventions
Note: For information on software installation, and system requirements, refer to the Xilinx ISE
Design Suite: Installation, Licensing, and Release Notes.

Guide Contents
This document contains the following chapters:
• Chapter 1, “Introduction,”provides an overview of the PlanAhead features.
• Chapter 2, “Understanding the PlanAhead Design Flow,”provides an overview of the
design flow.
• Chapter 3, “Working with Projects,”describes the initial setup and management of a
project within PlanAhead.
• Chapter 4, “Using the Viewing Environment,”describes the PlanAhead user interface.
• Chapter 5, “RTL Design,” describes the RTL environment.
• Chapter 6, “Synthesizing the Design,” describes the available Synthesis capabilities.
• Chapter 7, “Netlist Analysis and Constraint Definition,”describes the PlanAhead
design analysis and constraint definition capabilities.
• Chapter 8, “I/O Pin Planning,” describes the pin planning environment that enables
pin assignment.
• Chapter 9, “Implementing the Design,” describes the available Implementation
capabilities.
• Chapter 10, “Analyzing Implementation Results,” describes the timing and placement
analysis capabilities available in PlanAhead.
• Chapter 11, “Floorplanning the Design,” describes the various floorplanning
strategies and capabilities available in PlanAhead.
• Chapter 12, “Programming and Debugging the Design,”describes the process for
generating bitstream files, launching programming tools and how to use ChipScope™
debugging software debugging capabilities that are integrated into PlanAhead.
• Chapter 13, “Using Hierarchical Design Techniques,” describes how to use the
hierarchical design features.

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UG632 (v 12.4)
Preface: About This Guide

• Chapter 14, “Tcl and Batch Scripting,” describes how to use the Tcl commands and
scripting features
• Chapter 15, “Using PlanAhead With Project Navigator,” describes the PlanAhead
flows that are integrated with Project Navigator.
This document contains the following appendixes:
• Appendix A, PlanAhead Input and Output Files, describes the files used as input and
output in PlanAhead.
• Appendix B, PlanAhead Terminology,” provides an explanation of the terminology
used in PlanAhead software.
• Appendix C, Installing Releases with XilinxNotify, describes the PlanAhead release
strategy and explains how to update the software.
• Appendix D, Configuring SSH Without Password Prompting, describes how to setup
a passwordless SSH, which is required for running PlanAhead processes on multiple
hosts.

Additional Resources
The following documents are PlanAhead-specific:
• Xilinx ISE Design Suite 12: Installation, Licensing, and Release Notes (UG631)—This
document provides specific installation instructions and requirements. Available from
the software and from the Xilinx website.
• What’s New in PlanAhead (UG656)—The What’s New document provides specific
information about new features in this release. Available from the software and from
the Xilinx website.
• Floorplanning Methodology Guide (UG633)—This guide provides information about
various floorplanning strategies aimed at improving performance, repeatability of
results or reducing design times. Available from the Xilinx website.
• Hierarchical Design Methodology Guide (UG748)—This guide provides information
about using the Xilinx hierarchical partitioning capabilities. Available from the Xilinx
website.
The following documents are referenced:
• Xilinx Synthesis and Simulation Design Guide (UG626)
• Xilinx Constraints Guide (UG612)
• Spartan-6 PCB Design Guide (UG393)
The Partial Reconfiguration User Guide (UG702) and other Partial Reconfiguration
documentation are available at the following Xilinx website:
www.xilinx.com/tools/partial-reconfiguration
For more information, go to the Xilinx website (http://www.xilinx.com/planahead).
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/support/documentation/index.htm
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a webcase with Technical Support, see the Xilinx website at:
http://www.xilinx.com/support/mysupport.htm

6 www.xilinx.com PlanAhead User Guide

UG632 (v 12.4)
 Additional Resources

Xilinx Customer Education Training

• Essential Design with the PlanAhead Analysis & Design Tool—Attend this Xilinx
Customer Education Training Course to learn the basics about the PlanAhead
functionality.
• Advanced Design with the PlanAhead Analysis & Design Tool—Attend this Xilinx
Customer Education Training Course to learn about the advanced PlanAhead
functionality.

Tutorials
The following PlanAhead tutorials are available with the PlanAhead software and on the
Xilinx website: http://www.xilinx.com/tools/planahead.htm.
− Quick Front- to-Back Flow Overview (UG673)
− I/O Pin Planning (UG674)
− RTL Design and IP Creation using CORE Generator (UG675)
− Design Analysis and Floorplanning (UG676)
− Debugging with ChipScope (UG677)
− Leveraging Design Preservation for Predictable Results (UG747)
− Overview of Partial Reconfiguration Flow (UG743)
− Partial Reconfiguration with Processor Peripheral (UG744)
− Using Tcl and SDC Commands (UG760)

Video Demonstrations
• PlanAhead Technical Video Demonstrations—Watch the video demonstrations to learn
more about specific areas of the PlanAhead software. Available from the Xilinx
website: http://www.xilinx.com/design.

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UG632 (v 12.4)
Preface: About This Guide

Document Conventions
This document uses the following conventions. An example illustrates each convention.

Convention Meaning or Use Example

Typographical
Messages, prompts, and program files
Courier font speed grade: - 100
that the system displays
Literal commands that you enter in a
Courier bold ngdbuild design_name
syntactical statement
Commands that you select from a menu File > Open
Helvetica bold
Keyboard shortcuts Ctrl+C
Variables in a syntax statement for which
ngdbuild design_name
you must supply values
See the Command Line Tools User
References to other manuals
Italic font Guide for more information.
If a wire is drawn so that it overlaps
Emphasis in text the pin of a symbol, the two nets are
not connected.
Dark Shading Items that are not supported or reserved This feature is not supported
An optional entry or parameter.
ngdbuild [option_name]
Square brackets [ ] However, in bus specifications, such as
design_name
bus[7:0], they are required.
A list of items from which you must
Braces { } lowpwr ={on|off}
choose one or more
Vertical bar | Separates items in a list of choices lowpwr ={on|off}
IOB #1: Name = QOUT’
Vertical ellipsis IOB #2: Name = CLKIN’
. Repetitive material that has been omitted .
. .
.
allow block block_name
Horizontal ellipsis . . . Repetitive material that has been omitted
loc1 loc2 ... locn;
The prefix ‘0x’ or the suffix ‘h’ indicate A read of address 0x00112975
Notations hexadecimal notation returned 45524943h.
An ‘_n’ means the signal is active low usr_teof_n is active Low.
Online Documentation
See the section “Additional Resources”
Cross-reference link to a location in the for details.
Blue text
current document Refer to “Title Formats” in Chapter 1
for details.
Go to http://www.xilinx.com for
Blue, underlined text Hyperlink to a website (URL)
the latest speed files.

8 www.xilinx.com PlanAhead User Guide

UG632 (v 12.4)
Table of Contents
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Xilinx Customer Education Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Tutorials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Video Demonstrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Document Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 1: Introduction
About PlanAhead Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Using PlanAhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Project Creation and Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
RTL and IP Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Design Analysis and Constraints Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Pin Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Programming and Debugging Designs and ChipScope Integration . . . . . . . . . . . . . . .25
Hierarchical Design, Design Preservation, and Partial Configuration . . . . . . . . . . . . .25
Tcl Commands and Batch Scripting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Using PlanAhead with the ISE Project Navigator Environment . . . . . . . . . . . . . . . . . .26
Input and Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
PlanAhead Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Accessing Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Configuring Multiple Linux Hosts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Invoking PlanAhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Linux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Using the Getting Started Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PlanAhead Command Line Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Using a PlanAhead Startup Tcl Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Chapter 2: Understanding the PlanAhead Design Flow

PlanAhead Design Flows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
RTL to Bitstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Synthesized Netlist to Bitstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Device Exploration and I/O Pin Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Analyze Implemented Design Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Partial Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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 Design Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Design Flow Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Project Creation and Management of Project Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . 33
IP Customization and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
RTL Development and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Logic Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
I/O Pin Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Netlist Analysis and Constraints Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Results Analysis and Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Device Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Design Verification and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
User Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Basic User Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Advanced User Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Understanding the Flow Navigator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Using the Flow Navigator with an RTL Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Using the Flow Navigator with a Synthesized Netlist Project . . . . . . . . . . . . . . . . . . . 38
Launching Commands from the Flow Navigator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Using the Project Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Setting Command Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Running Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Running Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Generating Bitstream Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Launching Programming and Debug tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Working with Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Opening an RTL Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Using a Netlist Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Opening a Netlist Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Setting the Active Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Opening an Implemented Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Managing Open Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Closing Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Understanding the Open Design View Banner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Selecting the I/O Planner or Design Planner View Layout . . . . . . . . . . . . . . . . . . . . . . 45
Using the Design is Out of Date and Reload Banner . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Toggling Multiple Open Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Chapter 3: Working with Projects

Understanding PlanAhead Project Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
RTL Source-Based Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Synthesized Netlist-Based Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Implemented Design Results-Based Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
I/O Pin Planning Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Project Navigator Created Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Creating a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Using the Create New Project Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Entering a Project Name and Location for the Project . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Selecting the Design Source Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Creating a Project with RTL Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Importing Settings from XST or Synplify Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Creating a Project with a Synthesized Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

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 Adding Constraint Files to RTL and Netlist Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Selecting a Default Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Creating an I/O Planning Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Selecting a Default Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Creating a Project with ISE Placement and Timing Results . . . . . . . . . . . . . . . . . . . . . . 55
Importing Placement and Timing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Opening an Existing Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Opening Multiple Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Saving a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Closing a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Managing Project Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Using the Project Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Using the Sources View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Creating Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Adding or Creating Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Using Remote Sources or Copying Sources into Project . . . . . . . . . . . . . . . . . . . . . . . . 60
Viewing Source File Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Updating Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Enabling or Disabling Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Adding Existing IP Cores to the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Configuring IP using the CORE Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Using the IP Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Updating the IP Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Configuring IP Catalog Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Customizing IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Viewing IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Instantiating IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Generating IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Modifying IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Using PlanAhead with Xilinx Platform Studio and EDK . . . . . . . . . . . . . . . . . . . . . 68
Adding and Managing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Adding or Creating Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Adding Constraints When Creating a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Using the Add/Create Constraints Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Defining the Target UCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Referencing Original UCF Files or Copying Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Using Constraint Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Controlling Constraint File Processing Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Changing the Target UCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Creating Constraint Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Using the Save Design As Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Creating New Constraint Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Defining the Active Constraint Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Using Module-level Constraint Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Exporting Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Configuring Project Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Using General Project Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Using the Synthesis Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Using the Implementation Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Configuring IP Catalog Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Creating Synthesis and Implementation Strategies. . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Creating Common Group Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

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 Viewing Project Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Viewing Project State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Compilation Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Chapter 4: Using the Viewing Environment

Understanding the Viewing Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Viewing Environment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Primary Environment Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Using the Main Viewing Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Maximizing the Main Viewing Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Hiding the Flow Navigator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Hiding the Compilation Messages Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Restoring the Compilation Messages Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Toggling Between I/O Planner and Design Planner . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Using the I/O Planner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Using the Design Planner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Using the Compilation Message Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Using the Elaboration Messages View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Using the Compilation Log View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Using the Compilation Messages Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Using the Tcl Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Using the Color Bar Warning and Error Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Using the Tcl Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Using Tcl Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Using the Design Runs View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Working with Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Opening Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Navigating Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Manipulating Views using the View Banner Controls . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Floating Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Using Graphical Workspace Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Understanding Workspace Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Opening Workspace Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Viewing the Workspace Full Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Floating the Workspace View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Printing the Workspace View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Closing Workspace Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Splitting the Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Using the World View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Using Tree Table Style Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Expanding and Collapsing the Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Display the Entries Grouped or in a Flat List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Using the Show Search Capability to Filter the List . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Sorting Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Organizing Columns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Using View Specific Toolbar Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Using the Information Banner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Understanding the Context Sensitive Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Selecting Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Using the Select Main Menu Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

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 Selecting Multiple Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Using the Select Area Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Selecting Primitive Parent Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Using the Selection View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Fitting the Display to Show Selected Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Setting Selection Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Setting Object Selections in the Workspace Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Highlighting Selected Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Marking Selected Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Using Common PlanAhead Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Using the Sources View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Opening the Sources View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Using the Sources View Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Using the Text Editor to View and Edit Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Using the Device View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Using Device View Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Understanding Device Resource Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Displaying Clock Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Printing the Device View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Opening Multiple Device Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Using the Package View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Opening Multiple Package Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Printing the Package View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Using the Schematic View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Selecting Logic in the Schematic View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Viewing Logic Hierarchy in the Schematic View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Expanding Logic from Selected Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Expanding and Collapsing Logic for Selected Instances or Modules . . . . . . . . . . . . . . 114
Schematic View Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Traversing the Schematic Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Regenerating a Schematic View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Selecting Objects in the Schematic View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Removing Objects From the Schematic View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Printing the Schematic View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Schematic View-Specific Popup Menu Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Annotating Schematic Design Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Viewing Timing Path Logic in the Schematic View . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Using the Properties View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Opening the Properties View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Using the Properties View Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Using the Netlist View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Collapsing the Netlist Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Using the Primitives Folder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Using the Nets Folder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Understanding the Netlist View Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Selecting Logic in the Netlist View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Using the Netlist View Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Using the Hierarchy View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Using the I/O Ports View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Creating I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Using I/O Ports View Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Using the Package Pins View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Opening the Package Pins View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

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 Using Package Pins View Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Using the Design Runs View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Opening the Design Runs View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Using the Design Runs View Popup Menu Commands . . . . . . . . . . . . . . . . . . . . . . . . 129
Configuring and Saving the Viewing Environment . . . . . . . . . . . . . . . . . . . . . . . . . 130
Customizing PlanAhead Display Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Configuring Schematic Slack and Fanout Display Options . . . . . . . . . . . . . . . . . . . . . 131
Adjusting Display using Toolbar Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Selecting a Theme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Creating and Using a Customized Theme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Moving Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Creating Custom View Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Restoring a View Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Restoring the Default View Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Using Undo/Redo Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Configuring PlanAhead Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Setting Selection Rule Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Configuring Shortcut Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Setting General PlanAhead Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Chapter 5: RTL Design

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Managing the Design Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Editing RTL Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Using the Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Using the Text Editor-specific Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Instantiating Xilinx Supplied Language Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Using Find Commands to Search Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Elaborating and Analyzing the RTL Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Validating RTL Design Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Setting Elaboration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Viewing Elaboration Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Highlighting Issues in the RTL Source files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Filtering the Results for Errors Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Using the RTL Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Analyzing Resource Statistics in the Instance Properties view . . . . . . . . . . . . . . . . . . 144
Analyzing the RTL Logic Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Analyzing the RTL Design Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Running RTL DRCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Selecting DRC Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Analyzing DRC Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
RTL Rules: Power and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Power DRCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Performance DRCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Estimating Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Chapter 6: Synthesizing the Design

About Synthesis and Implementation in PlanAhead . . . . . . . . . . . . . . . . . . . . . . . . 153
Running Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Synthesis Methodology Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

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 Setting Synthesis Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Using the XST Option to Create a Hierarchical Netlist . . . . . . . . . . . . . . . . . . . . . . . . 156
Controlling File Compile Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Launching Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Launching a Synthesis Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Configuring Synthesis Run Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Monitoring Run Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Selecting The Next Step After Synthesis Completes. . . . . . . . . . . . . . . . . . . . . . . . . 159
Analyzing Run Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Launching and Managing Multiple Synthesis Runs . . . . . . . . . . . . . . . . . . . . . . . . . 160

Chapter 7: Netlist Analysis and Constraint Definition

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Using the Netlist Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Viewing and Reporting Resource Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Viewing Resource Estimates in the Project Summary . . . . . . . . . . . . . . . . . . . . . . . . . 163
Generating Hierarchical Resource Estimates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Viewing Resource Statistics for Logic Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Viewing Resource Statistics for Pblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Using the Statistics Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Exporting Resource Statistics Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Exploring the Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Exploring the Logic Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Exploring the Logical Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Analyzing Hierarchical Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Searching for Objects Using the Find Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Using the Find Results View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Inserting ChipScope Debug Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Defining Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Editing Constraints in the Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Using Xilinx-Supplied UCF Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Using the Timing Constraints View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Modifying Timing Constraints Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Adding New Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Removing Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Running Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
About PlanAhead Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Timing Analysis Options for a Netlist Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Timing Analysis Options for an Implemented Design . . . . . . . . . . . . . . . . . . . . . . . . 178
Using the Report Timing Analysis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Understanding the Targets Tab Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Understanding the Choose Points Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Understanding the Advanced Options Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Understanding the Timer Settings Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Analyzing Timing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Sorting the Timing Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Flattening the List of Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Removing Paths from the Timing Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Displaying Path Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Displaying Timing Path Reports in the Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

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 Using Slack Histograms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Setting Slack Histogram Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Using Slack Histogram Timer Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Analyzing Timing Histogram Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Selecting Paths for Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Changing Histogram Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Defining Physical Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Using the Physical Constraints View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Using the ROOT Design Pblock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Understanding the Physical Constraints View Icons . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Working with Relatively Placed Macro (RPMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Running the Design Rule Checker (DRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Running I/O Port and Clock Logic DRCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Running Netlist and Constraint DRCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Viewing DRC Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
DRC Rule Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Chapter 8: I/O Pin Planning

I/O Planning Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
I/O Pin Planning Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
I/O Planning Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Creating Pin Planning Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Elaborating and Checking RTL Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Synthesizing Netlist Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Implementing the Design and Final I/O Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
I/O Port Placement Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Using the I/O Planner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Splitting the Workspace to Display Device and Package Views . . . . . . . . . . . . . . . . 210
Merging Views to One Tabbed Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Viewing Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Viewing Package Pin Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Viewing I/O Bank Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Viewing Clock Region Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Viewing Clock Region Resource Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Viewing Multi-Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Defining Alternate Compatible Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Setting Device Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Defining and Configuring I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Importing I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Importing a CSV Format File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Using Custom CSV I/O Port Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Importing a UCF Format File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Creating I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Configuring I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Setting I/O Port Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Defining Differential Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Configuring DCI_CASCADE Constraints (VIrtex5 and Virtex6 only) . . . . . . . . . . . 222
Modifying or Removing DCI Cascade Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Prohibiting I/O Pins and I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Creating I/O Port Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Disabling or Enabling Interactive Design Rule Checking . . . . . . . . . . . . . . . . . . . 226

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 Placing I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Placing I/O Ports into I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Placing I/O Ports in a Defined Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Sequentially Placing I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Swapping I/O Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Automatically Assigning I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Placing Gigabit Transceiver I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Placing I/O Related Clock Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Validating I/O and Clock Logic Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Running I/O Port and Clock Logic Related DRCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Viewing DRC Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Filtering the Violation List by Severity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
I/O Port and Clock Logic DRC Rule Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Global Clock DRCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
IOB DRCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Bank I/O Standard DRCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Removing I/O Placement Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Exporting I/O Pin and Package Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Exporting Package Pin Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Exporting an I/O Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Using Noise Analysis Predictors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Running SSN Analysis (Virtex-6 and Spartan-6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Viewing the SSN Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Resolving SSN Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Viewing I/O Bank Properties in SSN Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Defining the I/O Port Switching Phase Groups in SSN . . . . . . . . . . . . . . . . . . . . . . . . 243
Running WASSO Analysis (Spartan-3, Virtex-4, Virtex-5) . . . . . . . . . . . . . . . . . . . . . 244
Viewing the WASSO Analysis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Chapter 9: Implementing the Design

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Running Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Setting Implementation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Launching Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Launching an Implementation Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Configuring Implementation Run Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Monitoring Run Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Using the Project Status Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Cancelling a Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Viewing the Compilation Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Pausing Output as Commands are Running . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Determining Project Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Project Status Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Design State in the Flow Navigator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Design Data Out-of-Date Banner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Analyzing Run Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Viewing Report Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Viewing Compilation Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Filtering and Grouping Compilation Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Highlighting Compilation Issues in RTL Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Understanding the Project Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

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 Viewing Project Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Viewing Project State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Understanding Compilation Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Viewing Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Viewing Timing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Selecting The Next Step After Implementation Completes . . . . . . . . . . . . . . . . . . 260
Creating and Launching Multiple Runs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Managing Multiple Runs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Using the Design Runs View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Setting the Active Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Viewing and Modifying Run Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Overriding ISE Command Options Set in a Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Launching Selected Runs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Resetting Runs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Deleting Runs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Copying Runs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Opening a File Browser in a Run Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Launching Runs on Remote Linux Hosts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Limitations on Launching Runs on Remote Linux Hosts . . . . . . . . . . . . . . . . . . . . . . 268
Configuring Remote Hosts (Linux Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Chapter 10: Analyzing Implementation Results

Opening the Implemented Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Opening Multiple Implemented Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Importing ISE Results From Outside PlanAhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Using the New Project Wizard to Create an ISE Results Project . . . . . . . . . . . . . . . . 275
Importing Placement Results into Existing Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Importing ISE TRCE Timing Results into an Existing Project . . . . . . . . . . . . . . . . . . . 275
Analyzing Placement and Timing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Exploring Xilinx TRACE Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Using the Timing Results View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Using the Path Properties View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Viewing Timing Paths in the Device View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Viewing Timing Paths in Schematic View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Exploring Logic Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Using the Show Connectivity Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Viewing Logic Connectivity using Show Connectivity Mode . . . . . . . . . . . . . . . . . . 279
Expanding and Selecting a Logic Fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Expanding Logic in the Schematic View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Searching for Objects using the Find Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Highlighting Logic Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Highlighting Selected Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Using the Select Primitives and Highlight Primitives Commands . . . . . . . . . . . . . . 281
Unhighlighting Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Marking and Unmarking Selected Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Marking Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Removing Marks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Locking Placement for Future Implementation Runs . . . . . . . . . . . . . . . . . . . . . . . . 284
Using the Fix Instances Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Fixing Specific Types of Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

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 Fixing Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Displaying Design Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Using the Metrics View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Displaying the Metric Maps in the Device View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Removing the Metric Map Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Using the Metrics Results View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Configuring the Metric Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Launching XPower Analyzer for Power Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Launching FPGA Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Cross Probing Timing Paths to FPGA Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Chapter 11: Floorplanning the Design

Floorplanning Strategy Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Working with Pblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Creating Pblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Using the Draw Pblock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Using the New Pblock Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Creating Multiple Pblocks with the Create Pblocks Command . . . . . . . . . . . . . . . . . . 291
Creating Nested Pblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Creating Clock Region Pblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Understanding Pblock Graphics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Viewing Pblock Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Configuring Pblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Setting Pblock Logic Type Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Assigning Logic to Pblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Unassigning Logic from Pblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Moving and Resizing Pblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Moving a Pblock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Resizing a Pblock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Using the Set Pblock Size Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Using Resource Utilization Statistics to Shape Pblocks . . . . . . . . . . . . . . . . . . . . . . . . 302
Placing Pblocks Based on Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Displaying Bundle Net Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Adjusting Bundle Net Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Using Non-Rectangular Pblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Creating Non-Rectangular Pblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Modifying Non-Rectangular Pblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Removing a Pblock Rectangle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Setting Attributes for Pblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Renaming a Pblock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Deleting a Pblock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Running the Automatic Pblock Placer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Working with Placement LOC Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Understanding Fixed and Unfixed Placement Constraints . . . . . . . . . . . . . . . . . . . . . 308
Understanding Site and BEL Level Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Assigning Site Location Placement Constraints (LOCs) . . . . . . . . . . . . . . . . . . . . . . . 308
Assigning BEL Placement Constraints (BELs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Adjusting the Visibility of Placement Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Moving Placement Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Swapping Placement Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Deleting Selected Placement Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

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 Selectively Clearing Placement Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Unplacing Instances and I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Moving Pblocks with Placement Constraints Assigned . . . . . . . . . . . . . . . . . . . . . . . 313
Locking Placement During ISE Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Setting Placement Prohibit Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Interfacing with ISE Outside of PlanAhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Exporting Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Exporting Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Exporting Pblocks for ISE Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Chapter 12: Programming and Debugging the Design

Generating Bitstream Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Debugging the Design with ChipScope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Overview of ChipScope Integration in PlanAhead . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Requirements and Limitations When Using Core Insertion Flow . . . . . . . . . . . . . . . 319
Using the Core Insertion Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Deciding Which Debug Core Insertion Mode to Use . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Selecting Nets for Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Using the Unassigned Nets List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Using the ChipScope Wizard for Debug Core Insertion . . . . . . . . . . . . . . . . . . . . . . . 322
Importing a ChipScope CDC File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Selecting or Confirming Debug Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Specifying Debug Nets and Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Inserting ILA Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Using the ChipScope Window to Add and Customize Debug Cores . . . . . . . . . . . . 324
Creating and Removing Debug Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Adding, Removing, and Customizing Debug Core Ports . . . . . . . . . . . . . . . . . . . . . . 325
Connecting and Disconnecting Nets to Debug Cores . . . . . . . . . . . . . . . . . . . . . . . . . 326
Customizing Debug Core and Port Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Implementing Debug Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Exporting Net Connections CDC File for ChipScope Analyzer Tool . . . . . . . . . . . . . 328
Implementing the Design with the Debug Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Launching ChipScope Pro Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Launching iMPACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

Chapter 13: Using Hierarchical Design Techniques

Understanding PlanAhead and ISE Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Using Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Design Preservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Partial Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Hierarchical Design Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Using PlanAhead for Design Preservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Setting Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Viewing Partition Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Configuring Runs for Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Promoting Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Using the Promoted Partitions View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Deleting Promoted Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Importing Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Updating Netlist Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Setting Partition Actions Based on Logic Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

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 Chapter 14: Tcl and Batch Scripting
Overview of Tcl Capabilities in PlanAhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Tcl in Journal Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Tcl Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Tcl Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Invoking PlanAhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Tcl Shell Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
General Tcl Syntax Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Sourcing a Tcl Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
General Syntax Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Example Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Unknown Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Return Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Sourcing a Tcl Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
First Class Tcl Objects and Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Object Types and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Querying Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Object Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Filtering Based on Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Large Lists of Objects – Collections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Object Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Errors, Warnings, and Info Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Project Creation and Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Object Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
GUI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Tcl References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Tcl Developer Xchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
About SDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Available Tcl Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

Chapter 15: Using PlanAhead With Project Navigator

Integration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
PlanAhead Processes within Project Navigator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Passing Logic and Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
I/O Pin Planning (Pre-Synthesis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
I/O Pin Planning (Post-Synthesis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Floorplan Area/IO/Logic (Post Synthesis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Analyze Timing/Floorplan Design (Post Implementation) . . . . . . . . . . . . . . . . . . . . 354

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 Appendix A: PlanAhead Input and Output Files
Inputs to PlanAhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
RTL Source Files (Verilog, VHDL, or other design text files) . . . . . . . . . . . . . . . . . . . 357
I/O Port Lists (CSV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Top-Level Netlists (EDIF, NGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Module-Level Netlists and Cores (EDIF, NGC, NGO) . . . . . . . . . . . . . . . . . . . . . . . . . 358
Constraint Files (UCF / NCF / XNCF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Xilinx ISE Placement Results (NCD / XDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Xilinx TRCE Timing Results (TWX/TWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Outputs for Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
I/O Pin Assignment (CSV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
I/O Pin Assignment (RTL - Verilog or VHDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Log File (planAhead.log) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Journal File (planAhead.jou) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Error Log Files (planAhead_pidxxxx.debug & hs_err_pidxxxx.log) . . . . . . . . . . . . . 360
DRC Results (results_x_drc.txt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Timing Analysis Results (Excel file) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Netlist Module, Pblock, and Clock Region Statistics Reports . . . . . . . . . . . . . . . . . . . 361
SSN Analysis Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
WASSO Analysis Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Outputs for Environment Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
View Display Options File (planAhead.ini & theme_names.patheme) . . . . . . . . . . . 361
Window Layout Files (layoutname.layout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Shortcut Schema (default.xml) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Strategy Files (strategyname.psg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Outputs for Project Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Project Directory (projectname) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Project File (projectname.ppr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Project Data Directory (projectname.data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Project Data - Netlist Subdirectory (netlist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Project Data - Constraint Set Subdirectories and Files (constraint_set_name) . . . . . 364
Project RTL Directory (projectname.srcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Outputs for ISE Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
ISE Launch Scripts (jobx.bat/sh & runme.bat/sh & .ISE_command.rst) . . . . . . . . . 367

Appendix B: PlanAhead Terminology

Appendix C: Installing Releases with XilinxNotify

PlanAhead Release Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Running XilinxNotify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
XilinxNotify Network Installations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

Appendix D: Configuring SSH Without Password Prompting

Setting Up SSH Key Agent Forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

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 Chapter 1

Introduction
This chapter introduces the PlanAhead™ software and contains the following sections:
• “About PlanAhead Software”
• “Using PlanAhead”
• “Invoking PlanAhead”

About PlanAhead Software

The PlanAhead software is a design and analysis product that provides an intuitive
environment for the entire FPGA design and Implementation process. To allow a seamless
design experience for Xilinx FPGA designers, the PlanAhead software is integrated with
the:
• Xilinx® ISE® Design Suite software tools for Synthesis and Implementation
• CORE Generator™ tool
• ChipScope™ Pro debugging tool
• iMPACT device programming tool
• XPower Analyzer tool
• FPGA Editor tool
With PlanAhead, you can improve circuit performance by analyzing the design Register
Transfer Level (RTL) sources, synthesized netlists, and Implementation results. You can
experiment with different Implementation options, refine timing constraints, and apply
physical constraints with floorplanning techniques to help improve design results. Early
estimates of resource utilization, interconnect delay, power consumption, and routing
connectivity can assist with appropriate logic design, device selection and floorplanning.
The PlanAhead software includes a hierarchical data model that enables an incremental
design capability referred to as Design Preservation. By partitioning the design, unchanged
modules can be preserved, therefore providing consistent results and in some cases
reduced runtimes. Also, with appropriate licensing, the PlanAhead software allows access
to the Partial Reconfiguration design application. See Chapter 13, “Using Hierarchical
Design Techniques,” for an overview of these advanced design techniques.
You can use PlanAhead as a standalone software tool, or launch PlanAhead for specific
purposes from the ISE software. The full suite of PlanAhead features is available when you
launch it as a standalone tool, and a subset of specific features are available when launched
from Project Navigator; this subset is called ISE Integration Mode. Refer to Chapter 15,
“Using PlanAhead With Project Navigator,” for more information about integration with
Project Navigator.

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Chapter 1: Introduction

Using PlanAhead
You can use the PlanAhead software for FPGA design at a variety of starting points. In
PlanAhead, you can:
• Manage the design data flow from Register Transfer Level (RTL) development
through bitstream generation with a push button Run process
• Perform RTL design and analysis using an elaborated RTL netlist
• Customize and implement IP using the integrated CORE Generator tool
• Configure and launch multiple Synthesis and Implementation Runs
• Perform I/O pin planning
• Manage constraints and perform floorplanning
• Estimate the resource utilization, timing, power consumption and perform Design
Rule Checks (DRCs)
• Debug core insertion and Implementation with the integrated ChipScope debugging
tool
• Analyze Implementation results
• Launch programming and design verification tools

Project Creation and Management

PlanAhead provides a variety of options for project creation and management, as well as
creation of various constraint sets for exploration purposes. Refer to Chapter 3, “Working
with Projects,” for more information.

RTL and IP Design

The PlanAhead RTL Design environment lets you create and manage RTL design files. You
can customize and implement IP through integration with CORE Generator. In addition to
basic source file creation and management, PlanAhead provides RTL design elaboration
enabling RTL logic exploration, an RTL Schematic Viewer, a set of RTL DRCs, and
RTL-based resource and power estimation. Chapter 5, “RTL Design,” contains more
information.

Synthesis and Implementation

The PlanAhead software includes a Synthesis and Implementation environment that
allows multiple Synthesis and Implementation attempts using different software
command options, and timing or physical constraints. The Synthesis and Implementation
attempts or Runs can be queued to launch sequentially or simultaneously with multi-
processor machines using the Xilinx ISE Synthesis and Implementation software.
Chapter 6, “Synthesizing the Design,” describes how to use PlanAhead for Synthesis, and
Chapter 9, “Implementing the Design,” describes how to use PlanAhead for
Implementation.

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 Using PlanAhead

Design Analysis and Constraints Definition

The PlanAhead software provides an environment in which you can analyze the design at
each stage of the design process. Early resource, timing and power estimations along with
DRCs enable you to experiment with various devices, constraints, as well as Synthesis and
Implementation options to achieve desired results. After Implementation you can also
launch FPGA Editor and XPower Analyzer tools directly from PlanAhead.
These capabilities are available both before and after Implementation by analyzing the
synthesized netlist design or the implemented design results.
See Chapter 7, “Netlist Analysis and Constraint Definition,” and Chapter 10, “Analyzing
Implementation Results,” for more information.

Pin Planning
The PlanAhead software contains a I/O Planner environment that provides an interface to
analyze the design and device I/O requirements, and lets you define an I/O pinout
configuration or “pinout” that satisfies the requirements of both the Printed Circuit Board
(PCB) and the Field Programmable Gate Array (FPGA) designers. Chapter 8, “I/O Pin
Planning,” contains more information about I/O pin planning,

Floorplanning
The PlanAhead software supports a floorplanning methodology that lets designers
constrain critical logic to ensure shorter interconnect lengths with less delay and to ensure
more predictable Implementation results. You can floorplan a Design by creating physical
block (Pblock) locations to constrain logic placement, or by locking individual logic objects
to specific device sites. See Chapter 11, “Floorplanning the Design,” for more information
about the floorplanning capabilities in PlanAhead and to obtain references to the
Floorplanning User Guide (UG633), which is available on the Xilinx website.

Programming and Debugging Designs and ChipScope Integration

PlanAhead is integrated with the Xilinx ChipScope debugging tool, which lets you add
debugging cores into your design. After Implementation, you can access the ISE tools to
generate bitstream files, and launch the iMPACT and ChipScope Analyzer software tools
directly from PlanAhead. See Chapter 12, “Programming and Debugging the Design,” for
more information.

Hierarchical Design, Design Preservation, and Partial Configuration

PlanAhead software provides some advanced hierarchical design features to support
design preservation and partial reconfiguration methodologies. See Chapter 13, “Using
Hierarchical Design Techniques,” for more information. A new document, the
Hierarchical Design Methodology Guide (UG748), is also available to describe the Hierarchical
Design methodological process.

Tcl Commands and Batch Scripting

There are Tcl command and batch options available in PlanAhead, which are described in
Chapter 14, “Tcl and Batch Scripting.”

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Using PlanAhead with the ISE Project Navigator Environment

The PlanAhead software is integrated within the Xilinx ISE Design Suite in the Project
Navigator software tool to provide an environment for improving your design results
throughout the design flow.
Project Navigator launches PlanAhead automatically at four different design process
steps:
• Pre-Synthesis:
− I/O pin planning
• Post-Synthesis:
− I/O pin planning
− Floorplan Area/IO/logic
• Post-Implementation:
− Analyze Timing and Floorplan design
See Chapter 15, “Using PlanAhead With Project Navigator,” for information about the
PlanAhead in the ISE Integration mode.

Input and Output Files

The PlanAhead software has a variety of input and output file types and formats. See
Appendix A, “PlanAhead Input and Output Files,”for descriptions of the input and output
files.

PlanAhead Terminology
The PlanAhead software uses specific terminology which is used throughout this
document, and is described in Appendix B, “PlanAhead Terminology.”

Accessing Updates
Xilinx uses a XilinxNotify utility that notifies you when there are updates available. See
Appendix C, “Installing Releases with XilinxNotify,” for more information.

Configuring Multiple Linux Hosts

The multiple host capabilities for executing PlanAhead software Runs uses the Secure
Shell (SSH), a service provided by Linux operating system. Prior to configuring multiple
hosts in the PlanAhead software, you can configure SSH so that you are not prompted for
a password each time you log in to a remote machine. See Appendix D, “Configuring SSH
Without Password Prompting,” for the commands to configure SSH without password
prompting.

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Invoking PlanAhead
You can invoke the PlanAhead software from any directory; however, invoking it from a
“project” directory might prove advantageous because project-specific log files can be
located more easily.
Note: Refer to the Xilinx ISE Design Suite: Installation, Licensing, and Release Notes for proper
installation of this product.

Linux
To invoke PlanAhead in Linux, type the following command at the Linux command
prompt:
# planAhead

Windows
To invoke PlanAhead in Windows, double-click the Xilinx PlanAhead 12 shortcut icon,
shown in Figure 1-1.

Figure 1-1: PlanAhead Icon

You can specify the PlanAhead Start in folder by modifying the desktop icon properties to
define where to write the PlanAhead log files.
The PlanAhead Environment opens to the Getting Started Page as shown in Figure 1-2.

Figure 1-2: PlanAhead Getting Started Page

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The PlanAhead Getting Started page assists you with creating or opening projects as well
as viewing the PlanAhead documentation. You can display the Getting Started jump page
by closing all open projects.

Using the Getting Started Page

When you invoke PlanAhead the Getting Started page displays. Select the command links
to invoke specific commands or to view documentation. The Getting Started options are:
• Create New Project—Invokes the New Project Wizard which lets you create any type
of PlanAhead project.
• Open Project—Invokes a browser enabling you to open any PlanAhead
project.ppr file.
• Open Recent Design—Displays the last 10 previously opened projects to reopen (by
default; this number is configurable in the General dialog box by selecting Tools >
Options > General). PlanAhead checks to ensure the project data is available before
displaying the projects.
• Open Example Project—Provides four sample design projects:
− A small RTL project BFT Core
− A larger RTL project CPU (HDL)
− A netlist-based project CPU (synthesized)
− An IP example with three embedded IP cores from CORE Generator,
Wave (HDL). You can use this design as a reference project to see how you can use
IP cores with PlanAhead projects.
You can open or download the PlanAhead documentation by selecting the documentation
links which then launch a PDF viewer or website download location.
• What’s New—Document describing the new features on PlanAhead.
• User Guide—Invokes the PlanAhead User Guide.
Note: PlanAhead ships with a placeholder PDF file for the User Guide. In that file, you are guided to
a web URL to download the latest document. There are simple installation instructions to enable the
link to then invoke the full local copy of the User Guide when selected.
• PlanAhead Methodology Guides—Web links to the Floorplanning Methodology Guide
and the Hierarchical Design Methodology Guide.
• PlanAhead Tutorials—A web link to a landing site containing all PlanAhead
tutorials and required sample design data.
All PlanAhead documentation is available in PDF format at the following web location:
http://www.xilinx.com/planahead

PlanAhead Command Line Options

PlanAhead has several command line options to control the behavior. To view the
PlanAhead command line options, type the following command at the command prompt:
# planAhead -help
A help menu displays in the shell window.

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Using a PlanAhead Startup Tcl Script

You can use the PlanAhead Tools > Run Tcl Script command to run a script. Also, you can
copy PlanAhead Tcl commands from the planAhead.jou file to create startup scripts.
Figure 1-3 shows a code snippet from a Tcl script.

Figure 1-3: Example PlanAhead Tcl Script

For more information about the PlanAhead journal file, see “Journal File (planAhead.jou),”
page 360. For more information about scripting actions for PlanAhead with Tcl, see
Chapter 14, “Tcl and Batch Scripting.”

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Understanding the PlanAhead Design Flow

This chapter contains the following sections:
• “PlanAhead Design Flows”
• “Design Flow”
• “User Models”
• “Understanding the Flow Navigator”
• “Working with Designs”

PlanAhead Design Flows

You can use the PlanAhead™ software, “PlanAhead,” at various places in the design flow.
The flows described in the following subsections also correspond to the project types that
can be created in PlanAhead. Project types are described in more detail in Chapter 3,
“Working with Projects.”
Design analysis and constraint definition capabilities are available at each stage of the
design flow, including elaborated Register Transfer Level (RTL) design, synthesized netlist
design, or any of the implemented design Runs.

RTL to Bitstream
You can use the PlanAhead software to manage the entire design flow process from RTL
development, IP customization, Synthesis and Implementation all the way through to
programming the device. You can add Verilog and Verilog Hardware Definition List
(VHDL) RTL sources, Intellectual Property (IP) cores, and constraints to a project. You can
experiment with Synthesis and Implementation options and constraints to help meet your
design objectives. Refer to Chapter 5, “RTL Design,” for more information.

Synthesized Netlist to Bitstream

PlanAhead can manage the back-end Implementation design flow process through to
programming the device. You can add synthesized netlists, netlist-based IP cores, and
constraints to a project. You can experiment with Implementation options and constraints
to help meet your design objectives.

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Device Exploration and I/O Pin Planning

PlanAhead provides an I/O planning environment in which you can analyze the device
resources and visualize the relationships. Proper clocking and I/O planning can improve
device performance and routability. It can also drastically improve Printed Circuit Board
(PCB) routing, signal integrity, and device system performance.
• You can start with an empty project and do device exploration and early I/O pin
planning.
• You can create I/O ports “on-the-fly” or import them from either Comma Separated
Value (CSV) or User Constraint File (UCF) formats.
You can perform I/O planning at each stage of the design process. The most
comprehensive Design Rule Checks (DRCs”) are available once a synthesized netlist is
produced, because clock and lock logic are available for analysis and placement. Refer to
Chapter 8, “I/O Pin Planning,” for more information.

Analyze Implemented Design Results

You can use PlanAhead to analyze the Implementation results that were generated with or
outside PlanAhead. You can examine placement and timing results to determine if RTL
changes, timing constraint adjustments, or floorplanning alterations are necessary.

Partial Reconfiguration
PlanAhead provides an environment to set up and manage a Partial Reconfiguration design
project. These design types require special software features and project structure to
manage the modules that are reconfigurable. This software feature is only available under
special licensing. Fore more information about Partial Reconfiguration, refer to
www.xilinx.com/tools/partial-reconfiguration.

Design Flow
This section describes the PlanAhead Design flow and Design tasks.

Design Flow Diagram

The common design flows, and the input and output formats of the PlanAhead software
are displayed in Figure 2-1, page 33.

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Figure 2-1: PlanAhead Design Flows

Design Flow Tasks

The following subsections describe the PlanAhead software design flow tasks in
sequential order.

Project Creation and Management of Project Sources

PlanAhead provides a wizard flow to facilitate project creation and the creation or addition
of source files to the project. You can:
• Create projects specific to the type of flow and sources you are using.
• Create new source files or add existing source files to the project.
• Reference remote, write-protected files or copy files into the local project folder.
• Disable or enable source files within a project.
• Create constraint sets to experiment with various constraints options or devices.
The PlanAhead project environment lets you create and store multiple variations of the
design constraints within a single project. This allows for the creation of multiple RTL
source versions, constraints sets, target devices, synthesized netlists, and Implementation
Run results using various Implementation strategies. As you modify the source files or
launch design tools, the software monitors and displays design flow status.

IP Customization and Implementation

You can use the integrated CORE Generator™ tool to browse, customize, instantiate, and
implement IP.

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RTL Development and Analysis

PlanAhead includes an integrated text editor to create or modify source files. You can copy
example logic constructs directly from the supplied Xilinx template library. PlanAhead
contains a Find in Files feature that lets you search these libraries using a variety of search
criteria.
You can then elaborate the RTL design to check RTL structure, syntax, and logic
definitions.
Opening RTL Design or the I/O Planner will elaborate the RTL design and load the RTL
netlist automatically. Analysis and reporting capabilities include:
• RTL compilation validation and syntax checking
• Netlist and schematic exploration
• Design Rule Checks (DRCs)
• Resource utilization and power consumption estimation
Also, early I/O pin planning is enabled using the RTL port list.
All views cross-select objects including instantiations and logic definitions within the
source files.

Logic Synthesis
PlanAhead lets you configure, launch, and monitor Synthesis Runs using the Xilinx®
Synthesis Technology (XST) tool.
You can experiment with different Synthesis options and create reusable strategies for
Synthesis Runs. For example, you could create strategies for power, performance, or area
optimization.
The Synthesis Run results display interactively and PlanAhead creates report files that are
easily accessible. You can select Synthesis Warnings and Errors from the Compilation
Messages view to highlight the logic in the source files.
• You can launch multiple Synthesis Runs simultaneously or serially.
• On a Linux system you launch Runs on remote servers.
When you have multiple Synthesis Runs, those Runs create multiple netlists which are
stored within the PlanAhead software project. The PlanAhead software then lets you load
the various versions of the netlist into the environment for analysis. After the netlist
import, you can perform device and design analysis, create constraints for I/O pin
planning, floorplanning, and implementation.

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I/O Pin Planning

The PlanAhead software provides a comprehensive I/O pin planning environment that
enables correct “by-construction” I/O port assignment either onto specific device package
pins or onto internal die pads. PlanAhead offers a variety of display views and tables in
which to analyze and design package and design I/O related data.
You can examine the internal I/O connectivity to ensure proper data flow through the
device as well as optimal access to internal device resources. System performance can be
improved by examining both the external and internal connectivity requirements and then
making informed decisions.
To ensure compliance to connectivity requirement, PlanAhead provides DRCs and
Simultaneous Switching Noise (SSN) analysis.
You can use a variety of source input formats to begin I/O pin planning including: CSV,
UCF, RTL, or synthesized netlists.
When you use a synthesized netlist as the source, the DRC coverage improves
substantially because often the clock logic dictates proper I/O assignment. The final I/O
verification step is to run the complete design through the Implementation tools.

Netlist Analysis and Constraints Definition

The PlanAhead software has design analysis and constraints assignment capabilities. The
design data is presented in many different forms using cross-selecting and coordinating
views.
PlanAhead provides interactive graphical representation views of the internal die and
external package through which you can analyze device resources and apply constraints.
Also, you can apply and analyze timing and physical constraints.
Early timing analysis, resource estimation, connectivity analysis, and DRCs help identify
design issues prior to Implementation.

Implementation
The PlanAhead software lets you configure, launch, and monitor Implementation Runs
using the ISE® Design Suite.
You can experiment with different Implementation options and create reusable strategies
for Implementation Runs. As an example, you can create strategies for quick runtimes,
performance, or area optimization.
The Implementation Run results display interactively, and report files are accessible. Also,
You can launch multiple Implementation Runs either simultaneously or serially; using the
Linux platform you can use remote servers. In PlanAhead, you can create Constraint Sets so
you can experiment with various logical constraints, physical constraints, or alternate
devices.

Results Analysis and Floorplanning

The PlanAhead software then lets you load the various Run results interactively for
analysis and floorplanning. The capabilities in the Implemented Design are described in
Chapter 7, “Netlist Analysis and Constraint Definition,” and Chapter 10, “Analyzing
Implementation Results.”
You can import results from any PlanAhead launched Run.

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When you open an Implemented Design, the original netlist, constraints and
Implementation results are loaded into the Results Viewer. You can open multiple designs
simultaneously. You can also launch XPower Analyzer and FPGA Editor tools directly
from PlanAhead for further design analysis.
Note: In Release 12.x, the constraints that were used to launch the Run are not loaded. Instead, the
active constraint set in PlanAhead displays when an Implemented Design is opened.

Device Programming
You can create programming bitstream files for any completed Implementation Run. Bit
file generation options are configurable, and you can launch the iMPACT tool to configure
and program the part.

Design Verification and Debug

You can configure and implement the Integrated Logic Analyzer (ILA) and ICON
ChipScope™ Pro debugging tool debug cores in the Netlist Planner, and select and
configure the required probe signals into cores. Then you can implement and manage the
cores from within the Netlist Planner. You can launch the ChipScope Analyzer tool on any
Run with a completed bitstream file.
Also, you can launch the ChipScope Analyzer tool directly from PlanAhead for further
analysis of the routing or device resources.

User Models
PlanAhead provide a Graphical User Interface (GUI) with “layered complexity.” It
provides an intuitive environment for new or casual users and also enables easy access to
the more advanced features. By default, PlanAhead opens with a push button flow suitable
for users that do not require more advanced analysis and floorplanning features. The flow
is controlled by a view called the Flow Navigator, which is described in “Understanding
the Flow Navigator,” page 37.

Basic User Flow

PlanAhead gives you the ability to execute the entire development cycle using the Run
buttons in the PlanAhead Flow Navigator. You can traverse the FPGA development
process front-to-back, beginning with importing source files, synthesizing design logic,
implementing synthesized netlists, analyzing the results, generating bitstreams, and
launching programming and verification tools.

Advanced User Features

PlanAhead provides a series of analysis environments at each stage of the design flow for
advanced design configuration and analysis. You can load the elaborated RTL design,
synthesized netlist design, and Implementation results into PlanAhead for analysis and
constraint definition. These environments are described in “Working with Designs,”
page 41.
The PlanAhead project environment lets you create and store multiple variations of the
design within a single project. This allows for the creation of multiple RTL source versions,
constraints sets, target devices, synthesized netlists, and Implementation Run results using
various Implementation strategies. And as you modify the source files or launch design
tools, the software provides a design status.

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You can configure, launch, and monitor multiple Synthesis and Implementation Runs
locally or on remote Linux servers. You can experiment with different command options,
constraints, or devices.
Note: The advanced flexibility in PlanAhead to create multiple versions of a design and multiple
Runs requires user control for design data management and version control.

Understanding the Flow Navigator

The Flow Navigator provides control over the major design process tasks such as project
configuration, Synthesis, Implementation, and bitstream creation. As these tasks are
completed, you can open the resulting designs to analyze results and apply constraints by
clicking the RTL Design, Netlist Design or Implemented Design buttons. When open, each
of these Designs exposes a set of commonly used sub-tasks for the applicable phase of the
flow.
The options that are available to you depend on the status of the design. Inapplicable steps
are greyed out until the appropriate design tasks are completed.
The following figures illustrate how the PlanAhead Flow Navigator view is used to
perform design tasks and to open the analysis environments at various stages of the design
process.

Using the Flow Navigator with an RTL Project

Figure 2-2 illustrates and describes the design flow when you use RTL sources as input to
PlanAhead.

Figure 2-2: PlanAhead Flow Navigator (RTL Project)

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Using the Flow Navigator with a Synthesized Netlist Project

Figure 2-3 illustrates and describes the design flow for synthesized netlist-based projects.

Figure 2-3: PlanAhead Flow Navigator (Synthesized Netlist Project)

Launching Commands from the Flow Navigator

The Flow Navigator facilitates a push button flow by enabling Synthesis and
Implementation to be run immediately after you add Sources to a project. There is no need
to open any of the Design environments to complete the design. The following subsections
describe how to implement a design with the Flow Navigator.

Using the Project Manager

When you open a project, the Project Manager opens by default. You can open the Project
Manager by selecting the Project Manager button in the Flow Navigator.
When you open the Project Manager, no design compilation is performed and no design
data is loaded into memory. This environment enables creating, importing, and managing
source files and constraint sets. You can use the Project Manager to browse, customize, and
create IP from the Xilinx IP catalog also.

The Project Manager displays the Sources and Project Summary views by default.
• For more information on using the Sources view to configure Project Sources, refer to
“Using the Sources View,” page 104.
• For more information on the Project Summary view, refer to “Understanding the
Project Summary,” page 257.
• For more information on customizing IP, see “Configuring IP using the CORE
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The Project Manager Flow Navigator menu contains the following commands:
− Project Settings—Opens the Project Settings dialog box. Refer to“Setting
Command Options,” page 39 for more information.
− Add/Create Sources—Invokes the Add/Create Sources dialog box. Refer to
“Managing Project Sources,” page 57.
− Add Existing IP—Enables importing existing CORE Generator™ project files and
resulting IP in the project. Refer to “Managing Project Sources,” page 57.
− Add/Create Constraints—Invokes the Add/Create Constraints dialog box. Refer
to “Adding and Managing Constraints,” page 68.
− IP Catalog—Opens the IP Catalog view. Refer to “Configuring IP Catalog
Settings,” page 77.
− Elaborate—Elaborates the RTL design and displays messages in the Elaboration
Messages view. Refer to “Elaborating and Analyzing the RTL Design,” page 141.
− Project Summary— Displays the Project Summary view. For more information
on the Project Summary view, refer to “Understanding the Project Summary,”
page 257.

Setting Command Options

You can set Synthesis and Implementation options by clicking Project Settings in the
Project Manager or Main toolbar. These options are also available from pulldown menus
within the Synthesis and Implementation buttons in the Flow Navigator. Figure 2-4 shows
the Project Settings button.

Figure 2-4: Main Toolbar Project Settings Button

See Chapter 6, “Synthesizing the Design,” and Chapter 9, “Implementing the Design,” for
more information.

Running Synthesis
After you add Sources to a project, you can use the Synthesis option to launch the XST
Synthesis tool. Figure 2-5 shows the Flow Navigator Synthesis button.

Figure 2-5: Flow Navigator Synthesize Button

See Chapter 6, “Synthesizing the Design,” for more information.

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Running Implementation
Once Synthesis has completed, you can run the ISE Implementation tools in the Flow
Navigator by clicking the Flow Navigator Implement button. Figure 2-6 shows the
Implement button.

Figure 2-6: Flow Navigator Implement Button

See Chapter 9, “Implementing the Design,” for more information.

Generating Bitstream Files

Once Implementation has completed, you can generate bitstream files and launch the
debugging and programming tools from the Flow Navigator by clicking the Program and
Debug button, which is actually a menu of available commands. Figure 2-7 shows the
Program and Debug button.

Figure 2-7: Flow Navigator Program and Debug Button

Refer to “Generating Bitstream Files,” page 317 for more information.

Launching Programming and Debug tools

PlanAhead can launch the ISE debugging and programming tools automatically including
iMPACT and the ChipScope analyzer. The ChipScope analyzer and iMPACT require a bit
file and are available only after the Generate Bitstream command is run. Figure 2-8,
page 41 shows the Program and Debug button.

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Figure 2-8: Flow Navigator Launch Programming and Debug Tools

Refer to Chapter 12, “Programming and Debugging the Design,” for more information.

Working with Designs

PlanAhead enables “Designs” to be opened at various stages of the design process. A
Design is defined as a netlist (elaborated RTL or synthesized), a constraint set, and a target
device. PlanAhead loads the Design into memory for analysis, constraint definition, or
ChipScope debug core insertion.
The Flow Navigator has buttons for RTL Design, Netlist Design, and Implemented Design.
The Implemented Design loads the specific design data used to launch the Run. You can
open the RTL and Netlist Designs with different target devices or constraint sets allowing
experimentation and constraints version control.
You can analyze the design at various stages of completion, including elaborated RTL,
synthesized netlist, or the implemented results. You can perform constraint modifications
such as timing or floorplanning at any phase by opening the corresponding Design.
Constraint change management is made possible by the ability to create and manage
multiple constraints sets. The available design levels of abstraction that you can open as
Designs in the PlanAhead environment are:
• RTL Design—Elaborated RTL design, constraint set, and target device
• Netlist Design—Synthesized netlist, constraint set, and target device
• Implemented Design—Netlist, constraints, and results from any implemented Run
For all Design views, the Design Planner view layout displays by default. You can select
the I/O Planner button in the view banner to toggle between view layouts depending on
the tasks you want to perform. See “Toggling Between I/O Planner and Design Planner,”
page 87.

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Opening an RTL Design

When you select the RTL Design button in the Flow Navigator, PlanAhead elaborates the
RTL design automatically and loads it into memory along with the active constraint set
and the target device. Elaboration messages display in the Elaboration Messages view.
To open a RTL Design select either:
• RTL Design in the Flow Navigator, to load the elaborated netlist and the active
constraint set and target device.
• The Open RTL Design command in the RTL Design pulldown menu of the Flow
Navigator, where you can specify an alternative constraint set and target device to
load into the design.
The RTL Netlist view displays the compiled logic hierarchy. See Chapter 5, “RTL Design”
for more information on analyzing the RTL logic design.
See Chapter 8, “I/O Pin Planning,” for more information about using the I/O Planner for
I/O pin planning.

Using a Netlist Design

The Netlist Design consists of combination of a synthesized netlist, a constraint set and a
target device. PlanAhead allows for multiple Synthesis Runs, and also provides support
for analysis of multiple Netlist Designs using varied combinations of these inputs. The
Design is loaded into memory and can be analyzed in either the I/O Planner or the Design
Planner.

Opening a Netlist Design

To open a Netlist Design select either the:
• Netlist Design button in the Flow Navigator, to open the active synthesized netlist
with the active constraint set, and the target device.
• Open Netlist Design command in the Netlist Design pulldown menu of the Flow
Navigator, where you can specify an alternative constraint set and target device to be
loaded with the Design. Figure 2-9 shows the Open Netlist Design dialog box.

Figure 2-9: Opening Netlist Design Dialog Box

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The Open Netlist Design dialog box lets you enter:

• Design Name—Enter a name to display in the view banner. The design is stored in
memory during the PlanAhead session only.
• Constraint Set—Select an existing constraint set to be opened against the netlist.
• Part—Select a target part.
Figure 2-10 shows the Open Netlist Design view.

Figure 2-10: Open Netlist Design

• For more information on using the Netlist Planner to analyze and constrain the
design, refer to Chapter 7, “Netlist Analysis and Constraint Definition.”
• See Chapter 8, “I/O Pin Planning,”for more information about using the I/O Planner
for I/O pin planning.

Setting the Active Netlist

If multiple Synthesis Runs exist, PlanAhead displays information and reacts to the “active
Run,” which displays in bold text in the Design Runs view. The Project Summary and
Compilation Messages areas display information about the active Run only.
Select the Synthesis Run in the Design Runs view and use the Make active popup menu
command to set the active netlist. PlanAhead then uses that netlist by default when
opening Designs or launching Runs.
For more information on creating and managing multiple Synthesis Runs, see
“Synthesizing the Design” in Chapter 6.

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Opening an Implemented Design

An Implemented Design consists of a completed Implementation Run only. Because
PlanAhead allows for multiple Implementation Runs, you can select any Implementation
Run to open in the Implemented Design view. The Implemented Design imports the
netlist, placement, and timing results from the Implementation Run directory. PlanAhead
loads the design into memory where you can analyze it in the Design Planner
environment.
To open a implemented design, select one of the following:
• The Implemented Design button in the Flow Navigator to open the active synthesized
netlist with the active constraint set, and the target device for a project.
• Open Implemented Design from the Implemented Design pulldown menu in the
Flow Navigator and then select any implemented Run listed.
• Select any completed Implementation Run in the Design Runs view and use the Open
Implemented Design popup menu command (or double-click on the Run).
The Design Planner view layout opens. Typically, you do placement and timing analysis
and floorplanning in this environment. Figure 2-11 shows the Implemented Design view.

Figure 2-11: Implemented Design View Layout

You can open multiple Implemented Design views simultaneously to display results from
multiple Runs.

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Tabs at the top of the view layout indicate which Run results are open and which are
displayed. For information on creating and managing multiple Implementation Runs, see
“Managing Multiple Runs,” page 263.
Note: Some capabilities that involve manipulation of the netlist, altering design partitions or Partial
Reconfiguration control might be restricted in the Implemented Design. You might need to open the
Netlist Design for these operations to ensure you are operating on the proper data.

Managing Open Designs

As you open Designs and PlanAhead loads the design into memory, an icon displays
within the appropriate button in the Flow Navigator. This provides a visual reference of
the data in memory and can help manage the PlanAhead session, as shown in Figure 2-12.

Figure 2-12: Open Design Indicator Icon

When multiple designs are open simultaneously, multiple icons display.

Closing Designs
You can close designs to reduce the number in memory and to prevent multiple locations
where sources could be edited. In some cases, you are prompted to close a design prior to
changing to another design representation. In some cases, such as for a Partial
Reconfiguration design, you must close the design when leaving the design.
You can close individual designs by clicking the Close button in the banner of the main
viewing area. You can close all designs by selecting the Close Design command from the
pulldown menu on any Design Button in the Flow Navigator.

Understanding the Open Design View Banner

The view banner reflects the design name, constraint set, and target part as shown in
Figure 2-13.

Figure 2-13: Open RTL Design Banner

As source files are updated, a banner appears at the top of the open RTL Designs indicating
that a newer version of the design data is available. You are prompted to reload what is
loaded in memory.

Selecting the I/O Planner or Design Planner View Layout

In RTL or Netlist Designs, you can elect to display either the Design Planner or the I/O
Planner view layouts. There are buttons in the Design view banner to toggle between the
two view layouts. Each one provides views appropriate for design task you are doing, as
shown in Figure 2-4, page 39.

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Using the Design is Out of Date and Reload Banner

In the course of any design process, source files often require modification. PlanAhead
manages the dependencies of these files and indicates when displayed design data is out-
of-date. Changing project settings can trigger an out-of-date status on a project also.
As source files, netlists, or Implementation results update, a banner opens at the top of any
open Planners indicating that a newer design data version is available than what is loaded
in memory. PlanAhead prompts you to reload to memory. Figure 2-14 shows the out-of-
date banner. Selecting the Reload button refreshes the data in memory.

Figure 2-14: Design Out of Date and Reload Banner

If a design step needs to be run to update the data, the Status Bar and Project Summary
indicate an out-of-date status. PlanAhead provides a link to run the next required step,
such as Synthesis or Implementation.

Toggling Multiple Open Designs

If multiple Designs are open, tabs display that allow you to toggle between the open
designs.
You can use the make active link in the view banner to set the constraint set associated with
the design as the active constraint set as shown in Figure 2-15.

Figure 2-15: Multiple Open Design Tabs

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 Chapter 3

Working with Projects

This chapter contains the following sections:
• Understanding PlanAhead Project Types
• Creating a New Project
• Managing Project Sources
• Adding and Managing Constraints
• Configuring Project Settings
• Creating Synthesis and Implementation Strategies

Understanding PlanAhead Project Types

You can use the PlanAhead™ software at different points in the FGPA design flow for
various reasons. To accommodate this, you can create the following types of PlanAhead
projects:
• Register Transfer Level (RTL) source-based
• Synthesized netlist-based
• Implemented design results-based
• I/O pin planning projects - Comma Separated Values (CSV), User Constraint File
(UCF)-based
• Projects created in Project Navigator
• Partial Reconfiguration projects (when license is enabled)
These projects are differentiated by the input source types used to create the project. You
can select the type of project during the Create New Project process.
Once you select a particular project type, it cannot be migrated to a different type later.
Note: PlanAhead uses a derivative type of project to support Partial Reconfiguration designs. This
capability is available only through special licensing, and is covered in the Partial Reconfiguration
User Guide (UG702).

RTL Source-Based Projects

You can use the PlanAhead software to manage the entire FPGA design flow from RTL
creation through bitstream generation. You can add RTL source files as well as IP
generated by CORE Generator™ and precompiled NGC/NGO-format IP netlists to the
project.

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You can elaborate and analyze the RTL to ensure proper constructs, launch, and manage
various Synthesis and Implementation Runs, and analyze the design and Run results.
Also, you can experiment with different constraints or Implementation strategies.

Synthesized Netlist-Based Projects

You can create projects from designs that were synthesized outside of PlanAhead using the
Xilinx® Synthesis Technology (XST) tool or any supported third-party Synthesis tool.
PlanAhead can import EDIF and NGC/NGO-format netlists. The netlist can be all-
inclusive in a single file or hierarchical in nature, consisting of multiple, module-level
netlists.
You can analyze the logic netlist, launch and manage various Implementation Runs, and
analyze the design and Run results. Also, you can experiment with different constraints or
Implementation strategies.

Implemented Design Results-Based Projects

You can create projects to allow analysis of Implementation results created outside of
PlanAhead using the Xilinx command line tools. The design netlist, Implementation, and
timing results can be imported to explore timing or placement related issues.

I/O Pin Planning Projects

You can perform I/O pin planning early in the design cycle by creating an empty I/O Pin
Planning project. You can create I/O ports within PlanAhead or import them with either
CSV or UCF input files. After I/O pin assignment, PlanAhead can create CSV, UCF, and
RTL output files for use later in the design flow when RTL sources or netlists are available.
The output files can also be used to create schematic symbols for use in the Printed Circuit
Board (PCB) design.
Also, you can create pin planning projects to explore the logic resources available in the
different device architectures.

Project Navigator Created Projects

For information about the project creation process used when PlanAhead is launched from
the ISE® Project Navigator environment, refer to Chapter 15, “Using PlanAhead With
Project Navigator.”

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Creating a New Project

The following subsections describe how to create a project, and the project options
available within the wizard.

Using the Create New Project Wizard

The New Project wizard takes you through the individual steps to define a project name
and location, add source files and constraint files to the project, and select a target device.
To create a new project:
1. Select one of the following commands:

• On the Getting Started jump page click the Create a New Project link.
• Select File > New Project.
The first dialog box of the New Project wizard gives an overview of the wizard.
2. To continue, click Next.
The Project Name page opens as shown in Figure 3-1.

Figure 3-1: New Project Wizard: Project Name Page

Entering a Project Name and Location for the Project

Enter a project name and location as follows:
3. In the Project Name page, specify a project name and disk storage location:
• Project name—Enter a name to identify the project directory (for example,
project_3).
• Project location—Enter a location to create the project directory.
4. After defining the required selections, click Next.

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Selecting the Design Source Data Type

Designate the Design Source input format by selecting one of the options shown in
Figure 3-2.

Figure 3-2: New Project Wizard: Design Source Page

5. After you select the design source, click Next.

6. Depending upon the design input, continue with the instructions in one of the
following sections:
• Creating a Project with RTL Sources
• Creating a Project with a Synthesized Netlist
• Creating an I/O Planning Project
• Creating a Project with ISE Placement and Timing Results
The next pages of the wizard will guide you through adding appropriate sources to the
project based on the project type you selected in the previous steps.

Creating a Project with RTL Sources

You can specify RTL source files to create a project. This can be used for RTL code
development and analysis purposes as well as Synthesis and Implementation. See
Chapter 5, RTL Design for more information on RTL development and analysis.
1. Follow the project creation steps described in Creating a New Project, page 49.
2. In the Design Source page shown in the following figure, select the Specify RTL
Sources option.

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Importing Settings from XST or Synplify Projects

You can optionally import an existing project file created for either XST or Synplify
Synthesis tools in to more easily add the source files contained in those projects to the new
PlanAhead project. In addition, settings such as top-module, target device, and VHDL
library assignment can also be imported from these existing project files.
To import an existing XST or Synplify project file:
1. In the Design Source page, click the checkbox for Import settings from XST or Synplify
project beneath the Specify RTL Sources option.
2. Select one of the following options from the Import Settings from XST or Synplify
Project dialog box:
• Import XST- Browse to specify an existing XST project file (.xst)
• Import Synplify - Browse to specify an existing Synplify project file (.prj)
• Do not import settings at this time - Do not specify an existing project file at this
time, and instead proceed to manually specify source files and settings.
3. Click Next.

Adding Source Files or Directories

The next page in the New Project wizard lets you select RTL source files or directories that
contain RTL source files. Additionally, you can choose to create new RTL source files from
this page, as shown in Figure 3-3.
Note: If you imported an XST or Synplify project file the source files that were detected in the
specified project file are displayed automatically in the Add Source table. You can add or remove files
from this list as described.

Figure 3-3: New Project Wizard: Add Sources Page

1. In the Add/Create Sources dialog box, use the options as follows:

• Add Files—Invokes the file browser to select RTL files to add to the project.
VHDL libraries can be specified by selecting from the drop down menu or typing
in a library name in the Library column of the Add/Create Sources dialog table.

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• Add Directories—Invokes directory browser to add all RTL source files from the
selected directories. Files in the directory hierarchy with valid source file
extensions are added to the project.
• Create File—Invokes the Create Source File dialog where you can create new
VHDL, Verilog, or Verilog Header files. For more information, see Creating
Source Files, page 57.
• Remove—Removes the selected source files from the list of files to be added.
• Copy Sources into Project—Copies the original source files into the PlanAhead
project and uses the local copied version of the file in the project. If you elected to
add directories of source files using the Add Directories option, the directory
structure is maintained when the files are copied locally into the project.
• Add Sources from Subdirectories—Adds files from all subdirectories of any
directories specified using the Add Directories option.
When adding sources, you can click on the Library field, and enter or select a library
name for the file or directory
Note: Selections made for Copy Sources into the Project and Add Sources from
Subdirectories are preserved for future PlanAhead sessions.
2. After adding the intended source files or directories, click Next.
Continue with the steps in section Adding Constraint Files to RTL and Netlist Projects,
page 53.

Creating a Project with a Synthesized Netlist

You can import synthesized netlists along with corresponding constraints to create a
PlanAhead project. You can then analyze, floorplan, or implement the design using the
Floorplanning and Implementation environment.
1. Follow the project creation steps described in Using the Create New Project Wizard,
page 49.
2. Select the Specify synthesized (EDIF or NGC) netlist option in the Design Source page.

Selecting a Top-Level Netlist and Module Search Path

The next page in the New Project wizard, shown in Figure 3-4, page 53 lets you specify a
top-level netlist file and a search path to find lower-level module netlists.

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Figure 3-4: New Project Wizard: Specify Top Netlist File

1. Edit the definable options:

• Top Netlist file—Enter a name to identify the top-level netlist in this project. Use
the File Browse button to select the top-level netlist file for the design.
• Netlist directories—Select directories in which to search for lower-level modules
and cores. By default, the PlanAhead invocation directory and the directory from
which the top-level netlist was selected are included in the search path.
You can arrange the order in which to search these directories by selecting them
and using the up or down arrows buttons. Remove directories from the search
path by using the Remove button in the dialog box.
• Copy Sources into Project—Copy the source files into the PlanAhead project
directory structure instead of referencing the original locations.
Note: The selection made for Copy Sources into the Project is preserved for future
PlanAhead sessions.
2. To continue with the wizard, click Next.

Adding Constraint Files to RTL and Netlist Projects

The New Project wizard prompts you with the optional Constraint Files screen shown in
Figure 3-5, page 54 to add top-level UCF files or module-level NCF files. Any UCF and
NCF files found in the same directories as the RTL or Netlist source files display by default
as constraint files to be added to the project. You can remove files you do not want to add
with the Remove button.

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Figure 3-5: Adding Constraint Files using the New Project Wizard

• Add Files—Browse to, and select the UCF or NCF file(s) to add to the project.
• Create File—Create a new top-level UCF file for the project.
• Remove—Remove the selected UCF file from the Constraint files list.
• Up / Down—Set the order of the selected UCF files. The UCF constraints are order-
dependent; the last setting made is used.
• Copy Sources into Project—Copy the constraint files into the PlanAhead project
directory structure instead of referencing the original locations.

Setting the Target UCF

When multiple UCF files are selected, you must define a target UCF. The target UCF is the
file where PlanAhead writes newly created constraints. PlanAhead writes existing,
modified constraints back to the constraint file from which they originated, not the target
UCF. You can change the target UCF at any time in the PlanAhead session.
After adding the constraint files and setting the target UCF, click Next.
For more information on adding and creating constraint files and constraint sets, see
Adding or Creating Constraints, page 68.

Selecting a Default Part

The New Project wizard prompts you to select a default part.
The available devices display in the scrollable list. Information about the device resources
displays in the table view. You can filter the list to help you select your target device using
the Product, Family, Sub-Family, Package, Speed Grade, and Temp Grade filters.
1. Select a device in the device list and click Next.
Note: You can change the Default Part during Synthesis and Implementation and when
opening an RTL or Netlist Design.
The New Project Summary page opens.

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2. To initiate the project, click Finish in the Summary page.

PlanAhead then displays the project environment with the Project Manager related
views available

Creating an I/O Planning Project

You can create an empty project for I/O pin planning purposes prior to having completed
HDL or synthesized EDIF. See Chapter 8, I/O Pin Planning for more information about
I/O pin planning. In the Design Source page, select the Create an I/O Planning Project
option.

Importing I/O Ports

The next page in the New Project wizard prompts you to select a file for importing I/O
Port definitions and constraints. The options are:
• Import CSV—Browse to and select a Comma Separated Value (CSV) format file with
I/O Ports definitions in PlanAhead format.
• Import UCF—Browse to select a UCF file with I/O Port-related constraints only.
• Do not import I/O ports at this time—Create an empty project. You can create or
import I/Os at a later time.
Select an I/O Port definition option and click Next.

Selecting a Default Part

The New Project wizard prompts you to select a default part.
The available parts display in the scroll-able list.
1. Select any of the sub categories in any field to filter the parts displayed in the list.
2. Select the target product family architecture and default part, and click Next.
Note: You can change the Default Part during Synthesis and Implementation and when opening an
RTL or Netlist Design.
The New Project Summary page opens as shown in Figure 3-4, page 53.
To initiate the project, click Finish in the Summary page.
PlanAhead then displays the I/O Design environment with related views available.

Creating a Project with ISE Placement and Timing Results

You can import netlists with ISE® Implementation results along with corresponding
constraints to create a PlanAhead project. This is used to analyze the Place and Route
results using the Implementation environment.
1. Follow the project creation steps described in Using the Create New Project Wizard,
page 49.
2. Select the Import ISE Place & Route results option in the Design Source page.
The steps for creating this type of project are identical to creating a synthesized netlist
project, except this wizard asks for placement and timing files to be opened also.
3. Follow the steps for Creating a Project with a Synthesized Netlist, page 52.

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Importing Placement and Timing Results

After completing the steps to create the project, the Import ISE Implementation Results
page displays. You can import the Place and Route results generated in ISE which are then
used to create a floorplan for viewing and analysis in PlanAhead.
1. In the Import ISE Implementation Results page, edit the definable options:
• Placement File (NCD)—Browse to and select an NCD format placement results
file from the ISE Implementation directory.
• Import Timing (TWX)—Check this option, and locate and select a timing results
file from the ISE Implementation, such as a TWX format file.
The New Project Summary page opens next.
2. Click Finish in the Summary page to complete the new project creation process.
The project opens and you are prompted to Open the Implemented Design.
3. Select Open Implemented Design and click OK.
PlanAhead then displays the Implemented Design environment with design placement
and timing results loaded and related views available.

Opening an Existing Project

You can open existing projects in the PlanAhead software. As projects are opened, the
PlanAhead software restores the project state from the time the project was last closed as
well as the state of all previous Implementation Runs.
To open a project in PlanAhead, use one of the following methods:
• In the Getting Started page, click either the Open Recent Project or Open Project
links.
• Select File > Open Project.
• Click the Open Project toolbar button, as shown in Figure 3-6.
• Double-click on the PlanAhead project file (.ppr) from Windows Explorer to invoke
PlanAhead and open the project.

Figure 3-6: Open Project Toolbar Button

The Open Project browser opens. Select a PPR project file.

The File Preview window in the Open Project dialog box displays information about the
file. PlanAhead saves updates automatically in the project as they are executed.

Opening Multiple Projects

You can open multiple projects simultaneously in a single PlanAhead session by using any
of the methods described in Opening an Existing Project, page 56. A separate PlanAhead
main window opens for each project.
Note: System memory requirements can hinder performance when opening multiple projects.

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Saving a Project
You can save projects from within PlanAhead with the File > Save Project or File > Save
Project As commands. When you save a project, you are prompted to save unsaved
changes to designs and source files. If PlanAhead detects unsaved changes to the same
data, a prompt is displayed to allow you to select the design to save.
The Save Project As command copies the entire project directory structure to a new
specified location and maintains the existing Runs’ status.

Closing a Project
You can close projects from within PlanAhead with the File > Close Project command.
When you close a project, you are prompted to save any unsaved changes to the design or
source files. You can elect to exit without saving the data, or choose to save the data.

Managing Project Sources

PlanAhead can create new source files and manage existing source files that can be local or
remote.

Using the Project Manager

When you open a project, the Project Manager opens by default. You can open the Project
Manager by selecting the Project Manager button in the Flow Navigator.
When you open the Project Manager, no design compilation is performed and no design
data is loaded into memory. This environment enables creating, importing, and managing
source files and constraint sets. You can use the Project Manager to browse, customize, and
implement IP from the Xilinx IP catalog also.

The Project Manager displays the Sources and Project Summary views by default.

Using the Sources View

Most of the source file creation and management is done in the Sources view. For more
information on editing source files, refer to Chapter 5, “RTL Design.”

Creating Source Files

You can create new Verilog, Verilog Header, or VHDL source files in the Sources view as
follows:
1. Select Add/Create Sources from the popup menu or from the Project Manager.
2. In the Add/Create Sources dialog box, click the Create File button as shown in
Figure 3-7, page 58.

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Figure 3-7: Create New Source File

3. Define the following information in the dialog boxes shown in the previous figure:
• File type—Select one of the following file types:
- Verilog—Create a Verilog format file (.v).
- Verilog Header—Create a Verilog Header format file (.vh).
- VHDL—Create a VHDL format file (.vhdl).
• File name—Enter a name for the new HDL source file.
• File location—Designate a location to create the file.
4. Click OK.
5. In the Add/Create Sources dialog box, you can specify the appropriate Library for the
source file. By default, sources are added to the work library.
The newly created file is added to the project and displayed in the Sources window.
Double-click the file, or select Open File from the popup menu to open the file in the Text
Editor for editing.

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Adding or Creating Source Files

You can add RTL sources to the project at any time using the Add/Create Sources dialog
box as shown in Figure 3-8.

Figure 3-8: Add/Create Source Dialog Box

1. Select Add/Create Sources from the popup menu or from the Project Manager.
2. In the Add/Create Sources dialog box, the options are:
• Add Files—Invokes file browser to select RTL files to add to the project. VHDL
libraries can be specified by selecting from the drop down menu or typing in a
library name in the Library column of the Add/Create Sources dialog table.
• Add Directories—Invokes directory browser to add all RTL source files from the
selected directories. Files in the directory hierarchy with valid source file
extensions are added to the project.
• Remove—Removes the selected source files from the list of files to be added.
• Copy Sources into Project—Copies the original source files into the PlanAhead
project and uses the local copied version of the file in the project. If you selected to
add directories of source files using the Add Directories... option, the directory
structure will be maintained when the files are copied locally into the project.
• Add Sources from Subdirectories—Adds files from all subdirectories of specified
directories using the Add Directories option.
When adding sources, you can click on the Library field, and enter or select a library name
for the file or directory.

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Using Remote Sources or Copying Sources into Project

To provide project management flexibility, you can reference source files from a remote
location or copy the source files into the project directory. Copying the files into the project
is recommended if you plan to move or archive the PlanAhead project because the files are
contained within the project.
When you add remote files, PlanAhead picks up the latest file version automatically, and
then prompts you to Refresh your open Designs or to Synthesize with the latest updates
made to the file.
Note: When you copy files into a project, the project is more easy to port to another system;
however, PlanAhead does not pick up external file changes automatically. When remote files change
you must remove and re-add or update the files using the commands in the Sources view.
When you add sources to the project, you can specify for the sources to be copied locally to
the project directory by selecting the Copy Sources into Project checkbox in the
Add/Create Sources dialog box. If you initially add the sources as remote sources but later
wish to copy them into the project directory, you can use the Copy into Project or Copy All
Files into Project command in the popup menu in the Sources view to copy individual
remote source files or all remote source files into the project directory.
• Local files that you copy into the project directory have a green dot next to the file
name in the Sources view.
• The absence of a green dot means that the file is a remote source.
Figure 3-9 shows an example of how these sources display in the Sources view.

Figure 3-9: Remote and Copied Source Files

Viewing Source File Properties

Selecting an RTL source file in the Sources view displays information in the Source File
Properties view. To view source file properties:
1. In the Sources view, select a source file.
2. Select the Source File Properties popup menu command.
The Source Files Properties view is shown in Figure 3-10, page 61.

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Figure 3-10: Viewing Source File Properties

The file information includes location, type, library, size, modified timestamp date,
location copied from, copy date, and parent module.
• You can change the file type using the Type option. This is useful in cases where
files may have non-standard extensions and the file type is not properly detected
by default.
• You can select a new target library using the Library option.
3. Click Apply to apply changes.

Updating Source Files

When referencing remote sources, PlanAhead picks up the updated source file changes
automatically. You are prompted to reload any open designs for the PlanAhead software to
recognize the new changes.
You can update copied source files using the following options:
• Make all RTL changes inside of PlanAhead using the Text Editor which saves changes
to the local version of the file.
• Select the source file in the Sources view and select the Update File command from the
popup menu. Browse to select a new file to replace the file in the project. The file can
be updated with the same file it was originally copied from, or a different file.
Note: The file must be a different file name or in a different location than the original file added
to the project. Adding the same name file from the same location is not currently possible in
PlanAhead.
• Click Add/Create Sources from the popup menu to add the newly updated sources to
the project, and then click Disable to disable the outdated sources.

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Enabling or Disabling Source Files

When you add or create source files, those files are enabled by default in PlanAhead. You
can disable source files, which prevents them from being elaborated or synthesized.
You can control different versions of source files by enabling and disabling the source files
in the Sources view.
• To disable source files, select the files, and select the Disable source files popup
command.
• To enable disabled files, select the files, and select the Enable source files popup
command.

Adding Existing IP Cores to the Project

You can add existing IP cores into a project. IP cores can be:
• Synthesized NGC / EDIF netlists
• Externally-generated XCO core files from the CORE Generator™ tool when in an RTL
project
• Through the Embedded Platform Studio or DSP tools
Note: XCO core files are supported in RTL-based projects only. To add existing XCO core files to
the project, use the Add Existing IP command in the Project Manager.
For netlist-based projects, add the generated NGC or EDIF netlist for the core using the
Add/Create Sources command.
The Sources view displays folders for each source type. You can modify and re-implement
CORE Generator cores.

Configuring IP using the CORE Generator

In RTL-based projects, you can browse the Xilinx IP Catalog to analyze, customize, and
instantiate IP, and you can access the IP Catalog from the Project Manager or the RTL
Design environment.

Using the IP Catalog

To open the IP Catalog, click IP Catalog in the Project Manager or RTL Design Flow
Navigator menus. Figure 3-11, page 63 shows an example of the IP Catalog.

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Figure 3-11: Xilinx IP Catalog

The IP displays by category in an expandable tree table, that provides the IP version,
Advanced eXtensible Interface (AXI) protocol compliance, status, and license
requirements. When you select an IP, a description displays in the lower pane of the view.
Click Data Sheet from the popup menu or the IP Catalog toolbar to bring up the IP
datasheet in a PDF viewer.
Other options available in the IP Catalog toolbar and/or popup menu include:
• Show Search—Displays a Search field to search the catalog for any text string.
• Collapse/Expand All—Collapses or Expands the IP Catalog tree.
• Hide Superseded and Discontinued IPs—Filters the list to current IP only.
• Hide incompatible IP—Filters the list to only the IP that is compatible with the
selected device family.
• Group by Category—Groups or flattens the list for better sorting and searching.
• Customize IP—Opens the customization GUI for the selected IP.
• License Status—Displays license requirements and status for the selected IP.
• Compatible Families—Displays a list of all device families that are compatible with
the selected IP.
• View Data Sheet, Version Information, Webpage and Answer Records—Displays
documentation for the selected IP.
• Catalog Settings—Opens Project Settings for the IP Catalog.
Refer to Using Tree Table Style Views in Chapter 4 for more information about tree table
views.

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Updating the IP Catalog

PlanAhead creates a local version of the IP Catalog when the tool is invoked for the first
time after installation. To update the IP Catalog to ensure it is current with the latest
installed IP, click Update IP Catalog from the popup menu in the IP Catalog.

Configuring IP Catalog Settings

You can define IP Catalog settings.
1. Click Project Settings in the Project Manager.
2. In the Project Settings dialog box, click IP Catalog, as shown in Figure 3-12.

Figure 3-12: IP Catalog Project Settings

The IP Catalog settings are:

• IP Catalog Location—Defines a location for the local IP catalog to be created and
stored.
• HDL Type—Defines the language to use when creating the IP. The Auto option derives
the preferred language automatically, based upon the language of the top-level HDL
file.

Customizing IP
You can select IP from the IP Catalog, and customize the IP using the integrated CORE
Generator tool.
1. Select the IP to customize from the IP Catalog.
2. Select the Customize IP command.
PlanAhead invokes the CORE Generator interface to enable core generation. The IP type
you select determines what type of interface displays.
The interfaces are:
• Memory Integration Generator (MIG) wizard
• CORE Generator wizard

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Figure 3-13 shows the CORE Generator wizard:

Figure 3-13: CORE Generator Interface

The wizard fields enable core logic configuration.

Click Generate inside of CORE Generator when invoked from PlanAhead to create a core
and add it as a source in the project. The core is not yet synthesized. This button has a
different effect in the Standalone Core Generator tool.
When you run Synthesize, the PlanAhead software first automatically synthesizes the IP
cores and then synthesizes the design. This bundles the time-consuming Synthesis tasks
into one Run session because you can instantiate the IP into the design prior to running
Synthesis.
• For information on using CORE Generator to generate IP, refer to
http://www.xilinx.com/tools/coregen.htm.

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• For information on using the MIG Memory Generator (MIG), refer to

http://www.xilinx.com/support/documentation/ipmeminterfacestorelement_memi
nterfacecontrol_mig.htm.
• For information on specific IP, refer to http://www.xilinx.com/ipcenter/ or the IP
Catalog. Refer to http://www.xilinx.com/ipcenter/axi4.htm for more information
regarding AXI IP.

Viewing IP
The IP Symbol panel in the IP Customization GUI shows a schematic symbol view of the
IP.
• To display device resource statistics for the core logic, select the Information tab.
• To display the IP datasheet in a PDF viewer, click Data Sheet.

Instantiating IP
After you generate IP and add it to a project, the IP displays in the Sources view under the
IP folder.
Expanding the IP core in the Sources view displays the CORE Generator XCO file and
VHO/VEO file containing the instantiation template that you can copy and paste into your
design RTL using Copy and Paste in the Text Editor. Figure 3-14 shows instantiated IP RTL
code.

Figure 3-14: Instantiated IP RTL Code

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Generating IP
When you generate IP in PlanAhead, the Xilinx Synthesis Tool (XST) runs on the core and
creates the logic content based on the customization settings.
You can individually generate any IP core in the project, or let the software generator them
automatically when the full design is synthesized.
The IP can be generated by either of the following commands:
• In the Flow Navigator, click Synthesize. This will synthesize the entire design,
including the IP cores.
• In the Sources view, select the IP core, and click Generate IP.
After the IP is generated, a check mark appears on the IP source icon and the synthesized
netlist files display with the other IP files in the Sources view. In Figure 3-15:
• char_fifo IP has not yet been generated
• clk_core and samp_ram IPs are generated

Figure 3-15: IP Displayed in Sources View

Modifying IP
You can modify IP and regenerate it within PlanAhead if that IP was generated within
PlanAhead. To re-customize IP, select it in the Sources view and click Re-customize IP. The
CORE Generator interface opens to allow core modification.

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Using PlanAhead with Xilinx Platform Studio and EDK

You can use the Xilinx Platform Studio (XPS) tool to build embedded systems on Xilinx
FPGA devices. XPS provides an environment for designers to integrate their hardware and
software system components.
In XPS, use either Hardware > Generate Netlist or Hardware > Generate Bitstream to create
the /synthesis and /implementation subdirectories.
• The /synthesis subdirectory contains Synthesis scripts (.scr), project files (.prj)
and report (.srp) files.
• The /implementation subdirectory contains design netlist files created as a result of
the Synthesis process.
Also, XPS creates Block Memory Map (BMM) files in the /implementation subdirectory
for configuring the block RAMs on the device. The PlanAhead tool is inserted in the design
flow by the EDK tools after you run Synthesis on the embedded system.
XPS uses the XST for design Synthesis. The generated Synthesis netlists are in NGC format.
The top-level file is named system.ngc and any other NGC files have the nomenclature
module_name.ngc. The system.ucf file contains the design constraints.
You can add these files to the PlanAhead project as sources either as top-level modules or
instantiated into a system-level design during project creation, or when using the Add
Sources command. The files are under the /Cores folder in the Sources view.

Adding and Managing Constraints

PlanAhead provides flexibility for defining and using constraints in a project. You can use
a single UCF file to add and maintain all constraints used in the design or you can use
multiple UCF files if you want to organize the constraints into separate files. You can add
the UCF file while creating the project or afterward by using the Add Constraints
command.
PlanAhead lets you create multiple constraint sets if you want to experiment with various
types of constraints or store multiple versions of constraints. Each constraint set can
contain one or more constraint files.
You can open multiple designs referenced from a single constraint set. You must be careful
to manage changes made in multiple designs that reference the same constraint set. If
PlanAhead detects unsaved changes in multiple designs, it prompts you to select which
design to save.

Adding or Creating Constraints

You can add constraints to a project during project creation or after, with the Add/Create
Constraints command. Constraints can be added as top-level UCF constraint files or
module-level NCF constraint files.

Adding Constraints When Creating a New Project

When you create a project, the New Project wizard prompts you to add top-level UCF files
or module level NCF files. For more information on this process, see Adding Constraint
Files to RTL and Netlist Projects, page 53.

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Using the Add/Create Constraints Command

You can add or create additional constraint files to a project at any time by selecting the
Add/Create Constraints toolbar button or popup menu command in the Sources view or
from the Project Manager in the Flow Navigator. Figure 3-16 shows the Add/Create
Constraints dialog box.

Figure 3-16: Add/Create Constraints Dialog Box

The Add/Create Constraints dialog box lets you add additional existing UCF or NCF
constraint files to the project, or create new top-level UCF files to be added to the project.
When you add constraint files to a project, you must specify the constraint set into which
the constraint file are placed. By default the currently active constraint set is selected, but
you can specify a different constraint set or create a new one using the dropdown menu.
For more information on constraint sets, see Using Constraint Sets, page 70.

Defining the Target UCF

When multiple UCF files are used in a constraint set, you must define a target UCF file. The
target UCF is the file where the PlanAhead software writes new constraints that you create
within PlanAhead.
You can change the target UCF at any time in the PlanAhead session. When you modify
existing constraints, PlanAhead writes the changes back to the constraint file where they
originated.

Referencing Original UCF Files or Copying Files

As with other source files, you can add remote UCF files or copy the files locally into the
project when they are added. When you add remote files, PlanAhead picks up the latest
file version automatically, and then prompts you to Reload your open Designs with the
latest updates made to the file.
Note: When you copy files into a project, the project is more easy to port to another system;
however, PlanAhead does not pick up external file changes automatically. When remote files change
you need remove and re-add or update the files using the commands in the Sources view.
To copy files into a project, in the Constraints Files page of the New Project wizard, click
the Copy Sources into Project button.

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Using Constraint Sets

A constraint set is made up of one or more UCF or NCF files. These files are maintained
independently and are concatenated together into a single UCF file that is passed to ISE
Implementation.
As you manipulate constraints, PlanAhead keeps the files intact to the extent that is
possible. If you modify existing constraint values in PlanAhead, the changes go into the
original files. PlanAhead writes new constraint values into the designated target UCF.

Controlling Constraint File Processing Order

If there are multiple constraint files in a constraint set, the order in which they appear in the
Sources view corresponds to the order in which PlanAhead will process the files, with the
first file in the list being the first processed. Constraint file processing order can be relevant
in cases where there are constraint conflicts between files. In this case, the last file
processed takes precedence.

Changing the Target UCF

You can change the target UCF at any time by selecting a different file as the target UCF in
the Sources view, and using the Set Target UCF popup menu command.

Creating Constraint Sets

In PlanAhead, you can create different constraints at various stages of the design flow. You
can define constraints in the:
• RTL Design
• Netlist Design
• Implemented Design
Also, you can type constraints in the UCF in the Text Editor.
You can create new constraint sets by saving changes made in either the RTL, the Netlist, or
Implemented Designs. The Save Design As dialog box lets you enter a new constraint set
name.
To create constraints sets in the Add/Create Constraints dialog box, select Create
Constraint Set and enter a name, as shown in Figure 3-16, page 69.

Using the Save Design As Command

With multiple places to make constraint changes, it is convenient to save changes to a new
constraint set to manage changes or experiment. You can use the File > Save Design As
command to save a constraint set to a new name from any open design. All individual UCF
files are kept intact with the latest changes incorporated.
The dialog box lets you make it the active constraint set also.

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Creating New Constraint Sets

You can use the Add/Create Constraints command to create a new constraint set, as shown
in Figure 3-17.

Figure 3-17: Add/Create Constraints Dialog Box

When you select the Create Constraint Set option in the Add/Create Constraints dialog
box, PlanAhead prompts you to enter name for the new constraint set, and provides a
button switch to make it the active constraint set. Then, you can use the Add Files button to
select UCF or NCF files to add files, or use the Create File to select a location and name for
the new UCF file.

Defining the Active Constraint Set

If more than one constraint set exists, you must designate an “active” constraint set.
PlanAhead uses the active constraint set by default when you launch the next
Implementation Run or when you open an RTL, Netlist, or Implemented Design.
To set the active constraint set, in the Sources view select the constraint set, and click the
Make active popup menu command.
Notice the constraint set now appears bold and has the (active) designation in the Sources
view as shown in Figure 3-18, page 72.

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Figure 3-18: Setting the Active Constraint Set

Using Module-level Constraint Files

PlanAhead adds module-level constraint files to a project which are typically associated
with a core. There are two types of files that PlanAhead accepts: Netlist Constraint File
(NCF) and Xilinx Netlist Constraint File (XNCF).
You can add NCF files to the project in the New Project Wizard or using the Add/Create
Constraints command. The NCF files display in the Add/Create Constraints page of the
New Project wizard when found in the same directory as the RTL or Netlist source files.
The actions are:
• The ngc2edif command creates XNCF files that PlanAhead picks up automatically
and adds to the constraint set.
• When an NGC format core has embedded timing constraints, as is often the case with
EDK and some CORE Generator cores, the timing constraints are extracted by the
ngc2edif command prior to passing the EDIF netlist to PlanAhead. This is done to
allow PlanAhead to recognize the constraints and to expose them during design
analysis.
PlanAhead treats these files as read-only and does not enable modification to them
directly; however, in PlanAhead you can define new values for module-level constraints.
New constraint values are written into the target top-level UCF. Because PlanAhead passes
the top-level UCF files to Implementation after the module-level NCF files, the new
constraint values are given higher precedence and are used during Implementation.
Note: When modifying module-level constraints, it is a “best practice” to edit the files in the original
source using the IP creation method.
Note: Module-level NCF files are processed if the name matches the name of the module-level
netlist, for all instances of the module in the design, which matches the ISE behavior.

Exporting Constraints
Often, designers use PlanAhead to create constraint files for use in scripting command line
design flows.
When you have a project open from which you would like to export constraints, click the
File > Export Constraints command.

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Configuring Project Settings

PlanAhead provides access to Project Settings from a variety of locations; depending on
where you invoke the Project Settings, the appropriate dialog box displays.
To access the Project Settings dialog box, select the one of the following:
• Project Settings toolbar button, shown in Figure 3-19.
• Project Settings command from the Project Manager menu in the Flow Navigator.
• Links in the Project Summary that also open the Project Settings dialog boxes.

Figure 3-19: Project Settings Toolbar Button

The Project Settings General dialog box opens as shown in Figure 3-20.

Figure 3-20: Project Settings Dialog Box

The Project Settings shows four categories:

• General—Displays a dialog box where you can view the project Name, the Top
Module Name, and set language options.
• Synthesis—Shows the Default Part and Default Constraints Set, and provides an
Options area for setting command options and Strategy Definition.
A description window displays the Tcl commands wherein you can select a command
and get a description of that command.
• Implementation—Contains a Part and Constraints window, and the Options area for
setting command options and Strategy Definition. A description window displays the
Implementation command wherein you can select a command option and get a
description of that option.
• IP Catalog—Shows the IP Catalog location and the HDL type. This dialog box is
described in detail in Adding Existing IP Cores to the Project, page 62.

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Using General Project Settings

Figure 3-21 show the General Project Settings dialog box.

Figure 3-21: General Project Settings and Language Options Dialog Box

The General Project Settings dialog box displays the following information:
• Name—Displays the project name.
• Top Module Name—Enter the top RTL module name of the design. You can enter a
lower-level module name to experiment with Synthesis on a specific module also.
• Language Options—Enter specific Verilog or VHDL options.
• Verilog Options—Specify Verilog Search Paths, Macro definitions, Uppercase
identifiers, and Verilog2001 language standard.
• VHDL Options—Specify VHDL Generic values.
• Top Library—Specify the top-level module library name.
• Loop Count—Specify the maximum loop iteration value. The default is 1000.
The Loop Count option is used during Elaboration, and not during Synthesis. For
Synthesis, specify the -loop_iteration_limit switch in the More Options
field of the Synthesis Settings dialog box. For more information on setting
Synthesis Options, see Chapter 6, “Synthesizing the Design.”

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Using the Synthesis Settings

Figure 3-22 shows the Synthesis Project Settings dialog box.

Figure 3-22: Synthesis Project Settings Dialog Box

The Synthesis Project Settings dialog box contains the following information:
• Default Part—Displays the default target part. Select the browser button to invoke the
Part Selector dialog box to choose another part.
• Default Constraint Set—Select the constraint set to be used for the Run. This selection
has no effect for a Synthesis Run.
• Strategy—Select the strategy to use for the Run. PlanAhead includes a set of pre-
defined strategies, or you can create your own. For more information see the
Launching Runs on Remote Linux Hosts, page 268. When you select a strategy, the
options associated with it display in the lower part of the dialog box.
• Description—Enter any text description of the Run.
You can override Strategy options by selecting the option directives as shown in
Figure 3-22.

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Using the Implementation Settings

Figure 3-23 shows the Implementation Project Settings dialog box.

Figure 3-23: Implementation Project Settings Dialog Box

The Implementation Project Settings dialog box contains the following information:
• Default Part—Displays the default target part. Select the browser button to invoke the
Part Selector dialog box to choose another part.
• Default Constraint Set—Select the constraint set to be used for the Run.
• Strategy—Select the strategy to use for the Run. PlanAhead includes a set of pre-
defined strategies or you can create your own. For more information, see the
Launching Runs on Remote Linux Hosts, page 268. When you select a strategy, the
options associated with it display in the lower part of the dialog box.
• Description—Enter any text description of the Run.
You can override Strategy options by selecting the option directives as shown in the
previous figure.

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Configuring IP Catalog Settings

Figure 3-24 shows the IP Catalog Project Settings dialog box.

Figure 3-24: IP Catalog Project Settings Dialog Box

The options are:

• IP Catalog Location—Defines the location to create the local IP Catalog. This is
performed the first time PlanAhead is invoked after a fresh install, or when you run
the Update Catalog command. Refer to Chapter 5, “RTL Design.”
• HDL Type—Select the default language in which to create the IP module. The values
include: Verilog, VHDL or Auto, where Auto uses the same format as the top-level
module.

Creating Synthesis and Implementation Strategies

A strategy is a set of command options for each ISE Implementation command. PlanAhead
software provides several commonly used Strategies that have been used extensively on
internal benchmarks. The option settings for these strategies are not editable.
You can copy and modify supplied Strategies to create your own. The Strategies are copied
to C:/Documents and Settings/username/Application Data/HDI/strategies
(on Windows) during installation.
Strategies are tool- and version- specific. Each major release of ISE has version-specific
command line options that are supported in PlanAhead.
To review, copy, and modify strategies:
1. Select Tools > Options > Strategies.
The Strategies dialog box, shown in Figure 3-25, page 78 contains a list of pre-defined
strategies organized by Flow for each ISE and XST version.

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Figure 3-25: Strategies PlanAhead Options

2. In the Flow Navigator option, select the corresponding version of ISE or the Run script
format.
3. Copy the supplied PlanAhead Strategies to the User Defined Strategies area for
modification by using one of the following commands:
• The Create a copy of this strategy toolbar button, shown in Figure 3-26.

Figure 3-26: Create a Copy of this Strategy Toolbar Button

• The Copy Strategy popup command.

PlanAhead creates a copy of the strategy in the User Defined Strategies area and
provides the command option values on the right side of the dialog box for you to
modify.
4. Edit the definable options in the Strategies dialog box as follows:
• Name—Enter a Strategy name to assign to a Run.
• Description—Enter the Strategy description which is displayed in the Design Run
results table.
5. Click a command option to view the option description at the bottom of the dialog box.

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6. Modify command options by clicking in the command option area (to the right), and
selecting an option from the pulldown menu. Available command option settings
display in the popup menu shown in Figure 3-27.

Figure 3-27: Command Options and Description

7. Click Apply and OK to save the new strategy.

The new strategy shows as a User Defined Strategy and can be used for Synthesis and
Implementation as shown in Figure 3-28.

Figure 3-28: Selecting User Defined Strategies

For more information about configuring and launching Runs, refer to the Launching and
Managing Multiple Synthesis Runs, page 160.

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Creating Common Group Strategies

Design groups that want to create and use group-wide custom strategies can copy any
user-defined Strategy to the InstallDir/strategies directory. Figure 3-29 shows the
Project Summary view.

Figure 3-29: Project Summary

The Project Summary displays design information. You can use the scroll bar or the
Collapse and Expand buttons to view or hide the data categories. Selecting anywhere in
the panel banner expands or collapses the view panel also.

Viewing Project Settings

The Project Settings displays the Project Name, Device Family, Default Part, and Top
Module Name. Selecting the Edit link invokes the Project Settings dialog box. Refer to
Configuring Project Settings, page 73.

Viewing Project State

The Project State panel contains the following information:
• State—Displays the project status or the status of the actively running command.
• Messages—Summarizes the number of errors and warnings encountered during
compilation commands.
• Go To—Links to open the Compilation or Reports views and links to run the next
design flow command. Refer to Using the Compilation Message Area in Chapter 4 for
more information.

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Compilation Settings
The Compilation Settings shows the target part, and the strategy used for the active
Synthesis and Implementation Runs. Also, it shows the Fmax and utilization estimates
reported from Synthesis and the timing score and unroutes reported from Implementation.
Click the links to invoke the Project Settings dialog box in the selected location, which lets
you configure the Synthesis and Implementation Runs. Tool tips describe the button
actions.

Resources
The resource utilization for the target device displays graphically in the provided chart as
shown in Figure 3-30.

Figure 3-30: Resource Estimates in the Project Summary View

PlanAhead populates the Project Summary Resources at each stage of the design process.
The types of logic objects displayed varies as the design progresses through the design
stages. As the information becomes available, the tabs at the top of the view panel become
selectable.
• RTL Estimation—Provides estimates from the PlanAhead RTL design after the
Estimate Resources command has run.
• Synthesis Estimates—Extracts resource estimates from the XST Synthesis report.
• Netlist Estimation—Provides estimates from the PlanAhead Netlist Design after the
Estimate Resources command has run.
• Implemented Utilization—Extracts actual resource utilization from the ISE MAP
report.
In some cases, links display in the Resources panel to guide you through the step involved
to populate the Resources chart.

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Timing
Once the design is implemented, the Timing pane of the Project Summary view provides a
summary of the overall timing results. A link to open the Timing Results view is available,
as shown in Figure 3-31.

Figure 3-31: Timing Results in Project Summary View

PlanAhead populates the Project Summary timing after Implementation is complete. The
Timing Score, Minimum Period, Maximum Frequency and worst Failing Constraint for the
active run display, and a link is provided to open the Implemented Design.

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Using the Viewing Environment

This chapter contains the following sections:
• Understanding the Viewing Environment
• Using the Main Viewing Area
• Using the Compilation Message Area
• Working with Views
• Selecting Objects
• Using Common PlanAhead Views
• Configuring and Saving the Viewing Environment
• Configuring PlanAhead Behavior

Understanding the Viewing Environment

The PlanAhead™ software has a dynamic viewing environment that comprises view
layouts which present the design and device information for the design task at hand. It
provides unique capabilities and viewing perspectives for design information.
Most views cross-select, meaning the selected information appears in the other views when
you select it in one, enabling efficient methods to examine the design and device
information.
You can use PlanAhead to control each major step of the FPGA design process, including
RTL development and analysis, logic Synthesis, constraints definition, physical design
analysis, floorplanning, and Implementation control with the Xilinx® ISE® Design Suite
software.
There are view layout configurations to enable various types of tasks. The presented views
reflect the selected tasks. The available viewing configurations are:
• Project Manager—Manage project sources, constraints, customize IP
• I/O Planner—Define I/O placement constraints
• Design Planner—Analyze netlist design, insert ChipScope™ analyzer tool debug
cores, floorplan, apply timing constraints, and manage partitions
PlanAhead lets you customize view layout configurations for the displayed views. Refer to
Configuring and Saving the Viewing Environment, page 130.
In PlanAhead, you can create different types of projects that vary based upon the input
formats.

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The Flow Navigator appearance and the displayed view layout is determined by the type
of project you create. For more information on the PlanAhead project types, see Chapter 3,
“Working with Projects.”
The following sections describe the PlanAhead viewing environment.

Viewing Environment Overview

The PlanAhead environment components are annotated by number in Figure 4-1.

Figure 4-1: PlanAhead Viewing Environment

1. Main Menu—Contains the available PlanAhead commands. The menus filter the
available commands based on project type and design status.
2. Main Toolbar—Contains commonly used commands and extends to include Design
specific commands.
3. Flow Navigator—Enables flow-like control over the design process. From the Flow
Navigator you can launch Synthesis, Implementation, and generate bitstream files as
well as open designs at each stage of the design process. This view expands as design
tasks are completed, and displays relevant commands for each design or project type.
4. Main Viewing Area—Displays the Project Manager, and any open design. When a
design is opened, you can switch between the I/O Planner and Design Planner view
layouts.

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5. Project Status Bar—Shows project status and the actively-running commands. You
can cancel Synthesis, Implementation and generate bitstream commands from this
component.
6. Tcl Console and Messages Area—An expandable area that shows command status
and message logs.
7. Information Bar—Displays information about the project and the objects being
dragged over by the cursor.

Primary Environment Components

The primary components of the PlanAhead viewing environment include the:
• Main viewing area
• Flow Navigator
• Tcl Console and Messages area
The main viewing area displays the design data within either the Project Manager, the I/O
Planner or the Design Planner. When you open a project and no design data is open in
memory the Project Manager view layout opens by default. Once a design is open, the
design data displays in the Design Planner view layout. You can display the I/O Planner
view layout by toggling the I/O Planner button in the Design view banner.
You can adjust the size of the main viewing area by minimizing the Flow Navigator or the
Compilation Messages area. Figure 4-2 shows the primary environment components.
.

Workspace Area

Figure 4-2: The Main Components of the PlanAhead Environment

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Using the Main Viewing Area

The following subsections describe the options of the main view area.

Maximizing the Main Viewing Area

You can use the entire PlanAhead main window by clicking the Maximize design view
button in the upper-right of the viewing area. Select the Flow Navigator and Compilation
Messages area, then minimize. Figure 4-3 shows the Maximize design view button.

Figure 4-3: Maximize Design View Button

Hiding the Flow Navigator

You can hide the Flow Navigator individually by clicking the Hide Navigator button on
the left side of the Flow Navigator. Figure 4-4 shows the Hide Navigator button.

Figure 4-4: Hide Flow Navigator Button

Hiding the Compilation Messages Area

You can hide the entire set of Tcl Console and Messages view by clicking Minimize in the
banner of any of the Compilation Messages area views. Figure 4-5 shows the Minimize
icon.

Figure 4-5: Minimize View Banner Buttons

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Restoring the Compilation Messages Area

When you minimize the Compilation Messages area, the available views show as tabs at
the bottom on the viewing area. Select any of the tabs to maximize the Compilation
Messages area back to the original location.

Toggling Between I/O Planner and Design Planner

Once you open a design, you can switch the view layout between the I/O Planner and the
Design Planner by selecting the Planner in the main viewing area banner. The respective
I/O Planner and the Design Planner share a common design in memory. The only change
is the view layout.

Using the I/O Planner

The I/O Planner presents views applicable to device I/O resource exploration and I/O pin
assignment. The I/O Ports view displays to the left of the Package view and the Package
Pins view displays across the bottom of the layout. Ports are either populated from the
elaborated RTL design or synthesized Netlist design. I/O-related information displays in
the various views.
See Chapter 8, “I/O Pin Planning,” for more information about using the I/O Planner for
I/O pin planning.

Using the Design Planner

Select the Design Planner button in the banner of the main viewing area to load the Design
Planner views. The Design Planner presents views applicable to logic exploration, resource
analysis, and constraints definition. Figure 4-6 shows the Design Planner view.

Figure 4-6: Design Planner View Layout

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For more information related to the Design Planner view, see:

• Chapter 5, “RTL Design,” for information about using the Design Planner for RTL
development and analysis.
• Chapter 7, “Netlist Analysis and Constraint Definition,” for information about using
the Design Planner for netlist analysis and constraint definition.
• Chapter 10, “Analyzing Implementation Results,” for information about using the
Design Planner for Implementation results analysis and constraint definition.

Using the Compilation Message Area

The status and results of the commands that are run from within PlanAhead display in a
set of views linked into the lower Messaging area of the PlanAhead environment. As
messages are generated, they appear in the appropriate view within this area.
The Message area can be minimized to provide more viewing area for the design by
selecting the minimize button, shown in Figure 4-5, page 86, in the view banner.
When the Message area is minimized, tabs display at the bottom of the PlanAhead
environment to restore the views, as shown in Figure 4-7.

Figure 4-7: Restore Tabs for Message Viewing Area

When you selecting a tab the view becomes active when the Message area displays.

Using the Elaboration Messages View

When you elaborate the RTL design, PlanAhead opens the Elaboration Messages view
shown in Figure 4-8.

Figure 4-8: Elaboration Messages View

• Double-click any of the violations to invoke the Text Editor; it opens with highlighted
violation lines of the RTL file.
• Expand or collapse the messages by toggling the tree widgets in the view or by
clicking the Expand All or Collapse All buttons.
• Toggle the Hide Warning messages buttons use the Show Find button to view
messages.

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Using the Compilation Log View

This view displays the active command output status of commands that compile the
design such as ngc2edif, XST, Map and Place and Route (PAR).
The Compilation Log view displays the standard output from the compilation commands.
It opens automatically when you launch a command on an active run. Refer to Launching
Selected Runs, page 265.
Open the Compilation Log view by selecting the:
• View tab at the bottom of the PlanAhead environment
• Windows > Compilation Log command.
The Compilation Log view is shown in Figure 4-9.

Figure 4-9: Compilation Log View

The output displays in a continuous scroll-able format and is not refreshed when new
commands are run.
You can use the Pause output button to scroll back or read reports while commands are
running.

Using the Compilation Messages Views

The Compilation Messages view provides a summary of information messages, warnings,
and errors reported during design compilation.
You can open the Compilation Messages view by selecting the View tab at the bottom of
the PlanAhead environment or by selecting the Windows > Compilation Messages
command as shown in Figure 4-10.

Figure 4-10: Compilation Messages View

The reports might have links to the offending objects or to Answer Records in the Xilinx
Customer Support database.

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You can:
• Expand or collapse the message by toggling the tree widgets in the view or by clicking
the Expand All or Collapse All buttons
• Filter the displayed messages by toggling the Hide warning messages or Hide info
messages buttons or by using the Show Search button
• Consolidate the list by clicking the Group duplicate messages button

Using the Tcl Console

The Tcl Console view displays messages from previously executed Tcl commands.
PlanAhead writes messages to the planAhead.log file. Command errors, warnings, and
successful completion echo to this window also.
The status of design netlists and constraints that open in the Netlist Planner and Results
Viewer display also.
To invoke the Console View, select Window > Tcl Console. Figure 4-11 shows the Tcl
Console.

Figure 4-11: Tcl Console

In the Tcl Console view, you can:

• Expand or collapse the console messages by toggling the tree widgets in the view or
clicking the Expand All or Collapse All buttons
• Filter the displayed messages using the Show Search button
• Use the Copy button to cut and paste commands within the Tcl Console
• Use the Clear all output button or Clear All Output popup menu command to clear
the Tcl console report

Using the Color Bar Warning and Error Indicators

Warnings or Errors show with a yellow or red bar on the right side of the Tcl Console as
shown in Figure 4-12.

Figure 4-12: Color Bar Warning and Error Indicator in Tcl Console

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Hold the cursor over one of the bar segments to display the messages in a tool tip.
You can double-click the color bar segment to auto-scroll the Tcl Console to the messages in
the selected segment.

Using the Tcl Command Line

You can use Tcl-format PlanAhead commands on the command line (shown in Figure 4-11,
page 90). Enter commands by clicking on the command line and typing Tcl commands in
the Command dialog box entry.
Every editing command that can be performed using the menu or by direct manipulation
(such as drag and drop) has an equivalent Tcl command.
When you invoke a command in the interface (in a menu or by direct manipulation), the
equivalent Tcl command invokes and displays on the message area, and is written to the
planAhead.jou file.
You can access command history using the Up arrow and Down arrow keys in the
Command Line window.

Using Tcl Help

Command line help is available for all commands by using the following syntax at the
command line:
Command> help
You can retrieve more detailed information about the commands by extending the help
query with the following command:
Command> help get_cells
The Tcl Console displays the list of available commands or command options based on the
help topic that you enter.
For explicit command syntax, perform the command once, then view the planAhead.jou
file in the PlanAhead invocation directory.
See Chapter 14, “Tcl and Batch Scripting,” for more information about the Tcl command
formats and help.

Using the Design Runs View

The Design Runs view displays information about all of the Synthesis and Implementation
runs defined in the project. When working with multiple runs or with partitions, the
Design Runs view can be a useful display. It is not displayed by default.
See Running Implementation, page 248 for more information about using the Design Runs
view.

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Working with Views

The PlanAhead software has different types of views for displaying different types of
information. You can independently control views with respect to size, visibility, and
location. Because all the PlanAhead views interact together, it is helpful to organize them
in such a way to easily facilitate analysis and interaction between them. The default view
layout shipped with the PlanAhead software is optimized; however, you can customize it
at will.
Custom view layouts can be created to restore view preferences. Refer to Creating Custom
View Layouts, page 133 for more information.

Opening Views
From the Main Menu, select the Window menu for the commands to open most window
types. Select a window that is already open to make it the active window.
As certain commands are run, new views open to interact with the command or to display
results.
The Schematic view requires at least one object to be selected and is opened using the
popup menu Schematic command or the Schematic toolbar button.
The Properties view requires at least one object to be selected and is opened using the
popup menu Object_type Properties command.
Select New Device View or New Package View to open an additional view in the
Workspace.

Navigating Views
Each available view has a tab in the viewing area. You can activate a view by clicking on
the tabs. Some view types allow multiple tabs.
The active view displayed in any viewing area is toggled by using the tab interface at the
bottom of the view area. Figure 4-13 is an example of the Netlist view tab.

Figure 4-13: Netlist View Tab

In views, the following actions are available:

• To display the view in the full screen, double-click the view tab.
• To restore workspace views, double-click the view tab again.
• Stretch the overall size of these viewing areas by sliding the view borders. The cursor
changes to a slider symbol you can use to stretch the view borders.
• Move the views by selecting a view tab and dragging it.
This produces a rectangular box which indicates where the view is located after the
move. You can manipulate the rectangle within the viewing areas to split them either
horizontally or vertically to display multiple views at once.
Dropping a view onto an existing view tab produces another tab next to it for the newly
moved view. For more information, refer to Configuring and Saving the Viewing
Environment, page 130.

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Manipulating Views using the View Banner Controls

Each view has a control box to manipulate the view. You can float, hide, maximize, or close
views to suit your needs. When you close one view or viewing area the views that remain
open resize to accommodate the available space. Control box commands are covered later
in this chapter.
Each viewing area can be manipulated using common window environment commands.
These commands are available using the right-click popup menu in the banner of the view
also.

Floating Views
You can un-dock views, including the Workspace, from the display docking area so that it
“floats” and can be moved and sized independently. To float a window do one of the
following:
• Click the Float Frame button
• Select Float from the popup menu
When you activate the floating option, the view appears in a separate floating window. In
this case, windows obviously overlap. Once a window is floating you can move it by
dragging the view banner. You can move a floating window outside of the PlanAhead
main window. PlanAhead stores the default locations and sizes in which to display all
floating views in your saved layouts.

Using Graphical Workspace Views

The views with a graphical interface and those that require a lot of screen space like the
Text Editor or the Report Viewer display in an area called the Workspace. These views are
different than other views because more than one can be opened simultaneously to view or
compare different information. They do not have the same view manipulation controls in
the view banner. These Workspace views can be made full size, floated or split by using the
popup menu commands on the view tab.

Understanding Workspace Views

The PlanAhead Workspace is the graphic viewing area, which displays the graphical views
and some report and log information. The views displayed in the Workspace are:
• Project Summary
• Text Editor
• Device
• Package
• Schematic
• Hierarchy
• Reports and log files

Opening Workspace Views

You can open the Device and Package views in the Workspace by using the Windows
menu commands. You can open multiple views of the same view type within the
Workspace area. For example, two Device views can display different areas of the device.

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To open a new Device or Package view, select Window > New Device View or
Window > New Package View.
To open a Schematic view:
1. Select at least one object to display in schematic format.
2. Select the Schematic command:
- From the popup menu
- Press F4, or
- Click the Schematic toolbar button, shown in Figure 4-14

Figure 4-14: Schematic Toolbar Button

The Schematic displays in the Workspace. Running subsequent Schematic commands

opens additional Schematic views in the Workspace.

Viewing the Workspace Full Screen

You can get a full screen display of a view by double-clicking the Workspace tab. To restore
the Workspace, double-click the view tab again.
Also, you can right-click the tab to view the Workspace tab popup menu. Select either
Maximize or Restore from the popup menu depending on the state of the Workspace.

Floating the Workspace View

To float the workspace, select the Workspace tab and use the Float Window popup menu
command.

Printing the Workspace View

You can print the view that is focus in the Workspace—Device view, Package view,
Schematic view, and Instance Hierarchy view. Select File > Print to print the current
viewable area.

Closing Workspace Views

You close the views within the Workspace by clicking on the X icon in a view tab, which is
shown in Figure 4-15.

Figure 4-15: Device View Tab with X Icon

Splitting the Workspace

You can split the Workspace viewing area horizontally or vertically to enable multiple
simultaneously displayed views. Use the popup menu in the Device view to select the
split. Figure 4-16, page 95 shows the New Vertical Group option as selected.

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Figure 4-16: Splitting the Workspace Vertically

Each panel now acts as an independent Device view allowing multiple views to be docked
for viewing as shown in Figure 4-17.

Figure 4-17: Two Workspace Views Displayed Vertically

You can open Multiple views of the same type, such as two Device views for viewing
different areas of the device or different zoom levels.

Using the World View

The World view displays a less detailed overview of the active Workspace to enable a quick
pan of the viewed area. This capability is available in the Device, Schematic, Package, and
Hierarchy views. To invoke the World view, click the World view icon in the lower right-
hand corner of the Workspace viewing area, as shown in Figure 4-18, page 96.

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Figure 4-18: World View

The World view reflects the zoom area and the selected objects for the active view for the
Schematic, Device, Package, and Hierarchy views.
A navigation rectangle displays the area that is visible in the active view. You can drag the
navigation rectangle to reposition the display area in the active view.
Selected Pblocks, instances, and I/O ports are highlighted in the World view for easier
location, as illustrated in Figure 4-19, page 96.

Figure 4-19: View Panning with the World View

Using Tree Table Style Views

PlanAhead has many similar views that look a lot like expandable spreadsheet tables.
These views all share some common characteristics and features described in the following
subsections, and illustrated in Figure 4-20.

Figure 4-20: Tree Table Style View

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Expanding and Collapsing the Table

You can toggle the expand and collapse widgets in the Name column to expand or collapse
the tree independently.
The Expand All and Collapse All buttons expand or collapse the entire tree as shown in
Figure 4-21.

Figure 4-21: Collapse and Expand All Buttons

Display the Entries Grouped or in a Flat List

Most of these style views have a Group by Type button or equivalent which will either
display the entries group by an expandable type or as a single flat list of entries.
Flattening the list is helpful to search and filter the overall list of entries as shown in
Figure 4-22.

Figure 4-22: Group by Type or Flat List Toggle Button

Using the Show Search Capability to Filter the List

You can click the Show Search button to display a search field in the banner of the view
enabling any text string to be entered to filter the list displayed in the table view. For best
results flatten the list first by using the Group by Type toggle button described in the
previous section. Figure 4-23 shows the Show Search button.

Figure 4-23: Show Search Button

Any column in the table can be used as search filter criteria. Select the pulldown menu in
the Search field to select a column header to search. Figure 4-24, page 98 shows the search
pulldown menu.

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Figure 4-24: Search Pull down Menu

Enter any text string and the list will adjust dynamically to list only those entries that
contain the string entered. Select the Show Search button again to remove the Search field
and sorting.

Sorting Columns
You can sort any table column by clicking in the column header. Clicking again will
perform a reverse sort. A visual indication of the sort order and direction displays in the
Column Header, as shown in Figure 4-25.

Figure 4-25: Up/Down Sort Arrows

Organizing Columns
You can move, hide, and restore columns.
• To move a column, select it and drag it into a new location.
• To hide a column, select it and use the popup menu in the column header to select the
Hide This Column command.
The popup menu also enables quick view configuration for each column.
• Auto Resize Column commands adjust the width of the columns per the displayed
data.
• The Reset to Default command restores PlanAhead defaults.

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Using View Specific Toolbar Commands

Most views have toolbar buttons displayed within the view to operate commands specific
to that view as shown in Figure 4-26.

Figure 4-26: Example View-specific Commands

These buttons become enabled only when certain data is selected or commands are active.
PlanAhead features are made available through these view-specific toolbar buttons so it is
beneficial to become familiar with them. These view-specific commands are covered in
more detail in the specific view sections of this document.

Using the Information Banner

The information banner at the bottom of the PlanAhead main window displays useful
information as shown in Figure 4-27.

Figure 4-27: Information Banner

The information banner displays the following information:

• Information Message—The first field in the Information Banner displays context-
sensitive information. For example, when the cursor is in the device view or the
schematic view, this field contains the name of the placed instance directly under the
cursor. The information message field also contains detailed description of PlanAhead
commands when the mouse is over its corresponding toolbar button or menu item.
• Coordinates—To the right of the Information Message field is the Coordinates field.
As the cursor moves over block RAM, DSP48, and other parts in the Device view, this
field displays the name and coordinates as shown in Figure 4-27. If the cursor is over a
pin in the Package view, this field displays pin information, such as coordinates, type
and name.
• Mode—The Mode field indicates the type of project, such as RTL Flow or Post-
Synthesis Flow. When PlanAhead is invoked from ISE Project Navigator, the ISE
Integration mode is displayed.

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Understanding the Context Sensitive Cursor

The cursor changes based on the available command mode. When the cursor:
• Changes into a horizontal, vertical, or diagonal stretch bar symbol, you can stretch
Pblock edges and Windows view borders.
• Changes into a hand symbol, you can move Pblocks or instances.
• Changes into a cross symbol, you can draw rectangles for zooming in, defining pin
assignment areas, or drawing Pblock rectangles.
• Displays a slashed circle symbol, you are dragging objects are over illegal placement
sites.
• Displays a move point-to-point symbol, you are dragging objects over legal
placement sites.

Selecting Objects
There are multiple methods of objects selection in the PlanAhead software. Click the object
to select it in the current view. When selected in any view, objects also become selected in
the other appropriate views.
To move objects, hold the left mouse down and drag it, release to drop it on a location. The
cursor changes to a hand symbol when the move mode is activated.
When objects overlap, PlanAhead uses a priority scheme where the smaller size objects are
selected. If objects become difficult to select in the Device view, use the Physical
Constraints or Netlist views to select them. Objects can always be selected from either of
these two views regardless of the Selection Rule setting in the PlanAhead Options dialog
box.
If you experience difficulty selecting the correct object, the Select commands in the popup
menu can be used to select a specific item within the stack of items under the cursor.

Using the Select Main Menu Commands

Several of the Selection, Unselect, Highlight, and Mark commands are available from the
Select menu.

Selecting Multiple Objects

In most selectable views and dialog box lists, you can select multiple objects by pressing
and holding the Shift key to select a range of elements in a tree or table. The Ctrl key is
used to select multiple elements individually.

Using the Select Area Command

You can draw a rectangle in any of the Workspace views in to select objects as follows:
1. Choose Select > Select Area, or click the Select Area toolbar button as shown in
Figure 4-28.

Figure 4-28: Select Area Toolbar Button

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All objects that the rectangle surrounds or touches are listed in the Select Area dialog
box, with which you can filter selection by type shown in Figure 4-29.

Figure 4-29: Select Area Dialog Box

2. Turn off the check box to filter Object types from selection.
3. Click OK to select all of the checked objects.

Selecting Primitive Parent Modules

The Select Primitives Parent command lets you select the parent modules for all selected
primitive logic. To access the command, select Select Primitive Parents from the popup
menu (available in most views).
Floorplans are much easier to maintain when logic modules are assigned to Pblocks rather
than primitive logic instances.
You can select a group of timing paths that selects the primitive logic instances contained
on the paths. The Select Primitive Parents command selects the parent modules
automatically for selected primitive logic.
The originally selected primitive logic is no longer selected. The command interpolates
what is selected and returns with only modules selected, unless ROOT level logic was
originally selected.
If you select modules, the command does not select parent modules; the pre-selected
modules remain selected.

Using the Selection View

The Selection view, as shown in Figure 4-30, page 102, displays the list of objects currently
selected. You can sort, unselect, or mark objects from this view. The list is updated
dynamically as you manipulate objects. To invoke the Selection view, select
Window > Selection.

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Figure 4-30: Selection View

To sort elements, click on the column header to use as alpha-numeric sort criteria. Objects
can be sorted by Name, ID number, or Type by clicking on the banner of the desired sort
column. Selected items can be removed from the list by using the Unselect, Unselect All
or Unselect All Except command from the popup menu.
You can select groups of objects by using the Ctrl and Shift keys. The total number of
objects selected is displayed in the view banner as shown in Figure 4-31.

Figure 4-31: Selection View Popup Menu Commands

Fitting the Display to Show Selected Objects

Views in the Workspace have a zoom option to fit all selected objects. To zoom fit the
selected objects, use one of the following methods:
• Select View > Fit Selection.
• Press F9.
• Click the Fit Selection toolbar button as shown in Figure 4-32.

Figure 4-32: Fit Selection Toolbar Button

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Setting Selection Rules

When selecting an object, other objects can become selected also (for example, selecting a
Pblock also selects the assigned netlist instances). You can control the selection behavior
when you set selection rules in the Selection Rules options, which is available from
Tools > Options > Selection Rules. Figure 4-33 shows the Selection Rules dialog box.

Figure 4-33: PlanAhead Options: Selection Rules

You can enable or disable automatic selection by clicking the Set column heading.
• Enabling a selection rule forces the PlanAhead software to select the other affiliated
“To” object types when the “From” object gets selected.
• Disabling the selection rule forces PlanAhead to select the “From” object only when it
gets selected.
The default selection rules enable PlanAhead to operate in the most efficient manner.

Setting Object Selections in the Workspace Views

Object selection is set in the PlanAhead Options dialog box, available when you go to
Tools > Options. For more information about setting object selections, see Customizing
PlanAhead Display Options, page 130.

Highlighting Selected Objects

You can highlight objects with color for display purposes. Highlighting remains until you
clear all highlights for the floorplan. For more information on highlighting, see Selecting
Primitive Parent Modules, page 101.

Marking Selected Objects

You can place a Mark symbol for all selected objects. Select the objects to mark use the
Mark command in the popup menu.
Select the UnMark All toolbar button to remove all marks.

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Using Common PlanAhead Views

The following subsections describe the common PlanAhead views.

Using the Sources View

You can use the Sources view to manage project source types and constraints files. The
Sources view appears in all view layouts.

Opening the Sources View

To open the Sources view, click the Sources button (shown in Figure 4-34) on the toolbar or
use the Windows > Sources command.

Figure 4-34: Sources Button

Figure 4-35 shows an example of the Sources view.

.

Figure 4-35: Sources View

The Sources view displays the files that were added to the project listed categorically and
by-type. Design source types include: Verilog, VHDL, NGC/NGO, EDIF, and IP.
The constraints are in folders called constraint sets, and can include multiple UCF files.
Module-level NCF and Xilinx Netlist Constraints File (XNCF) format constraint files show
as design sources adjacent to their cores and are read-only. Refer to Adding and Managing
Constraints in Chapter 3 for more information about constraints.

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The Sources view table contains the following information:

• Name—Lists source files grouped by type in an expandable tree table. Using Tree
Table Style Views, page 96.
• Library—Displays the VHDL library defined for each file.
• Location—Displays the location of the imported or externally referenced files.
When RTL source files display in red, the PlanAhead software could not find the required
files.
A green dot next to the source file name indicates that the source file has been copied into
the local project directory.

Using the Sources View Commands

You can add, view, or modify source files using the Sources view popup menu commands.
The Sources view specific commands are:
• Source File Properties—Invokes the Source File Properties view.
• Open File—Opens the selected file(s) in the Text Editor view. This command is
available in a view toolbar button also.
• Update File—Replaces Source files with the newly selected files.
• Copy into Project—Copies selected source files and directories into the project
directory.
• Import All Files—Copies all remotely referenced Source files into the local project
directory.
• Remove from Project—Deletes the selected source files from the PlanAhead project.
It also removes the files from the PlanAhead project disk location if the files were
initially copied into the project.
• Enable Source Files—Sets the source file status to active for elaboration and
Synthesis. Source files can be toggled between Enabled and Disabled to define source
file configurations.
• Disable Source Files—Sets the source file status to inactive for elaboration and
Synthesis. Source files can be toggled between Enabled and Disabled to define source
file configurations. Disabled Source files appear in a shaded grey color to indicate
disabled status.
• Set Target UCF—Lets you select the UCF file to add PlanAhead created constraints.
• Set Library—Lets you select a library for the selected RTL source file(s).
• Add/Create Sources—Allows you to add or create Verilog, Verilog Header, or VHDL
source files.
• Add/Create Constraints—Allows you to create or add constraint files and create new
constraint sets.
• Add Existing IP—Adds existing XCO format CORE Generator project files as IP.
• Find in Files—Invokes the Find in Files dialog box to enter text strings to search in
the selected files. The Find in Files Results view displays with the results of the search.
• Export to Spreadsheet—Allows you to export the source file list and associated data
to a spreadsheet format file (.xls).

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Using the Text Editor to View and Edit Source Files

For information on using the features in the Text Editor, refer to Using the Text Editor in
Chapter 5.

Using the Device View

The Device view is the main graphical interface which is used for many different purposes
related to design analysis and floorplanning. For more information, see:
• Chapter 7, Netlist Analysis and Constraint Definition
• Chapter 10, Analyzing Implementation Results
• Chapter 11, Floorplanning the Design
The I/O Pin Planning process uses the Device view also. See Chapter 8, “I/O Pin
Planning,” for more information about using the Device view during pin assignment.
The Device view displays the FPGA device resources including the logic fabric, clock
regions, I/O pads, BUFGs, DCMs, Pblocks, instance locations, and net connectivity. The
locations on the device where specific logic can be assigned are called Sites. Figure 4-36
shows a Device view.

Figure 4-36: Device View

The amount of logic object detail displayed is determined by the selected zoom level: the
more you increase the zoom level, the more logic object detail displays. The Device view
popup and toolbar menus contain self-explanatory zoom level commands.
The Device view has scroll bars and dynamic pan capabilities to pan the viewable area of
the device also.

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When you drag the cursor over an object in the Device view, a tool tip identifies the object.
The Properties view displays object properties for selected sites or logic objects.
Use Edit > Find to search for specific logic object sites.
The Device view uses a dynamic cursor that changes appearance based on the activity
being performed. For example, if you attempt a logic resource assignment that is illegal,
the dynamic cursor changes so you can make adjustments. For more information, see
Understanding the Context Sensitive Cursor, page 100.

Using Device View Commands

Toolbar buttons on the left side of the Device view are view-specific commands, which are
described in Using View Specific Toolbar Commands, page 99. The following commands
are available in the Device view toolbar:
• To create:
- Anew Pblock rectangle, use Draw Pblock.
- Non-rectangular Pblocks, use Add Pblock Rectangle.
• To add or change the shape of an existing Pblock rectangle, use Set Pblock Size.
• To toggle the display of:
- Assigned LOC constraints, use Show/Hide Loc Constraints.
- Bundle Net connectivity between Pblocks, use Show/Hide Bundle Nets.
- I/O connectivity to place LOCs or Pblocks, use Show/Hide I/O Nets.
• To change the selection behavior, use the Show connections for selected instances
mode. With this mode on, connectivity displays automatically for newly-selected
objects. This button toggles the mode on and off.
• To remove the timing paths that remain displayed after a timing path is selected, use
Hide All Timing Paths. Toggling this button keeps currently selected paths selected,
but hides all remaining displayed timing paths.
• To assign:
- A LOC and BEL placement constraint to the object being placed, use Create BEL
Constraint Mode.
- A LOC placement constraint to the objects being placed, use Create Site
Constraint Mode.
- Logic instances to Pblocks, use Assign Instance Mode. This is the default mode;
use this mode whenever possible to ensure proper command behavior.
- I/O Ports to I/O Banks, use Place I/O Ports in an I/O Bank.
- I/O Ports in a rectangular area, use Place I/O Ports in Area.
- I/O Ports sequentially, use Place I/O Ports Sequentially.
• To toggle Automatic enforcement of interactive I/O placement DRCs, use
Automatically Enforce Legal I/O Placement.

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Understanding Device Resource Display

The PlanAhead software displays the resources contained in a selected device. The level of
detail at which the device resources display depends on the active zoom level within the
Device view. Graphical sites display and are available for all of the device-specific FPGA
resources.
The PlanAhead software Device view resource placement process is:
• The I/O pads and clock objects display around the periphery and/or down the center
of the device.
- I/O banks display as thin color-shaded rectangles just outside the row of I/O
pads.
- Available I/O bank sites display as color-filled I/O bank rectangles.
- Some devices have unbonded I/O banks that display with empty I/O bank
rectangles.
- The I/O clock pads display as filled-in rectangles.
• All clock resources, such as BUFGs, BUFRs, and BUFGPs, show in the Device view.
When you select an I/O bank or clock region, the available device resources display in
the Properties view.
• The interior of the device is broken up into smaller rectangles called Tiles. Tiles are
placement sites for the different types of logic primitives for the architecture.
A tool tip identifies each site in the Device view when you hover the cursor over a
logic site.
See Viewing and Reporting Resource Statistics, page 163 for more information about
viewing device resources. You must zoom the view to see the CLBs, SLICEs, and BELs.
You can:
• Assign primitive logic instances to the appropriate displayed sites.
• Import ISE placement results to display the logic assignments.
At the zoom level, the placed instances appear as rectangles within a SLICE. When you
increase the zoom level, the logic symbols display. You can assign logic to specific sites that
generate LOC placement constraints. Using BEL constraints you can assign sites to specific
gates or to a SLICE. All logic imported from ISE displays as BEL-level constraints. For
more information about LOC placement constraints, see Working with Placement LOC
Constraints, page 308.

Displaying Clock Regions

The clock regions display as large rectangles indicating the periphery of the various device
clock regions. These outlines can help guide floorplanning for critical circuitry.
In the Device view, you can:
• Select the clock regions in the Clock Regions view.
• Select and specify that Clock regions display their resource statistical properties.
• View the clock placement statistics after importing the Implementation results.
• Change the display color of Clock Regions in the Device view using the Device dialog
box, which is available by selecting Tools > Options > Themes.
When you select the clock region, the PlanAhead software selects the associated I/O banks
and clock related logic sites also.

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See Viewing Clock Region Resource Statistics, page 213 for more information about
displaying Clock region statistics.

Printing the Device View

You can print the Device view using the File > Print command, which prints the current
viewable area. To print the entire Device view, zoom to fit and then print.

Opening Multiple Device Views

You can open multiple Device views for the same floorplan (now referenced by the term
Design). This enables you to work on different areas of the device.
To open a second Device view display, select Window > New Device View. A separate tab
opens for the second Device view (Device (2)). You can then split the view using the
dragging technique described in the Splitting the Workspace, page 94 to view different
design aspects. Figure 4-37 shows an example of a split view.

Figure 4-37: Displaying Multiple Device Views

Using the Package View

The Package view displays the physical characteristics of the design device, and is used
primarily during the I/O pin planning process. Pin types display in different colors and
shapes for better visualization. For information about using the Package view for I/O pin
planning, refer to the Chapter 8, “I/O Pin Planning.”
To open the Package view, select one of the following:
• The Package view tab in the Workspace
• The Window > New Package View command

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Opening Multiple Package Views

You can open Multiple Package views simultaneously. Figure 4-38 shows the Package
view.
.

Figure 4-38: Package View

Moving the cursor within the Package view shows the I/O pin coordinates actively on the
top and left sides of the view. Additional I/O pin and bank information displays in the
Information bar located at the bottom of the PlanAhead environment. The Package view
highlights the active object.
When you hold the cursor over the Package view it invokes a tool tip that displays the pin
information, as shown in Figure 4-38. You can:
• Drag ports and I/O buffer instances into the Package view for assignment and
reassign instances to other I/O pins within the Package view.
• View pins and I/O banks as follows:
- VCC and GND pins show as red and green square pins.
- Clock-capable pins display as hexagon pins.
- The colored areas between the pins display the I/O banks.
• Click the pins or bank to select them.
• Select I/O pins or banks to highlight them in the Device view. Pins or I/O banks that
you select in the Device view also highlight in the Package view.
• Display the differential pair pins in the Package view by toggling on the Show
Differential I/O Pairs toolbar button as shown in Figure 4-39, page 111.

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Figure 4-39: Show Differential I/O Pairs Toolbar Button

You can set the Package view to appear from the top or bottom of the package by clicking
the Show Bottom/Top View toolbar button, shown in Figure 4-40.

Figure 4-40: Show Bottom/Top View Toolbar Button

The upper-left corner of the Package view contains several toolbar buttons.

Printing the Package View

You can print the Package view using the File > Print command that prints the current
viewable area. To print the entire Package view, zoom to fit and then print.

Using the Schematic View

You can generate a Schematic view for any level of the logical or physical hierarchy view.
In the Schematic view you can view design interconnect, hierarchy structure or trace signal
paths for either the elaborated RTL netlist or synthesized netlist.
See Analyzing Run Results in Chapter 6 for more information about analyzing RTL netlist.
For more information about synthesized netlist analysis see Chapter 7, “Netlist Analysis
and Constraint Definition.”

Selecting Logic in the Schematic View

You can select logic directly from the Schematic view for use in analysis and floorplanning
in the Device view.
To create a Schematic view:
1. Select one or more logic elements.
2. Right-click and select Schematic from the popup menu, or select the Schematic
toolbar button shown in Figure 4-41.
.

Figure 4-41: Schematic Toolbar Button

The Schematic view displays the selected logic instances or nets. If only one instance is
selected, the module shows with all pins displayed as shown in Figure 4-42, page 112.

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Figure 4-42: Schematic View

When you select objects in the Schematic view those objects display in all other views. If
you have opened an implemented design, the logic and paths display in the Device view.

Viewing Logic Hierarchy in the Schematic View

Upper levels of hierarchy display as concentric rectangles when a Schematic view is
generated, as shown in Figure 4-43.

Figure 4-43: Viewing Hierarchy in the Schematic

Notice that no pins display for the upper levels of hierarchy in Figure 4-43. In most cases,
the lack of pins makes the Schematic view more readable.

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You can:
• Individually expand or collapse module pins and logic.
• Selectively expand the logic either from individual pins, instances, or the entire logic
content inside or outside the module.
To expand module pins for a selected module, use the Toggle Autohide Pins command or
the Toggle Autohide Pins for selected instance toolbar button in the Schematic view,
which is shown in Figure 4-44.

Figure 4-44: Toggle Autohide Pins for Selected Instances Toolbar Button

Expanding Logic from Selected Pins

The options to expand logic from a pin are:
• Double-click a pin for the logic net to expand to the next primitive logic elements.
• Expand buses to include all bits of the bus. Buses show as thick wires.
Expansion of signals can go beyond hierarchical boundaries, as shown in Figure 4-45.

Figure 4-45: Expansion of Signals in Schematic View

Other expansion options exist to expand logic to the next set of flip-flops or to the I/Os.
If too much logic is selected for expansion, a dialog box opens that indicates the selected
logic is not be suitable for schematic viewing.
To view the logic expansion options, select a pin or an instance and select the Expand
Cone popup menu command to view the options.

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The available Expand Cone logic options are:

• To Flops—Appends the view to display the entire cone of logic to the first flops or to
any sequential element, such as block RAMs, FIFOs, and embedded processors.
• To Primitives—Appends the view to display the entire cone of output logic to the
first primitives. This is also the default behavior when you double-click a pin.
• To I/Os—Appends the view to display the entire cone of output logic to the I/Os. This
can involve a large amount of logic. PlanAhead sends a warning and allows you to
cancel the command if more than 10 levels of logic are to be appended.

Expanding and Collapsing Logic for Selected Instances or Modules

You can expand or collapse logic contained either inside a selected module or outside in
the next level of hierarchy instantaneously. You can run a new set of commands on a single
module or multiple selected modules. These commands are available from the right-click
popup menu or from the Schematic view toolbar buttons.

Schematic View Toolbar Buttons

Table 4-1 describes the Schematic view toolbar buttons.

Table 4-1: Schematic View Toolbar

Toolbar Button Command Description
Schematic toolbar Opens the schematic toolbar.

Expand all logic inside Expands all logic inside selected instance.
selected instance

Collapse all logic Collapses all logic inside selected instance.

inside selected
instance
Expand all logic Expands all logic outside selected instance.
outside selected
instance
Collapse all logic Collapses all logic outside selected instance.
outside selected
instance
Regenerate schematic Regenerates the schematic.

Remove selected Removes the selected schematic.

schematic

The commands are intended to display all logic associated within a level of hierarchy, as
shown in Figure 4-46, page 115 in which the Expand Inside command is used.

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Figure 4-46: Displaying All Logic Within a Level of Hierarchy

Traversing the Schematic Hierarchy

You can double-click on a hierarchical instance to collapse the displayed logic and expand
the logic within the selected module. To go up a level of hierarchy, use the Expand
Outside command in conjunction with the Collapse Inside command.

Regenerating a Schematic View

Occasionally, after several expand and collapse commands, the Schematic view needs to be
refreshed. You can force a Schematic view regeneration by selecting the Regenerate
schematic toolbar command in the Schematic view, which is shown in Figure 4-47.

Figure 4-47: Regenerate Schematic Toolbar Button

This command redraws the active Schematic view.

Selecting Objects in the Schematic View

The following are object selection options for the Schematic view:
• Left-click an object in the Schematic view
• Use the Ctrl key to select multiple objects
• Use the Select Area command and draw a rectangle around multiple instances, ports
and nets
When you select instances in the Schematic view, they are also selected in all other views.
The cross-selection works when you select or highlight objects in other views so they are
highlight in the Schematic view also.
The Schematic view popup menu commands are described in Schematic View-Specific
Popup Menu Commands, page 116.

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Removing Objects From the Schematic View

You can remove selected objects and their associated connectivity using the Remove
Selected Elements From Schematic toolbar command in the Schematic view, which is
shown in Figure 4-48.

Figure 4-48: Remove Selected Elements From Schematic Toolbar Button

Printing the Schematic View

You can print the Schematic view using the File > Print command, which prints the current
viewable area. To print the entire Schematic view, zoom to fit and then print.

Schematic View-Specific Popup Menu Commands

You can select instances and nets within the Schematic view for manipulation. The
Schematic view command are:
• Expand Cone—Appends the view to display the entire cone of input logic either to
the first primitives, flip-flops, or to the I/Os.
• Toggle Autohide Pins—Toggles the display of module pins for selected modules.
• Remove Selected Elements From Schematic—Removes the selected objects from
the schematic.
• Expand Inside—Expands logic contained inside of selected modules.
• Expand Outside—Expands logic contained outside of selected modules. The
expansion will only occur on the parent module logic.
• Collapse Inside—Collapses logic contained inside of selected modules.
• Collapse Outside—Collapses logic contained outside of selected modules. The
collapsing will only occur on the parent module logic.
• Select All Primitive in Schematic—Selects displayed primitive logic in the active
schematic fit view.
• Select Primitive Parents—Selects all of the parent logic modules of the selected logic
(available only when instances are selected).

Annotating Schematic Design Information

The PlanAhead Schematic options dialog box lets you tag source pins with Fanout values
and destination pins with Slack values. Slack values do not display until after timing
analysis.

Annotating Slack, Fanout, and Values onto Schematic Pins

To access the PlanAhead Options dialog box, select Tools > Options > Schematic.
1. To annotate these values, you must first set the Attribute type field to Pin.
2. Select from the Available Attributes to annotate on the left of the following dialog box,
and use the arrow indicators to move them to the right side labeled Displayed
Attributes.
3. Click OK.

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Figure 4-49 shows the PlanAhead Options dialog box.

Figure 4-49: PlanAhead Options: Schematic Pin Annotation

Figure 4-50 shows an example of the resulting pin annotation.

Figure 4-50: Annotated Pins in the Schematic View

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Annotating Cell References and Instance Equations onto Instances

The PlanAhead Options dialog box Schematic options let you tag instances with Cell
References and Instance Equation values.
The PlanAhead Options dialog box is available by selecting
Tools > Options > Schematic. Figure 4-51 shows the Schematic options in the PlanAhead
Options dialog box.

Figure 4-51: PlanAhead Options: Schematic Instance Annotation

1. Set the Attribute type field to Instance.

2. Select from the Available Attributes to annotate on the left side of the dialog box
shown in Figure 4-51, and use arrows to move them to the right side labeled
Displayed Attributes.
3. Click OK.
Figure 4-52, page 119 is an example of the resulting instance annotation.

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Figure 4-52: Annotated Instances in the Schematic View

Viewing Timing Path Logic in the Schematic View

You can select Timing paths from the PlanAhead Timing Results view and the paths then
display in the Schematic view. All of the objects on the selected path or group of paths
display with the logic hierarchy boundaries and the interconnect wires, as shown in
Figure 4-53.

Figure 4-53: Logic Hierarchy in Schematic View

See Chapter 7, Netlist Analysis and Constraint Definition and Chapter 10, “Analyzing
Implementation Results,” for more information about setting the timing path logic.
Note: Occasionally, paths displayed from the Timing Reporter and Circuit Evaluation (TRACE) TWX
(an XML file) or TWR (a Text file) format timing reports are missing interconnect wires. This is
because the logic was optimized out of the path during ISE Implementation. The objects that display
in the Schematic view are all of the actual objects contained in the selected paths; however,
PlanAhead cannot interpolate the connectivity after objects have been optimized away and no longer
exist. You can use the Schematic view in conjunction with the Path Properties to trace the path
connectivity. Usually the schematic is drawn is such a way that it is easy to see the path direction. For
more information, see Analyzing Timing Results in Chapter 7.

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Using the Properties View

The Properties view displays information about any selectable logic object or device
resource. As you select objects, their properties appear in the Properties view
automatically. The Properties dialog box is dynamic by default; as you select new items,
the view updates automatically.

Opening the Properties View

To open the Properties view, select an object and use the Object-type Properties popup
menu command.
Objects can have multiple property-types displayed. View tabs are added to the bottom of
the Properties view to accommodate various types of information. Select the different tabs
to display or modify information about the selected object, as shown in Figure 4-54.

Figure 4-54: Property View With Tabs

Using the Properties View Commands

The Properties view toolbar contains the commands shown in Table 4-2:

Table 4-2: Properties View Toolbar

Toolbar
Command Description
Button
Previous object Reverts to the previously selected objects.

Next object Reverts to the next selected objects (This key is only enabled after a Previous
object command).

Automatically update the Toggles the Properties view to auto-update as new objects are selected or
contents of this window remain static on the originally selected object.
when new objects are
selected
New Adds a new object. This option is only available for certain object types and
in specific view panes.

Delete Deletes an object from within one of the property tabs.This option is only
available for certain object types and in specific view panes.

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Table 4-2: Properties View Toolbar (Continued)

Toolbar
Command Description
Button
Export statistics Saves data to file for later analysis. Available from the Statistics tab for the
Pblock, Clock Region and Instance Properties view only.
Select/Unselect object Sometimes the object whose properties you are viewing becomes
unselected. Use this button to select/unselect this object.

Group by Interface or Groups the selected items by interface or bus.

Bus or Group by I/O
bank
Show Search Opens a search dialog box.

Fit Selection Zoom fit the selected objects.

Using the Netlist View

The netlist is a hierarchical representation of the logic design beginning with the top-level
netlist name followed by top-level modules.
The Netlist view displays the logic instances and nets contained in the design. The netlist
can be navigated by expanding and collapsing the logic tree. Scroll bars are used to view
the entire netlist tree.
The default netlist tree setting is to expand and scroll the netlist object dynamically when
they are selected in other views. To disable this feature, select the Automatically scroll to
selected objects toolbar button in the Netlist view. Figure 4-55 shows the Netlist view.

Figure 4-55: Netlist View

Collapsing the Netlist Tree

The entire netlist tree can be collapsed by selecting the Collapse All toolbar button in the
Netlist view. For more information, see Using View Specific Toolbar Commands, page 99.
The Netlist tree collapses to display only the top-level logic modules.

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Using the Primitives Folder

When a module contains primitive logic, the primitive logic is placed in a /Primitives
folder. This helps condense the display of the modules in the Netlist view, and is shown in
Figure 4-56.

Figure 4-56: Primitives Folder in the Netlist View

You can assign the Primitives folder directly to a Pblock resulting in all primitives being
assigned.
Note: Netlist updates might require reassignment of the Primitives folder to the Pblock because
logic names might have changed during re-Synthesis.

Using the Nets Folder

The Nets folder contains all of the nets and busses defined at any level of hierarchy. You
can expand busses to show each individual bit, as shown in Figure 4-57.

Figure 4-57: Nets Folder in Netlist View

When you select nets, they highlight in the Device view. Selecting a bus highlights all nets
contained within that bus. You can view nets in the Schematic view.
You can select nets for ChipScope tool debug testing by using the Add to ChipScope
Unassigned Nets command. See Connecting and Disconnecting Nets to Debug Cores in
Chapter 12.

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Understanding the Netlist View Icons

Various icons are used to represent the state of the netlist logic.

Hierarchical Netlist Modules

Hierarchical netlist modules or “instances” are displayed with a yellow I icons, as shown
in the following figure.

Hierarchical Netlist Modules Assigned to Pblocks

Hierarchical netlist modules or “instances” are assigned to Pblocks are displayed with blue
checkmark icons, as shown in the following figure.

Black Box Modules

Modules that do not have netlists associated with them are displayed with a yellow I icon
and a dark background as shown in the following figure. This could be a result of a search
path not being specified during project creation or missing portions of the design.

Partition Modules
Modules that have been set as Partitions using the Set Partition popup menu command.

Partial Reconfiguration Partition Modules

Modules that have been set as Reconfigurable Partitions using the Set Partition menu
command in a PlanAhead Partial Reconfiguration project.

Primitive Logic Instances

Primitive logic instances display as follows:
• Without placement constraints assigned display as an “i” inside a yellow rectangle.
• With placement constraints assigned display a yellow rectangle with a blue stripe.
• Assigned to a Pblock display a blue checkmark inside a yellow rectangle.
• Placed and assigned to a Pblock display a checkmark and blue stripe in a yellow
rectangle.
Notice the logic types display also, as shown in the following figure.

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Selecting Logic in the Netlist View

You can select instances and apply commands using the menu, the toolbar, or using the
mouse context sensitive menu (popup menu).
Use the Shift key or the Ctrl key to select multiple elements in the Netlist view for use with
most commands. Selected logic is highlighted in the Netlist view.
Logic selected by any means in PlanAhead displays as selected in the Netlist view. The
Netlist tree will expand automatically to display all selected logic. You might need to scroll
the tree to view all selected logic. Collapsing the Netlist tree does not unselect logic.

Using the Netlist View Commands

For more information on the popup menu commands available from the Netlist View, see
Using the Netlist Design Environment, page 162.

Using the Hierarchy View

The Hierarchy view lets you visualize the logic hierarchy. You can see the relationship
between selected modules as well as their relative sizes. This view is used primarily during
design analysis and floorplanning. It is often helpful to see how a timing path traverses the
logic hierarchy, or to gauge how big a module is before you floorplan the module.
The Hierarchy view displays a graphical view of the logic hierarchy for both the elaborated
RTL design or the synthesized netlist design. Viewing the design from top to bottom, you
can identify module sizes and location within the design.
In the popup menu, select the Show Hierarchy command to invoke the Hierarchy view,
shown in Figure 4-58.
.

Figure 4-58: Hierarchy View

Only hierarchical instances display in the Hierarchy view. Primitive logic is grouped into
folders that are represented as sub-modules. Refer to Using the Netlist View, page 121 for
more information about primitive logic folders. The widths of the blocks in the Hierarchy
view are based on the relative FPGA resources, including LUTs, flip-flops, block RAMs,
and DSP48s.

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When you select logic it is highlighted so you can see where critical logic resides in the
design. The module highlights proportionally to the amount of logic selected, as shown in
Figure 4-59.

Figure 4-59: Display Percentage of Logic Selected in Module

When you double-click on a module in the Hierarchy view a sub-hierarchy for any sub-
modules displays also.
To select logic parent modules for Pblock assignment in this view, use the Select Primitive
Parents command.

Using the I/O Ports View

The I/O Ports view is used to create, configure, and place I/O ports onto I/O sites in either
the Package view or Device view. The I/O Ports view shows the I/O signal ports defined
in the design.

Creating I/O Ports

You can create ports manually or by import a port list from a CSV or UCF file.
Creating projects with an RTL Header, RTL sources, or synthesized netlists populates the
I/O Ports view with the I/O ports defined in the design.
To invoke the I/O Ports view, select Window > I/O Ports. Figure 4-60, page 126 shows the
display.

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Figure 4-60: I/O Ports View Displaying I/O Ports

The Port view lists port signal names, direction, package pin, bank, I/O Standard, Drive
strength, Diff pair partner, Slew type, voltage requirements and other signal information
for each I/O port.
Table values appear blank if they are default values, or with an asterisk (*) for non-default
values, and red when they are illegal or undefined values.
Cells with editable values can be directly edited in the I/O Ports view, either by entering
text or by selecting from drop-down menus.
Buses are in expandable folders that can be selected as one object for analysis,
configuration and assignment.

Using I/O Ports View Commands

You can display the ports according to category by interface, or alphabetically by clicking
the Group by Interface or Bus button in the I/O Ports view, as shown in Figure 4-61.

Figure 4-61: Group by Interface or Bus Toolbar Button

You can:
• Create I/O Ports manually, using the Create I/O Ports toolbar button.
• Select and group ports together into interfaces, using the Create I/O Port Interface
toolbar button or popup menu command You can select and place these interfaces as
one object within the I/O Planner environment.
• Open the Schematic viewer for selected I/O ports, by selecting the Schematic toolbar
button.
You can select ports and interfaces from the I/O Ports view and assign them using the I/O
Planner environment. See Using Tree Table Style Views, page 96 for more information
about using the tree table style views.

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Using the Package Pins View

The Package Pins view is used to display I/O related package information. The table can
be sorted and filtered in many ways to analyze the I/O pins and I/O ports information.

Opening the Package Pins View

To invoke the Package Pins view, select Window > Package Pins. Figure 4-62 shows the
Package Pins view.

Figure 4-62: Package Pins View

Device pin information such as I/O Bank number, Type, Differential pair partners, Site
Types, and Min/Max package delay are listed for each package pin.
Table values appear as follows:
• Gray for default values
• Black for non-default values
• Red for illegal values
Note: The unit of measurement for the Min/Max package trace delay in the Package Pins view is in
picoseconds (ps).
You can sort the information in the Package Pins view by clicking any of the column
headers. Clicking again reverses the sort order. To sort by a second column, press the
Ctrl key and click another column.
You can add as many sort criteria as necessary to refine the list order. Sorted results might
be more readable if you flatten the list of Package Pins using the Group by I/O Bank
toolbar button (shown in Figure 4-63, page 128).
Refer to the Using Tree Table Style Views, page 96 for more information.
Cells with editable values can be directly edited in the Package Pins view, either by
entering text or by selecting from drop-down menus.

Using Package Pins View Commands

Refer to the Using View Specific Toolbar Commands, page 99 for more information on
toolbar commands.
You can toggle to display pins according to category by I/O bank, or display the pins
alphabetically by clicking the Group by I/O Bank button in the Package Pins view, shown
in Figure 4-63, page 128.

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Figure 4-63: Group by I/O Bank Toolbar Button

Using the Design Runs View

You can use the Design Runs view to view, configure, launch, and analyze Synthesis and
Implementation runs. As Runs are created, launched, or imported, the status shows in the
Design Runs view. The Design Runs view is used extensively in the Partial
Reconfiguration flow to create and manage various design configurations.

Opening the Design Runs View

Select Tools > Design Runs to invoke the Design Runs view. Figure 4-64 shows the
Design Runs view.

Figure 4-64: Design Runs View

The view displays the status and results of the design runs defined, and provides
commands to modify, import, launch, and manage the design runs. Also, this view is used
to manage and report Synthesis and Implementation runs. The view indicates the runs as
follows:
• Currently running with a green arrow icon.
• Completed runs have a blue check mark icon.
Run information displays as the commands are being run. PlanAhead can be closed
without affecting runs in progress. When you re-open a project, the run status is updated to
reflect the latest status, which displays in the Design Runs chart.
The columns used for tracking information are:
• Name—Displays run name.
• Part—Indicates the target part selected for the run.
• Constraint—Displays the constraint set used for the run.
• Strategy—Displays the strategy assigned to the Run. Strategies appearing with an
asterisk (*) indicate that the command option values in the strategy have been
overridden in the Run Properties Options tab.
• Status—Indicates run status or the command that is currently running.
• Progress—Indicates overall progress of the entire ISE command sequence from
ngdbuild through XDL. The progress bar is non-linear, in that some steps may take
considerably longer then others.
• Start—Indicates the time ISE started working on the design.

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• Elapsed—Indicates the total elapsed time for all ISE commands run on the design.
• Device Utilization (for Synthesis runs only)—Indicates the resulting LUT utilization
for the run.
• Fmax (for Synthesis runs only)—Indicates the expected clock frequency for the run
from the XST Synthesis report.
• Timing Score (for Implementation runs only)—Indicates the current timing score on
the run in progress or after completion.
• Unrouted Nets (for Implementation runs only)—Indicates the current number of
unrouted nets on the run in progress or after completion.
• Description—Displays the description associated with the run. This description is set
initially to a strategy description when that strategy is applied to the run; however,
the description can be modified later.
The table is updated dynamically as the Run commands progress. Runs that are launched
outside of PlanAhead using the PlanAhead generated scripts cause the table to update
upon invoking PlanAhead.

Using the Design Runs View Popup Menu Commands

The Design Runs view popup menu contains the following commands:
• Synthesis or Implementation Run Properties—Displays the Run Properties view.
• Delete—Deletes the selected runs. You are prompted to confirm prior to removing
any runs.
• Make Active—Sets the selected run as the active run. This run will launch
automatically when the Implement command is used with the current selected set of
command and launch options.
• Save as Strategy—Lets you save any modifications made to the applied strategy to a
new strategy file for future use.
• Launch Runs—Invokes the Launch Runs dialog box to launch the selected runs.
• Reset Runs—Invokes the Reset Runs dialog box to remove previous run results and
to set the Run status back to Not Started for the selected runs.
• Open Implemented Design—Loads the resulting netlist from the Synthesis run or
Implementation results from ISE in to the PlanAhead analysis environment. The
active loaded run appears in bold text in the Design Runs view.
• Generate Bitstream—Invokes the Generate Bitstream dialog box to create a
bitstream. This command is available for completed Implementation runs only.
• Copy Run—Creates a new run using the same Strategy as the selected run.
• Create Multiple Runs—Invokes the Create Multiple Runs dialog box to create and
configure multiple runs.
• Open Run Directory—Opens a file browser in the selected run directory on disk.
• Promote Partitions—Invokes the Promote Partitions dialog box to promote
implemented partitions.
• Launch FPGA Editor—Invokes FPGA Editor with the current implemented design.
• Launch ChipScope Analyzer—Invokes ChipScope analyzer with the current BIT
file.
• Launch iMPACT—Invokes iMPACT with the current BIT file.
• Launch XPower Analyzer—Invokes XPower Analyzer with the current implemented
design.

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Configuring and Saving the Viewing Environment

PlanAhead has numerous user-configurable viewing options. The tool ships with default
customize-able settings.
You can save and restore view layout configurations for use in subsequent PlanAhead
sessions. PlanAhead stores a separate layout for the Project Manager, I/O Planner, and
Design Planner environments. PlanAhead creates a layout file to restore the overall
PlanAhead window size and location also. The view configurations are stored in your
home directory when exiting PlanAhead. You can save view configuration “Themes” and
view layouts for use in future PlanAhead sessions. For more information about file
locations and formats, refer to the PlanAhead Input and Output Files in Appendix A.

Customizing PlanAhead Display Options

You can adjust view display options to control the appearance and behavior of the
environment.
To view or edit the display options available in the PlanAhead Options dialog box, select
Tools > Options > Themes. All changes take effect after you modify options in the tabs,
and click OK or Apply. Clicking Cancel does not initiate any changes.
You can view and adjust the options that control the general environment appearance in
the Themes options. The tabs at the bottom of the Themes options allow various view
setting types to be modified, such as: General, Device, I/Os, and Bundle Nets. Figure 4-65,
shows the available tabs with the General tab selected.

Figure 4-65: General View Display Options

Table 4-3, page 131 lists the tab options.

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Table 4-3: Display Option Tabs

Tab Options
Common Option • In the Display column, toggle the check boxes off to hide the
Selection Behavior object types.
• In the Select column, toggle the check boxes off to make the
object types unselectable. They will still be visible if the
Display toggle is on.
Note: The Frame and Fill color options are not available for certain object
types. Some object types are device-specific, consequently, the display
options have no effect in some devices
General Select a color to expose a pulldown, and click the down arrow to open
a popup menu to select another color.
Device Adjust the default color, visibility and selection options for object
types in the Device view. You can toggle the check boxes to obtain
the display effect you want.
I/Os Adjust the default color, visibility, and selection options for each
object type in the Package view.
Bundle Nets Configure the characteristics of the displayed bundle nets. You can
adjust the signal count ranges for bundles using the From and To
columns. Each column represents a bundle net range which can be
configured independently. You can set the line width on which the
bundle appears in the Device view for each bundle net range by
adjusting the values in the Width column.

Configuring Schematic Slack and Fanout Display Options

The Schematic options enables you to tag source pins with Fanout values and destination
pins with Slack values. For more information, see Schematic View-Specific Popup Menu
Commands, page 116.

Adjusting Display using Toolbar Commands

You can adjust the view display using the Device view shown in Figure 4-66, page 131 or
main toolbar buttons also. Some buttons are active only when the appropriate object types
are displayed. A tool tip is available for all toolbar buttons.

Figure 4-66: View Display Control Toolbar Buttons

Selecting a Theme
PlanAhead has default view settings for both light and dark background themes. To use
either, select the PlanAhead Light Theme or PlanAhead Dark Theme options in the
Theme pulldown menu.

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These default options are defined in the planahead.ini file. For more information, see
Inputs to PlanAhead in Appendix A.

Creating and Using a Customized Theme

You can save your own custom view settings to create PlanAhead initialization files for use
in future PlanAhead sessions. Click the Save Theme As button next to the Theme
pulldown menu as shown in Figure 4-67.

Figure 4-67: Creating a Custom Theme

If you create your own theme, it is prudent to back-up the initialization file that contains
the custom settings. For detailed information about the default and custom initialization
files, see View Display Options File (planAhead.ini & theme_names.patheme), page 361.

Moving Views
Multiple views can share the space within the viewing area by displaying them together
either vertically or horizontally. Split viewing areas by clicking on a view tab and dragging
it into another viewing area.
An outline guides you to place the view at the correct position. You can watch the moving
window outline during the dragging process to determine the resulting window location
before you accept the placement.
To move a view to share the space in a viewing area, use the following actions:
1. Click the tab, for example, the Constraints tab.
2. Drag the tab to a location. The gray outline serves as a guide.
3. Release the tab at the location you want.
To restore the view to its original location, select Window > Undo Dragging, or repeat the
steps above to set the view back in place.
To move a view to a completely different docking area, such as moving the Constraints
view to the Properties view, drag the tab of the view you are moving to the banner of the
destination docking area.

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The steps are:

1. Click the tab.
2. Drag it to the banner of the destination docking area.
3. Release the tab to place the view and its tab.

Creating Custom View Layouts

Select the Layout menu commands to save and restore default and alternate view
configurations.

Restoring a View Layout

A number of commands are available to restore the layout of PlanAhead.
You can dock views back to their original locations by toggling the various options
previously selected to off again. The view banner manipulation commands also act as
toggles and can be selected to revert back to the previous setting.

Restoring the Default View Layout

Select Layout > Load Layout > PlanAhead Default to undo any changes to restore the
default PlanAhead layout.

Using Undo/Redo Commands

You can undo the view manipulation commands by selecting the Layout > Undo
command. To repeat a command, use the Layout > Redo command.

Configuring PlanAhead Behavior

PlanAhead configuration options include: selection rule options, shortcut keys, general
settings options, and window settings options. The following subsections describe the
configuration options.

Setting Selection Rule Options

Selection rule options control the object selection settings for all views. When you select an
object, other objects can become selected also (for example, selecting a Pblock also selects
the assigned netlist instances). For more information on setting selection rules, see Setting
Selection Rules, page 103.

Configuring Shortcut Keys

Most commonly used commands have pre-defined shortcuts using keyboard key
combinations. The shortcuts defined display next to the command in the popup menu.
For example, press F9 to access the Fit Selection command.
You can modify the default shortcut values by using the Shortcuts option of the PlanAhead
Shortcut Options dialog box, which is shown in Figure 4-68, page 134.

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Figure 4-68: Shortcuts Options Dialog Box

The Shortcuts dialog box lets you create new, custom shortcut settings.
At the top, the available shortcut schemas lets you manage Shortcut schemas. Click the
Copy button to copy the PlanAhead Default schema to create a new schema.
You can activate any schema in the list by selecting it from the pulldown menu of available
schemas. You must first copy the PlanAhead Default schema to make any modifications.
The bottom portion of the Shortcuts dialog box has an area where you can make
modifications to shortcuts in the copied schema. You can search through the list of views
and select commands to enter new shortcuts as follows:
1. Select the Add Shortcut button and type in the new shortcut in the dialog box.
2. Click OK to accept the new shortcut.
You can filter the commands listed for shortcut assignment using the Filter field. Enter
any text string to filter the list of available commands. Also, you can use different
shortcuts for the same command in different views.
User-specific shortcut schemas are saved to one of the following directories:
• (Windows) C:\Documents and Settings\Username\Application
Data\HDI\shortcuts
• (Linux) ~/.HDI/shortcuts
3. To delete shortcuts, click the Remove button.

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Setting General PlanAhead Options

To set the general PlanAhead options, select Tools > Options > General. The following
figure shows the General options in the PlanAhead Options dialog box.

Figure 4-69: General Options Dialog Box

The General options are:

• Source Files—Contains checkboxes to copy sources, recurse through the
subdirectories to locate source files, and to show the file path in the Text Editor.
• I/O Placement—Toggles the interactive I/O placement DRCs on or off.
• Connectivity Display—Controls how connectivity is displayed in the Device view.
• WebTalk— Controls whether WebTalk is able to send Xilinx usage information.
• Miscellaneous—Controls whether PlanAhead searches the Xilinx website
automatically for new software updates, and defines how many previously opened
Projects display in the Getting Started page.

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RTL Design
This chapter contains the following sections:
• Introduction
• Managing the Design Source Files
• Editing RTL Source Files
• Elaborating and Analyzing the RTL Design
• Running RTL DRCs
• RTL Rules: Power and Performance

Introduction
The PlanAhead™ software Project Manager environment lets you create and manage
Register Transfer Level (RTL) design files. Then, you can elaborate and analyze the RTL
design in the RTL Design environment. Included in PlanAhead is basic source file
management, a text editor, an RTL schematic viewer, a set of RTL Design Rule Checks
(DRCs), and a resource and power estimator.
Using the PlanAhead software you can then run logic Synthesis and Implementation. See
Chapter 6, “Synthesizing the Design,” and Chapter 9, Implementing the Design for more
information about running Synthesis and Implementation.

Managing the Design Source Files

You can add the following types of RTL source files: Verilog, VHDL, NGC/EDIF and
Xilinx® CORE Generator™ XCO, to a project and manage those files in a variety of ways.
Most of the interaction with source files is from within the Sources view. Refer to Managing
Project Sources and Using the Sources View in Chapter 4.

Editing RTL Source Files

The PlanAhead RTL environment provides an Text Editor in which to create or modify
RTL sources. The Text Editor uses color-coding to distinguish the various types of RTL
constructs. You can open multiple files simultaneously, and each open file displays a view
tab in the PlanAhead Workspace with access to all open files.
When you modify a file, PlanAhead appends an asterisk (*) to the file name in the view tab
until the file is saved. To save the file, right-click in the Text Editor and select Save File, use
the Save File toolbar button in the Text Editor, or select File > Save Project.
If you close a file with unsaved changes, PlanAhead prompts you to save the changes.

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Using the Text Editor

The RTL Design environment enables cross probing to and from the Text Editor with other
views, such as the Schematic, Elaborate Results, RTL Netlist, and Hierarchy views.

Using the Text Editor-specific Commands

The Text Editor commands are available from the popup menu or from the view-specific
toolbar buttons. The options are:
• Save File—Saves the individually displayed file.
• Save File As—Lets you rename and save a file.
• Undo, Redo—Reverses changes in sequential order.
• Cut, Copy, Paste—Cuts or copies selected text to the clipboard, and pastes the
contents of the clipboard to the selected location.
• Duplicate Selection—Copies the current selected text and inserts it at the current
cursor location.
• Find, Replace—Invokes the Find field to enter a text string to search or replace
individual or all the occurrences.
• Indent Selection, Unindent Selection, Comment with Line Comment, Comment
with Block Comment—Performs the functions described in the command titles.
• Insert Template—Invokes the Xilinx Language Templates, and lets you select a logic
construct to insert in the RTL file.
• Find in Files—Invokes the Find in Files dialog box for you to enter text strings for
searching the selected files. The Find in Files Results view displays with the results of
the search.

Instantiating Xilinx Supplied Language Templates

Standard RTL templates are available in the Text Editor to assist with defining certain logic
constructs. You can browse and review the library of templates. Templates are instantiated
into any RTL file that is open in the Text Editor.
To instantiate a language template:
1. In the Text Editor, click the location in the file to indicate where to instantiate a
template language.
2. Select the Insert Template command from the popup menu.
3. Browse and select a template.
4. Click OK.
Figure 5-1, page 139 shows an example of the Xilinx-supplied templates.

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Figure 5-1: Insert Template Dialog Box

Using Find Commands to Search Source Files

You can use Find or Find in Files to search for any given text string in an open source file
or a selected set of source files. You can perform the following actions as follows:
• Enter any text string, including wildcards (*), as search criteria.
• Use the filtering options to limit the search, based on all files in the project or all open
files.
• Specify a forward or backward direction for the search.
• Search in all files in the project or only open files.
Figure 5-2 shows the Find in Files dialog box.

Figure 5-2: Find in Files Dialog Box

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The search results display in the Find in Files Results view as a list of files that contain the
search string and the number of occurrences in each file.
You can select any occurrence in the list to load that file into the Text Editor and highlight
the string. Figure 5-3 shows an example of such a search.
.

Figure 5-3: Find in Files Results View

You can use the Find command to search within a single open source file. When you select
this command, a Find bar appears at the bottom of the open source file in the editor. You
can enter a search string to locate the string in the file and, optionally, choose to highlight
all occurrences of the string in the open file. Figure 5-4 shows an example Find bar.

Figure 5-4: Using Find Feature in an Open Source File

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Elaborating and Analyzing the RTL Design

PlanAhead lets you compile and analyze the RTL sources and makes elaboration available
to analyze the compiled RTL design prior to running Synthesis, without making
elaboration a required step prior to Synthesis.

Validating RTL Design Compilation

RTL source files imported into the project are elaborated regardless of whether they are
compiled as a part of the design or during Synthesis. Elaboration results are not saved with
the design. You can run and rerun elaboration until the design is synthesized.
1. After design source files are imported into the project, elaborate the design using one
of the following commands:
- In Flow Navigator under Project Manager, click Elaborate.
- Select Tools > Elaborate.
- In the Flow Navigator, click RTL Design. The RTL design is compiled, and the
RTL design environment opens.
The Top Module dialog box opens.
2. In the Top Module dialog box, enter the top-level module to elaborate.
3. Click OK.

Setting Elaboration Options

You can set the HDL language options to use during elaboration in the PlanAhead Project
Settings. See Using General Project Settings in Chapter 3 for more information.

Viewing Elaboration Results

The Elaboration Messages view displays the results of the compilation and flags
irregularities in the RTL source files.

Highlighting Issues in the RTL Source files

You can select any of the Warning or Error lines in the Elaboration Messages view to load
the appropriate RTL source file with the selected source code highlight in the Text Editor.

Filtering the Results for Errors Only

You can filter the RTL Elaboration results to display messages only.
Click Hide Warning Messages to filter the results for errors only. Figure 5-5 shows the
Hide Warning Messages button.

Figure 5-5: Elaboration Results: Hide Warning Messages Button

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Using the RTL Design Environment

When you click RTL Design, PlanAhead elaborates the RTL design automatically, and
upon successful elaboration the compiled RTL design, displays the design the RTL Design
environment.
Either the Design Planner or I/O Planner environment displays, and you can toggle
between the two viewing environments by clicking Design Planner or I/O Planner in the
main view banner.
Also, PlanAhead applies the active constraint set to the elaborated design when it opens
the RTL Design. This enables I/O pin planning, based on the RTL port list and the module-
level floorplanning from the RTL logic hierarchy. For more information on creating and
managing constraint sets, refer to Adding and Managing Constraints in Chapter 3.
Figure 5-6 shows the RTL Design Planner.

Figure 5-6: RTL Design Planner

PlanAhead can provide resource estimation statistics based on the compiled RTL design.
To populate the resource statistics data in the Resource Estimation view, use one of the
following commands:
• In Flow Navigator under the RTL Design, click Resource Estimation.
• Select Tools > Resource Estimation.
The Resource Estimation view displays in the Workspace.

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The resource types display based on the logic hierarchy of the design. You can expand the
logic tree using the view widgets to allow visibility into the logic hierarchy. Figure 5-7
shows an example of the Resource Estimation view.

Figure 5-7: Resource Estimation View for the RTL Design

You can select any level of logic hierarchy in the RTL Netlist view and analyze its hardware
resources.
Because the PlanAhead software obtains the resource utilization statistics from pre-
Synthesis design data, these statistics are an early estimation and can change after
Implementation.
The Confidence Level value, displayed in the Resource Estimation view, provides insight
into how accurate the resource estimation is likely to be, based on design characteristics
such as numbers of black boxes, bus widths and macro types.
Click the Confidence Level value link for details about the determining characteristics for
the design being analyzed.

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Analyzing Resource Statistics in the Instance Properties view

When you select the Statistics tab in the Instance Properties view, you can view the
estimated device resource requirements for the selected module or for the top-level
module in the RTL view. Logic resources are categorized as Arithmetic, Comparators,
Multiplexers, Storage, and so forth. Figure 5-8 shows an example of resource estimates in
the RTL view.

Figure 5-8: Viewing RTL Resource Estimates

Memory and primitive tables list all memories, their depth, bit width, number of ports,
and macros or primitives, broken down by bit width in the chosen level of the hierarchy.
The Resource Estimator provides information about hardware resources for an RTL design
without running Synthesis, and, consequently, with a much quicker run-time. The
accuracy is an average of +/-15%.
To save the Statistics report to an XML format (for parsing) or XLS format, click the
Export Statistics toolbar button in the Netlist Properties window.

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Analyzing the RTL Logic Hierarchy

PlanAhead provides the following views into the logical design hierarchy:
• The RTL Netlist view provides an expandable logic tree.
• The Hierarchy view provides a graphical representation of the logic hierarchy.
• The Schematic view provides a view in which to explore the logic and hierarchy in a
schematic representation.
All views cross-select offering a unique set of capabilities to explore and analyze the logical
design. For more information, see Using the Netlist View and Using the Hierarchy View in
Chapter 4.

Analyzing the RTL Design Schematic

You can select any level of logic hierarchy in the RTL Netlist view and display it in the RTL
Schematic view.
To invoke the RTL Schematic view for any selected logic, select one of the following:
• Right-click and select Schematic from the menu.
• Select Tools > Schematic.
For more information on traversing, expanding and exploring the RTL Schematic, refer to
Using the Schematic View in Chapter 4.
Once the RTL design is elaborated, you can use the Find command to search for logic
objects using a range of filtering techniques. Refer to Using Find Commands to Search
Source Files, page 139.

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Running RTL DRCs

The following subsections describe selecting DRC rules and analyzing DRC violations in
PlanAhead.

Selecting DRC Rules

PlanAhead provides Design Rule Checks (DRCs) that you can run after RTL design
elaboration. The available rules focus on power reduction and performance improvement
opportunities.
1. To run the DRC checks after elaborating the design, select one of the following
commands:
- In the Flow Navigator, from the RTL Design pulldown, click Run DRC.
- Select Tools > Run DRC.
The Run DRC dialog box opens as shown in Figure 5-9 to enable rule selection.

Figure 5-9: Run Design Rule Checker Dialog Box

2. In the Run DRC dialog box, select the required rules.

For rule descriptions, see RTL Rules: Power and Performance, page 148.
3. Click OK.

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Analyzing DRC Violations

If violations are found, the DRC Results view opens, as shown in Figure 5-10.

Figure 5-10: RTL Design with Objects that Violate DRCs

In the Violations Properties view you can perform the following actions:
• Select:
- A violation to display information.
- The links to highlight the design objects in question.
- The Show Source popup command to highlight a line of RTL source.
• Click the:
- Hide Warning and Information Messages toolbar button to hide all warnings
and informational messages and view only errors.
- Hide Warning and Information Messages toolbar button again to re-display
errors and warnings. Figure 5-11 shows the button.
.

Figure 5-11: Hide Warning and Information Messages Button

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RTL Rules: Power and Performance

The following tables list the RTL Power and the RTL Performance DRCs.

Power DRCs
Table 5-1: Power Rules
Rule Name Rule Abbrev Rule Intent Severity
Constantly RPRC A described RAM (either inferred or instantiated), which is constantly Warning
enabled enabled, was found in one or both ports. If it can be determined that this
synchronous RAM is not constantly accessed. Significant power reduction may be
RAM seen by describing the logic to disable the RAM unless it is being
accessed.
Inefficient RPRM A RAM in which there is an unconnected output port has been detected, Warning
dangling and the WRITE_MODE is set to a value other than NO_CHANGE. Modifying
BRAM port the description of the RAM in order to set unconnected output port
(WRITE_MODE set to NO_CHANGE) could save up to 10% of the
dissipated block RAM power.
Shallow RAM RPRS Virtex®-5 and Virtex-6 devices: For wide (over 18-bits) and shallow Warning
implemented in (64-bits or less) RAM, it is generally advantageous to choose SelectRAM
Block RAM (LUT-based RAM referred to as distributed RAM) whenever possible
unless the RAM is being used as a FIFO, in which case the cross-over
point becomes a depth of 32-bits or less. When building interfaces less
than 18-bits wide, the LUT-based SelectRAM could be a better choice for
depths up to 128-bits; however, generally past that, the dedicated block
RAM is a better choice for power.
Inefficient RPDS Small multipliers mapped to DSP or to other hard multipliers IP, such as Warning
mapping of MULT18X18, should be pushed to MSBs. The rest of the LSBs should be
small multiplier mapped to ground. In this way, the carry propagation is reduced to its
in DSP block minimum. Usual Implementation, especially when inferring the
multiplier, uses LSBs and sign extensions to map the MSBs.

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Performance DRCs
Table 5-2: Performance Rules
Rule Name Rule Abbrev Rule Intent Severity
Inefficient RPWL Found instance name of type library_component_name that Warning
library element belongs to another FPGA family. This might result in suboptimal
instantiation performance. The ISE software might remap this element automatically
onto a similar element in the selected family. However, modifying the
source code to infer or instantiate native elements will take advantage of
any added or expanded functionality in the element. This may in turn
improve area utilization and performance.
Missing RPPR Found multiplier with unregistered outputs. You can improve the Warning
pipeline register multiplier clock-to-out performance by adding a level of registers. In
addition, for best results, avoid using asynchronous control signals on
these registers.
Found RAM/ROM with unregistered outputs. You can improve the
RAM/ROM clock-to-out performance by adding a level of registers. In
addition, for best results, avoid using asynchronous control signals on
these registers.
Inefficient RPIP Found register_name (file_name:line_number) register with Warning
pipeline register asynchronous control signals on input or output of multiply function.
Dedicated DSP hardware resources do not have asynchronous control
signals, such as preset or clear. The registers will not be mapped into the
dedicated hardware resources resulting in suboptimal use of the device.
Found Black RPBX Component/Module component/module_name description Warning
Box instance not unavailable during Synthesis (file_name:line). Paths to and from
belonging to this black box cannot be optimized. Synthesis tool utilization estimates
UNISIM library and mapping decisions could be negatively affected.
Found latch in RPLD Found latch description for signal signal_name Warning
design (file_name:line_num). Latches creates difficult to analyze timing
paths which require post Implementation simulations to ensure
implemented design match expected behavior.
Found RPCL Found combinatorial loop for signal signal_name Warning
combinatorial (file_name:line_number). Combinatorial loops are generated when
loop in design a cone of combinatorial logic uses its outputs to feedback as partial input
to the same cone of logic. The total combinatorial delay from source to
destination should be increased by the feedback path delay. This type of
structure could be required from the design expected behavior or might
be unintentional.

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Estimating Power
PlanAhead provides early power estimation based on the design resources.
1. Select one of the following to run the Power Estimation:
- In Flow Navigator > RTL Design, click Power Estimation.
- Select Tools > Power Estimation.
The Power Estimation dialog box opens, as shown in Figure 5-12.

Figure 5-12: RTL Power Estimation Dialog Box

2. Enter the Toggle Rate information and click OK.

The Power Estimation view displays in the Workspace.

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A Power Summary displays along with an expandable power consumption graph, based
on the design logic hierarchy.
You can expand the logic tree using the view widgets to allow visibility into the logic
hierarchy. Figure 5-13 shows the Power Estimation view.

Figure 5-13: Power Estimation View

You can expand and select any level of logic hierarchy and analyze its power consumption
and hardware resources.

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Synthesizing the Design

This chapter contains the following sections:
• About Synthesis and Implementation in PlanAhead
• Running Synthesis
• Monitoring Run Status
• Selecting The Next Step After Synthesis Completes
• Analyzing Run Results
• Launching and Managing Multiple Synthesis Runs

About Synthesis and Implementation in PlanAhead

The PlanAhead™ software includes a Synthesis and Implementation environment that
facilitates a push button flow with single Synthesis and Implementation attempts or Runs.
PlanAhead manages the run data automatically, allowing repeated run attempts with
varying Register Transfer Level (RTL) source versions, Synthesis, or Implementation
options, or constraints.
Also, PlanAhead allows multiple Synthesis and Implementation runs using different
software command options, timing, and physical constraints. You can queue the Synthesis
and Implementation runs to launch sequentially or simultaneously with multi-processor
machines. Synthesis runs use Xilinx® Synthesis Technology (XST).
You can create and save Strategies, which are sets of option configurations for each
Implementation command, that are then applied to Runs for Synthesis or Implementation
using Xilinx ISE® Design Suite tools. For more information about Strategies, see Creating
Synthesis and Implementation Strategies in Chapter 3.
You can monitor progress, view log reports, cancel runs, and manage run data to identify
and import the best Synthesis and Implementation results.

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Running Synthesis
When you run Synthesis in PlanAhead you have the ability to set Synthesis options, run
Synthesis, and view the outcome of the run.

Synthesis Methodology Tips

The following are suggestions on a logic Synthesis methodology to use PlanAhead
optimally for design analysis, floorplanning or hierarchical design.
For more information on optimizing ISE Synthesis results, see the Xilinx Synthesis and
Simulation Design Guide, (UG626).
To the extent possible, partition the design at the RTL level to confine critical timing paths
to individual modules.
Note: Critical paths that span large numbers of hierarchical modules can be difficult to floorplan or
partition.
• Register the module outputs to limit the number of modules involved in a critical
path.
Note: Long paths in single large hierarchical blocks can make floorplanning a difficult task.
Consider dividing large hierarchical blocks in the RTL.
• If you expect to change the design often, consider an incremental approach to
Synthesis. Most third-party Synthesis tools enable a top-down approach for
incremental Synthesis and Implementation. This capability, coupled with Xilinx
partitions can be used to preserve unchanged modules of the implemented design.
Design Preservation, helps create an incremental flow but can hurt performance
because global optimizations across the hierarchy are disabled. Consider this trade-off
before you embark on an incremental methodology.
• Constrain the Synthesis engine to rebuild or to otherwise preserve the hierarchy in the
synthesized netlist. Flattened netlists could be optimal from a Synthesis perspective,
but make it difficult to floorplan and constrain placement reliably.
• Consider using Synthesis options that rebuild the hierarchy, such as the XST
command line option -netlist_hierarchy = rebuilt.

Setting Synthesis Options

There are several locations in the environment to configure Synthesis settings.
You can configure Synthesis setting in the following areas:
• Flow Navigator > Project Manager menu
• Project Summary view
• Main toolbar using the Project Settings button
Figure 6-1 shows the Project Setting button.

Figure 6-1: Project Settings Button

In the Project Settings dialog box, click Synthesis, if it is not already selected, as shown in
Figure 6-2, page 155.

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Figure 6-2: Synthesis Project Settings

The Synthesis Settings dialog box lets you set XST options to use in the next Synthesis
attempt. The options are:
• Strategy—Select an existing Strategy to use for the Synthesis run. For more
information on Strategies, see Creating Synthesis and Implementation Strategies in
Chapter 3.
• Description—Displays the Strategy description. This field is editable for user-defined
strategies only.
• XST options—Configure any XST option. You can find a brief description of each
option and its use in the lower dialog box pane. An asterisk (*) next to an option name
indicates that the value is currently set to a non-default value.
Note: Modifications to these options are not preserved if you do not run Synthesis prior to exiting
PlanAhead. If Synthesis results exist in the project, the Project Settings inherit the settings of the
active Synthesis run. If no Synthesis run exists in the project, the PlanAhead restores the defaults.

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Using the XST Option to Create a Hierarchical Netlist

PlanAhead XST Synthesis strategies are set with the -netlist_hierarchy = rebuilt
option, except the XST default strategy. This switch instructs XST to flatten the netlist to
perform logic optimization but then reconstruct the logic hierarchy based upon logic
names. This facilitates design analysis and floorplanning within the PlanAhead
environment.
If you encounter problems with the switch, set the -netlist_hierarchy option back to
as_optimized in the Synthesis Settings dialog box.

Controlling File Compile Order

RTL source files display in the Sources view in the order in which they are compiled by the
Synthesis engine. The file at the top of the list is compiled first and the file at the bottom of
the list is compiled last. You can drag and drop files in the Sources view in the order to
modify the compile order sent to Synthesis. This can be useful and necessary in cases
where declarations are made in files that must be compiled before other files where they
are used.

Launching Synthesis
You can launch Synthesis Runs from the Flow Navigator.

Launching a Synthesis Run

To launch Synthesis, click the Synthesize button, shown in Figure 6-3, from the Flow
Navigator or the main toolbar.

Figure 6-3: Synthesize Button

The PlanAhead software uses the current Synthesis Project Settings to launch the run.
The Status Bar indicates that Synthesis is running, and the Compilation Message views
begin to display the active command status.

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Configuring Synthesis Run Settings

You can set the Synthesis Run options using the Synthesis Settings command.
Figure 6-4 shows the Flow Navigator Synthesis button pulldown menu.

Figure 6-4: Configuring Synthesis Run Settings

The Synthesis Settings dialog box opens as shown in Figure 6-5.

.

Figure 6-5: Synthesis Settings Dialog Box

The Synthesis Settings dialog box options are:

• Top Module Name—Enter or accept the top-level RTL module name for the design.
• Part—Select or accept the target part. Click the browser button to invoke the Part
Chooser dialog box.

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• Constraint Set—Select or accept the constraint set.

• Options—Select the Synthesis Strategy to use for the run. Click the file browser to
modify XST command options. Figure 6-6 shows the Synthesis Options dialog box.

Figure 6-6: Set XST Options for the Run

• Launch Options—Select additional launch options. Figure 6-7 shows the Specify
Launch Options dialog box.

Figure 6-7: Synthesis Launch Options

The Specify Launch Options dialog box options are:

• Launch Directory—Specify a location to create and store the Synthesis run data.
Note: Defining any non-default location outside of the project directory structure makes
the project non-portable because absolute paths are written into the project files.
• Launch Runs on Local Host—Launch the Run on the local machine processor.
- Number of Jobs—Define the number of local processors to use for Runs. This
option is used only when you are launching multiple runs simultaneously.
Individual runs are launched on each processor. No multi-threaded processors are
used with this option.
• Launch Runs on Remote Hosts (Linux only)—Use remote hosts to launch one or
more jobs.
- Configure Hosts—Select this option to configure remote hosts. See Launching
Runs on Remote Linux Hosts in Chapter 9.
• Generate scripts only—Export and create the run directory and run script, but do
not launch the run from PlanAhead at this time. The script can be run at a later time
outside of the PlanAhead environment.
• Copy RTL sources into Launch Directory—Specify whether to copy RTL sources
into the Synthesis run directory. If set to false (default), RTL sources are left in the
original source directory (which can be local or remote to the project).
When you launch Synthesis that utility reads the files directly from that location
without copying the source into the Synthesis run directory.

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This behavior reliably preserves the relative file structure between referenced source
files, and also reduces unnecessary disk space usage.
Note: This feature applies to RTL sources only. Netlist sources, IP, and constraint files are
always copied into the Implementation run directory.
• Click Run to launch the run with the current settings.
• Click Save to save the settings, but not start the run.

Monitoring Run Status

You can monitor the status of a Synthesis run by reading the compilation log, or viewing
the compilation information, warnings, and errors in the Compilation Messages view. See
Monitoring Run Status, page 252 for more information.

Selecting The Next Step After Synthesis Completes

Once the Run is complete, the dialog shown in Figure 6-8 opens and prompts you to take
the next step.

Figure 6-8: Synthesis Completed or Failed Dialog Box

1. In the Synthesis Completed dialog box, select the option that matches how you want
to proceed. The options are as follows:
- Implement—Launches Implementation with the current Implementation Project
Settings. For more information on the Implementation process see Chapter 9,
“Implementing the Design.”
- Open Netlist Design—Imports the netlist, active constraint set, and target part
into the PlanAhead design analysis and floorplanning environment so you can
perform I/O pin planning, design analysis, and floorplanning. For more
information, see Netlist Analysis and Constraint Definition in Chapter 7.
- View Reports—Opens the Reports view so you can select and view the XST
Report file. For more information on report analysis, see Viewing Report Files,
page 254.
2. Click OK or Cancel.

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Analyzing Run Results

Once Synthesis completes, you can view the Synthesis reports, and open, analyze, and use
the synthesized netlist design to apply constraints to the design before Implementation.
See Analyzing Run Results in Chapter 9 and Using the Netlist Design Environment in
Chapter 7 for more information. Also refer to Understanding the Project Summary in
Chapter 9.

Launching and Managing Multiple Synthesis Runs

PlanAhead lets you create and launch multiple Synthesis runs to explore Synthesis options
and find the best results. PlanAhead queues and launches the runs serially, or in parallel on
multiple local CPUs. Remote servers can be used on Linux. See Creating and Launching
Multiple Runs in Chapter 9 for more information.

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Netlist Analysis and Constraint Definition

This chapter contains the following sections:
• Overview
• Using the Netlist Design Environment
• Viewing and Reporting Resource Statistics
• Exploring the Logic
• Inserting ChipScope Debug Cores
• Defining Timing Constraints
• Running Timing Analysis
• Using Slack Histograms
• Defining Physical Constraints
• Running the Design Rule Checker (DRC)

Overview
This chapter describes the design analysis and constraint definition features available in
the PlanAhead™ software. The described features are typically performed by opening a
netlist design and before running Implementation. However, many of the analysis and
constraints features described in this section are also available for implemented designs.
In Netlist Design environment, you can perform the following activities:
• Analyze various aspects of the design
• Validate resource and timing estimates
• Run DRCs
• Define physical and timing constraints for the Xilinx® ISE® Design Suite
Several PlanAhead design tasks must be performed in the Netlist Design environment,
such as:
• Inserting ChipScope™ Pro Analyzer debug cores
• Defining partitions for Design Preservation and Partial Reconfiguration
Chapter 5, “RTL Design,” and Chapter 6, “Synthesizing the Design,” describe additional
analysis features. You can use most of these features after implementing the design also.
Chapter 10, “Analyzing Implementation Results,” describes the range of features useful
for analyzing an implemented design.

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Using the Netlist Design Environment

PlanAhead provides an environment to analyze the design from several different
perspectives, and to apply constraints to the design prior to Implementation.
When you open a netlist design, PlanAhead loads the synthesized netlist, the active
constraint set, and the target device. See Using the Netlist View, page 121 for more
information.
The Design Planner view layout provides a variety of design information that lets you
examine the logic, view the resource utilization and timing estimates, run DRCs, and apply
timing and physical constraints.
The default views presented in the Design Planner include: the Project Summary, Device,
Netlist, Sources, Timing Constraints, and Physical Constraints views, as shown in
Figure 7-1.

Figure 7-1: Netlist Design Planner

You can open other views, if needed, including the Package view. For more information
about using specific views, refer to Using Common PlanAhead Views, page 104.

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Viewing and Reporting Resource Statistics

PlanAhead provides statistical information about the design logical content and device
utilization. The Project Summary contains a Resources pane with resource utilization
estimates for the elaborated RTL and synthesized netlists. The resource statistics from XST
and the ISE map reports are also shown in their respective tabs.
Also, PlanAhead lets you select any netlist instance or Pblock and view resource statistics
in the Instance or Pblock Properties view, including selecting the top-level design. The
information includes: logic object type counts, percentage of device resources utilized,
carry chain information, and clock reports. You can export this information into an Excel
spreadsheet.

Viewing Resource Estimates in the Project Summary

As resource information becomes available, PlanAhead displays it automatically in the
Project Summary Resources panel.

Generating Hierarchical Resource Estimates

You can display resource estimates graphically as an expandable hierarchical tree. As each
Resources type displays, you can expand it to view each level of logic hierarchy.
To display a graphical view of device resource estimates:
1. Open a netlist design.
2. From the Flow Navigator, click the Resource Estimation command, or select
Tools > Resource Estimation.
A Hierarchical Resource Utilization summary opens, as shown in Figure 7-2.

Figure 7-2: Hierarchical Resource Estimation

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Viewing Resource Statistics for Logic Instances

PlanAhead provides estimates of the number of device resources contained in the design.
You can display resource statistics for any logic instance, including the top-level, in the
Instance Properties view.
To display design resource statistics, select either the top-level module or any instance
module in the Netlist view. Figure 7-3 shows the Netlist view with a top module selected.

Figure 7-3: Netlist View with Top Module Selected

The Netlist or Instance properties open in the Properties view.

If the Netlist or Instance Properties do not display, right-click on the module, and select the
Netlist Properties or Instance Properties command from the popup menu.
• The Netlist Properties view contains one tab and should display the statistics by
default.
• The Instance Properties dialog box contains five tabs. If you are viewing the Instance
Properties, click the Statistics tab.
The Statistics tab displays valuable design information including: Primitive Instance
Counts, Interface Signal Counts, Clock Names and Clocked Instance Count, Carry Chain
Count, and Max Length.
Figure 7-4, page 165 shows an example of the Netlist Resource Statistics.

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Figure 7-4: Netlist Resource Statistics

Viewing Resource Statistics for Pblocks

PlanAhead provides logic utilization statistics for Pblocks that can help determine if
enough device resources are contained in the Pblock area to satisfy the assigned logic.
Also, the ROOT Pblock is considered the top of the design and can provide utilization
statistics for the entire design.
To display utilization statistics for a Pblock:
1. Select either the ROOT Pblock or any Pblock in the Physical Constraints view.
Figure 7-5 shows a selected ROOT Pblock.

Figure 7-5: Physical Constraints View with ROOT Selected

The Pblock Properties display in the Properties view.

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2. If the Pblock Properties do not display, right-click ROOT or Pblock, and select Pblock
Properties from the popup menu.
For more information, refer to Viewing Pblock Properties in Chapter 11.

Using the Statistics Tab

The Statistics tab displays design information that includes: overall device utilization for
the various device resources; carry chain count and max length, RPM count, maximum
sizes; clock names and clocked instance count; I/O utilization; signal and primitive
instance counts. Figure 7-6 provides an example of the Statistics tab.

Figure 7-6: Pblock Properties: Statistics Tab

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Exporting Resource Statistics Reports

You can save the displayed data to a spreadsheet file. PlanAhead generates a hierarchical-
style report, in which you can define how many levels of hierarchy to report with estimates
listed for each module at each level.
To export a resource statistics report:
1. Select the Export Statistics button, shown in Figure 7-7, to export the data to a
spreadsheet file.

Figure 7-7: Export Statistics Toolbar Button

The Export Netlist Statistics dialog box opens, as shown in Figure 7-8, page 167.

Figure 7-8: Export Netlist Resource Statistics

The Export Netlist Statistics dialog box options are:

- File Name—Enter the name and location of the spreadsheet file to be created.
- Format—XML is the selected format output file format.
- Levels —Indicate the number of levels of hierarchy to traverse and include in the
report as separated modules.
- Reports to Generate—Define the types of information from the Pblock Property
Statistics view to include in the output report file.
2. Select the options for the exported file.
3. Click OK.

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Exploring the Logic

PlanAhead provides several perspectives in which to analyze the design logic:
• The Netlist and Hierarchy views contain a navigable hierarchical tree-style view.
• The Schematic view allows selective logic expansion and hierarchical display.
• The Device view provides a graphical view of the device, placed logic objects, and
connectivity. All views cross-select and present the most useful information.
• The Implemented Design contains additional logic analysis capabilities. The
capabilities are more powerful after placement and timing results are imported. Refer
to Chapter 10, “Analyzing Implementation Results,” for more information.
The following subsections describe the logic exploration methods available in PlanAhead.

Exploring the Logic Hierarchy

The Netlist view displays the logic hierarchy of the RTL. You can expand and select any
logic instance or net within the netlist. As you select logic objects in other views, the Netlist
view expands automatically to display the selected logic objects. For more information,
refer to Using the Netlist View, page 121.
Information about instances or nets displays in the Instance or Net Properties views.
The Hierarchy view displays a graphical representation of the RTL logic hierarchy. Each
module is sized in relative proportion to the others, so you can determine the size and
location of any selected module. For more information, refer to Using the Hierarchy View,
page 124.

Exploring the Logical Schematic

The Schematic view allows selective expansion and exploration of the logical design. At
least one logic object must be selected before the Schematic view is available. You can view
and select any logic in the Schematic view.
Groups of timing paths can be displayed to show all of the instances on the paths. This is a
tremendous aid for floorplanning as it helps you visualize where the timing critical
modules are in the design.
To open the Schematic view:
1. Select one or more instances, nets, or timing paths.
2. Select the Schematic command from the view toolbar or the popup menu, or press the
F4 key.
The view opens with the selected logic displayed.
3. You can then select and expand the logic for any pin, instance or hierarchical module.
For more information, refer to Using the Schematic View, page 111.

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Analyzing Hierarchical Connectivity

PlanAhead provides the ability to examine the logic hierarchy, including visualizing
connectivity between the various logic modules.
Sometimes, it is helpful to create a top-level floorplan to help visualize the connectivity
flow of the design, as shown in Figure 7-9.

Figure 7-9: Viewing Top-level Design Connectivity

The Net bundles indicate the heaviest connectivity requirements between the modules.
When you select a Net, bundle information about the net content displays in the Net
Bundle Properties view.
The color and line thickness of the Net bundles can be configured depending on the
number of signals they contain. The Tools > Options > General dialog box contains
connectivity display options. One option is to display the Net Bundles as a Mesh or in a
Tree pattern.
You can also traverse the hierarchy and create submodules for the larger top-level
instances to gain more detailed granularity.
This top-level floorplan can be an indicator of the I/O pinout configuration quality, and
can help identify potential routing congestion issues.
Also, examining resource statistics and clock requirements for each module can aid in
understanding potential placement issues.
Refer to the Floorplanning Methodology Guide (UG633) for more information.

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Searching for Objects Using the Find Command

The PlanAhead software lets you selectively search for instances or nets using the Find
command. To invoke the Find command:
1. Select Edit > Find, or click the Find toolbar button, shown in Figure 7-10.

Figure 7-10: Find Toolbar Button

The Find dialog box opens as shown in Figure 7-11.

Figure 7-11: Find Dialog Box

2. View or edit the definable fields in the Find dialog box:

- Find—Select the object type (Instances, Nets, Pins, Pblocks, Sites and so forth) for
which you want to search.
Note: Most object types in the Find field refer to logical objects in the design netlist, but the
Sites object type refers to physical objects in the device, such as physical I/O Pads, slices,
global buffers, dedicated Block RAM and DSP components.
- Criteria—For each object type, a different set of search parameters are available in
the dialog box.
- In the first field, select the way in which you would like to search for the
objects. For example, Name, Status, Type, Parent Pblock, Module, or Primitive
count. The values in this field differ based on the object type that you have
chosen to search for in the Find field.
- In the second field, you can set boolean options for the search, such as:
matches, does not match, contains, and does not contain.
- Use the third field to select a category or input search criteria strings. You can
use the asterisk (*) as wildcards in the search strings also.
3. Optionally, click the More button to define additional search filters or to
simultaneously search for additional types of objects.

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A new row of search criteria fields display in the Find dialog box. An AND/OR field
appears to define the additional search criteria. Setting it to AND or OR defines an
additional search filter as shown in Figure 7-12.

Figure 7-12: Searching for Objects with Additional Search Criteria

4. Click the More or Fewer button to add or remove search criteria rows.
5. Click OK to perform the search.
The combined search results display in the Find Results view.

Using the Find Results View

The objects matching the Find dialog box criteria display in the Find Results view once you
initiate the search by clicking OK. Figure 7-13 shows the Find Results view.

Figure 7-13: Find Results View

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The PlanAhead software creates a new Find Results tab each time you run the Find
command, which is named according to the Search criteria and number of objects found.
You can select objects directly from the Find Results dialog box, and when you select
objects from the list of found objects those objects are selected in other PlanAhead views.
You can select multiple elements by using the Shift or Ctrl keys. Additional commands are
available using the popup menu. You can sort by:
• Clicking any of the column headers
• Pressing the Ctrl key and clicking a second column header
To close the Find Results views, click the X icon in a Find Results tab.

Inserting ChipScope Debug Cores

PlanAhead lets you insert and configure ChipScope Integrated Logic Analyzer (ILA) and
Integrated ChipScope Onboard Netlist (ICON) debug cores into the Netlist Design. Debug
nets can be selected and cores configured using the Set Up ChipScope wizard.
The cores are added in such a way that they are preserved through netlist iterations. The
ChipScope netlist overlay will reconnect with the selected debug nets after a new netlist is
added to and opened in a project. PlanAhead sends a warning if any discrepancies are
found.
For more information on inserting debug logic and debugging with ChipScope,
Debugging the Design with ChipScope in Chapter 12.

Defining Timing Constraints

PlanAhead provides the ability to define and modify timing constraints for the design.
The following subsections describe how to use the timing constraint options:
• Editing Constraints in the Text Editor
• Using the Timing Constraints View
• Modifying Timing Constraints Values
• Removing Timing Constraints

Editing Constraints in the Text Editor

PlanAhead enables you to directly view and modify the constraints in the UCF text file
where they are defined. This makes it easy to cut and paste constraints, and to modify
values of existing constraints. However, you must ensure that constraints are written to the
correct constraints set and target UCF file so that constraints are applied as expected.
To open a UCF constraints file in the Text Editor, double-click the appropriate constraints
file name in the Sources view. The following figure shows a UCF file open in the Text
Editor. You can open multiple files.
Figure 7-14, page 173 shows the Text Editor.

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Figure 7-14: Text Editor

For more information about the commands and features available in the Text Editor, refer
to Using the Text Editor, page 138.

Using Xilinx-Supplied UCF Templates

The ISE software includes common UCF language templates. To access the template
library, select the Insert Template command in the Text Editor and expand the /UCF
folder.
To instantiate a UCF language template:
1. Click the cursor in the text file where you want to insert the template.
2. Use the Insert Template command to select a UCF template.
3. Click OK to insert the text in the cursor location.
4. Replace the default constraint values with design specific names and information.
The following figure shows a Xilinx-supplied UCF language template.

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Figure 7-15: Xilinx-Supplied UCF Language Templates

Using the Timing Constraints View

You can use the Timing Constraints view to display, edit, and create timing constraints for
the design.
PlanAhead provides a view of the timing constraints defined in the design. Constraints are
constraint set-specific, and can vary between open designs within the same project. You
can experiment with different constraints, devices, I/O pins, and so forth.
You can modify defined values and create new constraints in the Timing Constraints view.
To view the timing constraints defined in the design, click the Timing Constraints view tab,
or select Window > Timing Constraints.
The Constraints view opens as shown in Figure 7-16, page 175.

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Figure 7-16: Timing Constraints Tab

The constraints are displayed in two different ways: by type, or as a list.

As shown in the preceding figure, constraints are sorted by type, allowing expansion and
collapsing of the levels of constraint types. Notice that the number of each type of
constraint is displayed in parenthesis.
To view a list of all timing constraints, click the Group by type button in the Constraints
view, which is shown in Figure 7-17.

Figure 7-17: Group by Type Toolbar Toggle Button

You can also display timing constraints as a list.

Modifying Timing Constraints Values

You can modify most constraint values by selecting a constraint and viewing the Timing
Constraints Properties. The appropriate changeable values for the constraint are shown in
the dialog box. Figure 7-18, page 176 shows the Timing Constraints Properties dialog
box.

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Figure 7-18: Modifying Timing Constraints Properties

The dialog boxes for each constraint type are too numerous to describe here. Use the
correct syntax when defining constraints values. Refer to the Xilinx Constraints Guide,
(UG625), for more information on constraints and constraints syntax.
When you make changes, click Apply to accept the changes, or click Cancel to deny the
changes.
Note: You must click the Apply button to initiate changes to constraints values.

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Adding New Timing Constraints

To add new timing constraints:
1. In the Timing Constraints view, click the New Timing Constraint button, shown in
Figure 7-19.

Figure 7-19: New Timing Constraint Toolbar Button

The New Timing Constraint dialog box opens as shown in Figure 7-20.

Figure 7-20: Create New Timing Constraint Dialog Box

2. On the left, select the type of constraint you want to create.

The appropriate fields display on the right.
3. Define the constraint values using the correct syntax. Refer to the Xilinx Constraints
Guide, (UG625), for more information on constraints and constraints syntax.
4. To accept the changes, click OK.

Removing Timing Constraints

To remove the constraint from the design, select a constraint or group of constraints in the
Timing Constraints view, and select Delete from the popup menu. You are prompted to
remove the selected constraint(s) prior to the removal of the constraint.
Note: Due to the interdependence between timing constraints, removing one constraint could result
in the removal of several other related constraints.
Note: Adding, editing, and deleting timing constraints cannot be undone.

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Running Timing Analysis

Information about the timing performance of the design is available during the different
stages of Implementation. Depending on the Implementation stage, the available
information can contain early estimations of path delays to accurate analysis of
Implementation results.
The following subsections describe how to run timing analysis in PlanAhead.

About PlanAhead Timing Analysis

The PlanAhead timing analysis is used in various modes during different stages of design
completion. It can provide early estimations of path delays to assist during floorplanning,
as well as for detailed path tracing, debugging, and constraint assignment.
The more physical constraints, such as Pblocks and placement constraints, that are
assigned in the design, the more accurate the analysis results will be.

Timing Analysis Options for a Netlist Design

Once a design netlist is created, several options for exploring the design timing are
available. Timing analysis of the netlist design is useful for ensuring that paths are covered
by constraints prior to implementing the design. Additionally, you can use timing
estimates to create a proper floorplan. These options for running timing analysis on a
netlist design include:
• Using the Report Timing Analysis Results
• Using Slack Histograms

Timing Analysis Options for an Implemented Design

Once the design has been implemented, several options for exploring the design timing are
available. Timing analysis of the implemented design is useful for inspecting the timing
performance of the placed design. These options for running timing analysis on an
implemented design include:
• Using the Report Timing Analysis Results
• Analyzing Timing Histogram Results
The following sections describe the timing analysis options.

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Using the Report Timing Analysis Results

1. Perform a timing analysis using one of the following methods:
- Tools > Report Timing
In the Flow Navigator:
- Netlist Design > Report Timing
- Implemented Design > Report Timing
Figure 7-21 shows the Netlist Design option for selecting a timing report.

Figure 7-21: Report Timing Option

The Report Timing dialog box opens and enables you customize the timing report, as
shown in Figure 7-22.

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Figure 7-22: Report Timing Dialog Box

Clicking OK runs the timing analysis with default values.

The Report Timing dialog box options are:
- Results Name—Specifies the name of the timing report.
- Targets tab—Allows the filtering of reported paths based on Start Points,
Through Points, and Endpoints.
- Options tab—Allows the specification of options used in generating the report.
The detailed options of this tab are further described below.
- Advanced tab—Contains advanced options used for generating and storing the
timing report. The detailed options of this tab are further described below.
- Timer Settings tab—Used to specify timing engine and delay options used to
generate the timing report. The detailed options of this tab are further described
below.
- Command—Contains the text of the Tcl command generated by the Report
Timing options.
2. Click OK to run the timing report.

Understanding the Targets Tab Options

The Targets tab of the Report Timing dialog box contains fields where you can specify the
starting points, through points, and end points of the paths to include in the timing report.
By default, the dialog box opens with the fields blank indicating all points will be included
in the report up to the maximum number of paths specified. By adding values to the fields,
you can generate a report that focuses on the paths of interest only. The Targets tab is
shown in Figure 7-23.

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Figure 7-23: Report Timing - Targets Options Dialog Box

The available fields are:

• Start Points—Lets you choose the synchronous elements to begin the paths for
analysis. The Start Point fields are:
- From—Contains the expression used to filter the starting points. Enter text in this
field to manually create the filter, or view the filter text created by the Choose
Start Points dialog box.
- Choose Start Points —Opens a dialog box used to build the expression that
filters the starting points. This dialog box is described in further detail below.
- Transition—Further filters the paths according to the active clock edge of the
starting point synchronous elements. This field contains the following values:
- Rise—Filters all starting point synchronous elements to those triggered by a
rising (positive) clock edge.
- Fall—Filters all starting point synchronous elements to those triggered by a
falling (negative) clock edge.
- Rise/Fall—Filters the starting point synchronous elements to those triggered
by both rising and/or falling clock edges.
• Through Point Groups—Enter paths that travel through a set of points for analysis.
The following fields are available:
- Through—Contains the expression used to filter the paths based on the points the
path travels through.
- Choose Through Points —Opens a dialog box to build the expression that filters
the paths based on the through points.
- Transition—Further filters the paths according to the active clock edge of the
through point synchronous elements. This field contains the following values:

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- Rise—Filters all through point synchronous elements to those triggered by a

rising (positive) clock edge.
- Fall—Filters all through point synchronous elements to those triggered by a
falling (negative) clock edge.
- Rise/Fall—Filters the through point synchronous elements to those triggered
by both rising and/or falling clock edges.
- More—Adds additional through point filter expressions
- Fewer—Removes existing through point filter expressions
• End Points—Enter paths that end in a set of synchronous elements. This section
contains the following fields:
• Choose End Points—Opens a dialog box used to build the expression that filters the
paths based on the ending points.
- Transition—Further filters the paths according to the active clock edge of the
starting point synchronous elements. This field contains the following values:
- Rise—Filters all ending point synchronous elements to those triggered by a
rising (positive) clock edge.
- Fall—Filters all ending point synchronous elements to those triggered by a
falling (negative) clock edge.
- Rise/Fall—Filters the ending point synchronous elements to those triggered
by both rising and/or falling clock edges.

Understanding the Choose Points Dialog Box

The Choose Points dialog box lets you choose the design elements for which you require
timing analysis based on element type and a pattern matching string and lets you enter
filter strings for the Start Points, Through Points, and End Point.
Figure 7-24 shows the Choose Start Points dialog box.

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Figure 7-24: Choose Start Points Dialog Box

The options are:

• Find Names of Type—Filters the points based on the type of design element. The
field contains the following options:
- Cells—Choose design elements based on cell name.
- Clocks—Choose design elements based on clock name.
- Pins—Choose design elements based on pin name.
- Ports—Design elements based on port name.
• Matching Style—Select the type of pattern matching used for filtering the design
elements. The field contains the following options:
- UCF—Choose UCF-based syntax for pattern matching.
- SDC—Choose a Synopsys Design Constraints (SDC)-based syntax for pattern
matching.
• Pattern—The pattern expression used to filter the design elements. This field is
modified with the following options:
- Regular Expression—Specifies the search string will use regular expression
syntax.
- Ignore Case—Specifies the search string will be case insensitive.
- Search Hierarchically—This option is available for SDC pattern matching, and
specifies that the SDC-based search pattern is applied to every level of hierarchy.

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• Objects—The field is used to select objects based on dialog box selection. The
following options are available:
- Include Leaf Pins—An SDC syntax option that specifies that the search string
should only match pins components, and not match pins across hierarchical
boundaries.
- Select Object Dialog Box—An SDC syntax option that launches an additional
object selection dialog box where you can generate recursive search expressions.
- Filter Matching Name with Expression—An SDC syntax option that specifies
the -filter command.
• Ignore Command Errors—Suppresses warning messages generated during Tcl
command processing of the timing report.
• Find Results—Contains the results of the object search.
• Selected Name—Contains the subset of the search result objects that are chosen for
the Points.
• Command—Contains the Tcl command used to represent the selected objects.

Understanding the Options Tab Selections

The Options tab of the Report Timing dialog box contains fields that let you specify the
type of timing report to be generated as well as the number of paths reported. The Options
tab is shown in Figure 7-25.

Figure 7-25: Report Timing - Options tab

The fields available in the Options tab dialog box are:

• Path Delay Type—Specifies the type of delays that are used in the timing report path
analysis. This field contains the following options:
- Max—Uses maximum delays for the clock and data paths during setup and hold
analysis.
- Min—Uses minimum delays for the clock and data paths during setup and hold
analysis.

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- Min_Max—Uses a combination of minimum and maximum delays for the clock

and data paths during setup and hold analysis.
• Path Report Format—Specifies the type of timing report to be generated. In many
cases, the format of the GUI timing report and written timing report are different,
based on the selected option. This field contains the following values:
- End—Specifies an endpoint report that contains only slack and endpoint
information for each path in the written timing report.
- Full—Specifies a timing report that contains full path details for the data path,
and hides the details of the clock path(s).
- Full_Clock—Specifies a timing report that contains full path details for the data
path, and summary details for the clock path(s).
- Full_Clock_Expanded—Specifies a timing report that contains full path details
for the data path, and full details for the clock path(s).
- Short—Specifies a timing report that contains summary details for the data path,
and hides the details of the clock path(s).
- Summary—Specifies a written timing report that only contains summary
information on the timing performance of the design.
• Do Not Report Unconstrained Path—Specifies that the report will contain details
for constrained paths only.
• Number of Paths Per Group—Specifies the number of timing paths reported per
group.
• Number of Paths Per Endpoint—Specifies the maximum number of timing paths
reported per endpoint.
• Limit Paths Per Group—Limits the paths to a group or set of groups. The group
identifier can be entered directly, or by using the Choose Path Groups dialog box.
• Display Paths With Slack Greater Than—Filters the displayed paths based on a
minimum slack value. Only paths with slack greater than this value will be shown.
• Display Paths With Slack Less Than—Filters the displayed paths based on a
maximum slack value. Only paths with slack less than this value will be shown.
• Significant Digits—Specifies the significant digits of the timing report delay values.
The default value is 3.
• Sort Paths By—Selects that parameter that will be used to sort the timing report. This
field contains the following values:
- Group—Sorts the timing report based on group name.
- Slack—Sorts the timing report based on path slack.
View and select any required Advanced options for the timing report.

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Understanding the Advanced Options Tab

The Advanced Options tab of the Report Timing dialog box contains fields that let you
specify pin and net details, report output locations, and command error processing. The
Advanced Options tab is shown in Figure 7-26.

Figure 7-26: Report Timing - Advanced Tab

The Advanced tab options are:

• Show input pins in the path—Shows the pins of each path element.
• List net names—Lists the name of the net connection each path element.
• Write results to file—Write the results of the timing report to a file. This field also
contains options to designate how the details of the report will be written to that file.
These options include:
- Overwrite—Overwrites the specified file with the details of the timing report.
- Append—Appends the timing report details to the specified file name.
• Quiet Mode—Suppresses messages in the timing report regarding errors in command
options.
View and select the appropriate timer settings for the timing report.

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Understanding the Timer Settings Tab

The Timer Settings tab of the Report Timing dialog box contains fields that allow the
designer to specify the delays parameters used by the timing engine in generating the
timing report. Figure 7-27 shows the Timer Settings tab.

Figure 7-27: Report Timing - Timer Settings Tab

The timer settings options are:

• Interconnect—Selects the type of delay values used for the interconnect delay. The
different delay values are as follows:
- Estimated—Uses estimated delays for the interconnect values
- None—Sets the interconnect delays to 0.
• Speed Grade—Selects the speed grade of the device used in the timing analysis. This
field allows the estimation of design timing using different device speed grades.
• Multi-Corner Configuration—Enables the use of multi-corner analysis in the timing
report. Multi-corner analysis simultaneously uses different process and operating
condition corners to perform a worst-case setup and hold analysis. This results in a
more accurate, but pessimistic, analysis than minimum or maximum delays alone.
The fields in this area are:
- Enable multi-corner analysis—Enables multi-corner analysis.

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- Slow corner—Selects the delay types used for the slow corner analysis. The
available values are:
- None—Specifies that no delays are used when generating minimum timing
analysis.
- Max—Specifies that maximum delays are used for the clock and data paths
during setup and hold analysis.
- Min—Specifies that minimum delays are used for the clock and data paths
during setup and hold analysis.
- Min_Max—Uses a combination of minimum and maximum delays for the
clock and data paths during setup and hold analysis.
- Fast Corner—Selects the delay types used for the fast corner analysis. The values
are:
- None—Specifies that no delays will be used in the generation of minimum
timing analysis.
- Max—Uses maximum delays for the clock and data paths during setup and
hold analysis.
- Min—Uses minimum delays for the clock and data paths during setup and
hold analysis.
- Min_Max—Uses a combination of minimum and maximum delays for the
clock and data paths during setup and hold analysis.
- Enable timing pessimism removal—Removes the skew delay generated by the
common clock path between source and destination registers when modeling on-
chip delay variation.

Analyzing Timing Results

You can populate the Timing Results view with timing results from either the PlanAhead
Timing Analysis or from the ISE TRACE timing analysis tools.
Either the PlanAhead Timing Analysis or the ISE TRACE tool must be run first to populate
the Timing Results view with paths. The Timing Results view contains the paths that meet
the criteria defined in the Run Timing Analysis dialog box, as described in Running Timing
Analysis, page 178. When you import TRACE results, or run the PlanAhead Timing
Analysis with the default options, paths are sorted and listed by constraint.
The Timing Results view opens when the PlanAhead Timing Analysis completes or when
you import the ISE TRACE results. Figure 7-28 shows an example of timing results.

Figure 7-28: Timing Results

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You can examine, sort, and select specific paths and instances in the Timing Results
interface.
In the Timing Results view, the following information displays for each path:
• Constraint Name—Displays the constraint name for the paths listed.
- Name—Shows a sequential number with which to sort back to the original order.
- Type—Displays whether the path is Setup or Hold related.
- Slack—Displays the total positive or negative slack on the path.
- From—Displays the path source pin.
- To—Displays the paths destination pin.
- Total Delay—Lists the total estimated delay on the path.
- Logic Delay—Lists the delay attributed to logic delay only.
- Net%—Displays the percentage of the delay attributed to routing interconnect.
- Stages—Displays the total number of instances on the path including the source
and destination which both contribute to the overall delay. This may be different
than the method used to calculate levels of logic in ISE.
- Source Clock—Displays the source clock name.
- Destination Clock—Displays the destination clock name.
Note: In the PlanAhead Timing Analysis, a carry chain interconnect is counted as individual stages
of logic.

Sorting the Timing Report

You can sort the Timing Results by clicking any of the column headers. For example, click
on the Stages column header to sort the list by stages of logic. Click the column header a
second time to reverse the sort order.
You can sort by a second column by pressing the Ctrl key and clicking a second column
header. You can sort by as many columns as necessary to refine the list order.
Refer to the Using Tree Table Style Views in Chapter 4 for information regarding working
with tree table style views.
Figure 7-29 shows a timing result sorted by stages of logic.

Figure 7-29: Timing Results Sorted by Stages of Logic

Press Ctrl and click the column header again to remove a sort from a column.

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Flattening the List of Paths

By default, the paths are categorized by constraint. You can flatten the list and view all
paths by clicking:
• Group by Constraint in the Timing Results view.
• The Group Paths by Constraint button in the Timing Results view toolbar, as shown in
Figure 7-30.

Figure 7-30: Group Paths by Constraint Toolbar Button

The Group by Constraint toolbar button toggles between a categorized list of constraints
and a flattened list of paths.

Removing Paths from the Timing Report

You can remove paths from the timing report to make for easier sorting and viewing of
critical paths.
1. Select the paths to remove paths from the timing report. To select multiple paths, press
the Shift or Ctrl keys, and select the paths.
2. Press the Delete key, or select Delete from the popup menu in the Timing Results view.

Displaying Path Details

When you select a path from the list, the Path Properties view is populated with
information about the path. Logic elements are listed with detailed delay information and
hyperlinks, as shown in Figure 7-31, page 191.

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Figure 7-31: Path Properties View: Report Tab

The report has a similar format to the TRACE report.

• By default, selecting a path also selects all instances contained within the path.
• Selecting any of the blue-hyperlinked objects in the report also selects them in other
views such as the Netlist and Device views.
• You can select multiple paths using the Shift and Ctrl keys.
• All instances contained in the selected paths are selected, but the Path Properties
displays information only about the first path selected.

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Displaying Timing Path Reports in the Workspace

An individual Timing Path Report can also be displayed in the Workspace for easier
viewing. Also, multiple path reports can be opened in separate views in the WorkSpace.
To view the report:
1. Select the timing path.
2. Select the View Path Report popup menu command.

Using Slack Histograms

The Slack histogram provides a visual indication of the timing delays in the design. This
view can assist the designer in determining the next course of action if the design is not
meeting performance requirements.
1. Select one of the following methods to generate a Slack histogram:
- Tools > Slack Histogram
In the Flow Navigator:
- Netlist Design > Slack Histogram
- Implemented Design > Slack Histogram
Figure 7-32 shows the Slack Histogram option from the Netlist Design environment.

Figure 7-32: Slack Histogram Option

The Generate Slack Histogram dialog box opens, as shown in Figure 7-33, page 193,
and you can customize the slack histogram.

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Figure 7-33: Slack Histogram Dialog Box

2. Selecting OK displays a slack histogram with default values.

The options are:
- Histogram Name—Specifies the name of the histogram report that is generated
- Options Tab—Allows the customization of the histogram report. The detailed
options of this tab are further described below.
- Timer Settings Tab—Specifies timing engine and delay options used to generate
the timing report. The detailed options of this tab are further described below.
- Command—Contains the text of the TCL command generated by the Generate
Slack Histogram options.
3. Select the appropriate options for the histogram report.

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Setting Slack Histogram Options

You can specify the option used to generate the sack histogram using the Options tab of the
Generate Slack Histogram dialog box. The Options tab is shown in Figure 7-34.

Figure 7-34: Slack Histogram Options Dialog Box

The options are:

• Endpoint Scope—Specifies the endpoints and delay types to be used in the slack
histogram generation. By filtering the endpoints based on clock name and group
name, a histogram can be generated to focused in on the paths of interest. The fields in
this area are as follows:
- Delay Type—Specifies the delay values that will be used in the generation of the
slack histogram.
- Min—Uses minimum delays for the clock and data paths for the slack
histogram.
- Max—Uses maximum delays for the clock and data paths for the slack
histogram.
- Min_Max—Uses a combination of minimum and maximum delays for the
clock and data paths for the slack histogram.
• Clock Name—Filters the endpoints by the associated clock name. The value for this
field can be entered directly or by using the Choose Endpoints dialog box.
• Group Name—Filters the endpoints by the associated group name. The value for this
field can be entered directly or by using the Choose Endpoint Path Groups dialog box.

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• Slack Range—Filters the endpoints based on the slack value. By filtering the
endpoints based on the slack value falling within a specific range, a histogram can be
generated to focused in on the paths of interest. The fields in this area are as follows:
- Greater Than—Specifies the maximum slack value of slack that a path may have
to be included in the histogram.
- Less Than—Specifies the minimum slack value of slack that a path may have to
be included in the histogram.
• Bin Display—Allows further customization of the histogram. This field contains the
following values:
- Number of Bins—Specifies the number of bins in the histogram. By selecting a
smaller number of bins, the histogram provides a general view of the timing
performance of the design. Histograms with larger number of bins are best used
within a slack range to focus in on the performance of a specific range of delays.
- Significant Digits—Specifies the number of significant digits that will be used in
the histogram. By default, this value is set to 3.
- Plot on Log10 scale—Specifies whether to draw the resulting slack histogram
with the Y axis on a logarithmic or linear scale. Log scale is useful when there are
delay bins that are very small relative to other larger bins, and consequently
difficult to see clearly with a linear scale. This setting can be controlled through
the toolbar after the histogram has been drawn also.

Using Slack Histogram Timer Settings

You can specify the delays parameters used by the sack histogram timing engine in the
Timer Settings tab of the Generate Slack Histogram dialog box. The Timer Settings tab is
shown in Figure 7-35.

Figure 7-35: Slack Histogram - Timer Settings Tab

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The Slack Histogram Timer Settings options are:

• Interconnect—Selects the type of delay values used for the interconnect delay. The
delay values are:
- Estimated—Uses estimated delays for the interconnect values.
- None—Sets interconnect delays to 0.
• Speed Grade—Selects the speed grade of the device used in the timing analysis. This
field allows the estimation of design timing using different device speed grades.
• Multi Corner Analysis—Enables the use of multi-corner analysis in the timing report.
Multi-corner analysis simultaneously uses different process and operating condition
corners to perform a worst-case setup and hold analysis. This results in a more
accurate, but also pessimistic, analysis than minimum or maximum delays alone. The
fields in this area are:
- Enable multi-corner analysis: Select this field to enable multi-corner analysis.
• Slow Corner—Selects the delay types that will be used for the slow corner analysis.
The different values available are:
- None—Specifies that no delays will be used in the generation of minimum timing
analysis.
- Max—Uses maximum delays for the clock and data paths during setup and hold
analysis.
- Min—Uses minimum delays for the clock and data paths during setup and hold
analysis.
- Min_Max—Uses a combination of minimum and maximum delays for the clock
and data paths during setup and hold analysis.
• Fast Corner—Selects the delay types that will be used for the fast corner analysis.
The available values are:
- None—Specifies that no delays are used in the generation of minimum timing
analysis.
- Max—Uses maximum delays for the clock and data paths during setup and hold
analysis.
- Min—Uses minimum delays for the clock and data paths during setup and hold
analysis.
- Min_Max—Uses a combination of minimum and maximum delays for the clock
and data paths during setup and hold analysis.
• Enable Timing Pessimism Removal—Removes the skew delay generated by the
common clock path between source and destination registers when modeling on-chip
delay variation.

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Analyzing Timing Histogram Results

Once the histogram is generated, you can use the results to obtain an indication of the type
of timing problems associated with the design Implementation. The Histogram View
contains a visual graph of the delays (bins) associated with the design and lists each of the
paths in the Timing Results view.
This interface lets you arrange the paths according to the column headers of the table, as
well as by selection from the graph. Figure 7-36 is an example of the slack histogram
results.

Figure 7-36: Slack Histogram

You can change the scale of the Y-axis to be either Logarithmic or Linear using the Plot
histogram on log10 scale toolbar button, shown in Figure 7-37.
.

Figure 7-37: Plot Histogram on Log10 Scale Button

Figure 7-38, page 198 displays an example of the slack histogram graph view using a
logarithmic scale.

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Figure 7-38: Slack Histogram - Log10 scale

Selecting Paths for Analysis

The Histogram provides selection and filtering of paths for analysis. The selected paths
display in the Timing Results view. The selection options include:
• View Individual Bin Paths—Select an individual path by left-clicking on a histogram
bin. The Timing Results view updates automatically to reflect the bin selection.
• View Paths from Multiple Bins—Filter the paths that are shown by left-clicking
several bins in the graph. To add and remove bins from the selection press the Ctrl key
and left-click the bin. The Timing Results view updates automatically to reflect the bin
selection.
• View All Paths—Select all paths in the design from the histogram by left-clicking on
any location in the graph that is not a bin. Once clicked, the Timing Results view
updates automatically to show all paths.

Changing Histogram Options

The histogram display can be redrawn at any time to reflect a new set of options. To bring
up the options to change the display right-click on the histogram. There are two methods
available to change the histogram display:
• Report Timing—Generates a new timing report using the Report Timing dialog box.
• Refresh Histogram—Generates a new histogram using the Generate Slack
Histogram dialog box.

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• View—Changes the view of the histogram to better focus in on paths of interest.

This selection contains the following options:
- Zoom In—Increases the zoom level.
- Zoom Out—Decreases the zoom level.
- Zoom Fit—Views the entire histogram in the display.
- Zoom Area—Fits a selected area in the entire display.
- Options—Invokes the main PlanAhead Options menu.

Defining Physical Constraints

PlanAhead provides a variety of means to apply physical constraints. Physical constraints
consist of LOC/BEL instance placement constraints, AREA_GROUP placement
constraints, DCI_CASCADE constraints and Device Configuration Mode constraints. For
more information on assigning physical constraints, refer to Chapter 8, “I/O Pin
Planning,” and Chapter 11, “Floorplanning the Design.”
The following subsections describe the Physical Constraints view and the available
options.

Using the Physical Constraints View

The Physical Constraints view is used to display and interact with a variety of physical
constraint types.
It displays the hierarchical structure of the design relative to the created Pblocks. The
physical hierarchy is dynamic; expanding and changing automatically when physical
hierarchy is manipulated. As objects are selected in other views, the appropriate elements
are highlighted in the Physical Constraints view.
The objects displayed in the Physical Constraints view are Relatively Placed Macros
(RPMs) and Physical Block (Pblocks), and DCI Cascade Constraints. You can select these
objects in the Physical Constraints view for manipulation in other views.

Using the ROOT Design Pblock

The physical hierarchy begins with the design name followed by the top-level Pblock
called “ROOT.” As you create lower-level Pblocks they display in a hierarchical fashion
under the /Pblock folder, with Child Pblocks nested under their parent Pblock, shown in
Figure 7-39.

Figure 7-39: Physical Constraints View

Selecting a Pblock selects all of the assigned logic for that Pblock.

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Understanding the Physical Constraints View Icons

The Physical hierarchy Pblock tree uses several icons that can help you identify the state of
the various objects. This display updates automatically as you manipulate the physical
hierarchy.
As you create Pblocks. they appear in a hierarchical fashion in the Physical Constraints
view. Each folder type in the Physical Constraints view displays a number in parenthesis
that details the number of objects in that folder.
Each instantiation of an RPM displays in the Physical Constraints view. If RPMs are
assigned to Pblocks, they appear in an RPM folder under the Pblock. Selecting an RPM in
the Physical Constraints view selects all of the logic contained in the RPM.

Pblocks With Assigned Instances

Pblocks with instances assigned and with rectangles defined in the Device view appear as
blue three-dimensional cubes with a yellow center as shown in the following snippet.

Pblocks with instances assigned and with no rectangles defined in the Device view appear
as blue two-dimensional squares with a yellow center as shown in the following snippet.

Pblocks Without Assigned Instances

Pblocks with no instances and with rectangles defined assigned appear as blue three-
dimensional cubes with a blue P in the center as shown in the following snippet.

Pblocks with no instances assigned with no rectangles defined appear as blue two-
dimensional squares with a blue P in the center as shown in the following snippet.

Partially Reconfigurable PBlocks

Partially reconfigurable partition Pblocks appear as yellow diamonds as shown in the
following snippet.

Working with Relatively Placed Macro (RPMs)

Relatively Placed Macros (RPMs) that exist in the design are listed under the RPMs
folders. RPMs can be assigned to Pblocks. If RPMs are assigned to Pblocks, they appear in
an RPM folder under the Pblock. Each instantiation of an RPM displays in the Physical
Constraints View (as shown in Figure 7-39). RPM Properties and statistics display in the
RPM Properties view, as shown in Figure 7-40, page 201.

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Figure 7-40: Displaying Relatively Placed Macros “RPMs”

When RPMs are assigned to Pblocks, the Pblock Properties view displays RPM size and
utilization statistics information as shown in Figure 7-41.

Figure 7-41: RPM Utilization Statistics for Pblocks

Running the Design Rule Checker (DRC)

The PlanAhead software contains a set of batch DRC commands that can help verify
design integrity prior to running the ISE software. The rules are categorized by type of
logic checks being performed. Many different types of checks are available.
These checks are designed to provide an early indication about potential design
Implementation issues. The final validation step to ensure the design is DRCs compliant is
to run the design through the ISE Implementation tools.

Running I/O Port and Clock Logic DRCs

Many of the DRC rules are related to I/O pin assignment and clock logic. For information
on running I/O Port and lock logic related DRCs, see Chapter 8, “I/O Pin Planning.”

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Running Netlist and Constraint DRCs

To run DRCs on the Netlist Design to validate netlist and constraint condition:
1. From the Flow Navigator or Tools menu, select the Run DRC command.
The Run DRC dialog box opens, as shown in Figure 7-42.

Figure 7-42: Run DRC Dialog Box

2. View or edit the Results Name field. Enter a name for the results for a particular run for
easier identification during debug in the DRC Violations browser.
3. Enter an Output File name to create a report text file.
4. In the Rules to Check group box, use the check boxes to select the design rules to
check for each design object. For a description of each rule, see Running Netlist and
Constraint DRCs, page 202.

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- Expand the hierarchy using the Expand All toolbar buttons, or click the + next to
each category or design object.
- Click the check box next to the design object to run all DRCs.
- Click individual DRCs to run individual ones.
- Click Select All to run a complete DRC.
5. Click OK to invoke the selected DRC checks.

Viewing DRC Violations

Once completed, the DRC Results view opens, as shown in Figure 7-43.

Figure 7-43: DRC Results

Each violation is expanded in the DRC Results view.

• Errors display a red icon.
• Warnings display an amber icon.
• Informational messages display a yellow icon.
By default, all errors and warnings display. You can hide all warnings and informational
messages and view only errors by clicking the Hide Warning and Information Messages
toolbar button. Click the toolbar button as shown in Figure 7-44, page 204 again to view all
errors and warnings again.

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Figure 7-44: Hide Warning and Information Messages Button

Select an error in the DRC Results view list, and the specific violation information displays
in the Properties view.
Select a blue link in the Properties view to highlight the violating design elements in the
Device view, Netlist view, and Schematic view as shown in the preceding figure.
Violations no longer display in the DRC Results view after you fix the error condition and
the re-run the DRC check.
Each time you run the Run DRC command and the DRCs detect errors, PlanAhead adds a
new results tab to the DRC Results view, and creates a separate results output file in the
PlanAhead invocation directory.

DRC Rule Descriptions

The following tables describe the DRC rules, rule intent, and severity.
• Floorplan Pblock DRCs
• Bank DRC
• DCI DRCs
• ClkBuf DRCs
• DSP48 DRCs
• RAMB16 DRC
• Netlist DRC
• Instance DRCs
Note: For Global Clock, IOB, and Bank IO Standard DRCs, see Chapter 8, “I/O Pin Planning.”

Floorplan Pblock DRCs

Table 7-1: Floorplan Pblock DRCs
Rule Name Rule Abbrev Rule Intent Severity
Longest Carry LCCH Checks that the Pblock height can Amber
Chain Height accommodate longest Carry Chain Warning
assigned to Pblock.
Pblock overlap FLBO Checks for overlapping Pblock Information
rectangles.
Pblock Partition FLBP Checks that the LUT to MUXCY and Error
MUXFx connection is not broken by a
Pblock partition.
Resource UTLZ Checks that Pblocks have enough Warning for
Utilization resources for logic assigned to them. SLICE logic.
Error for non-
SLICE logic.
Area Group Tile FLBA Checks that the site ranges in Warning
Argument AREA_GROUP constraints are aligned
with the CLB grid.

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Bank DRC
Table 7-2: DCI Cascade DRC
Rule Name Rule Abbrev Rule Intent Severity
DCI Cascade DCIC Checks that DCI cascade constraint is Error
Checks legal.

Table 7-3: IDelay Control DRC

Rule Name Rule Abbrev Rule Intent Severity
IDelayCtrl IDLYCTRL Checks that IDelay placement is Error
Checks consistent with IDlyController LOCs

For a full list of Bank IO standard rules see Bank I/O Standard DRCs in Chapter 8.

DCI DRCs
Table 7-4: DCI DRCs
Rule Name Rule Abbrev Rule Intent Severity
DCI Cascade DCICPC Warns the user to load the UCF file into Warning
with part other compatible parts, and to run DRC
compatibility manually to ensure the DCI cascades
are valid.
DCI check for DCICIOSTD Ensures that there are no conflicts Error
I/O standard related to Vcc and DCI termination of
legality I/O standards used within the DCI
Cascade.

ClkBuf DRCs
Table 7-5: IDelay Control DRCs
Rule Name Rule Abbrev Rule Intent Severity
BufR & BufIO BUFRIOC Checks that BUFR and BUFIO driven Error
Locations by the same regional clock terminal are
placed at mutually route-able locations.

See Global Clock DRCs in Chapter 8 for a full list of Global clock rules.

DSP48 DRCs
Table 7-6: DSP48 DRCs
Rule Name Rule Abbrev Rule Intent Severity
DSP output DPOR DSP48 has a register on the output Information
registers side; to use this register the register
should be synchronously controlled.
(Virtex-4 only)
DSP input DPIR DSP48 has a register on the input side; Information
registers to use this register the register should
be synchronously controlled.
(Virtex-4 only)

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Table 7-6: DSP48 DRCs (Continued)

Rule Name Rule Abbrev Rule Intent Severity
DSP output DPOP DSP48 has a register on the output Information
pipelining side; using this pipeline mechanism
will improve performance.
(Virtex-4 only)
DSP multiplier DMOP DSP48 output is not pipelined. Warning
output Pipelined output will improve
pipelining performance.
DSP input DPIP DSP48 has a register on the input side; Information
pipelining using this pipeline mechanism will
improve performance.
(Virtex-4 only)

RAMB16 DRC
Table 7-7: RAMB16 DRC
Rule Name Rule Abbrev Rule Intent Severity
RAMB16 output RBOR RAMB16 has a register on the output Information
registers side; to use this register, the register
should be synchronously controlled.
(Virtex-4 only)

Netlist DRC
Table 7-8: Net DRC
Rule Name Rule Abbrev Rule Intent Severity
Driverless Nets NDRV Checks that each net has a proper Warning
driver pin.

Instance DRCs
Table 7-9: Instance DRCs
Rule Name Rule Abbrev Rule Intent Severity
Black Box INBB Checks that there is no blackbox Warning
Instances (undefined logics in the netlist).
Mismatching ULMN Detects mismatching logic module Error
Block interfaces in the netlist.
Mismatching ULMP Detects mismatching logic module Error
Pin pins in the netlist.
Mismatching ULMA Detects mismatching logic attributes Error
Attribute in the netlist.

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I/O Pin Planning

This chapter contains the following sections:
• I/O Planning Overview
• Using the I/O Planner
• Viewing Device Resources
• Defining Alternate Compatible Parts
• Setting Device Configuration Modes
• Defining and Configuring I/O Ports
• Disabling or Enabling Interactive Design Rule Checking
• Placing I/O Ports
• Validating I/O and Clock Logic Placement
• Removing I/O Placement Constraints
• Exporting I/O Pin and Package Data
• Using Noise Analysis Predictors

I/O Planning Overview

The I/O Planner environment provides an interface to analyze the design and device I/O
requirements, and to define an I/O pinout configuration or pinout that satisfies the
requirements of both the PCB and the FPGA designers. The PlanAhead™ software lets you
create I/O port signals (I/O Planning project only), and import I/O port lists from Comma
Separated Value (CSV) files, User Constraint Files (UCF), or Register Transfer Level (RTL)
files project types only. This allows for early and intelligent pinout definition to eliminate
pinout-related changes that typically happen later in the design which can improve
performance. Often, designers are hindered by a non-optimal pinout that causes further
delays when trying to meet timing and signal integrity requirements. By considering the
data flow from Printed Circuit Board (PCB) to FPGA die, you can achieve optimal pinout
configurations quickly, thus reducing internal and external trace lengths as well as routing
congestion.

I/O Pin Planning Methodology

I/O pin planning is a complex process involving design groups that include PCB
designers, FPGA designers, and the System designer; each with their own specific set of
concerns and requirements.This chapter focuses on using the PlanAhead environment to
perform device exploration and I/O pin planning and related tasks. For more information
about Xilinx®-suggested I/O pin planning methodology, refer to the Spartan-6 PCB Design
Guide, (UG393).

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I/O Planning Stages

PlanAhead facilitates I/O planning at various stages of the design process. As the design
progresses, more information becomes available, enabling more complex rule checking as
the design is synthesized and implemented.
Proper I/O assignment can depend on how the clocks are configured. Assigning I/Os and
clock logic often go together. For the I/O placement DRCs to account for clocks, a
synthesized netlist design is required.Whenever possible, it is optimal to perform I/O
assignment with a netlist design.
The final validation of a I/O pin and clock configuration is to run the design through the
Implementation tools. Proper clock resource validation can require full Implementation of
all clocks.

Creating Pin Planning Projects

You can create an empty project to enable early device exploration and I/O port
configuration. You can create I/O ports manually or import them from CSV or UCF inputs.
You can export device and I/O port assignment in any of these formats for later use in the
design process when an RTL design exists.

Elaborating and Checking RTL Designs

You can perform I/O planning in a PlanAhead RTL-based project. The RTL design is
elaborated and certain basic DRC checks are provided. To check clock logic, validation
with a synthesized netlist is optimal.

Synthesizing Netlist Designs

You can perform I/O planning after Synthesis in the netlist design. Because all clock are
determined, a more thorough validation is performed because the tool has visibility to all
clocks. Whenever possible, I/O assignment should be performed using a netlist design.

Implementing the Design and Final I/O Validation

The design should be fully implemented to ensure a legal I/O pinout. Examine the
Ngdbuild and Map reports for I/O and clock-related messages. Only ISE Implementation
tools have sign-off DRCs.

I/O Port Placement Capabilities

You can select and configure ports or interfaces using the Configure I/O Ports command.
This command provides a way to set I/O standard, drive strength, and slew type. The I/O
Planner supports output to a CSV format file for use in PCB schematic symbol creation or
the HDL port list. See Configuring I/O Ports, page 220.
You can place Prohibits on individual I/O pins or I/O banks to prevent I/O assignment to
them. See Prohibiting I/O Pins and I/O Banks, page 224.
The I/O port placement can be performed in the following methods:
• Group I/Os together into interfaces to more identify them more easily or select them
for placement. See Creating I/O Port Interfaces, page 224.
• Drag groups of I/O ports and assign them into either the Package view or Device
views using one of three placement modes: in an I/O Bank, in an Area, or
Sequentially.

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Each I/O placement mode offers a different assignment method for the I/O ports to be
assigned to pins. The cursor tool tip provides information about the number of ports being
placed.
The I/O placement mode remains active until all of the selected I/O ports are placed or
until you press the Esc key. For more information, see Disabling or Enabling Interactive
Design Rule Checking, page 226.
The Tools > Autoplace I/O Ports command places the I/Os or any selected portion of the
I/Os automatically. The command obeys I/O bank rules, differential pair rules, and global
clock pins, and places as many of the I/O Ports as possible.This functionality is available
for certain device architectures only and you must have a synthesized netlist in order for
all available rules to be applied. See Automatically Assigning I/O Ports, page 230.
The PlanAhead software attempts to maintain correct assignment rules. Differential pair
ports are assigned into proper pin pairs. Also, interactive and batch DRCs are used to help
ensure legal I/O placement. See Validating I/O and Clock Logic Placement, page 232.

Using the I/O Planner

You can use the I/O Planner in the RTL Design, Netlist Design, and Implemented Design
environments. The view layout consists of a both Package and Device graphical views.
Other views provide additional I/O information: the Package Pins view, the I/O Ports
view, the Clock Region view, and the Properties view.
There are two ways to launch the I/O Planner view layout:
• Select the I/O Planner button in the banner of the open Design environment.
• Create a new Pin Planning project using the New Project wizard.
Figure 8-1, page 209 shows the I/O Planner environment.

Figure 8-1: I/O Planner Environment

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The following references in Chapter 4, “Using the Viewing Environment,”apply to the I/O
Planner environment:
• Using the Device View, page 106
• Using the I/O Ports View, page 125
• Using the Package Pins View, page 127
• Using the Design Runs View, page 128

Splitting the Workspace to Display Device and Package Views

It is often helpful to split the Workspace and display the two views side by side as shown
in Figure 8-1.
You can split the workspace by either of the two following methods:
• Select either view tab and drag it to the very far right scroll banner of the workspace.
A grey rectangle displays where the view would be placed. Position the cursor so that
the Workspace view arrangement is to your liking and release the mouse to move the
view and split the workspace. Figure 8-2 shows and example of a split view. This
same technique works with many of the views.
• Use the New Horizontal Group or New Vertical Group popup menu commands on the
view tab. This capability is available for the Workspace views only.

Figure 8-2: Splitting the Workspace to Display Package and Device Views

Merging Views to One Tabbed Area

To collapse the views back into one tabbed area, select either:
• Any view and drag it onto the view tab of another. The dragged grey rectangle
displays around the entire view.
• The Move to Previous/Next Horizontal/Vertical Group popup menu command on the
view tab.

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Viewing Device Resources

The Device and Package views display a graphical representation of the device and placed
logic resources. When any logic object or device site is selected in any view, information
about it is displayed in the Properties view. The Properties view often has tabbed panes to
display various types of information as shown in Figure 8-3, page 211.
To view properties for a selected object, display the Properties view. If the Properties view
is not visible, select the Object_Type Properties popup menu command on the object, or
select Window > Properties.
You can search for specific objects or device sites by using the Find command. There are a
variety of searchable object types and robust filtering capabilities to search the device or
design for specific objects. You can select objects directly from the Find Results view; for
more information, refer to Using Find Commands to Search Source Files in Chapter 5.

Viewing Package Pin Properties

You can select pins or I/O banks in the Package view and see the corresponding details in
the Properties view, as shown in the Figure 8-3.

Figure 8-3: Package Pin Properties

Viewing I/O Bank Resources

You can select I/O resources in any of the I/O Planner views and their corresponding data
is highlighted in all other views. This provides a visual indication of the relationship
between the physical package and the internal die. The views contain many types of device
and design information, such as:
• In the Package Pins view, you can select one of the I/O banks.
• In the I/O Bank Properties view you can click the General tab. Figure 8-4, page 212
illustrates the I/O bank display.

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Figure 8-4: Displaying I/O Bank Location and Resources

Viewing Clock Region Resources

The Clock Regions view allows easy selection of the clock regions. Selecting a clock region
highlights the related I/O banks and regional clock resources as shown in Figure 8-5.

Figure 8-5: I/O Planner Clock Region Sources

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Viewing Clock Region Resource Statistics

Selecting the Statistics tab in the Clock Region Properties view displays the resource
statistics available within the clock region as well as the logic content of the selected clock
region.
Selecting the Resources tab enables device clock sites to be located for logic assignment, as
shown in Figure 8-6.

Figure 8-6: Viewing Clock Region Resources

Viewing Multi-Function Pins

The Package Pins view contains a variety of data types that display in spreadsheet-like
columns. The view can be flattened, filtered, and sorted. You can move, hide, and
configure columns to display and compare the various multi-function pins. Cells with
editable values can be directly edited by entering text or selecting from drop-down menus.
Figure 8-7 shows an example of the Package Pins view.

Figure 8-7: Package Pin Tab

The Type column identifies multi-function types of pins. Other columns contain
information about logic or configuration modes involving multi-function type pins.
If your design contains Gigabit Transceivers (GTs), Memory controllers, or PCI logic,
information appears in this table that identifies conflicting multi-function pins.
Use the Set Configuration Modes command can to select the required device configuration
modes. Many of these configuration modes use multi-function pins. For more information,
see Setting Device Configuration Modes, page 215.

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Defining Alternate Compatible Parts

The PlanAhead software lets you select alternate devices for the design. PlanAhead
attempts to ensure that a legal I/O pin assignment is defined and will work across all of the
selected devices.
To define an alternate compatible part:
1. Select Tools > Set Part Compatibility from the main Tools menu or the popup menu
command in the Package, Package Pins, or I/O Ports view.
Compatible devices available in the same package display in a list as shown in
Figure 8-8.

Figure 8-8: Select Alternate Compatible Parts

This feature supports alternate parts available in the same package only.
2. Select any number of alternate parts. The number of available Package Pins for
placement diminishes as more parts are selected.
PlanAhead automatically prohibits signals from being assigned to any unbonded pins in
the selected alternate devices. A dialog box displays showing the number of prohibited
package pins. These package pins receive PROHIBIT constraints.
You can view Prohibits in the Package, Package Pins, and Device views also. You can view
and manage alternate parts defined in the Floorplan Properties view under the Part
Compatible tab.
Note: The Set Part Compatibility command supports Virtex®-5, Virtex-6 and Spartan®-6 parts only.
Note: If you are defining an alternate compatible part for a Spartan-6 LX25 or LX25T device, pins
that are bonded will be prohibited because of differences in the clocking topology between this device
and alternate compatible parts in the same package. Refer to AR 34885 for more information.

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Setting Device Configuration Modes

PlanAhead provides information about the various device configuration modes and lets
you set any number of them as shown in Figure 8-9.

Figure 8-9: Set Configuration Modes Dialog Box

To set the device configuration modes:

1. Select Tools > Set Configuration Modes or the popup menu command in the Package,
Package Pins, or I/O Ports view.
- Click any configuration mode to view information, including the schematic.
- Click Datasheet to invoke the device datasheet in a PDF viewer.
2. Select the configuration modes you want and click OK.
Setting configuration modes displays the associated I/O pins in the Config column of the
Package Pins view.
For more information about analyzing how the configuration modes might conflict with
other multi-function pins, refer to Viewing Multi-Function Pins, page 213.

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Defining and Configuring I/O Ports

You can create and configure I/O ports using the I/O Planner environment. You can create
empty projects and generate I/O ports.

Importing I/O Ports

The PlanAhead software supports importing UCF or CSV format files into an empty
PlanAhead project to begin I/O pin planning. RTL files or headers can be used to create an
RTL project for I/O pin planning.
Creating an RTL-based or synthesized netlist-based project populates the I/O Ports view
automatically with the I/O ports defined in the design.

Importing a CSV Format File

To import an I/O ports list from a CSV:
1. Select File > Import I/O Ports > From CSV.
The Import I/O Ports dialog box opens as shown in Figure 8-10.

Figure 8-10: Import I/O Ports Dialog Box

2. Select the CSV File option, and use the browse button to select the CSV file to import.
The CSV file format is shown in Figure 8-11.

Figure 8-11: I/O Port List CSV Format

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CSV Columns
CSV is a standard file format used by FPGA and board designers to exchange information
about device pins and pinout.
The CSV columns are:
• I/O Bank—The I/O Bank in which the pin is located. The software fills in this field for
all pins in the device. Values are a number or blank. This is not required in the input
CSV file.
• Pin Number—The name (or location) of the package pin. The software writes this out
for all pins in the device. This is not required in the input file. If used for input, it is
used to define placement. Values are legal pins in the device.
• IOB Alias—An alternate part name for the package pin. This field is specified by the
software, and is unused if specified in the input CSV file.
• Site Type—The pin name from the device data sheet. This field is specified by the
software, and is unused if specified in the input CSV file.
• Min/Max Trace Delay—The distance between the pad site of the die and the ball on the
package, in picoseconds.
This is specified by the tool to help the board engineer match trace delays. The Trace
Delay fields are in the output file only. They are not expected in the input file.
• Prohibit—Certain sites can be prohibited for many reasons to prevent user I/O from
being added to the site. Prohibits ease board layout issues, reduce cross-talk between
signals, and ensure that a pinout works between multiple FPGAs in the same
package. In the UCF this is represented by a CONFIG PROHIBIT constraint. Values are
TRUE or a blank field; leave this field blank when the Pin Number is left blank.
• Interface—An optional user-specified grouping for an arbitrary set of user I/O. As an
example, this field provides a means to specify a relationship for the data, address,
and enable signals for a memory interface. Values are a text string or blank.
• Signal Name—The name of the User I/O in the FPGA design. Values are a string or
blank for an unassigned Package Pin.
• Direction—The direction of the signal. Values are IN, OUT, INOUT, or blank when a
user I/O is not assigned to the site.
• DiffPair Type—Instructs the software about which pin is the N side of a differential
pair, and which pin is the P side. This is used for differential signals only.
The software uses this column instead of a naming convention to determine which
pin is the N side of the pair, and which pin is the P side.
Values are P, N, or blank when a user I/O is not assigned to the site.
• DiffPair Signal—Specifies the name of the other pin in the differential pair. Values are
the name of the user I/O or blank when unused.
• I/O Standard—I/O standard for a specific user I/O. When this field is blank for a user
I/O, the software uses the appropriate device defaults. Values are a legal I/O
standard for the user I/O in the device or blank.
• Drive—Drive strength of the I/O standard for a specific user I/O. Not all I/O
standards accept a drive strength. If this field is blank the tools will use the default.
Values are a number or blank.
• Slew Rate—Slew rate of the I/O standard for a specific user I/O. Not all I/O
standards accept a slew rate. If this field is blank the tools will use the default. Values
are FAST and SLOW.

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• Phase—Specifies the phase of an I/O relative to the phase of other I/O in the bank in
cases of a synchronous phase offset.
• OFFCHIP_TERM—Specifies the external board level termination of the I/O. This is
used for SSN calculations. If the field is left blank, PlanAhead uses the expected
terminations in the SSN calculations and shows this expected termination by default
in the SSN report and I/O Ports table. The expected terminations, as well as the
corresponding shortened names that display in PlanAhead, can be found in the
Spartan-6 SelectI/O User Guide (UG381).
• OUT_TERM—Defines the optional OUT_TERM driver impedance attributes for
Spartan-6. This is most commonly left blank and is not yet supported for production
devices. Using OUT_TERM overrides the SLEW and DRIVE STRENGTH attributes
and is not supported in SSN calculations.
You can attach other information also. The software will add any other fields with user-
defined values to the set of user-defined columns.

Using Custom CSV I/O Port Properties

PlanAhead has a specific expected format for importing I/O pin-related data, as described
in the previous section. CSV files may also contain additional information. If additional
columns exist in the imported CSV file, PlanAhead creates new columns in the Package
Pins view to display and/or modify the field values.
To modify or define values in the customer CSV fields, select the Set User Column Values
popup menu command.
When you select File > Export I/Os > CSV, the columns and new values are preserved and
exported in the output CSV file.

Importing a UCF Format File

PlanAhead lets you import a UCF format files as a way to populate the I/O Ports view. To
import I/O port definitions from a UCF file, select File > Import I/O Ports and select the
UCF option to browse to a UCF file, as shown in Importing I/O Ports, page 216.
Because the UCF format does not define port direction, the Direction field displays as
undefined. Select the Set Direction command from the I/O Ports popup menu to define
I/O port direction. See Setting I/O Port Direction, page 221 for more information.
Note: If the imported UCF references ports are defined using wildcard (*) syntax, PlanAhead does
not expand the wildcards and therefore does not apply the constraints.

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Creating I/O Ports

To create I/O ports:
1. In the I/O Ports view, select Create I/O Ports from the popup menu.
The Create I/O Ports dialog box opens as shown in Figure 8-12.

Figure 8-12: Create I/O Ports Dialog Box

2. View and edit the options in the Create I/O Ports dialog box:
- Name—Enter the name of the desired port or bus to create.
- Direction—Select the port direction.
- Diff Pair—Define differential pair signals or busses.
- Create Bus—Enter bus range for bus creation.
- Configure
- I/O Standard—Select the I/O Standard constraint.
- Drive Strength—Select the Drive Strength value.
- Slew Type—Select the Slew Type value.
- Pull Type—Select the Pull Type value.
- Phase—Enter a phase group or select an existing phase group. A phase group
is a logical grouping of ports that is used in Simultaneous Switching Noise
(SSN) calculations to indicate that the set of ports share the same frequency
and phase. For more information on using this option, see Defining the I/O
Port Switching Phase Groups in SSN, page 243.
Refer to Xilinx® device documentation for information regarding voltage capabilities of
the device.

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Configuring I/O Ports

To configure a port or a group of ports:
1. In the I/O Ports view, select the ports.
2. From the popup menu, select Configure I/O Ports.
The Configure Ports dialog box opens, as shown in Figure 8-13.

Figure 8-13: Configure Ports Dialog Box

3. View and edit the definable options in the Configure I/O Ports dialog box:
- I/O Standard—Select the I/O Standard constraint. You can set all I/O Standards
on any I/O regardless of whether the tool has awareness of differential pairs,
although this might result in DRC errors.
- Drive Strength—Select the Drive Strength value.
- Slew Type—Select the Slew Type value.
- Pull Type—Select the Pull Type value.
- Phase—Enter a phase group or select an existing phase group.

A phase group is a logical grouping of ports that is used in SSN calculations to

indicate that the set of ports share the same frequency and phase. For more
information on using this option, see Defining the I/O Port Switching Phase
Groups in SSN, page 243.
Refer to Xilinx device documentation for information regarding voltage capabilities of the
device.

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Setting I/O Port Direction

To set the I/O port direction, select the I/O ports, busses, or interfaces to be configured,
and select the Set Direction popup menu command in the I/O Ports view.

Defining Differential Pairs

In a Pin Planning project, to define a differential pin pair, select any two I/O ports, and
select the Make Diff Pair popup menu command in the I/O Ports view, as shown in
Figure 8-14.
Note: The Make Diff Pair option is not applicable in RTL-based projects. In RTL-based projects it is
assumed that differential ports are defined in the source code using appropriate I/O buffer
instantiations.

Figure 8-14: Make I/O Diff Pair

The two I/O Ports display in the dialog box with initial Positive End and Negative End
definitions.
• To reverse the Positive End and Negative End signals, click Swap.
• To remove the differential pair definition on any differential pin pair, select the Split
Diff Pair popup menu command.

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Configuring DCI_CASCADE Constraints (VIrtex5 and Virtex6 only)

You can configure the DCI_CASCADE constraint within the PlanAhead environment. For
information about the intent and use of the DCI_CASCADE constraint, refer to the
Xilinx Constraints Guide, (UG625).
The basic premise of the constraint is to link two or more adjacent I/O Banks together for
DCI reference voltage purposes. The I/O bank with the DCI reference voltage is called the
Master and all others are Slaves. All banks in a cascade must be in the same column of the
device. You can set the constraint by preselecting the I/O Banks you want prior to running
the command or by selecting them within the command dialog box.
To create the DCI_CASCADE constraint:
1. Select the I/O Banks to configure.
2. Right-click and select the Create a DCI Cascade popup menu command. The DCI
Cascade Editor opens as shown in Figure 8-15.

Figure 8-15: Creating a DCI Cascade

3. To include additional I/O banks, select the Add button.

Preselected I/O Banks appear in the dialog box
4. Select an I/O Bank to be the master.
5. Click OK.
Notice that as I/O Banks are selected, they are highlighted in the other PlanAhead views.
The DCI Cascades display in the Physical Constraints view as shown in Figure 8-16,
page 223.
When you select a cascaded in the Physical Constraints view, you can view and edit details
in the Properties view.

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Figure 8-16: Viewing DCI Cascades

As you select DCI cascades in the Physical Constraints view, PlanAhead also selects the
associated I/O banks.

Modifying or Removing DCI Cascade Constraints

You can modify DCI Cascades by selecting the DCI Cascade in the Physical Constraints
view and using the DCI_CASCADE Properties view. The available actions are:
• To save all changes, click Apply in the DCI_CASCADE Properties view.
• To change the master, select a different I/O Bank and assign it as the master.
• To remove I/O banks from the DCI Cascade, select the I/O banks in the
DCI_CASCADE Properties view, and click Delete I/O Banks.
• To include additional I/O banks in the DCI Cascade, select them in the
DCI_CASCADE Properties view and click Add I/O Banks.
The Add I/O Banks dialog box displays and you can select new I/O banks. The
newly-selected I/O banks highlight in the other PlanAhead views also.
• To remove DCI Cascade constraints, select the constraint in the Physical Hierarchy
view and click Delete.

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Prohibiting I/O Pins and I/O Banks

I/O Planner provides an interface to selectively prohibit individual I/O pins, groups of
I/O pins, or I/O banks. You can select and prohibit pins in the Package Pins, Device, and
Package views.
To prohibit I/O pins or I/O banks:
1. In the Package Pins or the Package view, select the I/O pins or I/O banks.
2. Select Set Prohibit from the popup menu.
A red X symbol is placed on the prohibited pins in the Package view, and a checkmark is
placed in the Prohibit column of the Package Pins view as shown in Figure 8-17.

Figure 8-17: Setting Prohibits on Package Pins

Creating I/O Port Interfaces

You can group multiple ports or busses together by creating an Interface. This aids in pin
assignment by treating all of the interface ports as one group. Assigning all of the pins
simultaneously helps condense and isolate the interface for clock region or PCB routing.
Also, it is easier to visualize and manage all of the signals associated with a particular logic
interface.
To create an interface:
1. In the I/O Ports view, select the signals you want to group together.
2. From the popup menu, select Create I/O Port Interface as shown in Figure 8-18,
page 225.

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Figure 8-18: Create I/O Ports Interface

3. Enter a name for the interface and adjust assignment selection.

4. Click OK.
The interfaces appear as expandable folders in the I/O Ports view. You can add additional
I/O ports to the interface by selecting them in the I/O Ports view and dragging them into
the Interface folder as shown in Figure 8-19.

Figure 8-19: Manage I/O Port Interfaces

To include additional I/O ports in an interface:

1. Select a port or bus.
2. From the popup menu, select Assign to Interface.
3. Select the target interface to which you will add the I/O ports.
To remove I/O ports and interfaces:
1. Select a port or interface.
2. From the popup menu, click Unassign from Interface.
To delete interfaces, select an interface, and select Delete from the popup menu, or press
the Delete key.

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Disabling or Enabling Interactive Design Rule Checking

The PlanAhead software attempts to ensure a legal pin out; however, only ISE
Implementation tools provide complete signoff DRCs. Therefore, you need to run your
design through the ISE pinning process to ensure final legal pinouts. The interactive I/O
placement routines check common error cases. You can toggle this capability on and off
using the Automatically Enforce Legal I/O Placement button in the Device or Package
view toolbar or in the I/O Placement section of the General dialog box (accessible using
Tools > Options > General).
When you enable automatic checking, the tool does not allow placement of I/O ports on
pins that cause a design issue. In Place I/O Ports Sequentially mode, if you attempt to
place an I/O Port on a problematic pin, a tool tip display that describes why the I/O Port
is not able to be placed. The online DRC checks are enabled by default.
Note: Many of these checks can run only when a synthesized netlist of the full design is loaded.
The interactive I/O placement rules include:
• Prohibiting placement on noise sensitive pins associated with Gigabit Transceivers
(GTs). I/O package pins that are potentially noise sensitive are prohibited.
• Prohibiting I/O standard violations.
• Ensuring that I/O standards are not used in banks that do not support them.
• Ensuring that banks do not have incompatible VCC ports assigned.
• Ensuring that banks that need VREF ports have free VREF pins.
• Proper assignment of global clocks and regional clocks (only with an imported
EDIF/NGC netlist and UCF).
• Ensuring Input and High Drive outputs only go to capable pins (for Spartan®-3
devices only).
• Differential I/O ports to the proper sense pin.
• Ensuring that no output pins are placed on input-only pins.
It is recommended that you begin your I/O port placement with DRCs enabled.

Placing I/O Ports

I/O Planner provides a variety of ways to assign I/O Ports to package pins. You can select
individual I/O ports, groups of I/O ports, or interfaces in the I/O Ports view and
graphically assign them to package pins in the Package view or I/O pads in the Device
view.
You can toggle the online DRCs on or off during interactive placement.
The placement mode options available for assigning I/O Ports are:
• Place I/O Ports in an I/O Bank
• Place I/O Ports in an Area
• Place I/O Ports Sequentially
The following subsections describe each placement mode option.
For information on automatic I/O Port assignment, see Automatically Assigning I/O
Ports, page 230.

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Placing I/O Ports into I/O Banks

To place I/O ports into I/O banks:
1. In the I/O Ports view, select an individual I/O port, a group of I/O ports or Interfaces.
2. In the I/O Ports view, the Package view, or the Device view, click the Place I/O Ports in
an I/O Bank button, which is shown in Figure 8-20.

Figure 8-20: Place I/O Ports in an I/O Bank Button

The group of I/O ports is attached to the cursor when it is dragged over a package pin
or I/O pad. A tool tip displays how many pins can be placed in the selected I/O bank.
3. Click on a pin or pad to assign the selected I/O ports.Figure 8-21 shows an I/O pad.

Figure 8-21: Placing I/O Ports in I/O Banks

4. If more I/O ports are selected than will fit in the I/O bank, the command is continued.
The cursor drags the remaining I/O ports to the next selected I/O bank, and so on
until all of the I/O ports are placed, or until you press the Esc key.
- Moving the cursor within the Package view actively displays the I/O pin
coordinates on the top and left sides of the view.
- Additional I/O pin and bank information displays in the Status Bar located at the
bottom of the PlanAhead Environment.
- The active object being reported is highlighted in the Package view.
- Holding the cursor over the Package view invokes a tool tip that displays the pin
information.
Ports are assigned in the order they appear in the I/O Ports view. The assignment order
can be adjusted by applying sorting techniques in the I/O Ports view prior to assignment.

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The assignment order is driven from the initial Pin that is selected for I/O bank assignment
also. Selecting a pin at one end of an I/O Bank results in a continuous bus assignment
across the I/O bank.
The PlanAhead software also keeps track of PCB routing concerns for buses. Pin ordering
during assignment attempts to keep the bus bits vectored within the assignment area. You
can customize assignment patterns to address other bus routing concerns.

Placing I/O Ports in a Defined Area

To place I/O Ports into a defined area:
1. In the I/O Ports view, select individual I/O ports, groups of I/O ports or interfaces.
2. In the I/O Ports view, the Device view, or the Package view, click the Place I/O Ports in
Area button, which is shown in Figure 8-22.

Figure 8-22: Place I/O Ports in Area Button

The cursor turns into a cross symbol which indicates that you can define a rectangle for
port placement.
3. In either the Package view or the Device view, draw a rectangle to define the
assignment area, as shown in Figure 8-23.

Figure 8-23: Placing I/O Ports in an Area

4. If you select more I/O Ports than fit in the defined area, the command is continued.
The cursor continues to display as a cross to draw another area to place the remaining
I/O ports until all of the I/O ports are placed, or until you press the Esc key.
Ports are assigned in the order that they appear in the I/O Ports view. You can adjust the
assignment order by applying sorting techniques in the I/O Ports view prior to
assignment.

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The direction in which you draw the rectangle dictates the I/O ports assignment order.
I/O ports are assigned from the inside pin of the first rectangle coordinate selected.
Creative definition of the area rectangles can provide very useful pinout configurations
from a PCB routing perspective.

Sequentially Placing I/O Ports

To place I/O ports sequentially:
1. In the I/O Ports view, select an individual I/O port, a group of I/O ports or interfaces.
2. Use one of the following commands:
- In the I/O Ports view, from the popup menu, select Place I/O Ports Sequentially.
- In either the Package view or the Device view, click the Place I/O Ports
Sequentially button as shown in Figure 8-24.

Figure 8-24: Place I/O Ports Sequentially Button

The first I/O port in the group is attached to the cursor when you move it over a
package pin or I/O pad. A tool tip displays the I/O port and package pin names.
3. To assign an I/O port, click a pin or a pad.
Figure 8-25 shows a sequential I/O port placement.

Figure 8-25: Placing I/O Ports Sequentially

4. If more I/O ports are selected, the command is continued. The cursor drags the next
I/O ports, and so on until all of the I/O ports are placed or until you press the Esc key.
PlanAhead assigns ports in the order that they appear in the I/O Ports view. You can adjust
the assignment order by applying sorting techniques in the I/O Ports view prior to
assignment.

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Swapping I/O Locations

You can select two placed I/O ports and swap their locations with each other. To swap I/O
locations:
1. Select two I/O ports from any of the available views. Hold down the Ctrl key while
clicking to select multiple ports.
2. Right-click and select Swap Locations.
If you swap two ports which are not yet fixed (if you are viewing the implemented
placement in the Implemented Design), the act of swapping them will also cause them to
be fixed and the resultant constraint will be written to the design constraint file.

Automatically Assigning I/O Ports

The I/O Planner environment can assign any or all selected I/O ports to package pins
automatically. The autoplacer obeys I/O standard and differential pair rules, and places
global clock pins appropriately.
Note: This functionality is available for Virtex®-6 device families only.
To automatically assign I/O ports to a subset of unassigned I/O ports:
1. In the I/O Ports view, select the unassigned I/O ports.
2. Click Tools > Autoplace I/O Ports, or in the I/O Ports view, click Autoplace I/O Ports
from the popup menu.
The Autoplace I/O Ports wizard opens as shown in Figure 8-26.

Figure 8-26: Autoplace I/O Ports Wizard

3. Select the group of I/O ports to place, and click Next.

4. If you select I/O ports that have already been assigned to package pins, the dialog box
opens as shown in Figure 8-27, page 231.

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Figure 8-27: Autoplace I/O Ports Wizard

5. Select the I/O ports to place, click Next, and then Finish in the Summary page.

Placing Gigabit Transceiver I/O Ports

To better manage Gigabit Transceivers (GTs), the I/O Planner groups the two related I/O
diff pairs and the GT logic object automatically during selection, placement, and moving.
The GT objects are selected as one object and move together, which prohibits illegal
assignment of the GT resources.
If the online DRCs are enabled, the noise sensitive I/O pins surrounding the GTs are
prohibited automatically during port placement. Refer to Disabling or Enabling Interactive
Design Rule Checking, page 226.

Placing I/O Related Clock Logic

You can manually place Global and regional clock related logic, such as BUFGs, DCMs,
BUFRs, and IDELAYCTRLs, in the Device view. Appropriate logic sites are displayed for
all device-specific resources.
To search for various site type that are available in the device, select Edit > Find. You can
then select the site type in the Find Results view, which highlights their location.
PlanAhead has several methods with which you can select the design clock-related logic,
such as the Find command or the Schematic and Netlist views.
To place clock logic manually:
1. In the Device view zoom to locate the appropriate device site to place the logic.
2. Select the Create Site Constraint Mode toolbar icon.
3. Select the logic to place in the Find Results, Schematic or Netlist views, and drag it onto
the available corresponding Device view site. Figure 8-28, page 232 shows an example
of manual clock placement.

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Figure 8-28: Manually Placing Clock Logic

Validating I/O and Clock Logic Placement

This section describes the required steps for running I/O Port and clock-related DRCs. See
I/O Port and Clock Logic DRC Rule Descriptions, page 235 for information on running
netlist and floorplan related DRCs.

Running I/O Port and Clock Logic Related DRCs

To select and run individual rules:
1. Select Tools > Run DRC.
The Run DRC dialog box opens as shown in Figure 8-29, page 233.

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Figure 8-29: Run DRC Dialog Box: I/O Pin and Clock DRC Rules

2. View or edit the Results Name field. Enter a name for the results for a particular run for
easier identification during debug in the DRC Violations browser. The output file
name matches the entered name.
3. In the Rules to Check group box, use the check boxes to select the design rules to check
for each design object. For information about each rule, see I/O Port and Clock Logic
DRC Rule Descriptions, page 235.
- Expand the hierarchy using the Expand All toolbar buttons, or click the + next to
each category or design object.

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- Click the check box next to design object if you want to run all DRCs.
- Select individual DRCs, or click All Rules to run a complete DRC (all rules for all
design objects).
4. Click OK to invoke the selected DRC checks.

Viewing DRC Violations

Once completed, the DRC Results view opens as shown in Figure 8-30.

Figure 8-30: Highlighting DRC Violations

In the DRC Results view, the software expands each violation as follows:
• Errors display a red icon.
• Warnings display an amber icon.
• Informational messages display a yellow icon.

Filtering the Violation List by Severity

By default, all errors and warnings display.
• To hide all warnings and info messages, and view only errors, click the Hide Warning
and Information Messages toolbar button.
• To view all errors and warnings, click the toolbar button again. Figure 8-31 shows the
Hide Warning and Information Messages button.

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Figure 8-31: Hide Warning and Information Messages Button

When you select an error in the DRC Results view list, the specific violation information
displays in the Properties view.
When you select a blue hyperlink in the Properties view, it highlights the violating design
elements in the Device view, Netlist view and Schematic view.
Violations display in the DRC Results view until the error condition is rectified and DRC is
re-run.
Each time you invoke the Run DRC command and DRCs detects errors, PlanAhead adds a
new results tab to the DRC Results view and creates a separate results output file in the
PlanAhead invocation directory.

I/O Port and Clock Logic DRC Rule Descriptions

The following tables describe the DRC rules, rules intent, and severity:
• Global Clock DRCs
• IOB DRCs
• Bank I/O Standard DRCs
Note: Selecting DRC Rules in Chapter 5 provides other DRC rule descriptions.
Note: The I/O Port and Clock Logic DRCs available in PlanAhead is not an exhaustive list of I/O-
related DRCs. Consult the device documentation for more information about I/O ports and clock
region specifications.
Note: In some cases the Severity level issued by PlanAhead may differ from the severity level of the
same condition reported by ISE Implementation tools.

Global Clock DRCs

Table 8-1 provides the global clock DRCs, abbreviation, intent, and severity.
Table 8-1: Global Clock Rules
Rule
Rule Name Rule Intent Severity
Abbrev
IBUFG to IDCM IBUFGs have dedicated routing only to all DCMs on Warning
DCM the same edge (top, bottom, left, right) of the device.
connectivity
DCM to BUFG DCMB DCM can connect to a maximum of four BUFGs. Error
connectivity There are pairs of buffers with shared dedicated
routing resources such that if both are driven by the
same DCM, one of the two will necessarily be driven
using non-dedicated routing resources; this causes
the design to fail. If the buffers are numbered 1
through 8 from left to right, there are four pairs of
exclusives: 1:5, 2:6, 3:7, 4:8. If a buffer is placed in Site
1, another driven by the same DCM should not be
placed in Site 5.

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Table 8-1: Global Clock Rules (Continued)

Rule
Rule Name Rule Intent Severity
Abbrev
Number of DCMN DCM can connect only up to 4 BUFGs. This is related Error
BUFGs to DCMB.
allowed for
DCM
DCM and DCME BUFGs have dedicated routing only to all DCMs on Warning
BUFG the same edge (top, bottom, left, right) of the device.
connectivity

IOB DRCs
Table 8-2 lists the IOB DRCs, abbreviation, intent, and severity.

Table 8-2: IOB DRCs

Rule Name Rule Abbrev Rule Intent Severity
IOB set reset sharing IOSR IOB site has input, output and Error
tri-state registers, each of these
registers share same set/reset signal.
Will not be able pack registers with
different reset signals.
Differential I/O pads IODI Differential I/O P and N signals Error
should be LOCed in dedicated
differential pair.
Non inputs placed on IOPR Checks that a port is not placed on a Error
input only pins prohibited pin.
Diff term loced to low IOLVDSCC Checks that differential output Error
capacitance IOB Site standards are not used on low-
capacitance sites that cannot support
them.
Prohibit not specified IOPCPR For designs that use part Error
for part compatibility compatibility, checks that if any
package pin does not exist on at least
one compatible part, it is marked as
“prohibit” and nothing is placed on
it.
Regional Clock Term IOBUFR Checks that a regional clock terminal Error
has no BUFR site and the related BUFR are placed at
mutually route-able locations.
Regional Clock Term IOBUFIO Checks that a regional clock terminal Error
has no BUFIO site and the related BUFIO are placed at
mutually route-able locations.

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Table 8-2: IOB DRCs (Continued)

Rule Name Rule Abbrev Rule Intent Severity
IOB clock sharing IOCS IOB sites are divided into pairs for Warning
the purpose of sharing clock routing
resources. These pairs are normally
LVDS pairs as well. In some cases
there could be routing issues based
on how the flops are packed inside
the IOB. To resolve this issue flops
need to be assigned to specific BEL.
MGT not allowed for IOPCMGT Indicates whether part compatibility Warning
part compatibility is used with two parts that have
different MGT supply voltages,
thereby disallowing the use of MGT.
I/O Crosstalk to MGT IOCTMGT Check for possible crosstalk Warning
problems between I/Os and MGT
Configuration Modes CFGM Check for possible problems Warning
involving active device configuration
mode(s); for example, multi-function
pins for which one function is needed
during configuration and a different
function is used after configuration.
I/O Standard Type IOSTDTYPE Ensures that a Diff pair I/O Standard Warning
has been applied to diff pair pins
only.
Number of IOs IOCNT Indicates whether more I/O Ports are Warning
defined than there are pins in the
target device.
Port Properties PORTPROP Check for inconsistencies within the Error
properties of a port

Bank I/O Standard DRCs

Table 8-3 lists the Bank I/O standard DRCs, abbreviation, intent, and severity.

Table 8-3: Bank I/O Standard DRCs

Rule Name Rule Abbrev Rule Intent Severity
Bank I/O BIVC IOSTANDARD-based VOUT voltage Error
Standard Vcc compatibility check for IOs in that bank.
Bank I/O BIIVRC checks for a conflict between the I/O Warning
Standard standards of a Bank and an
INTERNAL_VREF constraint on the bank.
Standards in a bank cannot require a
VREF voltage that differs from that
specified by an INTERNAL_VREF
constraint for the bank.
Bank I/O BIVB Checks that the I/O Standard is Error
Standard Support supported in the I/O bank.

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Table 8-3: Bank I/O Standard DRCs (Continued)

Rule Name Rule Abbrev Rule Intent Severity
Bank I/O BIVT IOSTANDARD-based DCI Termination Error
standard voltage compatibility check for IOs in
Termination that bank.
Bank I/O BIVR IOSTANDARD-based VREF voltage Error
Standard VREF compatibility check for IOs in that bank.
Bank I/O BIVRU IOSTANDARD-based VREF voltage Warning
Standard VREF compatibility check for IOs in that bank.
Occupied
Bank I/O DCIP There are dedicated VRP and VRN I/O Error
Standard sites in I/O bank which can be used as
VRN/VRP regular IOs also. If a DCI I/O standard is
Occupied used in that bank these IOs should be left
unoccupied.
DCI Check for DCICIOSTD Checks that there are no conflicts related Error
I/O standard to Vcco and DCI termination of I/O.
legality
Bank I/O BISLIM Checks the I/O placed within an I/O Error
Simultaneous bank against Simultaneous Switching
Switching Output Noise (SSN) Output.
Limits
Inconsistent Diff DIFFISTD Checks that the terminals of a differential Error
pair I/O pair have the same I/O standard.
Standards
Inconsistent Diff DIFFISTDDrv Checks that the terminals of a differential Error
pair I/O pair have the same drive.
Standards
Inconsistent Diff DIFFISTDSlew Checks that the terminals of a differential Error
pair I/O pair have the same slew.
Standards
Vccaux Voltage VCCAUX Warns of any requirements on Vccaux, Warning
requirement based on used I/O standards.

Removing I/O Placement Constraints

You can remove placement constraints by first selecting them, and then selecting the
Unplace popup menu command.
Refer to Working with Placement LOC Constraints in Chapter 11 for information on
selectively removing I/O related placement constraints.

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Exporting I/O Pin and Package Data

You can export I/O pin and pin package information as described in the following
subsections.

Exporting Package Pin Information

You can export the device package pin information from PlanAhead to a CSV format file.
The exported information includes information about all of the package pins in the device
as well as design-specific I/O Port assignments and their configuration.
The package pin section of the exported list is a good starting point for defining I/O port
definitions in a spreadsheet format. Refer to Defining and Configuring I/O Ports, page 216
for information on the exported CSV file format.

Exporting an I/O Port List

You can export the I/O Port list from the PlanAhead software to an HDL, UCF, or CSV
format file for use with RTL coding or PCB schematic symbol creation.
To export the I/O Ports list information, select the File > Export I/O Ports command as
shown in Figure 8-32.
.

Figure 8-32: Exporting I/O Port Lists

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Using Noise Analysis Predictors

The PlanAhead software uses the Simultaneous Switching Noise (SSN) calculations when
you select a Virtex-6 or a Spartan-6 device. If using a device other than these, refer to
Running WASSO Analysis (Spartan-3, Virtex-4, Virtex-5), page 244.

Running SSN Analysis (Virtex-6 and Spartan-6)

The PlanAhead software uses the Xilinx Simultaneous Switching Noise (SSN) predictor to
improve the prediction of simultaneous switching output noise in Virtex-6 and Spartan-6
devices. The SSN predictor provides estimates of the disruption that switching outputs can
cause on other outputs, and in the case of Spartan-6 inputs, in the I/O bank. The SSN
predictor incorporates I/O bank-specific electrical characteristics into the prediction to
better model package effects on SSN.
Because all power distribution networks within a packaged FPGA have different
responses to noise, it is important to understand not only the I/O standards and number of
I/O in a design, but also the response of the device power system to this switching.
In the Virtex-6 and Spartan-6 device families, I/Os are grouped into separate isolated I/O
banks, each with its own unique power distribution networks, and each with unique
responses to switching activity.
Xilinx characterizes all banks through three-dimensional extraction and simulation. This
information is incorporated into the SSN predictor such that it can take the expected
switching profile of a device and predict how the switching affects the power network of
the system, and in turn, how other outputs in the I/O bank are affected.
The SSN predictor is the best method available for accurately predicting how output
switching affects interface noise margins.
The calculation and results are based on a wide range of variables. These estimates are
intended to identify potential noise-related issues in your design and should not be used as
final design “sign off” criteria.
To run the SSN predictor:
1. In the Flow Navigator, or from the Tools menu, select Run Noise Analysis.
The Run SSN Analysis dialog box opens as shown in Table 8-33.

Figure 8-33: Run SSN Analysis Dialog Box

2. Optionally, enter a name in the Results Name field to identify the results in the SSN
Results view.
3. Optionally, click Export to File, and enter an output file name in the Output File field
and browse to select a location to write an external CSV format report file.
4. Click OK.

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Viewing the SSN Results

The SSN Results view displays the following information:
• Name—Displays the I/O Banks available in the device. Each I/O bank has pin icons
indicating how full the bank is, and puts a check mark for a passing predictor or a red
circle indicating failure.
- Group (Virtex-6 only)—Displays the various groups of pins with like I/O
standards assigned within the bank, and displays their status. Groups are
determined automatically based on the I/O standards, drive strength, slew rate,
and phase assigned.
• I/O Std, Vcco, Slew, Drive Strength—Displays the appropriate values for the port or
bank.
• Noise (V)
- Contributed (Virtex-6 only)—Contains the SSN aggregate of each group,
generated by the I/O standard, drive strength, and slew type of that group.
- Bank Total (Virtex-6 only)—Defines aggregate SSN predicted for a bank or group.
If multiple phases are specified for the groups of a given bank, the SSN
contributions of groups with different phases are accumulated separately, and the
maximum of these is reported. Because the SSN calculation is isolated to the
output of that bank, one SSN bank total does not affect another bank total.
This column identifies which I/O groups are creating the most SSN, and how
much margin they use.
• Off-Chip Termination (Spartan-6 only)—Describes the termination being used on the
board. Displays either None or a short description of the expected or defined off-chip
termination style; for example, FP_VTT_50 describes a “Far Point, 50 Ohm
termination to Vtt” termination style. The full list of termination styles is available in
the Spartan-6 SelectI/O User Guide (UG381).
This field automatically populates with the default terminations for each I/O
standard, if one exists. For some I/O standards it may be None, or no expected
external termination. You can change the settings either using the CSV file import
feature described in Importing a CSV Format File, page 216, or by using the pulldown
selection in the I/O Ports table.
• OUT_TERM (Spartan-6 only)—Displays the OUT_TERM attribute setting for the port if
one has been defined. “NONE” is most common. The OUT_TERM options are described
in the Spartan-6 SelectI/O User Guide (UG381).
• Margin (V)
- Available (Virtex-6 only)—Defines the allowable noise margin for that particular
I/O standard on the high side of the signal as it switches to a 1. It is strictly based
on the DC logic levels implicit in the I/O standard (no quantity information is
taken into account) and represents the margin that the weakest drive of a high
signal is above the JEDEC input thresholds. These margin values assume the
weakest drive conditions, JEDEC specification termination, and standard receiver
requirements for the standard. This is one place where conservative assumptions
are made in the analysis, providing some guard band.
- Remaining—Displays the amount of noise margin that is left over after
accounting for all SSN in the bank.
• Result—Displays a Pass or Fail condition with failures displayed in red.
• Notes—Displays information about the I/O bank or groups.

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The SSN results are relative to the state of the design when the SSN Analysis is run. It is not
a dynamic report.

Resolving SSN Issues

When a violation occurs there are a number of ways to improve the results:
• Use I/O standards that have a lower SSN impact for the failing group. Changing to a
lower drive strength, a parallel-terminated DCI I/O standard, or a lower class of
driver can improve SSN; for example, changing the SSTL Class II to an SSTL Class I.
• Spread the failing pins across multiple banks. This reduces the number of aggressive
outputs on the power system of one bank.
• Spread the failing group(s) across multiple synchronous phases. (See note below
regarding phase groups).
• If the Result is a Fail condition, assign phase groups to ports that are switching
concurrently.
Note: Phase groups are only supported in the software and SSN calculations for Virtex-6
devices. While phase shifting will improve the Spartan-6 device performance on SSN, the
improved performance cannot be seen in the software calculations. For Virtex-6, see Defining
the I/O Port Switching Phase Groups in SSN, page 243.
• Phase-shift the offending group by 90 degrees if at a DDR rate, or by 180 degrees if at
an SDR rate. This puts half the aggressive output switching out-of-phase with the
other half, and instead of interfering constructively, it interferes destructively.
Note: If you have a Spartan-6 design that fails SSN, see AR 36141. Certain failures can be ignored.
Also, see the “Pin Planning to Mitigate SSN Sensitivity” section in the Spartan-6 SelectI/O User
Guide (UG381).

Viewing I/O Bank Properties in SSN Results

Selecting an I/O bank in the SSN Results view displays information about the I/O ports,
pins and groups assigned to the I/O bank in the I/O Bank Properties view.
• Select the General tab to view information about the number and types of Ports
assigned to the I/O Bank.
• Select the Package Pins or I/O Ports tab to view the detailed information about the
Pins or Ports within the bank, as shown in Figure 8-34, page 243.

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Figure 8-34: I/O Bank Properties: Package Pins

Defining the I/O Port Switching Phase Groups in SSN

In some cases, different groups of I/O within a bank have a synchronous phase offset from
one another, meaning it is not possible for them to switch simultaneously. This is true of
data and strobe signals in many memory interfaces. In this case, proper SSN accounting
must be informed by phase information.
A phase group is a logical grouping of ports that are all in phase with each other from a
timing perspective (their clocks have the same frequency and phase). By creating a
grouping phase, not only is a group created, but I/Os with a different phase are being
separated.
The noise produced by the groups within a bank is summed to get the total noise for that
bank, and if all outputs are either in phase with each other, or do not have a synchronous
relationship, the output can be expected to switch (change values) at the same time.
If a bank is failing in the SSN analysis, phase groups can be used to group ports that are at
separate synchronous phases, thus lowering the total noise for that bank when the SSN
predictor is run again. To set the switching phase for a single or set of I/O ports:
1. In any of the I/O Planner views, select one or more I/O port.
2. In the I/O Ports view, Package Pins view, or SSN view, select the Configure I/O Ports
popup menu command as shown in Figure 8-35.
.

Figure 8-35: Configure Ports Dialog Box

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3. In the Configure Ports dialog box, ensure the I/O Standard is correct.
4. If the port(s) are in-phase, leave the Phase as default, or enter a unique phase, such as
180.
5. Click OK.
6. Once the appropriate phase groups are assigned, rerun the SSN analysis.
Note: Asynchronous groups should not be treated as separate synchronous phases, as it is
possible for them to switch simultaneously.

Running WASSO Analysis (Spartan-3, Virtex-4, Virtex-5)

PlanAhead contains a set of Weighted Average Simultaneous Switching Output (WASSO)
checks to validate signal integrity of the device based on the I/O pin and bank assignments
made in the design.
To run a WASSO analysis, select Run Noise Analysis from either the Flow Navigator or
from the Tools menu. The Run WASSO Analysis dialog box opens, as shown in
Figure 8-36.

Figure 8-36: Run WASSO Analysis Dialog Box

The Output File field can be used to specify a report file name and location to write to disk.
Tool tips are provided when dragging the cursor over each of the entry fields indicating
what values to enter.

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Viewing the WASSO Analysis Results

You can modify the device and board parameter values to reflect your specific design. The
analysis is performed across the entire device first and then within each I/O bank as they
relate to their neighboring I/O banks. The WASSO Results view displays in the Workspace
as shown in Figure 8-37.

Figure 8-37: WASSO Results

Notice that the report lists allowable loading, utilization, and status for I/O banks and
neighboring pairs.

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Implementing the Design

This chapter contains the following sections:
• Overview
• Running Implementation
• Monitoring Run Status
• Determining Project Status
• Analyzing Run Results
• Understanding the Project Summary
• Selecting The Next Step After Implementation Completes
• Creating and Launching Multiple Runs
• Managing Multiple Runs
• Launching Runs on Remote Linux Hosts

Overview
The PlanAhead™ software includes a Synthesis and Implementation environment that
facilities a push button flow with single Synthesis and Implementation attempts or Runs.
PlanAhead manages the Run data automatically, allowing repeated Run attempts with
varying Register Transfer Level (RTL) source versions, Synthesis, or Implementation
options or constraints.
Also, PlanAhead allows multiple Synthesis and Implementation Runs using different
software command options, and timing or physical constraints. You can queue the
Synthesis and Implementation Runs to launch sequentially or simultaneously with multi-
processor machines. Synthesis Runs use Xilinx® Synthesis Technology (XST).
You can create and save Strategies, which are sets of option configurations for each
Implementation command, that are then applied to Runs for Synthesis or Implementation
using Xilinx ISE® Design Suite tools. For more information about Strategies, see Creating
Synthesis and Implementation Strategies in Chapter 3.

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Running Implementation
When you run Implementation in PlanAhead you have the ability to set Implementation
options, run Implementation, and view the results of the Run.

Setting Implementation Options

There are several locations in the environment in which to configure Implementation
settings. Select the Project Settings command in the Flow Navigator Project Manager
Menu, the Project Summary, or in the main toolbar. Figure 9-1 shows the Project Setting
button.
.

Figure 9-1: Project Settings Button

In the Project Settings dialog box, select Implementation, if it is not already selected, as
shown in Figure 9-2.
.

Figure 9-2: Implementation Project Settings

The Implementation Project Settings dialog box contains the options to set ISE command
options in the next Implementation attempt as follows:
• Default Part—Select the target device to use for the Synthesis Run.
• Default Constraint Set—Select the constraint set to use for the Synthesis Run.
• Strategy—Select an existing Strategy to use for the Synthesis Run. For more
information on Strategies, see Creating Synthesis and Implementation Strategies,
page 77.

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• Description—Displays the description for the selected Strategy. This field is editable
for user-defined strategies only.
• ISE options—Configure any ISE option. Use the More Options field to specify options
that are not listed. You can find a brief description of each option and what it is used
for in the lower dialog pane. An asterisk (*) next to an option name indicates that the
value is currently set to a non-default value.
Note: If you exit PlanAhead before Running the modified Implementation Run, the options are not
preserved. If Implementation results exist in the project, the project settings are inherited when you
open the project. If no Implementation Run exists in the project, the PlanAhead uses the default
options.

Launching Implementation
You can launch and configure Implementation Runs as described in the following
subsections.

Launching an Implementation Run

To launch an Implementation Run, click the Implement button from the Flow Navigator or
main toolbar as shown in Figure 9-3.

Figure 9-3: Implement Button

The current Implementation project Settings are used to launch the Run.

Configuring Implementation Run Settings

You can set the Implementation Run options using the Implementation Settings command
in the Flow Navigator Implementation button pulldown menu as shown in Figure 9-4.

Figure 9-4: Configuring Implementation Run Settings

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The Implementation Settings dialog box appears, as shown in Figure 9-5.

.

Figure 9-5: Implementation Run Settings Dialog Box

The Implementation Settings dialog box options are:

• Part—Select or accept the target part. Select the browser button to invoke the Select
Part dialog box.
• Constraint Set—Select or accept the constraint set.
• Options—Select the Implementation Strategy to use for the Run. Click the file browser
to modify ISE command options, shown in Figure 9-6.

Figure 9-6: Design Run Settings Dialog Box

• Launch Options—Select additional launch options. Figure 9-7 shows the Specify
Launch Options dialog box.

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Figure 9-7: Implementation Launch Options

The options are:

- Launch Directory—Specify a location to create and store the Implementation Run
data.
Note: Defining any non-default location outside of the project directory structure makes a
project non-portable because an absolute path is written into the project files.
- Launch Runs on Local Host—Launches the Run on the local machine processor.
- Number of Jobs—Define the number of local processors to use for Runs. This
option is used only when launching multiple Runs simultaneously.
Individual Runs are launched on each processor. No multi-threaded
processors are used with this option.
- Launch Runs on Remote Hosts (Linux only)—Use remote hosts to launch job or
jobs.
- Configure Hosts—Configure remote hosts. For more information, refer to
Launching Runs on Remote Linux Hosts, page 268.
- Generate scripts only—Export and create the /Run directory and Run script, but
not launch the Run from PlanAhead. The script can be Run at a later time outside
of the PlanAhead environment.

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Monitoring Run Status

You can monitor the status of a Synthesis or Implementation Run by reading the
compilation log, viewing the compilation information, warnings, and errors in the
Compilation Messages view, viewing the Project Summary, or opening the Design Runs
view.
The following subsections describe the Run status monitoring options.

Using the Project Status Display

The Project Status indicator in the upper right corner of the PlanAhead environment
shown in Figure 9-8, serves functions that include:
• Displaying the overall status of the project and the progress of running commands
• Providing a Cancel command to stop any running commands

Figure 9-8: Project Status Display

Cancelling a Run
You can stop the Run by clicking the Cancel button in the Project Status Display, shown in
Figure 9-8.

Viewing the Compilation Log

The Compilation Log view opens once you launch a Run, and shows the standard output
messages. Figure 9-9 is an example of a compilation log.
.

Figure 9-9: Compilation Log

Pausing Output as Commands are Running

The Pause output button lets you scroll and read the log while a command is running.

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Determining Project Status

The PlanAhead software provides several visual indicators about the overall status of a
project as well as methods to take in the next step of the process. Only the results of the
major design tasks in the design process are reported in the project status.
The overall project status displays in the Project Summary and in the Status Bar so you can
quickly visualize the status of a project upon opening the project, or while you are running
the design flow commands. These include RTL Elaboration, Synthesis, Implementation,
and Bitstream Generation.
The following subsections describe how you can see the project status in PlanAhead.

Project Status Bar

The overall project status displays in the upper-right corner of the viewing environment,
as shown in Figure 9-10.
.

Figure 9-10: Project Status Bar

As you run the Elaborate, Synthesize, Implement, and Generate Bitstream commands, the
Project Status Bar changes to indicate either a successful or failed attempt. Failures are
displayed with red text.
If source files change, the project can be marked Out of Date if Synthesis or Implementation
is complete as shown in Figure 9-11. The Status Bar indicates an Out-of-Date Status. You
can select the more link to display the reason.

Figure 9-11: Information on why Project is Out-of-Date

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Design State in the Flow Navigator

The Flow Navigator helps visualize the design state by providing access to only the
commands applicable to the design state. For example, if Implementation is not run, the
Implemented Design button is greyed out. This visually guides you in the Flow Navigator
to click the next step in the design process.

Design Data Out-of-Date Banner

As source files, netlists, constraints, or Implementation results update, a banner appears in
the top of the open design indicating that a newer version of the design is available than
what is loaded in memory. PlanAhead prompts you to reload what is loaded in memory as
shown in Figure 9-12.

Figure 9-12: Out-of-Date Banner and Reload button

Analyzing Run Results

Once Synthesis or Implementation completes, you can view the ISE reports, and open,
analyze, and use the netlist or implemented design to apply timing or physical constraints
and re-implement the Run. The following sections describe how to use the reports and the
Project Summary. See Creating Synthesis and Implementation Strategies, page 77 for
information on using the Implemented Design view to analyze the design further.

Viewing Report Files

You can view report files generated by the ISE tools from within the Reports view. The
view is usually opened automatically after commands are run. if it is not available, select
the Reports link in the Project Summary. The Reports view opens as shown in Figure 9-13.

Figure 9-13: Selecting Report Files to View

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Select any available report files to view it in the Workspace, shown in Figure 9-14,
page 255.

Figure 9-14: Viewing Report Files

When viewing reports, you can:

• Browse the report file using the scroll bar.
• Select the Find or Find in Files buttons to search for specific text.
• Use the Go to the beginning or Go to the End toolbar buttons to scroll to the
beginning or end of the file.

Viewing Compilation Messages

The Compilation Messages view provides a filtered list of the Compilation Log that
includes only the main messages, warnings, and errors. The view has further filtering
capabilities using view toolbar buttons to show only errors or warnings. Figure 4-10,
page 89 shows an example compilation log.
The Implementation messages are organized by ISE command and severity.
Click the expand and collapse tree widgets to view the individual messages.
The command buttons on the left provide searching and filtering capabilities. The Show
Search, Collapse All, and Expand All command options are described in Using Tree Table
Style Views, page 96.

Filtering and Grouping Compilation Messages

You can use the Hide information messages and Hide warning messages buttons to filter
the messages to include only Warnings and/or Errors.

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The Group duplicate messages button flattens the list and groups similar messages
together, shown in Figure 9-15, page 256.

Figure 9-15: Message Filtering and Grouping Buttons

Highlighting Compilation Issues in RTL Sources

Selecting any of the Synthesis messages in the Compilation Messages view that have a
referenced line number automatically opens the RTL file and highlights that line of source
code. Figure 9-16 shows an example of the error navigation process.

Figure 9-16: Error Navigation to RTL Sources

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Select any message and use the Search for Answer Record popup menu command to
search the Xilinx Customer Support database for related answer records.

Understanding the Project Summary

PlanAhead provides an interactive Project Summary view that details information about
the design and the project. The Project Summary view updates dynamically as design
commands run. There are also links to launch commands, or to display more detailed
information.
You can open the Project Summary using one of these methods:
• Select the Project Summary command from the Project Manager Flow Navigator
menu.
• Select the Project Summary toolbar button.
• Select the Windows > Project Summary command.
The Project Summary view opens as shown in Figure 9-17.

Figure 9-17: Project Summary

The Project Summary displays design information. You can use the scroll bar or the
Collapse and Expand buttons to view or hide the data categories. Selecting anywhere in
the panel banner expands or collapses the view panel also.

Viewing Project Settings

The Project Settings section in the Project Summary displays the Project Name, Device
Family, Default Part, and Top Module Name.

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Selecting the Edit link invokes the Project Settings dialog box. Refer to Setting General
PlanAhead Options, page 135 for more information on Project Settings.

Viewing Project State

The Project State panel contains the following information:
• State—Displays the project status or the status of the actively running command.
• Messages—Summarizes the number of errors and warnings encountered during
compilation commands. Clicking on the link opens the Compilation Messages view
where you can look at the messages.
• Next Step—Links to the next design flow Run command.
• Go To—Links to open the Compilation or Reports view (when available). Refer to
Using the Compilation Message Area, page 88 for more information.

Understanding Compilation Settings

The Compilation panel shows the target part, and the strategy and constraint set used for
the active Synthesis and Implementation Runs. Also, it shows the Fmax and utilization
estimates reported from Synthesis and the timing score and unroutes reported from
Implementation.
Clicking on the links invokes the Project Settings dialog box in the selected location to
enable configuration of Synthesis and Implementation Runs. Tool tips describe the button
actions.

Viewing Resource Utilization

The resource utilization for the target device displays in either a graphical format or
tabular format as shown in the following figures. Click the link in the upper right of the
Resources section of the Project Summary to toggle between the graph and table views.
Figure 9-18 shows a graph view and Figure 9-19, page 259 shows a table view.

Figure 9-18: Resource Estimates in the Project Summary View - Graph View

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Figure 9-19: Resource Estimates in the Project Summary View - Table View

PlanAhead populates the Project Summary Resources at each stage of the design process.
The types of logic objects displayed varies as the design progresses through the design
stages. As the information becomes available, the tabs at the top of the view panel become
selectable. Resources, page 81 describes the resource options.
In some cases, links display in the Resources panel to guide you through the step involved
to populate the Resources chart.

Viewing Timing Results

Once you implement a design, the Timing pane of the Project Summary view provides a
summary of the overall timing results. A link to open the Timing Results view, as shown in
Figure 9-20, is available.

Figure 9-20: Timing Results in Project Summary View

PlanAhead populates the Project Summary Timing after Implementation is complete. The
Timing Score, Minimum Period, Maximum Frequency and worst Failing Constraint for the
active Run display, and a link is provided to open the Implemented Design.

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Selecting The Next Step After Implementation Completes

Once the Run is complete, a dialog box opens prompting you to take the next step as
shown in Figure 9-21.

Figure 9-21: Implementation Completed Successfully Dialog Box

1. In the Implementation Completed dialog box, select the option that matches how you
want to proceed:
- Open Implemented Design—Imports the netlist, active constraint set, ISE
placement and timing results, and the target part into the PlanAhead design
analysis and floorplanning environment so you can perform design analysis and
floorplanning. See Chapter 10, “Analyzing Implementation Results,” for more
information.
- Generate Bitstream—Launches the Bitgen Command Settings and Run dialog
box. See Chapter 12, Generating Bitstream Files for more information.
- View Reports—Opens the Reports view for you to select and view ISE Report
files. See Chapter 9, Viewing Report Files for more information.
2. Click OK to take the selected action.

Creating and Launching Multiple Runs

PlanAhead lets you create and launch multiple Synthesis and Implementation Runs to
explore options and find the best results. You can queue and launch the Runs serially, or in
parallel using multiple local CPUs. On Linux systems, you can use remote servers. See
Launching Runs on Remote Linux Hosts, page 268.
Note: PlanAhead provides flexibility to create multiple Synthesis Runs, Implementation Runs, and
constraint sets. You can create a project with multiple Run attempts; consequently, you must manage
the various Run data. PlanAhead issues messages about out-of-date data after source files,
constraints or project settings are modified. You can delete and manage stale Run data using the
Design Runs view.
The steps to create multiple Runs are:
1. Select one of the following:
- Tools > Create Multiple Runs.

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- In the Flow Navigator, click Create Multiple Runs from the Synthesize or
Implement pulldown menu.
Figure 9-22 shows both options.

Figure 9-22: Create Multiple Runs Command - From Synthesis and Implement

The Create Multiple Runs wizard opens.

2. In the Introduction page, click Next to proceed.
The Set Up Implementation Runs page opens as shown in Figure 9-23.

Figure 9-23: Create Multiple Runs: Set Up Implementation Runs Dialog Box

- For Implementation Runs, select a Synthesis Run, Constraints Set, and Part to use
for the Runs.
- For Synthesis Runs, select a Constraint Set and Part to use for the Runs.

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3. If you are running Synthesis, click Next to bring up the Choose Synthesis Strategies
page as shown in Figure 9-24, page 262.

Figure 9-24: Choose Synthesis Strategies

4. Select a Name and Strategy for the first Run.

5. Click More to add more Runs.
6. Enter names and choose strategies for additional Runs as shown in Figure 9-25.

Figure 9-25: Choose Implementation Strategies

7. Click Next to invoke the Launch Options dialog box. Refer to Setting Synthesis
Options, page 154 or Setting Implementation Options, page 248 for more information
on setting launch options.
8. Click Next and review the Create Multiple Runs Summary, and click Next again.
9. Click Finish to create the defined Runs and execute the specified Launch options.

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Managing Multiple Runs

PlanAhead lets you configure and generate a multiple Run results data. When you
configure multiple Runs, you must manage and remove stale Run data. The following
subsections describe how you can use the Design Runs view to manage multiple Run data
for both Synthesis and Implementation Runs. Most of the described features are available
for both Synthesis and Implementation Runs.

Using the Design Runs View

The Design Runs view displays all of the Synthesis and Implementation Runs created in a
project, and provides commands to manage and launch them.
Select Window > Design Runs to open the Design Runs view as shown in Figure 9-26.

Figure 9-26: Design Runs View

Each Synthesis Run displays the associated Implementation Runs below it in tree form.
You can expand and collapse Synthesis Runs using the tree widgets in the view.
Information about the Runs is displayed in the table. Refer to Using Tree Table Style Views,
page 96.
You can use the Show Search, Collapse All, and Expand All buttons to filter the Runs
displayed in the table. The options are:
• Launch Selected Runs—Launches the active Run.
• Reset Selected Runs—Resets a Run to a Not Started status and remove the data.
• Create Multiple Runs—Invokes the Create Multiple Runs wizard.
• Import Run Results—Opens the Implemented Design environment with the Run
results loaded.

Setting the Active Run

PlanAhead displays compilation and summary information for the “active” Run only.
Select any Run, and use the Make Active command from the popup menu to set it as active.
The Compilation Messages views, Status Bar and Project Summary display the
information for the active Run. When you click the Implement button, PlanAhead resets
and re-launches the active Run.

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Viewing and Modifying Run Properties

You can view or modify Run properties for each Run. The viewing and modification Run
rules are:
• Modification of most Run properties is possible only before launching the Run.
• After you launch a Run, the properties are locked to those previously selected.
• To modify the Run properties after a launch, select Reset Run to clear the Run.
Figure 9-27 shows the Implementation Run Properties dialog box with the General tab
selected.

Figure 9-27: Implementation Run Properties: General Tab

Table 9-1 lists the tabs and options in the Implement Run Properties tabs and the tab
options.

Table 9-1: Implementation Run Properties Tabs

Tab Options
General • Name—Defines the Run name.
• Part—Accept or change the target part. Select the browser button to
open the Select Part dialog box.
• Description—Defines the Run description.
• Status—Displays the status of the Run.
• Synthesis Run—Displays the synthesized netlist associated with the
Run. This field is not displayed in Synthesis Run Properties.
• Constraints—Accept or change the constraint set for the Run.
• Run Directory—Displays the location of the Run data.
Options The command line options and their preset values display in the view.
Select a command option to see a description of the command.
When you select an option a pulldown menu opens on the right side for
you to view the available option values. You can override any preset
Strategy options. See Overriding ISE Command Options Set in a Strategy,
page 265.

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Table 9-1: Implementation Run Properties Tabs

Tab Options
Monitor This view displays the same “standard out” command status logs that
displays when in the Compilation Log view. Figure 4-9, page 89 shows
an example of the Compilation Log.
The Monitor view continues to update as the commands are run. You
can use the scroll bar to browse through the command log reports.
Click Automatically update the contents of this view to stop the active
reporting. This lets you scroll easier and read results while the
command is running
Reports View report files generated by the ISE tool from within the PlanAhead
software. In the Run Properties view, select the Run, and then select
the Reports tab to display the list of available report files, and to open
a report in the Workspace.
Messages View Run messages. An example of the Messages view is shown in
Figure 4-10, page 89.

Overriding ISE Command Options Set in a Strategy

The Options tab lets you modify Strategy options.
Using the popup commands, you can:
• Override (edit) the Strategy for the selected Run, and save (or save as) the options to a
new User Defined Strategy.
• Enter additional command options that are not displayed in More Options under a
command.
Click the Apply toolbar button to apply changes.
Any modified values show an asterisk (*) next to the option to show that the default
Strategy value has changed. The Strategy field for the Run in the Design Runs view
receives an asterisk to show that the default Strategy has changed also.
After you launch the Run (which is described in the following section), the Strategy
options can no longer be modified. To edit an option, you need to reset the Run and then
edit the option. See Resetting Runs, page 266.

Launching Selected Runs

The Launch Runs command launches existing Runs in the Design Runs view. You can
launch Runs in any state, including completed Runs. The Launch Selected Runs dialog box
displays first so you can set launch options.
1. In the Design Runs view, select one or more Runs. Use Shift+click or Ctrl+click for
multiple selections.
2. Select one of the following commands:
- Launch Runs popup command.
- The Launch selected Runs Design Runs toolbar button as shown in Figure 9-28.

Figure 9-28: Launch Selected Runs Toolbar Button

The Launch Selected Runs dialog box opens as shown in Figure 9-29.

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Figure 9-29: Launching Existing Runs

The Launch Selected Runs dialog contains the following options:

- Launch Directory—Specify a location to create and store the Implementation Run
data.
Note: Defining any non-default location outside of the project directory structure makes
the project non-portable because absolute paths are written into the project files.
- Launch Runs on Local Host—Select this option to launch the Run on the local
machine processor.
- Number of Jobs—Define the number of local processors to use for Runs. This
option is only used when launching multiple Runs simultaneously.
Individual Runs will be launched on each processor. No multi-threaded
processors are used with this option.
- Launch Runs on Remote Hosts (Linux only)—Select this option to use remote
hosts to launch job or jobs.
- Configure Hosts—Select this option to configure remote hosts. For more
information, see Launching and Managing Multiple Synthesis Runs in
Chapter 6.
- Generate scripts only—Select this option to export and create the Run directory
and Run script, but not to launch the Run from PlanAhead. The script can be run
at a later time outside of the PlanAhead environment.
3. Click OK to create the Run with the selected launch options.
If the selected Runs are in a state other than “Not Started,” you are prompted to first reset
the Runs prior to launching them.

Resetting Runs
The Reset Runs command removes the results of the selected Runs. You are prompted to
remove the Run data from disk, which is advisable. The Run status is set back to Not
Started.
1. Select one or more Runs in the Design Runs view. Press Shift+Click or Ctrl+Click for
multiple selections.
2. Select the Reset Runs popup command.
The Reset Runs dialog box prompts you to remove all Implementation data from disk
for the selected Runs.

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3. In the confirming dialog box, click Reset.

If any ISE processes are currently running or queued, you are prompted to stop them.
4. Click Yes to proceed.
The status for the selected Runs is reset.

Deleting Runs
The Delete command removes selected Runs from the Design Runs view and removes
their associated data from disk. You are prompted to confirm the deletion of the selected
Runs.
1. Select one or more Runs in the Design Runs view. Use Shift+Click or Ctrl+Click for
multiple selections.
2. Select one of the following:
- The Delete toolbar button, as shown in Figure 9-30.

Figure 9-30: Deleting Selected Runs Toolbar Button

- The Delete popup menu command in the Design Runs view.

- The Edit > Delete command.
- The Delete key.

Copying Runs
You can create a new Run based on an existing Run by using the Copy Run popup
command in the Design Runs view. This command creates a new Run using the same
strategy and inputs as the selected Run you are copying from. The Run status is reset to Not
Started in the newly created copied Run.

Opening a File Browser in a Run Directory

You can open a file browser directly from the Runs view in order to browse files in the Run
directory on your system. To do this, select a Run in the Design Runs view, then right-click
and select the Open Run Directory popup menu command.

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Launching Runs on Remote Linux Hosts

The PlanAhead software ships functionality to allow parallel execution of Runs on
multiple Linux hosts. This is accomplished with simplified versions of more robust load-
sharing software, such as Grid Engine by Sun® MicroSystems, and LSF.®
Job submission algorithms are implemented using a “greedy,” Round-Robin style with Tcl
pipes within Secure Shell (SSH).

Limitations on Launching Runs on Remote Linux Hosts

The limitations are as follows:
• Host execution is performed with SSH, a service provided by Linux operating system,
and not PlanAhead. For this to work, you must configure SSH so that you are not
prompted for a password each time you log in to a remote machine. If you have not
configured key-agent forwarding for passwordless SSH, or if you have configured
SSH and you are prompted for a password, see Appendix D, “Configuring SSH
Without Password Prompting.”
• Linux-to-Linux hosting is the only supported platform because of security and lack of
remote-shell capabilities on windows systems.
• ISE tool installation is assumed to be available from any login shell, which means that
$XILINX and $PATH are configured correctly in your.cshrc/.bashrc setup scripts.
If you can log into a remote machine and enter map -help without sourcing any
other scripts, this flow will work. If you do not have ISE set up upon login (.cshrc or
.bashrc), you can use the Run pre-launch script option to pass an environment
setup script to be Run prior to all jobs.
• PlanAhead installation must be visible from the mounted file systems on remote
machines. If the PlanAhead installation is stored on a local disk on your own machine,
it will not be visible from remote machines.
• PlanAhead project files (.ppr) and directories (.data and.runs) must be visible
from the mounted file systems on remote machines. If the design data is saved to a
local disk, it is not visible from remote machines.

Configuring Remote Hosts (Linux Only)

After you have configured SSH, as described in Setting Up SSH Key Agent Forward in
Appendix D, the PlanAhead software enables Runs to be launched using remote servers.
To do so, they must first be configured.
1. To configure a remote host select one of the following commands:
- Tools > Options > Remote Hosts
- Synthesis > Launch Runs > Configure Hosts
- Implementation > Launch Runs > Configure Hosts
- Configure Hosts in the Launch Selected Runs options dialog box
The Remote Hosts dialog box displays as shown in Figure 9-31, page 269.

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Figure 9-31: Configuring Remote Hosts

2. Click the Add button to enter the names of remote servers.

3. Toggle the Jobs option to specify how many processors on the remote machine to use.
Individual Runs are launched on each processor. No multi-threading of processors is
used.
4. Toggle the Enable option to specify whether to use the server. You can use this field
when launching Runs to specify which servers to use for the selected Runs to be
launched.
5. Optionally, modify the launch jobs in the field to change the remote access command.
The default is ssh.
Note: Use extreme caution when modifying this field. For example, removing ‘BatchMode =yes’
could cause the process to hang because the shell incorrectly prompts for an interactive
password.
6. Optionally, click the Run pre-launch script button and define a script to Run prior to
launching the Runs. Use this option to pass an environment setup script if you do not
have ISE set up upon login (.cshrc or .bashrc).
7. Optionally, click the Run post-completion script button and define a custom script to
Run after the Run completes.
8. Optionally, click the Send email to button and enter an email address to send
notification when the Run completes.
9. Select one or more hosts, and click the Test button to verify that the server is available
and the configuration is set up properly.
Note: It is strongly recommended that you test each host to ensure proper set up.
10. Select the Remove button to delete selected remote hosts.
11. Click OK to accept the Remote Host configuration settings.

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Analyzing Implementation Results

This chapter contains the following sections:
• Opening the Implemented Design
• Opening Multiple Implemented Designs
• Importing ISE Results From Outside PlanAhead
• Analyzing Placement and Timing Results
• Exploring Logic Connectivity
• Searching for Objects using the Find Command
• Highlighting Logic Objects
• Marking and Unmarking Selected Objects
• Locking Placement for Future Implementation Runs
• Displaying Design Metrics
• Launching XPower Analyzer for Power Analysis
• Launching FPGA Editor
• Cross Probing Timing Paths to FPGA Editor

Opening the Implemented Design

You can load Implementation results that were created either inside or outside of the
PlanAhead™ software into PlanAhead for analysis and floorplanning purposes.
PlanAhead imports placement and timing results from the Xilinx® ISE® Design Suite only.
Routing resources are not available for analysis.
If you used PlanAhead to launch the Implementation run, you can open the
Implementation results by clicking Implemented Design from the Flow Navigator.
The button is available only when a successfully implemented design exists in a project;
see Figure 10-1, page 272.

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Figure 10-1: Project Manager Screen

PlanAhead loads the original netlist the ISE placement and TRACE timing results in the
Design Planner environment.
The Implemented Design menu becomes available in the Flow Navigator also, as shown in
Figure 10-2, page 273.
An icon displays within the Implemented Design button to indicate that an implemented
design is open.

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Figure 10-2: Implemented Design Environment

The placed design shows in the Device view. When you import placement results from ISE,
placed instances are displayed as “unfixed” in PlanAhead. Placed instances that were
constrained with LOC constraints prior to Implementation are referred to as “fixed” and
display with a different color.
You can lock any placement in place for subsequent Runs by using the Fix Instances
popup menu command. Refer to Chapter 11, Floorplanning the Design and Analyzing
Implementation Results, page 271.
Note: ISE can optimize and change logic to improve placement and routing results. When this
happens, logic in the original netlist is removed or replaced. This results in a mismatch between the
pre-Implementation netlist opened in PlanAhead and the Implementation results. The Tcl Console
will report these discrepancies as the Implemented Design is being opened. It does not pose any
problems other than the logic in the netlist does not match the viewed results exactly.
PlanAhead extracts the timing results from the ISE TRACE program TWX file output and
displays the results in the Timing Results view.
Timing paths are organized by constraint and you can expand and collapse the paths using
the tree widgets in the view.
You can select and highlight paths in the Device view. You can examine timing path details
in the Path Properties view. Refer to Analyzing Placement and Timing Results, page 276
for more information.

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Opening Multiple Implemented Designs

You can open any Implementation run by one of the following options:
• Selecting it in the Design Runs view and using the Open Implemented Design
popup menu command.
• Setting the run as the active run, then clicking the Implemented Design button in the
Flow Navigator. Refer to Setting the Active Run, page 263.
You can open multiple Implementation runs if they were launched from PlanAhead. Tabs
display in the upper left corner of the viewing environment to enable switching between
open implemented designs as shown in Figure 10-3.

Figure 10-3: Multiple Implemented Designs Open Tabs

You can open and close available Implemented designs using the pulldown menu in the
Flow Navigator. Each Implementation run shows under the Open Implemented Design
menu enabling any completed run to be opened as shown in Figure 10-4.

Figure 10-4: Opening and Closing Implemented Designs

When multiple implemented designs are open, the Implemented Design button displays
with multiple icons.

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Importing ISE Results From Outside PlanAhead

You can import existing ISE results using the New Project wizard or import timing results.
The following subsections describe the options for importing ISE results.

Using the New Project Wizard to Create an ISE Results Project

You can create a new project and populate the project with a netlist, and timing and
placement results from an ISE software Implementation.
For more information about creating a new project that imports ISE Implementation
results, see Creating a Project with ISE Placement and Timing Results, page 55.

Importing Placement Results into Existing Project

You can import placement results generated outside PlanAhead into the PlanAhead
environment. Placement constraints will be assigned for all placed logic objects.You can
select an implemented NCD file to import, and PlanAhead converts the design
automatically to an XDL format file to read the placement information.
You must have an RTL design, a netlist design or an implemented design loaded for the
Import Placement command to be available. See Working with Designs, page 41 for more
information.
To import placement results:
1. Select File > Import Placement. The Import Placement dialog box opens.
X-Ref Target - Figure 7-41

2. Select an NCD file to import placement from the Import Placement dialog box.
PlanAhead automatically converts the NCD file to XDL format, and imports the XDL
result file.
Note: If a current XDL file already exists you can also choose to import that file directly.
3. Click OK to import the placement results.

Importing ISE TRCE Timing Results into an Existing Project

The PlanAhead software has the ability to import the TWX format timing report files
generated by the Xilinx® Timing Report And Circuit Evaluation (TRACE) command. Once
imported, all the signal tracing and viewing capabilities described in this chapter are
available in the PlanAhead environment.
You must have an e RTL design, a netlist design, or an implemented design for the Import
Timing command to be available. See Working with Designs, page 41 for more
information.
To import timing results:
1. Select File > Import Timing. The Import Timing dialog box opens.
2. View and edit the definable fields in the Import Timing Results dialog box:
- File Name—Select a TWX file for PlanAhead to import results.
Note: You can alternatively select to import a TWR format file if the TWX file does not exist.
If both files exist, TWX is the preferred format to use to import timing results.
- Results Name—Define a name to appear on the Results tab in the Timing Results
view.

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3. Click OK to import the timing results.

The timing results display within the PlanAhead environment.
You now can:
• Explore all of the path selection, highlighting, and tracing capabilities using the
PlanAhead interface.
• Sort the timing results by clicking any of the column headers. You can sort by a second
column by pressing the Ctrl key and clicking a second column header. Add as many
sort criteria as necessary to refine the list order.
• Display multiple timing results for a floorplan.
Each result receives a tab at the bottom of the report. Slack values are red for paths with
negative slack values.

Analyzing Placement and Timing Results

The following sections describe the options for analyzing placement and timing results.

Exploring Xilinx TRACE Results

PlanAhead displays the results from ISE timing analysis by extracting information from
the TWX timing report files. These files display automatically if the Implementation Run
was launched from PlanAhead. Otherwise, the Implementation results must be imported
into PlanAhead. Refer to Importing ISE Results From Outside PlanAhead, page 275.
Once imported, the timing results display in the Timing Results view. If no timing
constraints were used to launch ISE, then no timing results display.

Using the Timing Results View

Timing results imported from the ISE trce display differently than the PlanAhead Report
Timing command results described in Chapter 7, “Netlist Analysis and Constraint
Definition.” The TRACE results report the exact timing information coming from the
implemented design, while the PlanAhead report estimates routing delays.
The Timing Results view also displays the TRACE timing path information sorted by clock
constraint. Timing paths can be expanded and collapsed using the tree widgets in the view.
Failing paths Slack numbers display in red.
Figure 10-5 shows a TRACE result.

Figure 10-5: ISE TRACE Timing Results

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Using the Path Properties View

Selecting a Path in the Timing Results view displays information about the logic and delay
on that path in the Path Properties view.
The display of timing paths imported from TRACE differs from the displays of PlanAhead
Report Timing command results, described in Chapter 7, “Netlist Analysis and Constraint
Definition.” The TRACE results report additional information such as Clock Skew and
Jitter, as shown in Figure 10-6.

Figure 10-6: Timing Path Property View

Selecting any logic object highlights that object in all other PlanAhead views.
PlanAhead provides links under the Delay Type column to invoke a PDF viewer with the
device data sheet. A search is then performed automatically for the selected logic object.
For more information about analyzing timing results using the Timing Results and Path
Properties views, see Chapter 7, “Netlist Analysis and Constraint Definition.”

Viewing Timing Paths in the Device View

You can view timing paths in the Device view when you select a path row or rows in the
Timing Results view. The path is highlighted in the Device view. You can select multiple
paths and all instances found in the path are selected and highlighted. Figure 10-7,
page 278 shows a highlighted timing path in the device view.

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Figure 10-7: Highlighted Timing Paths in the Device View

Viewing Timing Paths in Schematic View

When you select Schematic from the Timing Results toolbar or popup menu, PlanAhead
generates a Schematic view that displays the instances found in the selected paths. The
Schematic view displays the instances clearly along with the hierarchical modules as
shown in Figure 10-8.

Figure 10-8: Timing Paths Displayed in Schematic View

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When PlanAhead generates the Schematic view for a timing path, it displays all of the
objects. When you select a Schematic view for individual logic instances to be generated,
only the selected instances display.
You can display the instances from a group of paths in this manner making it easy to
identify what modules should be grouped together for floorplanning. Pblock creation
popup commands in the Schematic view let you make direct assignment to Pblocks in the
device view. For more information about Schematic expansion and traversal commands,
see Using the Schematic View, page 111.

Exploring Logic Connectivity

The following sections describe logic connectivity options in PlanAhead.

Using the Show Connectivity Command

The Show Connectivity command highlights all of the nets connected to the selected
elements. To use this command, perform one of the following:
1. Select a Netlist, a Pblock instance, or a combination thereof.
2. From the popup menu, select Show Connectivity.
For example, if you select an instance or Pblock in the Schematic view, all of the nets
connecting to that element are highlighted in the Device view, as shown in Figure 10-9.

Figure 10-9: Net Connectivity in the Device View

Viewing Logic Connectivity using Show Connectivity Mode

You can run the Show Connectivity command continuously on newly-selected objects by
toggling the Show connections for selected instances toolbar button on and off.

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The Show connections for selected instances mode remains active, which lets you select
additional logic objects for viewing connectivity. Toggle the toolbar button, shown in
Figure 10-10 to turn off Show connections for selected instances mode.

Figure 10-10: Show connections for selected instances Mode Toolbar Button

Expanding and Selecting a Logic Fanout

You can run the Show Connectivity command sequentially to continue to select and
expand a logic fanout.
1. Select a Netlist, a Pblock instance or a combination thereof.
2. From the popup menu, select Show Connectivity. The command highlights all nets
connected to the selected element.
3. From the popup menu, select Show Connectivity a second time. The command selects
the set of connected instances to those nets. You can use the Ctrl+T shortcut key also.
4. From the popup menu, select Show Connectivity a third time. The command
highlights the next level of nets connected to the selected instances, and so on.
This is an easy way to select a logic fanout starting at a particular instance or I/O port.

Expanding Logic in the Schematic View

You can trace logic throughout the design hierarchy using the Schematic view. Anything
selected in the Schematic view is highlighted in the Device view also.
You can expand signals interactively by double-clicking on the pins of the instance to be
traced. Figure 10-11 shows an example of expanded logic in the Schematic view.

Figure 10-11: Logic Expanded in the Schematic View

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Also, you can expand and display instance and module connectivity, and content
interactively.
For more information about exploring logic in the schematic, see Using the Schematic
View, page 111.

Searching for Objects using the Find Command

Once the placement is displayed in the Device view, you can use the Find command to
search for and locate any type of logic. The Edit > Find command dialog box provides
flexibility for filtering the search criteria in many different ways.
For more information about searching for logic objects see Chapter 7, “Netlist Analysis and
Constraint Definition.”

Highlighting Logic Objects

There are two commands for highlighting objects, as follows:
• The Highlight command is for highlighting specifically selected objects.
• The Highlight Primitives command is for highlighting all of the primitive logic
associated with selected modules.

Highlighting Selected Objects

PlanAhead has a highlight mechanism that lets you selectively highlight objects.
Highlighting lets you display multiple placement groups at once using one or more colors.
Highlighted objects remain highlighted even when you click elsewhere in PlanAhead.
They are highlighted in all applicable views including the Schematic.
You can highlight any number of selected objects, as follows:
• Once you select an object you can highlight it with the Select > Highlight command
or you can select Highlight from the popup menu in most views. This command
operates on the selected logic.
• When highlighting all Netlist module or Pblock logic, you can use the Highlight
Primitives command to highlight the lower level logic. For more information, see the
following section.

Using the Select Primitives and Highlight Primitives Commands

After you import the ISE placement, you can use the Select Primitives command to select
the underlying primitive logic elements for Pblocks and logic modules. This command is
often used in conjunction with the Show Connectivity, Fix instances or Clear LOC
Constraints commands.
After you import the ISE placement, you can use the Highlight Primitives command to
highlight the underlying primitive logic elements selectively for Pblocks and logic
modules, and then select a color to highlight their associated placement.
When you select multiple instances, you can select the same color for all or use Cycle
Colors to use different highlight colors for each of the selected modules.
PlanAhead marks modules and primitives in the Netlist view with the matching highlight
color in the Device, Schematic, and Package views, as shown in Figure 10-12, page 282.

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Figure 10-12: Matching Highlighting Color in the Netlist and Device Views

Unhighlighting Objects
To un-highlight objects, use one of the following commands:
• Choose Select > Unhighlight All to unhighlight all objects.
• Choose Select > Unhighlight Color to unhighlight based on color.
• Click the Unhighlight All toolbar button as shown in Figure 10-13.

Figure 10-13: Unhighlight All Toolbar Button

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Marking and Unmarking Selected Objects

The PlanAhead software lets you place a Mark symbol and remove the Mark in all
applicable views for selected objects.

Marking Objects
Marking a selected object is helpful when displaying small objects that you want to see in
the Device view.
To mark selected objects, select Select > Mark, or press Ctrl+M. This command is available
in other views, including the Netlist and Physical Hierarchy views.
When marking timing paths, the start point is marked in green, the end point in red, and
all intermediate points in yellow, as shown in Figure 10-14.

Figure 10-14: Marked Timing Path Symbols in Device View

Removing Marks
You can remove marks using one of the following methods:
• Choose Select > Unmark to unmark the selected instance.
• Choose Select > Unmark All or click the Unmark All toolbar button as shown in
Figure 10-15 to unmark all marked instances.

Figure 10-15: Unmark All Toolbar Button

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Locking Placement for Future Implementation Runs

When you import placement results from ISE, placed instances display as unfixed in
PlanAhead. Placed instances that were constrained with LOC constraints prior to
Implementation are referred to as fixed and display with a different color.

Using the Fix Instances Command

You can lock placement in place for subsequent runs by selecting the desired logic and
using the Fix Instances popup menu command.
You can use this capability to help ensure consistent Implementation results. Once the you
have saved the implemented design, the fixed logic will receive LOC and BEL constraints in
the UCF, and can be passed to the subsequent Implementation runs.

Fixing Specific Types of Logic

A method for improving consistency of Implementation result is to lock some or all of the
block macro logic such as block RAMs and DSPs. You can do this manually in PlanAhead
using your own knowledge of the design or by leveraging successful ISE Implementation
results. If your design has a lot of block RAMs or DSPs, this method can help produce more
consistent results and improve runtime.
Refer to Working with Placement LOC Constraints, page 308 for information about
manually assigning LOC constraints.
To Fix specific types of logic, use the Find command to select specific types of logic such as
block RAMs and DSPs. You can then select all of them in the Find Results view and use the
Fix Instances popup menu command.

Fixing Logic Modules

A method for improving consistency of Implementation result is to lock critical logic in
place. This can involve locking specific logic, timing paths or entire logic modules.
To Fix (place) all logic in a particular module, select the module or modules and use the
Select Primitives command to select the primitive logic instances associated with the
logic module. To lock the logic, use the Fix Instances command.

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Displaying Design Metrics

The following subsections describe the design metrics options:

Using the Metrics View

The PlanAhead Metrics view displays a list of design metrics that you can display using a
colored graph of the potential problem areas in the design. The metrics include utilization,
routing congestion, and timing checks at the Pblock and implemented design level.
To open the Metrics view, select Window > Metrics. Figure 10-16 shows the Metrics view.

Figure 10-16: Metrics View

The Metric Properties view provides a description of the selected Metric function along
with the bins defined to highlight potential problems, as shown in Figure 10-17.

Figure 10-17: Properties View: Set Metric Range Values

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Displaying the Metric Maps in the Device View

To display a Metric map in the Device view, select the metric and select the Show popup
menu command. PlanAhead displays a color-based metric map. Figure 10-18 shows an
example of a Metric map in the Device view.

Figure 10-18: Metric Map in the Device View

You can display multiple metric maps simultaneously.

• To display any of the slack related metrics, you must run a PlanAhead timing
estimation first using the Report Timing command.
• To display any of the CLB or BEL constraints type metrics, import the placement
results from ISE Implementation.
For more information, see Opening the Implemented Design, page 271 and Importing ISE
Results From Outside PlanAhead, page 275.

Removing the Metric Map Display

To hide a metric map in the Device view, select the metric, and from the popup menu,
select Hide or Hide All Metrics.

Using the Metrics Results View

After you select the Show command, the metric results display in the bottom view. In the
Metric Results view, you can:
• Sort the information by clicking any of the column headers.
• Sort by a second column by pressing the Ctrl key and clicking a second column
header.
• Add as many sort criteria as necessary to refine the list order.

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The Pblock metric results update automatically as you modify the Pblocks. The different
types of metrics such as for Pblocks, CLBs, and primitives, display in different charts. Each
type has a tab along the bottom of the Metrics Results view, as shown in Figure 10-19.

Figure 10-19: Metric Results View

Configuring the Metric Ranges

Within the Properties view you can configure the bin ranges for each map.
Colors and the range display are adjustable. You can add or delete new bins to define
ranges. To do so, select the Apply changes button in the Metrics Properties view or select
Apply Changes from the popup menu.
To insert a new range bin, select the bin you want to split, and select Insert Bin from the
right-click popup menu. Figure 10-20 allows the definition of the range and color.

Figure 10-20: Insert Bin Dialog Box

The ranges are adjusted to accommodate the newly defined range.

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Launching XPower Analyzer for Power Analysis

You can launch the XPower Analyzer tool directly from PlanAhead to perform power
analysis on any implemented design.
To invoke XPower Analyzer, in the Flow Navigator, open the Implemented Design, then
select the Launch XPower Analyzer command from the Implemented Design task list as
shown in Figure 10-21.

Figure 10-21: Launch XPower Analyzer

Alternatively, to launch XPower Analyzer without first loading the implemented design,
you can select Launch XPower Analyzer from the main Flow menu in PlanAhead.
The routed NCD file is passed automatically to the XPower Analyzer when launched from
PlanAhead. For more information on using XPower Analyzer, see the ISE Help.

Launching FPGA Editor

You can launch the FPGA Editor directly from PlanAhead on any implemented design.
To invoke the FPGA Editor, in the Flow Navigator, open the implemented design, then
select the Launch FPGA Editor command from the Implemented Design task list.
Alternatively, to launch FPGA Editor without first loading the implemented design, you
can select Launch FPGA Editor from the main Flow menu in PlanAhead.
The routed NCD file passes automatically to the FPGA Editor when launched from
PlanAhead. For more information on using FPGA Editor, see the ISE Help.

Cross Probing Timing Paths to FPGA Editor

You can cross probe from a timing path in PlanAhead to FPGA Editor. To perform this task,
follow these steps:
1. Select a timing path from the Timing Results view or the Device view, and select Cross
probe to FPGA Editor from the popup menu. You can also select individual logic
instances to cross probe to FPGA Editor.
2. FPGA Editor will open with the selected path or instance highlighted.
If FPGA Editor is not open, you are prompted to open the tool.

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Floorplanning the Design

This chapter contains the following sections:
• Floorplanning Strategy Overview
• Working with Pblocks
• Configuring Pblocks
• Working with Placement LOC Constraints
• Interfacing with ISE Outside of PlanAhead

Floorplanning Strategy Overview

The PlanAhead™ software supports a floorplanning methodology that lets designers
constrain critical logic to ensure shorter interconnect lengths with less delay.
This methodology involves user interaction with the physical design and is not a push-
button flow. Designers can use the analysis capabilities in PlanAhead coupled with their
own knowledge of the design to define constraints and tool options for improving
performance.
Floorplanning can be accomplished by creating physical block (Pblock) locations to
constrain logic placement or by locking individual logic objects to specific device sites.
The complexity of floorplanning requires more explanation than is practical to provide in
this user guide. For more information, see the Floorplanning Methodology Guide (UG633).

Working with Pblocks

The following subsections describe how to work with Pblocks:

Creating Pblocks
The process of floorplanning begins by dividing some or all of the logic in the design into
groups and constraining that logic. The PlanAhead software provides the ability to
hierarchically divide the design into smaller, more manageable physical blocks (Pblocks).
These Pblocks can include logic modules and primitive logic from anywhere in the logic
hierarchy. You can group critical or associated logic together into a single Pblock, which
prevents logic migration, limits interconnect lengths, and reduces delays.
Creating a Pblock results in an AREA_GROUP constraint that is written into the exported
UCF constraint file. The constraints in PlanAhead reflect the assigned logic, specified
ranges, and defined attributes.

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Using the Draw Pblock Command

The Draw Pblock commands assigns pre-selected logic to a new Pblock in the Device view.
You can select the logic to assign to the Pblock before you invoke the command.
To create a Pblock:
1. Select the logic in any view, such as the Netlist view, to assign to the Pblock.
2. Click Draw Pblock, in either the popup or on the toolbar. Figure 11-1 shows the
Draw Pblock button.

Figure 11-1: Draw Pblock Toolbar Button

3. Move your cursor to the location in the Device view where you want to start drawing
a Pblock.
4. Press and hold the left mouse button, move the mouse cursor to the opposite corner of
the Pblock, and release the mouse button.
The New Pblock dialog box opens as shown in Figure 11-2.

Figure 11-2: New Pblock Dialog Box

5. Edit the options in the New Pblock dialog box:

- Name—Enter a name for the Pblock. If no name is entered, a default name of
pblock_n or Pblock_instancename is used.
- Grids—Select the device resource ranges to be constrained by the Pblock.
- Assign selected instances—Select to assign the selected instances to the new
Pblock. Occasionally, users inadvertently have logic selected, which is not
intended for assignment.
6. Click OK.
The Pblock displays and you can select it in the Device view and the Physical Constraints
view.
The initial Pblock size and location are not critical during manual creation. Pblocks can be
appropriately sized and located by using dynamic Resource Utilization Statistics in the
Pblock Properties dialog box. You can determine how to reposition Pblocks by viewing
the connectivity display in the Device view.

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Sometimes, it is helpful to initially create all of the Pblocks with small rectangles to help
visualize the logic connectivity flow between the Pblocks prior to attempting sizing as
shown in Figure 11-3.

Figure 11-3: Pblock Connectivity Analysis in the Device View

See Analyzing Hierarchical Connectivity, page 169 and Using the Show Connectivity
Command, page 279 for more information about this view.

Using the New Pblock Command

The New Pblock command creates a new Pblock in the Physical Constraints view, but does
not create a rectangle in the Device view.
You must pre-select logic for assignment to the new Pblock. If no logic is pre-selected, the
command creates an empty Pblock.
To create new Pblocks with or without pre-selected logic, select New Pblock from the
popup menu.

Creating Multiple Pblocks with the Create Pblocks Command

You can create multiple Pblocks in a semi-automated way by using the Create Pblocks
wizard. The wizard creates a separate, unplaced Pblock for each selected netlist instance.
To use the wizard, pre-select a set of instances for inclusion into individual Pblocks.
To create multiple Pblocks for specific netlist instances:
1. Select the instances to include in a Pblock.
2. Select Tools > Create Pblocks.
The Create Pblocks wizard opens with a list of the selected instances as shown in
Figure 11-4, page 292.

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Figure 11-4: Create Pblocks Wizard: Create Pblocks from Instances

- To add additional netlist instances to this list, click the Add button to invoke a
browser in which you can select other instances.
- To remove any netlist instances from the list, click the Remove button.
- To clear netlist instances from the list, click the Clear button.
3. Click Next.
The Create Pblocks wizard gives you the option to specify a naming scheme.
4. In the Create Pblocks wizard, edit the naming scheme fields:
- Prefix—Defines a name prefix to be used for the Pblock names. Enter a new prefix
or allow the default instance name or number to be used.
- Suffix—Select Instance name to append the instance name onto the prefix, or
select Numeric to append a number starting with 1 to the prefix.
5. Click Next.
6. Verify the contents in the Summary page.
7. Click Finish to create the Pblocks with these settings.
The Pblocks now show in the Physical Constraints view as in Figure 11-5.

Figure 11-5: Pblocks in Physical Constraints

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To create rectangles for the newly-created Pblocks:

1. Select each of the new Pblocks (one at a time) in the Physical Constraints view.
2. Click the Set Pblock Size button in the Device view toolbar, which is shown in
Figure 11-6, page 293.

Figure 11-6: Set Pblock Size Toolbar Button

3. Draw a rectangle in the Device view.

Creating Nested Pblocks

You can create Pblocks within Pblocks (nested Pblocks) to provide further control for
constraining logic. This can be helpful when trying to improve performance of critical
modules. The top-level Pblock contains all the lower-level Pblocks during utilization
estimates.
Note: The ISE Implementation software does not support extensive use of this feature.
Occasionally, map and placement errors result when creating nested Pblocks.

Creating Clock Region Pblocks

You can define a Pblock to include all resources within a specific clock region or regions.
To define a Pblock as a clock region in the Device view:
1. Draw a Pblock with a rectangle that encompasses the boundary of the clock region.
The PlanAhead software displays the clock region boundaries.
To change the color or display characteristics of the clock region boundaries, refer to
the Customizing PlanAhead Display Options in Chapter 4.
Figure 11-7 shows a clock region Pblock.

Figure 11-7: Creating Clock Region Pblocks

The tool tip changes to indicate the Pblock range is a Clock Region.

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2. Select OK in the Set Pblock dialog box to define the Pblock range as the clock region
(CLOCKREGION_X) as shown in Figure 11-8.

Figure 11-8: Set Pblock Dialog Box to Confirm Pblock as Clock Region
Note: The Pblock rectangle must encompass the clock region boundary to enable the
CLOCKREGION option in the Set Pblock dialog box. When you unselect the
CLOCKREGION_X button, you can define the Pblock using traditional logic based ranges.
Note: You can toggle the two types of Pblocks by selecting or deselecting the
CLOCKREGION button in the Set Pblock dialog box or in the Pblock General Properties view.
The Pblock clock region coordinates display in the Pblock General Properties view.

Understanding Pblock Graphics

The default display options show what is a Pblock and what are the instances assigned to
the Pblock.
• The outer rectangle is the Pblock border.
• The rectangles contained inside the Pblock are the netlist instances assigned to it.
You can place multiple instances into a Pblock, and instance rectangles displayed inside
the Pblock are sized based on the amount of logic they contain, relative to the other
instances in the same Pblock.
If many instances are assigned to a Pblock, they might appear as lines instead of rectangles
as shown in Figure 11-9, page 295.

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Figure 11-9: Pblocks With Assigned Instances Displayed Graphically

Using the default selection rules, selecting the Pblock rectangle selects all of the netlist
instances contained in it also. You can drag and assign Instances into other Pblocks.
Note: You can view and modify Selection Rules for the tool by selecting
Tools > Options > Selection Rules.
Note: Be careful when manipulating Pblocks to ensure the Pblock rectangle is selected and not the
smaller rectangles indicating the assigned instances. It is helpful when manipulating Pblocks to turn
off the selection ability for instances. This ensures Pblocks and not the instances assigned to them
are selected in the Device view. To define how instances and Pblocks are selected, select Tools >
Options > Themes > Device, and define the selection ability. For more information, see Creating
and Using a Customized Theme, page 132.
I/O Nets are drawn connected to the center of the instance inside the Pblock rather than in
the Pblock center as shown in Figure 11-10, page 296.

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Figure 11-10: I/O Connectivity Displays to Center of Instance Rectangles

Child Pblocks appear in a different color to differentiate the rectangles. You can configure
the color configuration in the Tools > Options > Themes > Device dialog box.
Pblocks might contain multiple rectangle ranges. Multiple rectangle ranges display with
dashed lines connecting them to indicate that they are part of the same Pblock. The
assigned instance rectangles and connectivity display in the largest rectangle as shown in
Figure 11-11.

Figure 11-11: Creating Pblocks with Non-Rectangular Shapes

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Viewing Pblock Properties

You can display various types of information with the Pblock Properties view. To display
or edit Pblock properties, select the Pblock and view the Pblock Properties view. The
Pblock Properties view tabs are listed in Table 11-1.

Table 11-1: Pblock Properties Tabs

Tab Options
General • Name—Displays the Pblock name.
• Parent—Displays the Parent Pblock. This field is a non-editable field for some Pblocks. If a
Pblock has multiple potential parent Pblocks, the field becomes active allowing definition of the
Parent Pblock.
• Grid Range—Enables the Pblocks to be specified with specific AREA_GROUP RANGE
properties. Selecting specific ranges constrains only the selected logic types within the Pblock
area. The grid range coordinates display for each logic type once the Pblock is created.
• CLOCKREGION—Defines the Pblock range to be an entire clock region. The Pblock rectangle is
drawn to match the clock region boundary.
• Apply / Cancel—Saves or discards changes.
Statistics • Physical Resources Estimates—A chart of each resource type in the device.
- Site Type—The Site Types defined within the Pblock rectangle.
- Available—The number of sites contained in the Pblock.
- Required—The number of sites required for the logic assigned to the Pblock.
- % Utilization—The estimated percentage of the sites populated in the Pblock.
• Carry Statistics—The number of vertical carry chain logic objects assigned to the Pblock. It also
displays the tallest carry chain assigned to the Pblock and the percentage of its height in relation
to the Pblock height. Carry height utilization values over 100% can cause PlanAhead DRC errors
and ISE map errors.
• Clock Report—Clock signals (Local, Global, and Resource) contained in the Pblock as well as the
number of clocked instances on each clock.
• RPM Statistics—The number of Relatively Placed Macros (RPM) objects assigned to the Pblock.
It also displays the tallest and widest RPM assigned to the Pblock and the percentage of its size
in relation to the Pblock size.
Note: RPM utilization values over 100% will cause PlanAhead DRC errors and ISE map errors.
PlanAhead does not indicate whether multiple RPMs will fit inside the Pblock rectangle.
• Clock Region Statistics—The utilization percentage of each clock region that the Pblock
overlaps.
• Primitive Statistics—The number of each type of logical resource assigned to the Pblock.
Note: You can save the contents to a text file using the Export Statistics icon.
Instances Displays information about the instances contained in the Pblock. You can select the instance fields
and use them to seed many popup menu commands.
Rectangles Displays information about the various rectangles created for the Pblock. The Rectangle tab is used
for selecting rectangles of a Pblock. Refer to the Using Non-Rectangular Pblocks, page 304.
Attributes Lets you define Attribute properties to a Pblock. See Setting Attributes for Pblocks, page 305.

Note: To accept any changes made, click Apply. To cancel any changes, click Cancel. Selecting
another item or closing the Properties view will not initiate any changes unless you click Apply.

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Configuring Pblocks
The following subsections describe configuring Pblocks:
• Setting Pblock Logic Type Ranges
• Assigning Logic to Pblocks
• Moving and Resizing Pblocks
• Using Resource Utilization Statistics to Shape Pblocks
• Placing Pblocks Based on Connectivity
• Using Non-Rectangular Pblocks
• Removing a Pblock Rectangle
• Setting Attributes for Pblocks
• Renaming a Pblock
• Deleting a Pblock
• Running the Automatic Pblock Placer

Setting Pblock Logic Type Ranges

You can set Pblock AREA_GROUP range types in the Pblock Properties view by modifying
the Grid Range options in the General tab. Adjusting these options controls which type of
logic is to be constrained within the Pblock rectangle, as shown in Figure 11-12.

Figure 11-12: Setting AREA_GROUP Range Types

If you resize a Pblock or move it to a location that includes new device logic types, such as
block RAM and DSP, a dialog box displays prompting you to add the new range types to
the Pblock definition. The contents of this dialog may vary depending on where the Pblock
is located.
Toggling the ranges off results in the Pblock being shown differently in the Device view.
As the Pblock is selected the shading will only affect the logic types for the ranges set on
the Pblock, as shown in Figure 11-13, page 299.

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Figure 11-13: Pblock Shading Reflects Logic Contained in Pblock

Assigning Logic to Pblocks

Once a you create a Pblock, you can assign netlist instances. This can be done by either
dragging and dropping logic, or by using the Assign popup command.
To use the drag and drop method:
1. Click and drag logic instances from the Netlist, Schematic, Hierarchy or Find Results
views.
2. Drop the instances into the Pblock rectangle area.
To use the Assign command method to assign logic to existing Pblocks:
1. Select logic instances in the Netlist view.
2. Select the Assign popup command.
The Select Pblock dialog box displays the allowable selections of the Pblock
assignment as shown in Figure 11-14, page 300.

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Figure 11-14: Select Pblock Dialog Box

Unassigning Logic from Pblocks

Instances can be removed from Pblocks, as follows:
1. Select the instances by any means.
2. Select the Unassign popup command.
A confirmation dialog box opens asking to confirm the removal of instances from the
Pblock.

Moving and Resizing Pblocks

The following subsections describe how to move, resize, and set Pblocks.

Moving a Pblock
You can move a Pblock by selecting and dragging the Pblock within the Device view, and
dropping it in the new location. The dynamic cursor shaped like a hand indicates that the
Pblock is selected for moving. Ensure that the outer Pblock rectangle is selected and not
one of the assigned instances.
If the Pblock is moved to a location that includes new device logic types, such as a block
RAM or a DSP, a dialog box displays prompting you to add the new range types to the
Pblock definition.
Pblocks behave differently when assigned logic has a placement constraint inside the
Pblock borders. The target location should contain adequate resources to accommodate the
placement constraints. As the Pblock is moved, the cursor indicates which sites are legal
for a move, based on placement requirements. If you attempt to move a Pblock to an
inadequate location, a dialog box displays prompting you to either remove or leave the
location constraints intact.
Fixed (Placed) and unfixed (Unplaced) location constraints are listed separately in the
dialog box, allowing you to handle them differently.

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Figure 11-15 shows the Choose LOC mode dialog box.

.

Figure 11-15: Setting Behavior for Modifying Pblocks with LOCs

To cancel an active move operation, press the Esc key and the active command is
terminated.
Note: If you are having difficulty moving Pblocks, click the Set Pblock Size toolbar button to redraw
the rectangle elsewhere. You might need to remove placement constraints prior to moving Pblocks.

Resizing a Pblock
You can stretch Pblock edges by selecting the Pblock and moving the cursor near one of its
edges or corners. When the cursor changes to a drag symbol, click and drag to reshape the
Pblock.
To cancel an active stretch operation, press the Esc key, and the active command is
terminated.

Using the Set Pblock Size Command

You can size or resize existing Pblocks with a new rectangle by using the Set Pblock Size
command. To create a new rectangle for an already existing Pblock:
1. In the Physical Constraints view or Device view, select the Pblock.
2. Click the Set Pblock Size toolbar button as shown in Figure 11-16.

Figure 11-16: Set Pblock Size Toolbar Button

The cursor changes to enable you to draw a new rectangle in the desired location in the
Device view.
3. Use the cursor to draw a new rectangle.
Also, you can use this command to draw a rectangle for an existing Pblock with no
rectangle yet defined, such as one created with the New Pblock(s) commands. For more
information, see Creating Multiple Pblocks with the Create Pblocks Command, page 291.
If a Pblock has multiple rectangles, this command regenerates the Pblock with a single
rectangle. Often, this is useful when a Pblock gets fragmented into multiple rectangles.

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If you resize the Pblock to a location that includes new device logic types, such as a block
RAM or a DSP, a dialog box displays prompting you to add the new range types to the
Pblock definition.
Pblocks behave differently when assigned logic has a placement constraint inside the
Pblock borders. The target size should contain adequate resources to accommodate the
placement constraints. If you attempt to resize a Pblock to an inadequate size, a dialog box
displays prompting you to either remove or leave the location constraints intact.
Pblocks behave differently when location placement constraints are assigned inside of
them. If location constraints are assigned to the Pblock, a dialog box displays prompting
you to either remove or leave the location constraints intact.
Fixed and Unfixed location constraints are listed separately in the dialog box allowing you
to handle them differently.
To cancel an active resize operation, press the Esc key on the keyboard.

Using Resource Utilization Statistics to Shape Pblocks

You can use the utilization estimates in the Pblock Properties view to size and place
Pblocks. The tool estimates resources required by the logic assigned to the Pblock and
compares that against available device resources to compute utilization estimates.
To display the utilization estimates for a Pblock:
1. Select the Pblock, and view the Pblock Properties.
2. Click the Statistics tab as shown in Figure 11-17.

Figure 11-17: Pblock Properties View: Statistics Tab

3. In the Statistics tab, view the utilization estimates in the following three columns.
- Available—Displays the number of available sites in the Pblock.
- Required—Displays the number of sites that the assigned logic requires.
- % Utilization—Displays the estimated utilization percentage for each logic type.
The appropriate utilization can be met by resizing the Pblock. If Utilization for
some logic objects is over 100%, the text appears in red, as shown in Figure 11-17.
4. Scroll down to view the required RAM sites for the Pblock.
The dialog box is dynamic and updates each time you modify the Pblock.

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If the Pblock does not contain a site for a specific logic device element, the dialog box
shows the following values:
- Available—0.
- Required—The required number.
- Utilization—Percentage of available resources used by the logic in the Pblock. A
value of Disabled means that the Site Type has been disabled (on the General tab)
and is not available for use. If there are sites of this type required by the Pblock,
this is an error condition. A value of No Sites means that the Pblock range on the
device does not include any sites of that type.
Note: The Pblock SLICE utilization calculation assumes maximum site utilization. In reality, the
maximum site utilization is rarely achieved in placement and routing tools. Thus, a designer should
optimize for a target utilization of approximately 80% or higher. This number is a function of the device
used and the characteristics of the design and its constraints.
Note: Pblock utilization is affected by carry chains, RPM macros, and the geometry of the Pblock
rectangle. These statistics are estimates to help guide you to a successful ISE Implementation. All of
the Pblock Statistics must be taken into account when sizing Pblocks. Occasionally, Pblocks must be
enlarged for ISE to place them successfully.

Placing Pblocks Based on Connectivity

The PlanAhead software provides dynamic connectivity feedback to help guide placement
of Pblocks. Figure 11-11, page 296 shows an example of a connectivity display.
The combined connectivity between Pblocks shows as bundled nets. PlanAhead sizes and
colors each bundle based on the number of connections between Pblocks so that the
heavily connected Pblocks are easy to identify.
A reasonable strategy is to define the Pblocks with the largest net bundles close together.
Typically, the Pblocks should be placed in such a way as to achieve the shortest net lengths
and to avoid routing conflicts or congestion.

Displaying Bundle Net Properties

You can view connectivity information by displaying properties for net bundles or for
individual nets. To view connectivity information:
1. Select the net or bundle net.
2. View the Net Properties or Bundle Net Properties view.
The Nets tab in the Bundle Net Properties dialog box displays the nets contained in the
bundle as shown in Figure 11-18.

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Figure 11-18: Bundle Net Properties: Nets Tab

Adjusting Bundle Net Defaults

You can define the color, line width, and signal count range in the view-specific settings of
the Themes dialog box (Tools > Options > Themes > Bundle Nets).

Using Non-Rectangular Pblocks

PlanAhead supports the creation, modification, and deletion of non-rectangular Pblock
shapes with multiple rectangles per Pblock. It is recommended that you use this approach
sparingly and only when necessary, because non-rectangular Pblock shapes can increase
difficulty for downstream tools.

Creating Non-Rectangular Pblocks

To add additional rectangles to existing Pblocks with rectangles, use the Add Pblock
Rectangle toolbar button, as shown in Figure 11-19.

Figure 11-19: Add Pblock Rectangle

Pblocks with multiple rectangles appear as separate rectangles with a dashed line
connecting them as shown in Figure 11-11, page 296.

Modifying Non-Rectangular Pblocks

When you select a Pblock with multiple rectangles defined, all of its rectangles are selected.
They can be moved individually, or together as a group.
To reshape one of the rectangles of a multiple rectangle Pblock, select a rectangle and use
the Set Pblock Size command or resize it manually.
To select or resize a rectangle individually, use one of the following methods:
• For a single Pblock rectangle, click Select in the popup command.
• To select them individually, select the Pblock Properties Rectangles tab.
Pblocks defined that span PowerPC® (405 and 440) processors, MGT sites or configuration
blocks might receive multiple rectangle regions automatically. This is done to enable the
correct rectangle ranges to be defined for Implementation. Figure 11-20, page 305 shows an
example of an individually-selected Pblock.

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Figure 11-20: Selecting the Pblock Rectangles Individually

Note: The tools are not optimized to handle too many ranges per the AREA_GROUP constraint. It
is best to use simple shape configurations such as L or T shapes.

Removing a Pblock Rectangle

You can remove the Pblock rectangle by selecting the Pblock and clicking the
Clear Rectangle popup command.
• Individual Pblock rectangles can be cleared one at a time.
• Multiple rectangles and Pblocks can be cleared simultaneously.
• Clearing Pblock rectangles does not delete the Pblock from the Physical Constraints.

Setting Attributes for Pblocks

Attribute properties can be assigned to Pblocks in the Pblock Properties Attributes tab.
Assigning attributes sets various options for ISE.
Note: Setting these attributes can affect Implementation results or cause failures.
Figure 11-21 shows the Attributes tab.

Figure 11-21: Pblock Properties View: Attributes Tab

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To define new attributes for the Pblock:

1. In the Attributes tab of the Pblock Properties View, select Add pre-defined attributes
from the popup menu, or the toolbar button shown in Figure 11-22.

Figure 11-22: Add Pre-defined Attribute Toolbar Button

The Add Pre-defined Attributes dialog box opens as shown in Figure 11-23.

Figure 11-23: Define Attribute Dialog Box

2. Select the attribute to assign, and click OK.

The specified attribute type is added in Attributes tab.
3. You can then specify an attribute value.
4. Click Apply to accept the changes.

Renaming a Pblock
You can rename Pblocks using the General tab of the Pblock Properties view. Enter the new
Pblock name in the Name field and click Apply. Alternatively, you can modify the Name
attribute on the Attributes tab of the Pblock Properties view.

Deleting a Pblock
You can delete selected Pblocks as follows:
1. In the Physical Constraints view, select one or more Pblocks.
2. Press the Delete key, or select the Delete popup menu command.
3. In the Confirm Delete dialog box, you can select the Remove Pblock children option to
remove any nested Pblocks along with their partitions. Otherwise, when left
unselected, you will delete the selected Pblock only and move any nested Pblocks up
one layer of hierarchy.
4. Click OK to remove the Pblock partition from the Physical Constraints view.

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Running the Automatic Pblock Placer

PlanAhead enables automatic Pblock placement using the Auto-create Pblocks command.
This method is used primarily to create top-level Pblocks to view the data flow of the
design and to understand the relative size and relationship between the various logic
modules in the design. Normally, the designer has some concept of the critical modules
and circuitry in the design and begins floorplanning with those modules.
The automatic floorplanning features are not meant to be used as the only floorplanning
methodology. They are to be used as a tool to help the designer understand the physical
design. Floorplanning is a manual process that leverages designer insight to help guide the
ISE tools.
The PlanAhead Pblock placer sizes and places Pblocks automatically in the device. Pblocks
are sized based on SLICE content only. All other device types are ignored when Pblocks are
created. The Pblocks are created with all RANGES defined.
Note: The resulting Pblocks from the Place Pblocks command might not be suitable for ISE
Implementation. They are sized based on SLICE logic only. You are required to size the Pblocks
manually to include non-SLICE based logic resources.
The Pblock Placer command is intended to provide a quick placement of the selected
pblocks. This is often very helpful to view the data flow through the design. You are
required to adjust Pblock shapes manually before ISE Implementation to include non-
SLICE resources.
To run the block placer:
1. Select Tools > Place Pblocks.
The Place Pblocks dialog box opens.
2. Edit the definable options in the Place Pblocks dialog box:
- Parent Pblock—Select the level of hierarchy to place Pblocks. Pblocks can be
placed at the top “ROOT” or any partitioned Pblock-level of hierarchy.
- Pblocks to place—Displays the Pblocks that exist under the parent Pblock.
- Place—The check boxes control the Pblocks to be placed. Deselecting Place
preserves existing Pblock rectangle locations.
- Pblock—Lists all Pblocks.
- Utilization—Enables specific SLICE utilization targets to be set individually
for each Pblock.
- Set Utilization on all Pblocks—Specifies a new target SLICE utilization target for
all Pblocks listed. This value will override any individual utilization values you
have modified.
3. Click OK to place Pblocks in the design.
A Place Pblocks progress meter displays while the Place Pblocks command is
running.
The Pblocks are sized and placed automatically based on SLICE utilization only.
Refer to the PlanAhead Tutorial: Design Analysis and Floorplanning (UG676) for instructions
how to create top-level floorplans using the Create Pblocks and Place Pblocks commands.

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Working with Placement LOC Constraints

You can assign primitive logic elements to specific logic sites using either the Create Site
Constraint Mode or the Create BEL Constraint Mode command.
PlanAhead includes BEL-level constraint assignments to lock logic to specific gates within
the site.

Understanding Fixed and Unfixed Placement Constraints

PlanAhead differentiates placement constraints that are user-assigned to those that are
assigned by the ISE Implementation tools. User-assigned constraints are either defined
within imported UCF files or manually assigned in PlanAhead.
Constraints that are user assigned are considered fixed and display in a different color.
Placement constraints imported from ISE are considered “unfixed.” You can set placement
constraints to fixed using the Fix Instances popup menu command.
PlanAhead exports fixed constraints are by default to the ISE Implementation tools to lock
the placement. The Tools > Export Constraints and Tools > Export Pblocks dialog boxes
have a switch to enable exporting both fixed and unfixed placement constraints.

Understanding Site and BEL Level Constraints

Site constraints result in a LOC constraint being assigned to the instance. The logic element
is locked to the CLB SLICE site only, and not to any specific gate. The following is an
example code snippet:
INST “receiver/uartInst/G_98_1” LOC = SLICE_X49Y69;
BEL constraints result in a LOC constraint and a BEL constraint being assigned to the
instance in the saved and exported UCF files. BEL constraints will assign a logic element to
a specific gate within the CLB, as shown in the following example code snippets:
INST “channel/receiveRE[8]” BEL = FFX;
INST “channel/receiveRE[8]” LOC = SLICE_X59Y2;

Assigning Site Location Placement Constraints (LOCs)

You can place a leaf-level primitive instance such as a LUT, BRAM or Flip-Flop into a
specific device resource site by dragging it from the netlist tree and dropping it into a
specific site. When you place instances into sites, PlanAhead adds Instance LOCs to the
exported UCF files for ISE. The locations are assigned as fixed and locked during
subsequent ISE attempts.
To place a primitive instance into a device site, click the Create Site Constraint Mode
toolbar button, shown in Figure 11-24, then click and drag instances from the Netlist view
into desired sites in the Device view.

Figure 11-24: Create Site Constraint Mode Toolbar Button

The dynamic cursor does not allow instance placement to an illegal site, or a site that is
already occupied. A legal placement site is indicated when the dynamic cursor changes
from a slashed circle to an arrow or diamond.

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The dynamic cursor does not allow instances to be placed if the SLICE will be over-packed
with logic. Certain logic groups, such as carry-chain logic, move as a single object, which
requires open placement sites for all logic on the carry chain.
After location constraint assignment is complete, return to the default Assign instance to
Pblock mode by clicking the Assign Instance Mode toolbar button as shown in
Figure 11-25.

Figure 11-25: Assign Instance Mode Toolbar Button

To view location constraint properties, select the placement constraint, and view the
Instance Property view.

Assigning BEL Placement Constraints (BELs)

A leaf-level primitive instance can be placed into a specific device gate site by dragging it
from the netlist tree and dropping it onto a specific BEL site. See Appendix B, PlanAhead
Terminology for a description of leaf-level primitives.
Placing instances into gates assigns BEL constraints for ISE. The assigned locations are
assigned as fixed and locked during subsequent ISE attempts.
To create a BEL constraint, click the Create BEL Constraint Mode toolbar button shown in
Figure 11-26, then click and drag instances from the Netlist view onto desired BEL sites in
the Device view.

Figure 11-26: Create BEL Constraint Mode Toolbar Button

The dynamic cursor will not allow instance placement to an illegal or already occupied
gate site. A legal placement site is indicated when the dynamic cursor changes from a
slashed circle to an arrow. The dynamic cursor does not allow instances to be placed if the
SLICE will be over-packed with logic.
After location constraint assignment is complete, return to the default Assign instance to
Pblock mode by clicking the Assign Instance Mode toolbar button, as shown in
Figure 11-27.

Figure 11-27: Assign Instance Mode Toolbar Button

To view location constraint properties, select the placement constraint, and view the
Instance Property view.

Adjusting the Visibility of Placement Constraints

To change how assigned placement constraints display, you can adjust the zoom level.
• From a zoomed out view, the LOCs and BELs display as a filled in rectangle inside the
assigned site.
• When the zoom level increases, the logic displays as being assigned to specific logic
gates within the site.

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Figure 11-28 shows a zoomed-out Device view.

Figure 11-28: Zoomed Out Device View

To display or hide the location constraints, click the Show/Hide LOC Constraints toolbar
button, as shown in Figure 11-29.

Figure 11-29: Show/Hide LOC Constraints Toolbar Button

To adjust other display characteristics for the LOC and BEL constraints:
1. Select Tools > Options > Themes > Device.
The Device dialog box displays.
2. Adjust values in the display, select columns or adjust the colors in the Frame Color and
Fill Color columns.
Fixed and Unfixed placement constraints have individual color and selection controls.

Moving Placement Constraints

To move placement constraints:
1. Select a placement constraint by clicking on the Instance in the Device view, Netlist
view or Schematic view.
2. Drag and drop the selected placement constraint to another legal site.

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The primitive instance is assigned to the new site. You can display Net flight lines from
the location constraint to connected placed logic or Pblocks.
Moving a combinational logic object such as a MUX or a Carry Chain results in the
entire group of LOCs being selected for move. The cursor indicates legal placement
sites for the entire group and PlanAhead moves all objects to new relative locations.
You can assign all logic to sites outside of the Pblock rectangle. This allows flexibility
when locking placement for of logic elements, such as RAMs and DSPs.
3. After location constraint assignment is complete, return to the default Assign Instance
to Pblock mode by clicking the Assign Instance Mode toolbar button, as shown in
Figure 11-30.

Figure 11-30: Assign Instance Mode Toolbar Button

To view location constraint properties, select the placement constraint, and view the
Instance Property view.

Swapping Placement Locations

You can select two placed components and swap their locations with each other. To swap
locations:
1. Select two component instances from any of the available views. Hold down the Ctrl
key while clicking to select multiple ports.
2. Right-click and select Swap Locations.
If you swap two components which are not yet fixed, the act of swapping them will also
cause them to be fixed and the resultant constraint will be written to the design constraint
file.

Deleting Selected Placement Constraints

Selected instance location constraints can be deleted by selecting the placed instances, and
using one of the following methods:
• Select Tools > Clear Placement Constraints. The following section, “Selectively
Clearing Placement Constraints,” describes how to clear placement constraints.
• Click the Unplace popup menu command.

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Selectively Clearing Placement Constraints

You can selectively remove instance location constraints, I/O Port placements, or both
from the design. You can filter the type of constraints you want to clear based on ISE
assigned selected logic, or Pblocks and specific logic types.
Preselected objects dictate the behavior of the Clear Placement Constraints wizard.
• If Pblocks are pre-selected, the wizard displays default settings to clear placement
constraints inside of those Pblocks.
• If Instances are selected, the wizard displays default settings to remove those
instances.
To clear placement constraint assignments:
1. Select Tools > Clear Placement.
The Clear Placement Constraints wizard displays.
2. In the Clear Placement Constraints wizard, specify the type of placement constraints to
remove: Instance placement, I/O Port placement, or both, and click Next.

Unplacing Instances and I/O Ports

The next dialog box changes based upon what types of objects were selected prior to
invoking the command:
• If a Pblock is selected, it defaults to clear the contents of the Pblock.
• If instances are selected, it defaults to remove them.
Additional options are presented depending on the preselected set.
3. In the Unplace Instances page, select the category of instances to be unplaced.
4. Click Next.
The Clear Placement Constraints wizard opens and provides a mechanism to filter the
types of placement constraints to unplace:
- Instance placement
- I/O Port placement
- Both
5. In the Unplace Instances: Types to Unplace page, select the Primitive Types checkbox
that you want to unplace.
6. Click Next.
The appropriate dialog box opens.
- In the Fixed Placement dialog box, specify whether to unplace the fixed
instance(s). Fixed instances are those you placed or “fixed” in your design, or
those you imported using the input UCF file(s).
- In the Unplace Ports dialog box, select the category of I/O ports to be unplaced.
7. Click Next.
8. Verify the contents of the Summary page, and click Finish.
The specified primitive instance assignments are removed from the design, and additional
options are presented depending on the preselected set.

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9. Click Next, verify the contents of the Summary page, and click Finish.
- The specified I/O ports assignments or instances are removed from the design.
- Previously assigned ports are not cleared prior to reading a new UCF file.
- New port assignments write over previous assignments.
Note: A best practice is to first clear all port assignments prior to importing new port assignment
constraints.

Moving Pblocks with Placement Constraints Assigned

You can move a Pblock with location constraints assigned. All placement constraints are
reassigned relative to the new location.
Pblocks behave differently when location placement constraints are assigned inside of
them. The destination location should contain adequate resources to assign the placement
constraints. The cursor indicates legal placement sites as the Pblock is being dragged.
If there are not adequate resources, a dialog box displays, prompting you to either remove
or leave the location constraints intact.
The Choose LOC mode dialog box, shown in Figure 11-31, lists Fixed and Unfixed
locations separately, which enables you to handle them differently.

Figure 11-31: Choose LOC Mode Dialog Box

Locking Placement During ISE Implementation

Placement constraints assigned in PlanAhead are designated as fixed, and when exported
they result in the locked placement during subsequent exported ISE attempts.
PlanAhead provides several ways to select constraints. The Find and Select Primitives
command are two ways to selectively fix (place) logic objects.
For more information, refer to Searching for Objects using the Find Command, page 281
and Using the Select Primitives and Highlight Primitives Commands, page 281.
Use the Fix Instances popup commands to fix selected logic.

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Setting Placement Prohibit Constraints

You can create a prohibit constraint for any logic site on the device. To do so:
1. Select the sites in the Device view.
You can use Select Area to select more than one site, as described in Using the Select
Area Command in Chapter 4.
2. Select the Set Prohibit popup menu command.
The prohibited sites display a red X, shown in Figure 11-32.

Figure 11-32: Prohibited Sites in the Device View

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Interfacing with ISE Outside of PlanAhead

The PlanAhead software lets you selectively export files required for external ISE software
Implementation. If you are using PlanAhead for design Implementation, you do not need
to export files, since all Implementation is done within PlanAhead rather than external to
PlanAhead.
PlanAhead also enables the creation of a project based on existing command line-based
Implementation results. For more information. see Importing ISE Results From Outside
PlanAhead, page 275 for more information about this feature.

Exporting Constraints
Exporting constraints to ISE consists of exporting a UCF constraints file for the entire
design or for individual Pblocks.
To export the constraints:
1. In the Sources view, select the desired constraint set to export and use the Make Active
popup menu command to set it as the active constraint set.
2. Select File > Export Constraints.
The Export Constraints dialog box opens.
3. Edit the definable options in the Export Constraints dialog box:
- File name—Enter the file name and location to create the UCF format constraints
file.
- Export fixed location constraints only—Select this option to export only the user
assigned “fixed” placement LOC constraints or uncheck it to export all of the
fixed and unfixed placement constraints imported from ISE.
4. Click OK to export the constraints.
PlanAhead creates the designated top-level UCF format constraint file in the export
directory. This file can be used as input for custom ISE Implementation scripts.
For more information about the exported files, see Appendix A, “Outputs for Reports.”

Exporting Netlist
Exporting the PlanAhead Netlist to ISE consists of exporting a single EDIF format netlist
file for the entire design or for individual Pblocks.
To export the design netlist:
1. Click the Floorplan tab.
2. Select File > Export Netlist. The Export Netlist dialog box opens.
3. Edit the File name and location to create the EDIF format netlist file in the Export
Netlist dialog box:
4. Click OK to export the netlist.
For more information about the exported files, see Appendix A, “Outputs for Reports.”

Exporting Pblocks for ISE Implementation

PlanAhead has the ability to export Pblock-level files for Implementation. These Pblocks
consist of logic from anywhere in the logic hierarchy. Exporting a Pblock creates an EDIF
netlist and UCF physical constraints file for each Pblock selected for export.

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To export Pblocks to EDIF and UCF:

1. Select one or more Pblocks.
2. Select File > Export Pblocks. The Export Pblocks wizard opens as shown in
Figure 11-33.

Figure 11-33: Export Pblocks Wizard

3. Edit the definable options in the Export Pblocks dialog box:

- Directory name—Enter the directory name or use the file browser to select a
directory to export the files. PlanAhead creates a subdirectory called
pblockname_CV for each exported Pblocks.
To keep track of EDIF and UCF files associated with a typical PlanAhead design
scenario, it is a good practice to specify a unique directory name for each ISE
attempt. The export directory is used to seed the Import Placement and Import
TRACE Results command file browsers.
- File types to generate
- Netlist (EDIF)—Select this option to export the netlist.
- Constraints (UCF)—Select this option to export all or only fixed placement
constraints.
- Pblocks—Lists the Pblocks selected for export.
4. Click the Add and Clear buttons to select and remove Pblocks from the export list,
respectively.
5. Click Next or Finish to continue. When Next is chosen, the Export Pblocks Summary
dialog box displays Pblock export selections.
6. Click Finish to perform the export.
The PlanAhead software creates separate EDIF and UCF files for each of the exported
Pblocks named pblockname_CV.edn and pblockname_CV.ucf.
PlanAhead creates a /pblockname_CV directory for each exported Pblock containing the
Pblock-specific files.

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Programming and Debugging the Design

This chapter contains the following sections:
• Generating Bitstream Files
• Debugging the Design with ChipScope
• Launching ChipScope Pro Analyzer
• Launching iMPACT

Generating Bitstream Files

Once an Implementation has completed successfully, you can run the ISE bitgen
command on the results to create the bitstream data. To do so:
1. In the Flow Navigator, click the Program and Debug Flow button and, from the popup
menu, click Generate Bitstream. Figure 12-1 shows the command.
.

Figure 12-1: Running the Generate Bitstream Command

The Generate Bitstream dialog box opens as shown in Figure 12-2, page 318.

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Figure 12-2: Setting Bitgen Options

You can set the ISE Bitgen command options prior to running the command.When you
select an option, a description of the option displays in the dialog box. A pulldown
menu of the available options values shows on the right side.
2. Click OK to start the Bitgen command.
You can view the command status in the Compilation Log and Compilation Messages
views and the Bitgen report file in the Reports view after it completes.
PlanAhead generated the resulting bit file in the project Run directory.

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Debugging the Design with ChipScope

The PlanAhead™ software is integrated with the ChipScope™ Pro debug software.
The ChipScope Pro integration provides simplified post-Synthesis insertion and
connection of the ChipScope Pro Integrated Logic Analyzer (ILA) debug cores in the
PlanAhead tool.

Overview of ChipScope Integration in PlanAhead

PlanAhead provides a GUI wizard for quick and easy design debug for most situations. A
non-wizard GUI and Tcl command flow are available for precision debug core and net
connection control. This flow provides a robust ILA core connection solution without
leaving the PlanAhead tool. Figure 12-3 illustrates the debug core integration.

User’s Design Logic

User’s Design Logic

PlanAhead / Chipscope
Core Insertion

ChipScope
ILA Debug
Cores
X11123

Figure 12-3: Block Diagram of PlanAhead/ChipScope Integration

Requirements and Limitations When Using Core Insertion Flow

To use the ChipScope integration features in PlanAhead, you must have Xilinx® ISE®
Design Suite 12.x tools, including ChipScope Pro and PlanAhead, installed. To perform
runtime design debugging you must also have the Xilinx Platform USB cable. For more
information about ChipScope Pro, see
http://www.xilinx.com/support/documentation/dt_chipscopepro.htm.

Limitations of the PlanAhead/ChipScope integration are as follows:

• PlanAhead 12, ISE 12, and ChipScope Pro 12 tools must be used with this flow. Mixing
and matching tool versions is not supported.
• This flow is not available with the Project Navigator or the ChipScope Pro Core
Inserter flow. However, you can import ChipScope Debug Cores (CDC) into
PlanAhead.
• This flow is not available when in ISE Integration mode, refer to Integration
Overview, page 351 for more information.
• You can view, but not change, pre-existing debug cores connected to a ChipScope Pro
Integrated CONtroller (ICON) core.

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• This flow is not compatible with a pre-existing ICON core generated without a
BSCAN primitive that requires connection to a BSCAN primitive instantiated outside
of the core.
• Because the PlanAhead tool adds debug cores to the post-Synthesis design netlist,
some nets might be unavailable for debugging due to trimming or other optimization
that takes place during the Synthesis process.
• Only ChipScope Pro ILA cores can be created and connected using this flow.

Using the Core Insertion Flow

Insertion of ChipScope debug core in the PlanAhead tool is presented in a layered
approach to address different needs of the diverse group of PlanAhead users:
• The highest level is a simple GUI wizard that creates and configures ILA cores
automatically based on the selected set of nets to debug.
• The next level is the main ChipScope view allowing control over individual cores,
ports and their parameters.
• The lowest level is the set of Tcl debug commands that you can enter manually or
replay as a script for ultimate control.
You can use a combination of the modes to insert and customize debug cores also.
Figure 12-4 illustrates the levels of debug core insertion.

ChipScope Fast and simple

Wizard

ChipScope Window
in Main PlanAhead GUI

Precise control
ChipScope Tcl debug commands

X11122

Figure 12-4: Debug Core Insertion Modes

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Deciding Which Debug Core Insertion Mode to Use

The following table summarizes how to decide what insertion mode(s) to use based on the
debugging goal.

Table 12-1: Debugging Goals and Core Insertion Modes

Debugging Goal Core Insertion Mode
Quickly create ILA debug core(s) with default settings for the ChipScope Wizard
selected nets.
Change parameters on existing debug cores. ChipScope Window
Manually create or delete existing debug cores. ChipScope Window
Manually create, delete, or configure trigger or data ports on an ChipScope Window
ILA core.
Manually assign nets to the trigger/data/clock channels. ChipScope Window
Play back a recorded script of debug commands later. Tcl Commands

Selecting Nets for Debug

The first step in the PlanAhead/ChipScope debug flow is to identify the set of netlists to
debug.
All ChipScope debug core insertion and configuration operations must be performed in
the Netlist Design because you must add the cores to the netlist prior to Implementation.
For more information on using the Netlist Design environment see Using the Netlist
Design Environment, page 162.
PlanAhead lets you make debug net selection by picking a set of nets or buses in the Netlist
view, and selecting the Add to ChipScope Unassigned Nets popup command. You can
perform net selection by selecting nets or busses in any view including the Schematic view.
There is also a net selector built into the Setup ChipScope wizard.

Using the Unassigned Nets List

PlanAhead maintains an Unassigned Nets list (shown in the following figure) in the
ChipScope view (Window > ChipScope). The Unassigned Nets list is a convenient place to
bookmark nets of interest while browsing the design.
You can store nets for later debug by dragging and dropping from the netlist or schematic
view into the Unassigned Nets list.
Also, you can add nets to the Unassigned Nets list by selecting the nets, and selecting the
Add to ChipScope Unassigned Nets popup menu command, which is shown in
Figure 12-5, page 322.

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Figure 12-5: Unassigned Nets List in ChipScope Window

Using the ChipScope Wizard for Debug Core Insertion

The ChipScope debug wizard is the easiest and fastest way to add debug cores in the
PlanAhead design tool.
To use the Set Up ChipScope wizard to insert debug cores:
1. Optionally, select a set of nets for debug either using the unassigned nets list or direct
net selection.
2. In the Flow Navigator, invoke the Set Up ChipScope wizard from the Netlist Design
menu, or click Tools > Set Up ChipScope. Figure 12-6 shows where to launch the
ChipScope wizard.

Figure 12-6: Launching the Set up ChipScope Wizard

3. Follow the instructions screen-by-screen to connect and configure the debug cores.

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Importing a ChipScope CDC File

The Set Up ChipScope wizard lets you add an existing ChipScope Debug Core (CDC) file
to the project.
When you click the Set up ChipScope box, a wizard pane prompts you to select the CDC
file.
Select the CDC file, and click Next.
Note: Not all ChipScope cores are importable. CDC files originating from the ChipScope Core
Inserter or PlanAhead contain the required core information required for import.

Selecting or Confirming Debug Nets

If nets have been added to the Unassigned Nets list, you are prompted to use them or to
select new nets. PlanAhead invokes an Add/Remove Nets dialog box to search for and
select nets to debug.
Add or remove nets as needed, and click Next.

Specifying Debug Nets and Clock Domains

The ChipScope wizard attempts to detect the correct clock automatically for each selected
net or bus as shown in Figure 12-7, page 323.

Figure 12-7: Specifying Debug Nets and Clock Domains

If multiple clocks are detected for a given net, a dropdown list allows the selection of
different clocks for the net or bus.
1. To modify the debug net selection further, click the Add/Remove Nets button.
2. Configure each net or bus for use as a trigger, data storage, or both.
3. When the net and clock configuration is correct, click Next to proceed to the summary
screen.
If ILA cores exist in the design, you are prompted to remove them and regenerate
based on the new information or to keep them intact and generate new cores.

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Inserting ILA Cores

The ChipScope wizard inserts one ILA core per clock domain.
The nets that were selected for debug are assigned automatically to the trigger and data
ports of the instantiated ILA cores.
The last wizard screen shows the core creation summary displaying the number of clocks
found and ILA cores to be created and/or removed.
If you are satisfied with the results, click Finish to instantiate and connect the ILA cores in
the design.

Using the ChipScope Window to Add and Customize Debug Cores

The main ChipScope view provides more fine-grained control over ILA core insertion than
what is available in the ChipScope wizard.
The controls available in this window allow core creation, core deletion, debug net
connection, and core parameter changes.
To bring up the ChipScope view, select Window > ChipScope, shown in Figure 12-8.

Figure 12-8: ChipScope View

The main ChipScope view:

• Shows the list of debug cores that are connected to the ICON controller core.
• Maintains the list of unassigned nets at the bottom of the window.
You can manipulate debug cores and ports from the popup menu or the toolbar buttons on
the top of the view.

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Creating and Removing Debug Cores

You can create ChipScope debug cores in the ChipScope view by clicking the
Create ChipScope Debug Core popup menu command or toolbar button.
Using this interface, you can change the parent instance, debug core name, and set
parameters for the core.
To remove an existing debug core, in the ChipScope view, select the core and select the
Delete popup command.

Adding, Removing, and Customizing Debug Core Ports

In addition to adding and removing debug cores, you can add, remove, and customize
ports of each debug core to suit your debugging needs. To add a new port:
1. Select the core.
2. Click the Create ChipScope Debug Port popup menu command, or toolbar button.
The Create Debug Port dialog box opens, as shown in Figure 12-9.

Figure 12-9: Customizing Ports and Options of Debug Cores

3. Select the port type in the dropdown.

Any configurable options for the port display in the Options area. The port width will
start as a default, but expands or contracts as you add or remove nets from the port.
4. Click OK.
To remove a debug port, in the ChipScope tab select the port, and select Delete from the
popup menu.

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Connecting and Disconnecting Nets to Debug Cores

You can select, and then drag and drop nets and busses (vectors of nets) from the
Schematic view or the Netlist view onto the debug core ports (shown in the following
figure). This expands the port as needed to accommodate the net selection.
Also, you can right-click on any net or bus, and select Assign to ChipScope Debug Port.
To disconnect nets from the debug core port, select the nets that are connected to the debug
core port, and click Disconnect Net from the popup menu. Figure 12-10, page 326
illustrates these activities.

Figure 12-10: Dragging and Dropping Nets onto Debug Core Ports

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Customizing Debug Core and Port Parameters

ChipScope Debug cores have parameters that can be customized.
To access these core parameters:
1. In the ChipScope view, select one of the ChipScope debug cores.
2. In the Properties tab, select Options to configure the core parameters as shown in
Figure 12-11.

Figure 12-11: Debug Core Parameters

You can modify port parameters by first clicking the Trigger or Data port of a debug core,
and selecting Properties > Options, as shown in Figure 12-12, page 328.

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Figure 12-12: Debug Port Parameters

Implementing Debug Cores

The PlanAhead software creates ChipScope Pro ICON and ILA cores initially as black
boxes. These cores must be implemented prior to running through map, place, and route.
ChipScope debug core Implementation is automatic when running the Implementation
flow using the Implement command in the Flow Navigator or Tools menu; however, you
can force debug core Implementation manually for floorplanning or timing analysis by
clicking the Implement toolbar button on the left side of the ChipScope view.
The Xilinx CORE Generator™ tool invokes in batch mode for each black box debug core.
This operation can take some time. A progress dialog box shows that the operation is
running. When the debug core implementation is complete, the debug core black boxes are
resolved and you can access the generated instances.

Exporting Net Connections CDC File for ChipScope Analyzer Tool

A ChipScope Analyzer CDC file is generated automatically when design Implementation
is complete. Also, you can export a CDC file manually from the Export Debug Net Names
popup command in the ChipScope view. You can import this CDC file into the ChipScope
Analyzer to automatically set up the net names on the ILA core data and trigger ports.

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Implementing the Design with the Debug Cores

Once ChipScope debug cores are created and connected, you can run the standard
PlanAhead Implementation flow to create a bitstream for the device.
Start the Implementation flow by selecting the Implement command in the Flow Navigator
or Tools menu.

Launching ChipScope Pro Analyzer

When the ChipScope Pro Analyzer software is installed, you can launch it directly from
PlanAhead on any implemented design on which the Generate Bitstream command has
been run.
To launch ChipScope Pro Analyzer, do one of the following:
• In the Flow Navigator, select Launch ChipScope Analyzer from the Program and
Debug menu.
• In the ChipScope view tab, right-click and select Launch ChipScope Analyzer from
the context menu.
Planahead passes the BIT bitstream and CDC netlist name files automatically to the
ChipScope Pro Analyzer. For more information about ChipScope Pro Analyzer see the
Xilinx website, http://www.xilinx.com/support/documentation/dt_chipscopepro.htm.

Launching iMPACT
The iMPACT tool lets you perform Device Configuration and File Generation.
• Device Configuration lets you directly configure Xilinx FPGAs and PROMs with the
Xilinx cables (Parallel Cable IV, Platform Cable USB, or Platform Cable USB II).
Operating in Boundary-Scan mode, iMPACT can configure or program Xilinx FPGAs,
CPLDs, and PROMs.
• File Generation enables you to create the following programming file types: System
ACE CF, PROM, SVF, STAPL, and XSVF files.
iMPACT also lets you:
• Readback and verify design configuration data
• Debug configuration problems
• Execute SVF and XSVF files
You can launch the iMPACT software tool directly from PlanAhead on any implemented
design on which the Generate Bitstream command has been run. To invoke iMPACT, in
the Flow Navigator, select the Launch iMPACT command from the Program and Debug
menu.
The BIT bitstream file is passed automatically to iMPACT when launched from PlanAhead.
For more information on using iMPACT, see the ISE Help.

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Using Hierarchical Design Techniques

This chapter contains the following sections:
• Understanding PlanAhead and ISE Capabilities
• Using PlanAhead for Design Preservation

Understanding PlanAhead and ISE Capabilities

The PlanAhead™ software has several capabilities to support a hierarchical design
process. Deciding to use such an approach on your design is something that you need to
determine before starting the design. For best results, the decision to use a hierarchical
approach requires some forethought about design partitioning and Register Transfer Logic
(RTL) coding decisions. Results can vary if you start using this methodology late in a
design cycle in an attempt to close timing or reduce run time.
Note: All of the features described in this chapter are available for netlist-based projects only.
PlanAhead does not support RTL-based hierarchical projects using partitions. Each partition requires
a separately synthesized netlist or a netlist with third party Synthesis incremental compile points. This
netlist isolation makes it possible to manage updates and reuse partitions.

Using Partitions
The hierarchical capabilities all revolve around setting and managing hierarchical
boundaries in the design called partitions. These boundaries prevent the Synthesis and
Implementation tools from optimizing the logic across the boundaries making it possible
to isolate the logic for reuse.
Effective partitioning relies on good logic design practices and knowledge of the design.
These practices are detailed in the Hierarchical Design Methodology Guide (UG748).
After you have implemented designs with partitions, you can export the results for use in
future runs. The partition definition and behavior is defined in an XML file called
xpartitions.pxml. The ISE® Design Suite tools search the Run directory for that file and
act accordingly. Partitions are defined as well as the specified partition “action” such as
Implement or Import. The Hierarchical Design Methodology Guide (UG748) describes the
xpartitions.pxml file usage and syntax.

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Design Preservation
The PlanAhead project structure lets you create and manage projects from hierarchical
netlist sources. This bottom-up Synthesis approach lets you selectively update modules
while keeping the rest of the design intact.
PlanAhead, coupled with the ISE partition features, can then lock the placement and
routing of selected partitions for subsequent runs.
This incremental design approach can help produce more consistent Implementation
results, reduce verification time, and reduce design closure time. This capability is called
Design Preservation, which is the ability to implement and lock specific modules of a single
design for subsequent runs.

Partial Reconfiguration
PlanAhead provides an environment to configure, implement and manage Partial
Reconfiguration projects. PlanAhead uses the partitions and Partial Reconfiguration
capabilities that are built into the ISE Design Suite Implementation tools.

Hierarchical Design Documentation

For more information about Hierarchical Design techniques, refer to
Hierarchical Design Methodology Guide (UG748) and the
Partial Reconfiguration User Guide (UG702).
Partial Reconfiguration documentation is located at:
http://www.xilinx.com/tools/partial-reconfiguration
The following tutorial documents are available at
http://www.xilinx.com/sw_manuals/xilinx12_4/tutorials.htm:
• PlanAhead Tutorial: Leveraging Design Preservation for Predictable Results (UG747)
• PlanAhead Tutorial: Partial Reconfiguration Flow Overview (UG743)
• PlanAhead Tutorial: Partial Reconfiguration with Processor Peripherals (UG744)
Licenses can be obtained through the Xilinx® website at:
http://www.xilinx.com/getproduct

Using PlanAhead for Design Preservation

The following subsections describe the features that are available to you when you use the
Design Preservation features from PlanAhead:
• Setting Partitions
• Configuring Runs for Partitions
• Promoting Partitions
• Importing Partitions

Setting Partitions
You can set partitions on any hierarchical design module in the netlist. Design Preservation
requires that you define the partitions on the same logic modules that were synthesized
separately. This will ensure the netlists and the partitions can be isolated and reused.

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Note: PlanAhead supports netlist-based projects only for hierarchical design capabilities. The
Partition commands will not be displayed in RTL-based projects.
To set a partition:
1. In the Netlist view, select the module instances on which to set partitions.
2. Select the Set Partition popup menu command.
3. The instance receives a new icon in the Netlist view and a Partitions tab in the Instance
Properties view as shown in Figure 13-1.

Figure 13-1: Setting Partitions in the Netlist View

Once a partition has been set in the project, the rest of the design becomes a partition
automatically also. You can promote or import this “top” partition to preserve it if it
remains unchanged during a design revision.

Viewing Partition Properties

You can access the Instance Partition Properties by selecting the Partition Instance and
viewing the Instance Properties view. Select the Partition tab in the Instance Properties
view as shown in the previous figure.
The view contains the locations and dates of each time the Partition was promoted.

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Configuring Runs for Partitions

You can configure partition “Action” settings for each Implementation run launched from
PlanAhead. You need to determine whether each partition is implemented or imported
and if imported, from where. PlanAhead attempts to set the appropriate action based on
recent promotions. Check to ensure the partition actions are set correctly before each run is
launched.
To set a partition action:
1. In the Flow Navigator, select the drop down menu on the right side of the Implement
button, and select Implementation Settings as shown in Figure 13-2.

Figure 13-2: Implementation Settings

The Implementation Settings dialog box lets you configure the launch options for the
run. The Specify Partitions field displays the current action set on the partitions.
2. Select the browser button on the Specify Partitions field as shown in Figure 13-3.

Figure 13-3: Implementation Settings Dialog Box

In the Specify Partition dialog box, shown in Figure 13-4, page 335, you can set the
Action for each Partition to either Implement or Import.

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The first time a design is implemented, all partitions must be set to Implement, because
there are no promoted locations to import the implemented partitions.

Figure 13-4: Specify Partitions Dialog Box

3. Set the partition action as follows:

- If you are importing partitions, browse to select the Import from directory, and
click OK.
- In the Implementation Settings dialog box, select Run to launch the
Implementation run with the new Partitions Action settings.
- Monitor the ISE command status in the Compilation Log view.
4. Once the ISE ngdbuild command completes, review the NGDBuild report by
selecting it from the Reports view, shown in Figure 13-5. The actions taken for the
partitions in the run display in the NGDBuild report.

Figure 13-5: Viewing Partition Actions in NGDBuild Report

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Promoting Partitions
Once satisfactory Implementation results are achieved, you can copy the ISE result files to
a repository area for future import operations. This process is called “Promoting” the
partitions. You can only promote partitions from successfully implemented runs in
PlanAhead.
To promote partitions:
1. In the Flow Navigator, select Promote Partitions. The Promote Partition dialog box
opens, as shown in Figure 13-6.

Figure 13-6: Promoting Partitions

The Promote Partitions dialog box lets you define the partitions to promote. By
default, all partitions are selected for promote; the top-level of the design is not
selected for promote.
2. Accept the defaults values in the dialog box or select the partitions to promote.
3. Optionally, enter a description in the Description field.
4. Click OK.
The Promoted Partitions view opens.
Note: It is recommended that you promote and Import all partitions to a single location. The default
is to use the same promote directory. PlanAhead prompts you to overwrite the previously promoted
directory in an attempt to enforce this methodology. For more information, refer to the Hierarchical
Design Methodology Guide (UG748).
Once a partition is promoted, the default partition action setting for the next
Implementation run is set to import.

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Using the Promoted Partitions View

The Promoted Partitions view displays each time you perform a Promote Partitions
command.
To open the Promoted Partitions view, select Window > Promoted Partitions. Figure 13-7
shows the Promoted Partitions view.

Figure 13-7: Promoted Partitions View

Each promotion displays in a tree table detailing the partitions promoted, the source
Implementation run, the promote date and time, and the description.

Deleting Promoted Partitions

You can remove previously promoted directories to clean up the /Project directories.
The entire promoted directory is removed including all promoted partitions from the run.
To delete promoted directories, select the promoted directory in the Promoted Partitions
view and click the Delete popup menu command.

Importing Partitions
After you have promoted partitions, you can import those partitions for subsequent runs.
Importing partitions results in the placement and routing being copied out of the
promoted partitions run and imported into the new run prior to implementing the rest of
the design, ensuring identical results.

Updating Netlist Sources

As design modifications occur, the updated netlists are either picked up automatically, if
you are using remote sources, or updated in the project to update the existing netlists. Once
the source files are updated you can open or reload the Netlist Design to apply the logic
changes. Refer to Managing the Design Source Files, page 137 for more information.

Setting Partition Actions Based on Logic Updates

You must set the Partition action for each run as described in Configuring Runs for
Partitions, page 334.
• Partitions with updated netlists must be set to Implement to ensure that the logic is re-
implemented with the changes.
• Unchanged partitions must be set to Import for results to be preserved.

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PlanAhead sets the Partition actions automatically to Import for any promoted partitions
and selects the most recent promoted directory from which to import. PlanAhead does not
track logic updates or set the appropriate partitions to Implement.
Figure 13-8 shows the Specify Partitions dialog box.

Figure 13-8: Importing Partitions

The ISE NGDBuild report provides information about the Partition actions for each run. To
access the report, select the Reports view tab and open the NGDBuild report. Figure 13-9
shows the Partition activity in an NGDBuild report.

Figure 13-9: Partition Import Activity in the NGDBuild Report

Successfully preserved partitions are copied from the promoted area and pasted into the
new run. This should provide identical results for imported partitions.
For more information about Design Preservation methodologies, refer to the
Hierarchical Design Methodology Guide (UG748) and the
PlanAhead Tutorial: Leveraging Design Preservation for Predictable Results (UG747).

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Tcl and Batch Scripting

This chapter contains the following sections:
• Overview of Tcl Capabilities in PlanAhead
• Invoking PlanAhead
• General Tcl Syntax Guidelines
• First Class Tcl Objects and Relationships
• Errors, Warnings, and Info Messages
• Tcl Commands
• Tcl References

Overview of Tcl Capabilities in PlanAhead

The Tool Command Language (Tcl) is the scripting language integrated in the
PlanAhead™ software environment. Tcl is a standard language in the semiconductor
industry for design constraints and Synopsys® Design Constraints (SDC).
SDC is the mechanism for communicating timing constraints for FPGA Synthesis tools
from Synopsys Synplify as well as other vendors, and is a timing constraint industry
standard; consequently, the Tcl infrastructure is a “Best Practice” for scripting language.
Tcl lets you perform interactive queries to design tools in addition to executing automated
scripts. Tcl offers the ability to “ask” questions interactively of design databases,
particularly around tool and design settings and state. Examples are: querying specific
timing analysis reporting commands live, applying incremental constraints, and
performing queries immediately after to verify expected behavior without re-running any
tool steps.
The following sections describe some of the basic capabilities of Tcl with PlanAhead.
Note: This chapter is not a comprehensive reference to Tcl commands. This chapter does provide
references to Tcl resources, and describes the general capabilities of Tcl in the PlanAhead
environment.

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Tcl in Journal Files

When you invoke the PlanAhead software, it creates two files that maintain a log of the
operations performed either in the GUI or in batch mode:
• PlanAhead.log
• PlanAhead.jou
You can copy Tcl commands from the log files for use either in the Tcl command window or
in a batch file.
Refer to Appendix A, PlanAhead Input and Output Files for information regarding the file
locations.

Tcl Help
The Tcl help command provides an overview of the available, supported Tcl commands.
The help command with no arguments provides a list of all commands. You can pass a
specific command to the help command as an argument, for example:
help get_cells
The Tcl help then prints the specific command information to both the console and the log
file. Additionally, a global –help option is implemented that returns help syntax; for
example:
get_cells –help

Tcl Console
The PlanAhead GUI environment contains an area that echoes the Tcl commands as
operations are performed, and provides information, warnings, and error messages that
result from tasks performed. The Tcl Console is located along the bottom of the PlanAhead
environment and fixed to the width of the GUI. Along the right side of the Tcl console, just
to the right of the scrollbar is an area with color coded indicators for warnings and errors.
Any warnings issued to the console are colored yellow and errors are marked red. This is
a very useful feature to scroll back through message history and quickly navigate to view
warnings and errors in the context of the command that was performed. Figure 14-1 shows
the Tcl Console within the environment:

Figure 14-1: Tcl Console

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Invoking PlanAhead
PlanAhead provides three primary modes of operation:
• The GUI mode (default)
• Invocation of the PlanAhead executable by a Tcl command-line option (Batch mode)
• Tcl shell mode
The following subsections describe Batch and Tcl shell modes.

Batch Mode
Batch mode executes a script and then shuts down the tool. To invoke PlanAhead in
batch mode:
planAhead –mode batch –source script_name.tcl

Tcl Shell Mode

Tcl mode invokes a shell similar to windows command shell or a linux shell. This is an
interactive shell session that does not invoke the GUI.
Optionally, you can pass a script with the –source switch, which executes the script and
then passes the control to the interactive shell where you can manually enter Tcl
commands. To launch PlanAhead in Tcl shell mode:
PlanAhead –mode tcl –source script_name.tcl

General Tcl Syntax Guidelines

Tcl uses the Linux file separator (/) convention regardless of the OS on which you are
operating.
The following subsections describe the general syntax guidelines for using Tcl in
PlanAhead.

Sourcing a Tcl Script

You can source a Tcl script from a command-line option:
source -file_name
Within the PlanAhead GUI you can source a Tcl script from Tools > Run Tcl Script.

General Syntax Structure

The general structure of the PlanAhead Tcl commands is:
command [optional_parameters] required_parameters
Command syntax is of the verb-noun and verb-adjective-noun structure separated by the
underscore (“_”) character.
Commands are grouped together with common prefixes when they are related.
• Commands that query things are generally prefixed with get_.
• Commands that set a value or a parameter are prefixed with set_.
• Commands that generate reports are prefixed with report_.

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The commands are exposed in the global namespace, which means the commands do not
need to be qualified with hdi:: as in previous versions of PlanAhead. Commands are
“flattened,” meaning there are no “sub-commands” for a command.

Example Syntax
The following is an example of the return format on the get_cells -help command:
get_cells -help
Description:
Get a list of cells in the current design
Syntax:
get_cells [-hierarchical] [-regexp] [-nocase] [-filter arg] [-
of_objects args] [-quiet] [patterns...]
Returns:
list of cell objects
Usage:
Name Optional Default Description

-hierarchical yes false Search level-by-level in current

instance

-regexp yes false Patterns are full regular

expressions
-nocase yes false Perform case-insensitive
matching

-filter yes Filter list with expression

-of_objects yes Get cells of these pins or nets

-quiet yes false Ignore command errors

patterns yes * Match cell names against

patterns

Unknown Commands
Tcl contains a list of built-in commands that are generally supported by the language,
PlanAhead-specific commands which are exposed to the Tcl interpreter, and user-defined
procedures.
Commands that do not match any of these known commands are sent to the OS for
execution in the shell from the exec command. This allows users to execute shell
commands that may or may not be OS-specific. If there is no shell command, then an error
message is issued to indicate that no command was found.

Return Codes
Some commands are expected to provide a return value, such as a list or collection of
objects on which to operate. Other commands perform an action but do not necessarily
return a value that can be used directly by the user. Some tools that integrate Tcl interfaces
return a “0” or a “1” to indicate success or error conditions in the command, but this is not
reliable combined with commands that returns lists of objects.
To test if a command successfully executed, use the Tcl built-in command catch.

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All PlanAhead commands return TCL_OK and TCL_ERROR, and $ERRORINFO through
the standard Tcl mechanisms which makes the catch command the most robust mechanism
for trapping errors in Tcl scripts. These values will not be returned and set to variables in
the interpreter, nor do the commands return a 0 or 1 in log files upon success or failure of
a given command. Generally, the catch command and the presence of numbered
info/warning/error messages should be relied upon to asses issues in Tcl scripted flows.

Sourcing a Tcl Script

A Tcl script can be sourced from either one of the command-line options or from the GUI
using the File > pulldown. Once a Tcl script is invoked from the GUI, a progress bar dialog
box displays and all operations in the GUI are blocked until the scripts completes.
Currently, there is no way to interrupt script execution during runtime; consequently,
standard OS methods of killing a process must be used to force interruption of the tool. If
the PlanAhead process is killed, you will lose all work since the last time you saved the
project.

First Class Tcl Objects and Relationships

PlanAhead Tcl provides direct access to the object models for netlist, devices, and projects.
These objects are first-class which means they are more than just a string representation,
and they can be operated on and queried. There are a few exceptions to this rule, but
generally “things” can be queried as objects, and these objects have properties that can be
queried and they have relationships that allow you to get to other objects.

Object Types and Definitions

There are many object types in PlanAhead; this chapter provides definitions and
explanations of the basic types. The most basic and important object types are associated
with entities in a design netlist, and these types are listed in the following subsections:

Cell
A cell is an instance, either primitive or hierarchical inside a netlist. Examples of cells
include flip-flops, LUTs, I/O buffers, RAM and DSPs, as well as hierarchical instances
which are wrappers for other collections of cells.

Pin
A pin is a point of logical connectivity on a cell. A pin allows the internals of a cell to be
abstracted away and simplified for easier use, and can either be on hierarchical or
primitive cells. Examples of pins include clock, data, reset, and output pins of a flop.

Port
A port is a special type of hierarchical pin, a pin on the top level netlist object, module or
entity. Ports are normally attached to IO pads and connect externally to the FPGA device.

Net
A net is a wire or collection of wires that eventually be physically connected directly
together. Nets can be hierarchical or flat, but will always short together a collection of pins.

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Clock
A clock is a periodic signal that propagates to sequential logic within a design. Clocks can
be primary clock domains or generated by clock primitives such as a DCM, PLL, or
MMCM. A clock is the rough equivalent to a TIMESPEC PERIOD constraint in UCF and
forms the basis of static timing analysis algorithms.

Querying Objects
All first class objects can be queried by a get_ Tcl command that generally has the
following syntax:
get_object_type pattern
Where pattern is a search pattern, which includes if applicable a hierarchy separator to get
a fully qualified name. Objects are generally queried by a string pattern match applied at
each level of the hierarchy, and the search pattern also supports wildcard style search
patterns to make it easier to find objects, for example:
get_cells */inst_1
This command will search for a cell named inst_1 within the first level of hierarchy
below the top level of hierarchy. To recursively search for a pattern at every level of
hierarchy, use the following syntax:
get_cells –hierarchical inst_1
This command searches every level of hierarchy for any instances that match inst_1.
For complete coverage of syntax, see the specific online help for the individual command:
help get_cells
get_cells -help

Object Properties
Objects have properties that can be queried. Property names are unique for any given
object type. To query a specific property for an object, the following command is provided:
get_property property_name object
An example would be the lib_cell property on cell objects, which tells you what Unisim
component a given instance is mapped to:
get_property lib_cell [get_cell inst_1]
To discover all of the available properties for a given object type, use the
report_property command:
report_property [get_cells inst_1]

Key Value Type

bel OLOGICE1.OUTFF string
class cell string
iob TRUE string
is_blackbox 0 bool
is_fixed 0 bool

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Key Value Type

is_partition 0 bool
is_primitive 1 bool
is_reconfigurable 0 bool
is_sequential 1 bool
lib_cell FD string
loc OLOGIC_X1Y27 string
name error string
primitive_group FD_LD string
primitive_subgroup flop string
site OLOGIC_X1Y27 string
type FD & LD string
XSTLIB 1 bool

Some properties are read-only and some are user-settable. Properties that map to attributes
that can be annotated in UCF or in HDL are generally user-settable through Tcl with the
set_property command:
set_property loc OLOGIC_X1Y27 [get_cell inst_1]

Filtering Based on Properties

The object query get_* commands have a common option to filter the query based on
any property value attached to the object. This is a powerful capability for the object query
commands. For example, to query all cells of primitive type FD do the following:
get_cells * -hierarchical –filter “lib_cell == FD”
To do more elaborate string filtering, utilize the =~ operator to do string pattern matching.
For example, to query all flip-flop types in the design, do the following:
get_cells * -hierarchical –filter “lib_cell =~ FD*”
Multiple filter properties can be combined with other property filters with logical OR (||)
and AND (&&) operators to make very powerful searches. To query every cell in the
design that if of any flop type and has a placed location constraint:
get_cells * -hierarchical –filter {lib_cell =~ FD* && loc != “”}
Note in the example above, the filter option value was wrapped with curly braces {}
instead of double quotes. This is normal Tcl syntax that prevents command substitution by
the interpreter and allows users to pass the empty string “ ” to the loc property.

Large Lists of Objects – Collections

Commands that return more than one object generally return a container that looks and
behaves like a native Tcl list. This is a feature of PlanAhead in that it allows dramatic
optimization of large collections of Tcl objects handling without the need for special
iteration commands like the foreach_in_collection which is handled with the Tcl
built-in foreach.

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There are a few nuances with respect to large lists, particularly in the log files and the GUI
Tcl console. Typically, when you set a Tcl variable to the result of a get_* command, the
entire list is echoed to the console and to the log file. For large lists, this is truncated when
printed to the console and log to prevent memory overloading of the buffers in the tool.
What is echoed is the list printed to the log and console is truncated and the last element
appears to be “…” in the log and console, however the actual list in the variable
assignment is still correct and the last element is not an error.
An example of this is querying a single cell versus every cell in the design, which can be
large:
get_cells inst_1
inst_1
get_cells * -hierarchical
XST_VCC XST_GND error readIngressFifo wbDataForInputReg fifoSelect_0
fifoSelect_1 fifoSelect_2 fifoSelect_3 ...
%set x [get_cells * -hierarchical]
XST_VCC XST_GND error readIngressFifo wbDataForInputReg fifoSelect_0
fifoSelect_1 fifoSelect_2 fifoSelect_3 ...
%lindex $x end
bftClk_BUFGP/bufg
%llength $x
4454
In this example, all four thousand cells were not printed to the console and the list was
truncated with a “…” but the actual last element of the list is still correct in the Tcl variable.

Object Relationships
Related objects can be queried using the –of option to the relevant get_* command. For
example, to get a list of pins connected to a cell object, do the following:
get_pins –of [get_cells inst_1]
Figure 14-1, page 347 is a diagram of the object types in PlanAhead and their relationship,
where an arrow from one object to another object indicates that you can use the –of option
to the get_* command to traverse logical connectivity and get Tcl references to any
connected object.

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Figure 14-1: PlanAhead Object Relationships

Errors, Warnings, and Info Messages

Messages that result from individual commands appear in the log file as well as in the GUI
console if it is active. These messages are generally numbered to identify specific issues
and are prefixed in the log file with either “INFO”, “WARNING”, or “ERROR” followed by a
subsystem identifier and a unique number.
The following is an example of an INFO message that appears after reading the timing
library.
INFO: [HD-LIB 1] Done reading timing library
These messages make it easier to search for specific issues in the log file to help to
understand the context of operations during command execution.
Generally, when an error occurs in a Tcl command sourced from a Tcl script, further
execution of subsequent commands is halted. This is to prevent unrecoverable error
conditions. There are Tcl built-ins that allow users to intercept these error conditions, and
to choose to continue. Please consult any Tcl reference for the catch command for a
description of how to handle errors using general Tcl mechanisms.

Tcl Commands
The following subsections describe the most common commands in PlanAhead.

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Project Creation and Manipulation

There are a number of Tcl commands that control the creation and management of
PlanAhead projects. The following table lists the most common commands relating to
project manipulation:

Table 14-1: Tcl Project Manipulation Commands

Command Description
create_project Create a new project.
open_project Open an existing project.
close_project Close the current project.
get_project Query project by name if multiple projects are
open.
current_project Return the current open project if multiple projects
are open.
save_project_as Save the current project to a different location.
add_files Add source files to a project.
remove_files Remove source files from a project.
open_rtl_design Open the elaborated RTL design.
open_netlist_design Open the post-Synthesis netlist design.
open_impl_design Open the post-Implementation design.
close_design Close the current design.

For specific information about each command, consult the online help for the individual
command.

Flow Control
The following table contains a list of Tcl commands that control the flow of Synthesis and
Implementation.

Table 14-2: Flow Control Commands

Command Description
launch_runs Launch a Synthesis or Implementation run.
wait_on_run Block script execution until launched run completes.
create_run Create a new run based on a strategy.
reset_run Reset run status.
current_run Return the current run.
get_runs Query all configured runs.
delete_run Delete a given run.

For specific information about each command, please consult the online help for the
individual command.

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Object Access
The following table lists Tcl commands that query objects.

Table 14-3: Tcl Query Commands

Command Description
get_cells Query cell objects.
get_pins Query pin objects.
get_ports Query port objects.
get_nets Query net objects.
get_clocks Query clock objects.
get_sites Query device site objects.
get_iobanks Query IO bank objects.
report_property Generate a list of available properties on an object.
set_property Set a property value on an object.
get_property Query a specific property on an object.

For specific information about each command, consult the online help for the individual
command.

Reporting
The following table lists the most common Tcl commands that generate informational
reports, either printed to the console or written to a report file on the filesystem.

Table 14-4: Tcl Reporting Commands

Command Description
report_property Return a list of property names and descriptions for a given object.
report_timing Generate static timing analysis timing report.
repot_ssn Generate Simultaneous Switching Noise (SSN) report.
report_drc Generate Design Rule Check (DRC) report.
report_power Generate power estimation report.
report_constraint Generation constraint violation report.
report_resource Generate resource utilization report.

For specific information about each command, consult the online help for the individual
command.

GUI Control
Table 14-5, page 350 lists the Tcl commands that control some behavior in the GUI, if it is
active. These commands are very helpful for things such as finding objects in the device
view and cross probing between schematic and placement on the device. These commands
do nothing in batch and interactive Tcl modes where the GUI is not active.

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Table 14-5: Tcl GUI Commands

Command Description
select_objects Select an object, which is equivalent to clicking on it in the
GUI. Useful for zoom-to-selection.
unselect_objects De-select an object.
mark_objects Mark an object with a marker that is visible regardless of
zoom level.
unmark_objects Remove marker.
highlight_objects Highlight an object with a specified color.
unhighlight_objects Remove highlight.

For specific information about each command, consult the online help for the individual
command.

Tcl References
The following subsections provide recommended Tcl references.

Tcl Developer Xchange

Tcl reference material is available on the Internet. Xilinx recommends the Tcl Developer
Xchange, which maintains the open source code base for Tcl, and is located at:
http://www.tcl.tk
An introductory tutorial is available at:
http://www.tcl.tk/man/tcl/tutorial/tcltutorial.html

About SDC
SDC is an acronym for Synopsys Design Constraints, and is an accepted industry standard
for communicating design intent to tools, particularly for timing analysis. A reference copy
of the SDC specification is available from Synopsys by registering for the TAP-in program
at:
http://www.synopsys.com/Community/Interoperability/Pages/TapinSDC.aspx

Available Tcl Documents

Tcl reference documents are available in book stores or online retailers.

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Using PlanAhead With Project

Navigator
This chapter contains the following sections:
• Integration Overview
• PlanAhead Processes within Project Navigator

Integration Overview
The PlanAhead™ software is integrated with the ISE® software to let you perform specific
design tasks. When you invoke the PlanAhead software from the ISE Project Navigator
environment, the PlanAhead software is in “ISE Integration mode.” In this mode, the
available PlanAhead features apply only to specific design tasks, including I/O pin
planning, floorplanning, and timing analysis. The Project Navigator environment creates
and manages the PlanAhead software project automatically.
There are four processes in the Project Navigator Processes pane from which you can
invoke the PlanAhead software:
• Pre-Synthesis
- I/O Pin Planning
• post-Synthesis
- I/O Pin Planning
- Floorplan Area/IO/Logic
• Post-Implementation
- Analyze Timing/Floorplan Design
The data passed between the two tools and the view layout presented in the PlanAhead
software depends upon which step you invoke. Refer to the PlanAhead Processes within
Project Navigator, page 352 for more information on the mechanics of the integration
including data passing and processes.
PlanAhead has two default view layouts for the many design tasks:
• The I/O pin planning environment, called the I/O Planner, which contains views
pertinent to I/O pin planning and assignment.
• The Design Planning environment which contains views pertinent to design analysis
and floorplanning.
It is important to ensure the proper view layout is loaded for the desired design task.

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For more information about using the PlanAhead Viewing Environment, see Chapter 4,
“Using the Viewing Environment.” For more information about configuring and loading
view layouts, refer to Configuring and Saving the Viewing Environment in Chapter 4.

PlanAhead Processes within Project Navigator

Project Navigator and the PlanAhead software are two independent environments
operating under a separate system process. The two processes are integrated to ensure that
data is passed effectively between the two tools. Changes to design data in one tool are not
recognized automatically in the other in real time, and you should not to edit logic or
constraints simultaneously in both tools. Invoke PlanAhead for the intended purpose and
close it before updating the Project Navigator design data. The Project Navigator process
steps are synchronized to recognize edits to the UCF file made in the PlanAhead software
once the data is saved. The following sections describe the steps involved and the data
transactions that enable the integration.

Passing Logic and Constraints

PlanAhead in ISE Integration mode enables only physical constraint modification for I/O
pins, logic LOC, and AREA_GROUP constraints. Logic connectivity in the form of RTL
sources or synthesized netlists are passed into the PlanAhead software for analysis
purposes only, and not passed back to Project Navigator. The PlanAhead software features
that enable logic or timing constraint modification are disabled in ISE Integration mode.
You must perform logic modifications in Project Navigator, an external RTL, or in
Synthesis tools. The PlanAhead software passes only the UCF constraint files to Project
Navigator.
The PlanAhead software maintains the original content and format of the UCF files,
including comments, incomplete constraints, and so forth. The legality of constraints in the
design is not checked upon opening or closing the PlanAhead software. The Translate
Process step in Project Navigator does the constraint checking.
When you invoke PlanAhead, the UCF source files in the Project Navigator project are
passed to the PlanAhead software where you can add or modify physical constraints.
When you use the Save Project command in PlanAhead, that software writes the
modified UCF files back to the original Project Navigator source location. If you make
constraint changes in the PlanAhead software and select the Exit command, you are
prompted to save changes back to the Project Navigator project before the tool closes.
If PlanAhead is invoked and no UCF file exists in the Project Navigator project, you are
prompted to create one. This empty UCF file is then passed to the PlanAhead software.
PlanAhead supports Project Navigator projects with more than one UCF source file. Before
PlanAhead is invoked, a dialog box prompts you to select one of the UCF files.
• All new constraints defined in PlanAhead are written to the selected UCF file.
• Any physical constraints that exist in a non-chosen UCF file remain in that file, even if
the value of that constraint is modified in PlanAhead.
The Project Navigator design flow does not pass core-level NCF files to PlanAhead. To use
or view any physical constraints in these files in PlanAhead, you must merge them
manually into a top-level UCF file prior to invoking the PlanAhead software.

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Project Navigator creates a temporary PlanAhead project in the ISE project directory, and
removes and replaces this project every time you invoke the PlanAhead software from
Project Navigator.

I/O Pin Planning (Pre-Synthesis)

You can elect to perform early I/O pin planning prior to having a synthesized netlist either
by using the standalone PlanAhead software or by selecting this process step in Project
Navigator.
Note: At this stage of the design process, logic Synthesis has not been run. The tool has no concept
of clock ports, clock related logic, differential pairs, or GTs. You must ensure these types of ports are
placed appropriately to avoid Implementation errors. Whenever possible, you should perform the I/O
pin planning after logic Synthesis. The presence of a netlist ensures that the clocks, clock logic,
differential pairs, GTs, and so forth are recognized and considered automatically during pin
assignment in PlanAhead. Also, there are many Design Rule Checks (DRCs) that are performed
based on logic connectivity and clocks to ensure a legal placement prior to Implementation.
To perform I/O pin planning in Project Navigator prior to running Synthesis:
• In the Processes pane, expand User Constraints and double-click IO Pin Planning
(PlanAhead) - Pre-Synthesis,
or
• Select the Tools > PlanAhead > Pre-Synthesis - IO Pin Planning command.
When you invoke the PlanAhead software, Project Navigator passes all of the RTL source
files, the top-level module name and the UCF file(s) to PlanAhead. The PlanAhead
software opens with a display of the default I/O pin planning (I/O Planner) view layout.
PlanAhead performs an RTL elaboration to extract and display the top-level I/O ports in
the PlanAhead I/O Ports view.
When you save or close the PlanAhead project it updates the original Project Navigator
source UCF file(s). This resets the Project Navigator design process state, if appropriate.
Refer to Passing Logic and Constraints, page 352 for more information about the
integration mechanics and process.
Refer to Chapter 8, “I/O Pin Planning,” for more information about using the PlanAhead
I/O pin planning environment (I/O Planner).

I/O Pin Planning (Post-Synthesis)

Note: Whenever possible, I/O pin planning should be performed after logic Synthesis. The presence
of a netlist ensures that the clocks, clock logic, differential pairs, GTs, and so forth are recognized and
considered automatically during pin assignment in PlanAhead. There are also many Design Rule
Checks (DRCs) that are performed based on logic connectivity and clocks to ensure a legal
placement prior to Implementation.
To perform I/O pin planning in Project Navigator after running logic Synthesis, in the
Processes pane:
• Expand User Constraints and double-click IO Pin Planning (PlanAhead) - Post-
Synthesis,
or
• Select the Tools > PlanAhead > Post-Synthesis - IO Pin Planning command.

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When you invoke PlanAhead, Project Navigator passes the synthesized NGC or EDIF
format netlist and the UCF file(s) to PlanAhead. PlanAhead opens with a display of the
default I/O pin planning (I/O Planner) view layout, and the I/O ports display in the
PlanAhead I/O Ports view.
When you save or close the PlanAhead project, it updates the original Project Navigator
source UCF file(s), and this resets the Project Navigator design process state, if appropriate.
Refer to Passing Logic and Constraints, page 352 for more information about the
integration mechanics and process. Refer to Chapter 8, “I/O Pin Planning,” for more
information about using the PlanAhead I/O pin planning environment.

Floorplan Area/IO/Logic (Post Synthesis)

You can use the PlanAhead software design analysis and floorplanning environment prior
to or after Implementation. To analyze the design or to perform floorplanning from Project
Navigator after running logic Synthesis and prior to Implementation:
• In the Processes pane, expand User Constraints, and select Floorplan Area/IO/Logic
(PlanAhead) - Post-Synthesis,
or
• Select the Tools > PlanAhead > Post-Synthesis - Floorplan Area/IO/Logic
command.
When PlanAhead is invoked, Project Navigator passes the synthesized NGC or EDIF
format netlist and the UCF file(s) to PlanAhead. PlanAhead opens with the default
PlanAhead design analysis and floorplanning environment displaying.
Note: In Project Navigator, set the Translate process property Macro Search Path (-sd) to the
appropriate directory if lower-level NGC format core files are used in the design and are not added as
sources.
When you save or close the PlanAhead project, it updates the original Project Navigator
source UCF file(s), and resets the Project Navigator design process state, if appropriate.
Refer to Passing Logic and Constraints, page 352 for more information about the
integration mechanics and process. Refer to Chapter 5, “RTL Design,” for more
information about using the PlanAhead environment prior to Implementation.
Chapter 10, “Analyzing Implementation Results,” and Chapter 11, “Floorplanning the
Design,” have more information about using the PlanAhead environment after
Implementation.

Analyze Timing/Floorplan Design (Post Implementation)

You can use the PlanAhead software design analysis and floorplanning environment after
Implementation. When you analyze the design after Implementation you can view the
placement and timing results to catch potential design issues.
Often, physical LOC or AREA_GROUP floorplanning constraints can help drive the
Implementation tools toward better and more consistent results, and reduce
Implementation runtimes.
To analyze the design or to perform floorplanning from Project Navigator after
Implementation:
• In the Process pane, expand Implement Design, expand Place & Route, and double-
click Analyze Timing/Floorplan Design (PlanAhead) - Post-Synthesis

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or
• Select the Tools > PlanAhead > Post-Implementation - Analyze Timing/Floorplan
Design command
Project Navigator passes the following files to PlanAhead when it opens:
• Synthesized NGC or EDIF format netlist
• UCF file(s)
• ISE placement data
• Timing results
PlanAhead is invoked with the default PlanAhead design analysis and floorplanning
environment displayed. For PlanAhead to extract the ISE placement data, you must first
run an XDL command to produce a file with an XDL extension.
A progress bar displays in PlanAhead while this command is running. To expedite re-
invoking PlanAhead, the interface first checks for the existence of the XDL file and does
not regenerate the file if it is still current.
When you select Tools > PlanAhead > Post Implementation - Analyze Timing
/Floorplan Design with the Implementation process out-of-date, you are prompted to
either re implement the design and launch PlanAhead, or launch PlanAhead on the
existing result data without rerunning the Implementation tools.
When you save or exit the PlanAhead project, the PlanAhead software updates the original
Project Navigator source UCF file(s), and this resets the Project Navigator design process
state also, if appropriate.

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 Appendix A

PlanAhead Input and Output Files

This appendix contains the following sections:
• Inputs to PlanAhead
• Outputs for Reports
• Outputs for Environment Defaults
• Outputs for Project Data

Inputs to PlanAhead
This appendix describes the formats and processes used while importing design data.
The input files are as follows; you can click the linked file name and go directly to the
description:
• RTL Source Files (Verilog, VHDL, or other design text files)
• I/O Port Lists (CSV)
• Top-Level Netlists (EDIF, NGC)
• Module-Level Netlists and Cores (EDIF, NGC, NGO)
• Constraint Files (UCF / NCF / XNCF)
• Xilinx ISE Placement Results (NCD / XDL)
• Xilinx TRCE Timing Results (TWX/TWR)
While reading the input files, the PlanAhead™ software writes out any errors, warnings,
and messages in to the planAhead.log file. These messages display in the PlanAhead
Console view also.

RTL Source Files (Verilog, VHDL, or other design text files)

You can import and elaborate Verilog and/or VHDL files to analyze the logic or modify the
source. The original source files can be referenced and left in place or they can be copied
into the project for portability. You can specify the search directories when importing RTL
source files. All recognized files and file types contained in the directories are imported
into the project.

I/O Port Lists (CSV)

You can import a Comma Separated Values (CSV) format file to populate the I/O Ports
view within I/O Planner. This functionality is available in an Empty I/O pin planning
project only.

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You can then assign these I/O Ports to physical package pins to define the device pin
configuration. Refer to for more information about the CSV file content and format.

Top-Level Netlists (EDIF, NGC)

Currently, PlanAhead supports the importing of EDIF or NGC netlists. The netlist should
be synthesized for a Virtex®-4, Virtex-5, Virtex-6, Spartan®-3 or Spartan-6 device.
PlanAhead can construct the design using multiple netlists supporting a hierarchical
design methodology. When you select the top-level logic, lower-level modules are
imported automatically. Incremental netlist import capabilities allow netlist updates at any
level of design hierarchy. In-process floorplanning constraints are maintained through
iterations.

Module-Level Netlists and Cores (EDIF, NGC, NGO)

PlanAhead can construct the design using multiple EDIF or NGC netlists supporting a
hierarchical design methodology. When you select the top-level logic, lower-level modules
are imported automatically. You can define a search path to locate the design modules. The
advantage to this process is more flexibility when updating the design. The PlanAhead
software has an incremental netlist import capability which allows netlist updates at any
level of the design hierarchy.
The PlanAhead software can support designs that use NGC format netlists, such as Xilinx®
core files and XST output netlists. The software behavior is different based on whether the
NGC file is a top-level netlist or a module-level netlist. Upon netlist import, PlanAhead
converts NGC and NGO format core files to EDIF automatically, as follows:
• The Xilinx ngc2edif command converts NGC format files to EDIF.
• The Xilinx ngcbuild and ngc2edif commands convert NGO format files to EDIF.
For secure cores, the conversion utilities strip the LUT equations out of the converted EDIF.
These types of NGC or NGO core files have typically been “hand placed” for maximum
performance, and it is unlikely that floorplanning will improve their performance. It is not
recommended that you floorplan logic inside the core modules. However, you can
floorplan the location for the entire core and all surrounding logic.
Note: You can view the output log for the ngc2edif command in the PlanAhead terminal window
where PlanAhead was invoked. Occasionally, the ngc2edif command produces an EDIF that is
unusable or that has discrepancies with the accompanying NCF constraints. Report these issues to
Xilinx along with the data with which to reproduce the file. You can continue to floorplan without the
cores imported. PlanAhead creates black boxes for the missing logic. You must then copy the NGC
core files netlists to the ISE /run directory.

Constraint Files (UCF / NCF / XNCF)

The PlanAhead software supports importing UCF, NCF, and XNCF format files for timing
and physical constraints. PlanAhead can import multiple UCF files which allows for
separation of physical constraints, I/Os, and timing constraints.
Module-level constraints that are specific to cores, such as NCF files, can also be imported.
For more information, see
PlanAhead supports all of the UCF constraints supported by Xilinx. Refer to the
Xilinx Constraints Guide, (UG612) for more information about UCF constraints and the
supported syntax.

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Xilinx ISE Placement Results (NCD / XDL)

The PlanAhead software can import ISE placement results using XDL format data. XDL
data is created automatically when Implementation runs are launched from PlanAhead.
Once the ISE commands have completed satisfactorily, an XDL format file can be created
from the placed_design_name.ncd file. You can create and XDL files and import
placement for individual blocks or for the entire design.
When using the Import Placement command, PlanAhead will run the XDL command
automatically when you select a placed_design_name.ncd file in the Import
Placement dialog box.
To run the command by hand, use the following file syntax:
xdl –ncd2xdl placed_design_name.ncd
Running this command creates a placed_design_name.xdl file.
The XDL command status displays in the PlanAhead Terminal window.

Xilinx TRCE Timing Results (TWX/TWR)

The PlanAhead software can import the timing report generated by the Xilinx TRACE
command. This includes TWX and TWR files. Once imported, all signal tracing and
selection is available through the Timing Analysis View.
Note: If both files exist, TWX is the preferred format to use to import timing results.

Outputs for Reports

This section provides a brief description of the files that the PlanAhead software creates
during normal design operations. These files can contain valuable information. The last
two reports are not generated automatically, and require user interaction to create.
The output log and report files are:
• I/O Pin Assignment (CSV)
• I/O Pin Assignment (RTL - Verilog or VHDL)
• Log File (planAhead.log)
• Journal File (planAhead.jou)
• Error Log Files (planAhead_pidxxxx.debug & hs_err_pidxxxx.log)
• DRC Results (results_x_drc.txt)
• Timing Analysis Results (Excel file)
• Netlist Module, Pblock, and Clock Region Statistics Reports
• SSN Analysis Report (requires user interaction)
• WASSO Analysis Reports (requires user interaction)

I/O Pin Assignment (CSV)

The I/O Pin Assignment is stored in a Comma Separated Value (CSV) format file that
contains the I/O port assignment and relative package pin information.
This file is intended to be used for RTL port header definition and PCB schematic symbol
generation.

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I/O Pin Assignment (RTL - Verilog or VHDL)

This Verilog or VHDL format file contains the I/O port assignments defined as ports in the
file header in a legal language format. This file is intended to be used for RTL port header
definition.

Log File (planAhead.log)

The log file, planAhead.log, captures the contents of the messages created from running
PlanAhead commands.
PlanAhead creates the file in the following directory, based on the OS:
• (Linux) the PlanAhead invocation directory
• (Windows) C:\Documents and Settings\user\Application Data\HDI
You can view the file by in PlanAhead by selecting Window > View Log File.

Journal File (planAhead.jou)

The journal file, planAhead.jou, captures the Tcl commands from the invoked
PlanAhead session. The file is created in the following directory, based on the OS:
• (Linux) the PlanAhead invocation directory
• (Windows) C:\Documents and Settings\user\Application Data\HDI
You can replay the journal file to reproduce the commands of the previous session. You can
create Tcl scripts by copying commands from the journal file for replay later in PlanAhead.
It might be necessary to edit this file to remove any erroneous commands or commands
from multiple PlanAhead sessions prior to replay.
Note: Not every action in PlanAhead logs a Tcl command into the journal file.

Error Log Files (planAhead_pidxxxx.debug & hs_err_pidxxxx.log)

The error files can provide valuable information for debugging PlanAhead in the event of
an unexpected interrupt. If PlanAhead issues a dialog box that warns of an internal
exception error, the error files are stored n the following directory, based on the OS:
• (Linux) the PlanAhead invocation directory
• (Windows) C:\Documents and Settings\user\Application Data\HDI
When you open a case with Xilinx Technical Support, include any generated error log files,
the PlanAhead journal file (planAhead.jou), and the log file (planAhead.log). These
files contain no design data.

DRC Results (results_x_drc.txt)

The results from the Design Rule Check (DRC) are reported in the results_x_drc.txt
files created in the following directory, based on the OS:
• (Linux) the PlanAhead invocation directory
• (Windows) C:\Documents and Settings\user\Application Data\HDI
Each time DRC is run, a new file is produced in the PlanAhead project directory with a
corresponding number to results listed in the PlanAhead DRC dialog box.

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Timing Analysis Results (Excel file)

The results from timing analysis can be exported into a text file. To export the data, in the
Timing Results view select Export Statistics.

Netlist Module, Pblock, and Clock Region Statistics Reports

The resource statistics displayed in the Instance Properties, Clock Region and Pblock
Properties View can be exported to an Microsoft Excel format file. This information
includes resource utilization, RPM and carry chain sizes, clocks and clocked instances, and
other relevant resource data.
To export the data, from the Statistics tab of the Instance, Clock Region or Pblock Properties
View, select Export Statistics. The dialog box lets you define the information to include in
the report as well as how many levels of hierarchy to report. A browser lets you specify a
file name and location.

SSN Analysis Report

The results from the PlanAhead Simultaneous Switching Noise (SSN) analysis can be
exported to a CSV report file by specifying a file name and location in the Run SSN
Analysis dialog box.

WASSO Analysis Reports

The results from the PlanAhead Weighted Average Simultaneous Switching Output
(WASSO) analysis can be exported to a text report file by specifying a file name and
location in the Run WASSO Analysis dialog box.

Outputs for Environment Defaults

This section provides a brief description of the files that are created during normal
PlanAhead design operations. These files can contain valuable information. The last two
reports are not generated automatically, and require user interaction to create.
The output files are:
• View Display Options File (planAhead.ini & theme_names.patheme)
• Window Layout Files (layoutname.layout)
• Shortcut Schema (default.xml) (requires user interaction)
• Strategy Files (strategyname.psg) (requires user interaction)

View Display Options File (planAhead.ini & theme_names.patheme)

The initialization file, planAhead.ini, captures the settings in the current Tools >
Options that include display color and other viewing options for the PlanAhead
environment. PlanAhead saves user settings to this file for future sessions when you exit
PlanAhead.
The file is created automatically in your home directory, which is typically the following
directory: C:\Documents and Settings\user\Application
Data\HDI\version_number>\planAhead.ini.

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When you invoke PlanAhead, it imports the file automatically from the PlanAhead
installation directory first, and then from the following directory, based on the OS:
• (Windows) C:\Documents and Settings\user\Application
Data\HDI\version_number, if it exists
• (Linux) ~/.HDI/planAhead.ini
You can save custom theme files for use in future PlanAhead sessions by clicking the Save
As button in the Themes dialog box (accessed using Tools > Options > Themes).
You can select a Theme file to use during the active PlanAhead session from a pull-down
selection menu. For more information, see Configuring PlanAhead Behavior, page 133.
When you select the Light/Dark Theme buttons of the View Options dialog box, the
software overrides the following directory with the preset defaults:
• (Windows) C:\Documents and Settings\user\Application
Data\HDI\version_number\planAhead.ini file
• (Linux) ~/.HDI/planAhead.ini file
To avoid loss of any custom settings, keep a backup of the custom settings file.

Window Layout Files (layoutname.layout)

You can create Window layout files using the Save Layout As or Save as Default Layout
commands that save the current PlanAhead Desktop view configuration to be recalled at a
later time. The configurations for the viewing environments are stored in the following
subdirectories:
• (Windows) C:\Documents and Settings\Username\Application
Data\HDI\version_number\layouts\
• (Linux) ~/.HDI directory.

Shortcut Schema (default.xml)

When you use the Options dialog box you can create Accelerator key definitions or
“shortcut schema.” These schema define a mapping from keyboard shortcuts to
PlanAhead commands. For example, the keystroke Ctrl + F by default maps to the Edit >
Find command. You can define and configure multiple schemas, all of which are stored in
the default XML file in the following locations:
• (Windows) C:\Documents and Settings\Username\Application
Data\HDI\version_number\shortcuts.
• (Linux) ~/.HDI/shortcuts

Strategy Files (strategyname.psg)

Strategy files contain your specified default command line options for all of the ISE
Implementation commands. You can apply a strategy to any given ISE attempt using
PlanAhead. You can either create strategies from scratch or copy one of the factory
supplied strategies. User-defined strategies are stored in your home directory, as follows:
• (Windows): C:\Documents and Settings\Username\Application
Data\HDI\version_number\strategies.
• (Linux) ~/.HDI/strategies.

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Outputs for Project Data

This section gives a brief description of the files that the PlanAhead software creates for
saved PlanAhead projects. These files are maintained by PlanAhead and should not be
modified manually. The project output files are as follows:
• Project Directory (projectname)
• Project File (projectname.ppr)
• Project Data Directory (projectname.data)
• Project Data - Netlist Subdirectory (netlist)
• Project Data - Constraint Set Subdirectories and Files (constraint_set_name)
• Project RTL Directory (projectname.srcs)

Project Directory (projectname)

When a new project is created, PlanAhead creates a project directory to store the project
file, the project data directory, and the ISE Implementation results. The project directory
has the same name as the project name entered in the New Project wizard.

Project File (projectname.ppr)

The Project PPR file stores the state of the project. It contains information about the netlist
and the various constraint sets and sources contained in the project.
The file is continuously maintained while PlanAhead is invoked. It does not require
saving. This file should not be edited manually.
The PPR file is the item selected in the PlanAhead browser when opening an existing
project.

Project Data Directory (projectname.data)

The project data directory stores the constraint and netlist-related data contained in the
project. These folders are maintained by PlanAhead and do not require your attention.
Caution! Modifying any of these files could result in project data corruption.

Project Data - Netlist Subdirectory (netlist)

A subdirectory called /netlist contains a copy of the netlist files for the entire design.
For RTL-based projects, a subdirectory for each Synthesis run is created containing the
netlist produced. It is refreshed each time the Synthesis run is reset.
For netlist-based projects, as single netlist directory is created containing the imported
netlist, including copies of all NGC core files used in the design.
You can use the File > Update Netlist command to update the subdirectory contents.

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Project Data - Constraint Set Subdirectories and Files

(constraint_set_name)
As you create constraint sets, PlanAhead creates matching subdirectories under the
/projectname.data directory.
The files in the constraint set directory are as follows:
• *.ucf—All imported UCF file names (might differ from input files)
• iseloc.xml—Used to differentiate the PlanAhead fixed placement constraints from
the unfixed placement constraints imported from ISE
• pfi.xml—Contains target device for the design
• pfp.xml—Contains current PlanAhead experiment information for the design
• expX subdirectories—Contains PlanAhead experiment information about each Run

Project RTL Directory (projectname.srcs)

The project sources directory stores the HDL source files that are imported into a project.
These folders are maintained by PlanAhead and do not require your attention.
Caution! Modifying any of these files could result in project data corruption.

Outputs for ISE Implementation

This section provides a brief description of the files that are created during PlanAhead ISE
Implementation design operations. These files are maintained by PlanAhead and should
not be modified manually.
The output files for ISE Implementation are:
• Run Directory (projectname.runs)
• EDIF Netlists (.edf)
• Run Implementation and Launch Runs
• Exported Netlists
• ChipScope Core Netlists (.ngc)
• Constraint Files (.ucf)
• Run Implementation and Launch PlanAhead Runs
• Exported Constraints
• Exported Pblocks
• Exported IP

Run Directory (projectname.runs)

PlanAhead lets you launch and queue multiple ISE Implementation attempts or Runs. You
are prompted to enter a location to create the Run directory. The default location is in the
project directory.
Each Run directory contains a complete EDIF netlist and UCF constraint file for that Run.
The PlanAhead software creates a run script to launch the ISE commands with your
specified options in each PlanAhead Run directory.

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Each Run directory contains the Implementation design data including the netlist and the
constraints files. When a satisfactory Implementation result is achieved, the entire Run
directory can be copied and archived because it is self contained.

EDIF Netlists (.edf)

The PlanAhead software exports EDIF format ASCII netlist files. These files are created
during the following commands:
• Implement and Launch Runs (PlanAhead)
• File > Export Netlist
• File > Export Pblocks
• File > Export IP

Run Implementation and Launch Runs

The purpose of launching PlanAhead Runs is to automatically export the files required to
implement the PlanAhead Runs and to launch the ISE commands with the options
specified in the Strategy applied to the Run.
When you use the Launch Run > Launch Runs command, the EDIF and UCF data is
exported automatically. When a Run is launched, a Run directory is created containing a
single EDIF-format netlist file and UCF-format constraint file for the entire top-level
design. The file names correspond to the original top-level netlist name contained in the
originally imported EDIF file.
If NGC/NGO format module netlist files are used, they are copied to each Run directory.
The PlanAhead General Run Properties indicate where the actual Run directory resides
on disk.

Exported Netlists
The purpose of exporting a Netlist is to supply the design EDIF file for ISE Implementation
outside of the PlanAhead environment. When a Netlist is exported, the original logical
netlist hierarchy is maintained in the output netlist. You can specify an output file name in
the Export Netlist dialog box.

ChipScope Core Netlists (.ngc)

PlanAhead is integrated with ChipScope™, which lets you insert and configure Integrated
Logic Analyzer (ILA) cores interactively. An NGC format netlist for the core is compiled
when the core is implemented. PlanAhead places the core in the project /netlist
directory and copies it to each Implementation Run directory as Runs are launched. Refer
to Chapter 12, “Programming and Debugging the Design,” for more information.

Constraint Files (.ucf)

PlanAhead writes User Constraint File (UCF) ASCII files containing timing and physical
constraints that are used for ISE. These files are created during the following commands:
• Implement and Launch Runs (PlanAhead)
• File > Export Constraints
• File > Export Pblocks

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• File > Export IP

Run Implementation and Launch PlanAhead Runs

When you use the Launch Run > Launch Runs command PlanAhead exports the
Electronic Data Interchange Format (EDIF) and UCF data automatically. When a Run is
launched, the PlanAhead software creates a Run directory which contains the original
logic hierarchy in the output netlist. The exported files for the Run consist of a single EDIF
format netlist file and a UCF format constraint file for the entire top-level design. The file
names correspond to the original top-level netlist name of the imported EDIF file.

Exported Constraints
When you export constraints the PlanAhead software attempts to preserve the original
UCF file content and structure, including comments.
You can specify the output constraints file in the Export Constraints dialog box.

Exported Pblocks
The purpose of exporting a Pblock is to write out the EDIF and UCF files for the specified
Pblocks to use for ISE Implementation outside of the PlanAhead environment.
When you export a Pblock, the PlanAhead software derives the netlist hierarchy based on
the Pblock assignments.
The resulting UCF references the PlanAhead physical hierarchy structure to match the
exported EDIF netlist names and provides flexibility when using a block-based
Implementation strategy.
The exported Pblock files consist of a single netlist file and constraint file. PlanAhead
automatically creates and maintains a block-level directory structure. When you export
selected Pblocks, the PlanAhead software creates pblockname_CV subdirectories
containing pblockname_CV.edn and pblockname_CV.ucf files.
Export Pblocks is typically used for a complex IP that contains the physical hierarchy,
which you can close timing on and then use those instances in other designs without
having to restructure your code to get a netlist.

Exported IP
The purpose of exporting IP is to write out the EDIF and UCF files for specified netlist
modules to be used for creating reusable IP blocks.
When you run the Export IP command on a selected module instance in the design it
exports the Pblock logical hierarchy and placement constraints. The exported files include
the EDIF netlist and UCF physical constraints in the original logical netlist format. This
allows for easier implementation in the next design by keeping the interface identical.
You can use the exported UCF file to re-create the Pblock placement constraints. You can
duplicate identical placement for multiple modules by moving the modules after they are
imported.
Figure A-1 is an example of how Export Pblock and Export IP can be used to export
different parts of the design based on either logical (Export IP) or physical (Export Pblock)
hierarchy:

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Figure A-1: Example of Export Pblock and Export IP

ISE Launch Scripts (jobx.bat/sh & runme.bat/sh & .ISE_command.rst)

When you use the PlanAhead Implement or Launch > Launch Run commands the
software creates ISE launch scripts automatically. These scripts contain commands and
command-line options specified in the PlanAhead Strategy.
The jobx.bat/sh scripts are located under the project Run directory in a /jobs
subdirectory and these scripts sequentially launch each selected Run. The script calls each
Run-specific runme.bat|sh script. You can launch these scripts independently also.

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 Appendix B

PlanAhead Terminology
BEL Placement Constraint (BEL)
Basic Element (BEL) constraints can be assigned to the leaf-level instances that have
placement sites assigned to specific logic device gates. Assigning a BEL constraint results
in a LOC and a BEL constraint being “fixed” and written in the exported UCF files for the
instance. Depending on the zoom level, these LOCs appear in the Device view either as
rectangles within their respective assigned sites, or as logic functions symbols within the
site.

Constraint
A constraint can either be a description of the timing of logic, some behavioral requirement,
or a physical placement requirement. I/O Port assignments are also defined by constraints.

Constraint Set
A constraint set is one of more constraint files used for analysis and implementation
purposes. They are managed within the Sources view in PlanAhead. Different constraint
sets can be used to experiment with constraints or to explore different devices.

Design
A Design is defined as a netlist (elaborated RTL or synthesized), a constraint set, and a
target device. You do not need to create Designs to use PlanAhead. Designs are stored in
memory during the PlanAhead current session only, and are used to analyze the design
snapshot and to launch Runs. Implementation runs can be launched using any external
User Constraints File (UCF). Each project netlist can support multiple Designs using
different constraints or devices.

I/O Port
I/O ports are user I/Os to be assigned to physical package pins. Each I/O signal is defined
as a port.

Instance
Elements in the Netlist referred to as instances include leaf-level logic primitives and
hierarchical module components. The module components are referred to as modules in
this document.

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Module
Elements in the netlist that represent hierarchical module instantiations are referred to as
modules or components. Leaf-level primitive logic is referred to as instances or primitives.

Netlist
A netlist represents a logical description of the design. A netlist should be hierarchical
consisting of a top-level netlist with child netlists for underlying levels of hierarchy
(“modules”). PlanAhead RTL-based projects can contain multiple netlists because multiple
Synthesis runs are enabled.

Package Pin
Package Pins are the physical pins of the package to which I/O Ports are assigned. The
Package Pins are grouped into I/O Banks. Refer to the device specifications for more
information about the Package Pins and I/O Banks.

Project
Each PlanAhead™ software session initiates an active project. You can create a project with
various input formats, depending upon the design flow being applied:
• Register Transfer Level (RTL) source files can be used to create a project that is
suitable for the RTL through bitstream flow.
• A synthesized netlist can be used in the netlist through bitstream flow.
• An empty project can be created to explore device resources or to begin I/O pin
planning, as described in
There is also a project creation method which allows results to be imported from a previous
command line Implementation attempt.
Depending on the type of project type you create, the project can contain one or more
versions of the netlist. Each with any number Implementation attempts or Runs.
The project information is stored in directory structure containing a combination of the
following:
• A project file, such as project_1.ppr
• A project data directory, such as project_1.data
• A project sources directory, such as project_1.srcs
• A project runs directory, such as project_1.runs
The sources directory contains all source files copied into the project. The data directory
contains the netlist directories containing the project netlists and directories for each
design in the project. The Runs directory contains all ISE Implementation attempts created
by PlanAhead.
The project data is maintained automatically by PlanAhead. The tool expects to find
project data in the state in which it was left; therefore, you should not attempt to modify
these files manually.
PlanAhead restores the state of the project automatically upon opening the project. The
project status including all opened or closed designs and each associated Run are updated
and available to you when a project is re-opened.

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A Pblock is defined in PlanAhead during floorplanning. Traditionally, a single or group of
logic instances are assigned to a Pblock. The Pblock can have an area, such as a rectangle
defined on the FPGA device, to constrain the logic. Netlist logic placed inside of Pblocks
will receive AREA_GROUP constraints for ISE. Pblocks may be specified with specific
RANGE types to contain various types of logic only (such as SLICE, RAM/MULT, and
DSP). Pblocks can be defined with multiple rectangles to enable non-rectangular shapes to
be created, such as ‘L’ shaped and ‘T’ shaped.

Primitive
Elements in the netlist that represent leaf-level logic objects are referred to as primitives
(such as LUTs and Flip-Flops).

Run
Each Synthesis or Implementation attempt is called a Run. Each Run is associated with a
specific strategy. You can launch multiple runs either simultaneously with multiple
processors or serially. Runs will be queued sequentially with the status displayed in
PlanAhead.

Site
PlanAhead displays a tile grid representation of the specific FPGA device resources that
can be used to implement the design netlist. Primitive logic sites are displayed and are
available for placement of netlist instances. These sites vary in shape and color to
differentiate the object types (for example RAMs, MULTs, CLBs, DSPs, PPCs, and MGTs).
Leaf-level logic can be assigned to specific SLICEs with placement constraints “LOCs”, or
to gates within the SLICE with LOC and BEL constraints.

Site Placement Constraint (LOC)

Location constraints or LOCs can be assigned to the leaf-level instances that have fixed
placement sites assigned to a specific SLICE coordinate. These are different than BEL
constraints as they do not lock the logic into specific logic gates within the SLICE.
Assigning a LOC constraint will result in a LOC constraint being “fixed” and applied in
the exported UCF files for the instance.
Depending on zoom level, these LOCs appear in the Device view either as rectangles
within their respective assigned sites or logic functions symbols within the site.

Source
Projects can be created with a variety of input file formats. Projects can be created by
importing RTL source files in Verilog and VHDL, IP core modules and synthesized netlists
in NGC or EDIF format. These files are considered source files.

Strategy
A Strategy is a predefined set of tool command-line options. You can apply factory
delivered Strategies or create your own. Strategies can be applied to individual runs.

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Installing Releases with XilinxNotify

This appendix contains the following sections:
• PlanAhead Release Strategy
• Running XilinxNotify

PlanAhead Release Strategy

The PlanAhead software release strategy is the same as other Xilinx® software tools. The
PlanAhead software is targeted to introduce new technology and respond to customer
requests. New releases are periodically introduced. The version number reflects the release
(for example: 12.3 or 12.4). The Help > About PlanAhead command displays the currently
installed PlanAhead version.
To check for new PlanAhead releases, run the Help > Check for Updates command, as
described below.
Refer to the Xilinx ISE Design Suite: Installation, Licensing, and Release Notes (UG631) for
more information about Xilinx tool installation.

Running XilinxNotify
The XilinxNotify tool is the preferred method of obtaining software updates. It performs
the following activities:
• Compares the latest version of Xilinx software updates available on
http://www.xilinx.com/support with what you have installed, and notifies you if a
newer version is available.
• Provides a Download button which launches a browser, allowing you to login to the
Xilinx Download Center.
Once you login, the download of your selected product will begin.
• XilinxNotify can be run in any of the following ways:
• Automatic periodic checks at PlanAhead startup.
• Select Help > Check for Updates.
• Type xilinxnotify in a Linux shell
Note: The Edit > Preferences menu selection lets you control the frequency of automatic checks at
startup time.

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XilinxNotify Network Installations

By default, the Automatically check for software updates option at startup is enabled on
the machine used to install the PlanAhead software to the network location.
All clients pointing to this network location have this option disabled by default.
Client users have the option of enabling this option (Tools > Options > General >
Miscellaneous > Automatically check xilinx.com for software updates on startup)
and also running manual checks. Figure C-1 shows the option.

Figure C-1: Automatically Check xilinx.com for Software Updates

Note: To perform a software update installation, you must have write permissions for the $XILINX
installation directory.
Quarterly releases for all platforms are regularly made available on the Download Center
at: http://www.xilinx.com/support/download/index.htm.

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 Appendix D

Configuring SSH Without Password

Prompting
Setting Up SSH Key Agent Forward
The multiple host capabilities for executing PlanAhead™ software runs uses Secure Shell
(SSH), a service provided by Linux operating system. Prior to configuring multiple hosts in
the PlanAhead software, you can configure SSH so that you are not prompted for a
password each time you log in to a remote machine. SSH configuration is accomplished
with the following commands at a Linux terminal or shell:
Note: This is a one-time step, and once successfully set up does not need to be repeated.
1. Run the following command at a Linux terminal or shell to generate a public key on
your primary machine. Though not required, it is a good practice to enter (and
remember) a private key phrase when prompted for maximum security.
ssh -keygen -t rsa
2. Append the contents of your publish key to an authorized_keys file on the remote
machine. The remote_server below should be changed to a valid host name:
cat ~/.ssh/id_rsa.pub | ssh remote_server “cat - >> ~/.ssh/
authorized_keys”
3. Run the following command to prompt for your private key pass phrase, and enable
key forwarding:
ssh -add
You should now be able to ssh to any machine without typing a password. The first time
you access a new machine, it will prompt you for a password, then subsequent accesses
will not. If you are always prompted for a password, contact your System Administrator to
have your Linux account set up for passwordless SSH.
After a passwordless SSH is set up, you can continue configuring the remote host. (Linux
only.)

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