Report on

“Library cell implementation of RHBD

SUBMITTED BY
TASMIYA SINDAGERI
VIVEKANANDA T
JAMEEL AHMED KUSTAGI
VIDYASAGAR DODDAMANI
(VLSI DESIGN AND EMBEDDED SYSTEM)

SUBMITTED TO
PROF.JAMUNA
 Reduced Complexity RHBD Logic Cells
for 32-nm SOI ASICs
INTRODUCTION
The first step in the fabrication of RHBD PROM is the library cell implementation
of PROM. Antifuse is used as the basic library cell as the memory cell to store the
memory. It is used because of its immunity towards radiations present in the
space. The various other low power electronic cells used are buffer to drive data
signals ,2 input nand gate, clkbuf to drive the clock, positive edge triggered d flip
flop,TIE1 andTIE0. Reduced complexity 32-nm silicon-on-insulator (SOI) logic cell
libraries and test chips have been developed for evaluation in harsh radiation
environments. SOI-specific radiation hardened by design (RHBD) methods,
including body contacts and stacked transistors, were leveraged for improved
radiation hardness. The number of cells and their complexity was intentionally
limited to lower development costs and simplify portability to other SOI
technology nodes.

All the required process information is fed to the antifuse based on the PROM
design specifications. Various RHBD designs are operated on the same antifuse.
These designs can be applied in both circuit level and layout level. In the circuit
level sense amplifiers such as inverters are used due to its robustness. Dual
interlocked latch(DICE) cell amplifiers are used at the external nodes of RHBD
PROM. DICE amplifiers are used to mitigate the single event upsets(SEU). At the
layout n - transistors and guard rings are used. Guard rings basically protect the
satellites from single event latchups(SEL). Radiation-hardening-by-design (RHBD)
employs layout and circuit architecture changes for the radiation hardening of
space electronic systems using commercial foundry processes, with no
modifications to the existing process or violation of design rules.

Schematic entry
In the schematic entry of RHBD PROM, the transistors are sized and scaled in
accordance with the device technology. This can be done using heterogenous
bipolar junction silicon-germanium transistor of width 3.48 micrometer. At the
device-level, RHBD C-B-E SiGe HBTs with single collector and base contacts and
significantly smaller deep trench-enclosed area than standard C-B-E-B-C devices
with dual collector and base contacts are used to reduce the upset sensitive area.
The SEU performance of these shift registers was then tested using heavy ions
and standard bit-error testing methods. The results obtained are compared to the
unhardened standard shift register designed with CBEBC SiGe HBTs. The RHBD-
enhanced shift registers perform significantly better than the unhardened circuit,
with the TMR technique proving very effective in achieving significant SEU
immunity.

Three different types of 16-bit shift registers in the current mode logic (CML)
family were investigated in this work. The clock “tree” architecture in these shift
registers was identical to the one used in shift registers reported in, with a master
clock buffer driving four intermediate clock buffers, each in turn providing clock
inputs to a set of 4-D flip flops (Fig. 1). Thus, as was noted in , an upset occurring
in the clock tree has the potential to cause multiple bit upsets. Therefore, to
improve their SEU immunity, the clock buffers in the present designs featured
circuit-level hardening based on the gated-feedback cell (GFC) RHBD technique.
Two RHBD local circuit-redundancy based circuit-level hardening techniques were
employed in the design of the constituent D-flip flops in two of the three shift
registers, while the remaining shift register, referred to as “standard MS SR” (“std.
SR”), featured unhardened conventional CML master-slave (MS) D-flip flops, and
was used as the baseline circuit (control) to enable meaningful comparisons. To
study the effects of reduced bias current on the SEU characteristics of the shift
registers, low-power (mA) and high-power (mA) versions were implemented. Itail
is the tail current of any differential pair in the D-flip flops. Upon complete
switching the current flowing through the load resistor connected to the ON
transistor is very close to itail.

Figure :2 implantation of triple module redundancy(TMR)

Fig:3 heterojunction transistor of SiGe

antifuse

Process info RHBD designs

Layout level
Circuit level

Sense Guard rings

Cadence abstract Visual T CAD

abstract
Critical parasitic
information
Schematic
netlist entry
Once the schematic entry has
been done, the transistors can be scaled using the bipolar heterojunction
RHBD C-B-E RHBD C-B-E-B-C
Pin name
transistor of silicon and germanium. Partsim or Xilinx can be used for schematic
entry. Next in order to know how our model would perform from the design pre
layout simulation is done. The
Prelayout
Cell layout design we can use cadence virtuoso, altsim
simulation
name
or microwind. To verify layout design rule check(DRC) is performed and DRC file is
generated that shows the errors if any of the dimensions have been violated. LVS
Layout design
is also generated that compares the schematic and layout. It is performed to
report about circuit nodes and device sizes. Next is the post layout simulation, we
DRC/LVS files
can use cadence abstract generator to generate the netlist, PR boundary, pin
Post layout simulation
name and cell name. We can also use visual TCAD to know the critical parasitic
information of the design without using any of the programming language.
While DICE (Dual Interlocked storage Cell) registers are often used to harden bulk
silicon processes against single event upsets, SOI processes can leverage more
efficient stacked transistor architectures to achieve a similar benefit . Figure
shows a 32-nm stacked transistor DFFR register cell, where redundant series
devices are used to mitigate upsets on any single transistor. We also used stacked
devices in the combinational logic cells to decrease the generation rate of single
event transients in the data path logic and clock net

Table:2 Rhbd test chip configurations

Conclusion
The basic library cell implementation of RHBD prom is very similar to digital IC
design flow. Seven 32-nm reduced complexity logic cell libraries and their
associated test chips were developed to evaluate the radiation performance of
SOI body contacted and stacked transistor cell designs. These chips will be
fabricated at the IBM Trusted Foundry and undergo evaluation in relevant
radiation environments. The use of RHBD C-B-E SiGe HBTs with 73% smaller
trench-enclosed (DT-enclosed) area than conventional C-B-E-B-C devices, and
circuit RHBD techniques such as the dual-interleaving, gated-feedback, and TMR,
proved effective in improving the overall SEU immunity of the, to high LET values.