IPC-2226

ASSOCIATION CONNECTING
ELECTRONICS INDUSTRIES ®

Sectional Design
Standard for High
Density Interconnect
(HDI) Printed Boards

Developed by the HDI Design Subcommittee (D-41) of the HDI

Committee (D-40) of IPC

Users of this standard are encouraged to participate in the

development of future revisions.

Contact:

IPC
2215 Sanders Road
Northbrook, Illinois
60062-6135
Tel 847 509.9700
Fax 847 509.9798
IPC-2226 April 2003

Table of Contents
1 SCOPE ...................................................................... 1 4.5 Embedded Electronic Components ................... 12
1.1 Purpose ................................................................. 1 4.5.1 Embedded Resistors ........................................... 12
1.2 Document Hierarchy ............................................ 1 4.5.2 Embedded Capacitors ........................................ 12
1.3 Presentation .......................................................... 1 4.5.3 Embedded Inductors .......................................... 13
1.4 Interpretation ........................................................ 1
5 MECHANICAL/PHYSICAL PROPERTIES ............. 13
1.5 Classification of HDI Types ................................ 1 5.1 HDI Feature Size ............................................... 13
1.5.1 Core Types ........................................................... 1 5.1.1 Minimum Hole Sizes for Plated-Through
1.5.2 HDI Types ............................................................ 1 Hole Vias ............................................................ 13
1.6 Via Formation ...................................................... 1 5.2 Construction Types ............................................ 13
1.7 Design Features ................................................... 1 5.2.1 HDI Type I Constructions -
1 [C] 0 or 1 [C] 1 .............................................. 13
2 APPLICABLE DOCUMENTS ................................... 1
5.2.2 HDI Type II Constructions -
2.1 IPC ....................................................................... 1 1 [C] 0 or 1 [C] 1 .............................................. 13
2.2 Underwriters Laboratories ................................... 2 5.2.3 HDI Type III Constructions - ≥2 [C] ≥0 .......... 13
3 GENERAL REQUIREMENTS ................................... 2 5.2.4 HDI Type IV Constructions - ≥1 [P] ≥0 .......... 15
3.1 Terms and Definitions ......................................... 2 5.2.5 Type V Constructions (Coreless) -
Using Layer Pairs .............................................. 15
3.1.1 Microvia (Build-Up Via) ..................................... 2
5.2.6 Type VI Constructions ....................................... 17
3.1.2 Capture Land (Via Top Land) ............................. 2
3.1.3 Target Land (Via Bottom Land) .......................... 2 6 ELECTRICAL PROPERTIES ................................. 19
3.1.4 Stacked Vias ......................................................... 3 6.1 Equivalent Circuitry ........................................... 19
3.1.5 Stacked Microvias ............................................... 3 6.2 Final Metal Traces ............................................. 19
3.1.6 Staggered Vias ..................................................... 3 6.2.1 Inductance and Capacitance .............................. 19
3.1.7 Staggered Microvias ............................................ 3 6.2.2 High Frequency Performance ............................ 21
3.1.8 Variable Depth Microvia/Via ............................... 3 7 THERMAL MANAGEMENT .................................... 21
3.2 Design Tradeoffs .................................................. 3 7.1 Thermal Management Concerns for Bump
3.3 Design Layout ...................................................... 5 Interconnects on HDI ........................................ 22
3.3.1 Design Considerations ......................................... 5 7.1.1 Junction to Case Thermal Models .................... 23
3.4 Density Evaluation ............................................... 5 7.2 Thermal Flow Management Through HDI
3.4.1 Routability Prediction Methods ........................... 5 Substrate ............................................................. 24
3.4.2 Design Basics ....................................................... 6 8 COMPONENT AND ASSEMBLY ISSUES ............. 27
8.1 General Attachment Requirements .................... 27
4 MATERIALS .............................................................. 8
4.1 Material Selection ................................................ 8 8.1.1 Flip Chip Design Considerations ...................... 27
4.1.1 HDI Material Options .......................................... 8 8.1.2 Chip Size Standardization ................................. 27
4.1.2 Designation System ............................................. 9 8.1.3 Bump Site Standards ......................................... 28
4.2 Application Levels ............................................. 11 8.1.4 Bump Options .................................................... 29
4.3 Material Description by Type ............................ 11 8.2 Chip Scale Design Considerations .................... 31
4.3.1 Dielectric Materials ............................................ 11 8.2.1 Chip Scale Area Arrays (FBGA and FLGA) .... 32
4.3.2 Materials for Conductive Paths (In-Plane 8.2.2 Peripheral Leaded Chip Scale Packages
or Inter-Plane) .................................................... 11 (TSOJ and SOC) ................................................ 32
4.3.3 Materials with Dielectric and Conductive 8.3 Printed Board Land Pattern Design .................. 32
Functionality ...................................................... 12 8.4 Substrate Structure Standard Grid Evolution ... 32
4.4 Copper Foil ........................................................ 12 8.4.1 Footprint Design ................................................ 33
4.4.1 Pits, Dents and Pinholes .................................... 12 8.4.2 Design Guide Checklist ..................................... 33

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April 2003 IPC-2226

8.4.3 Footprint Population .......................................... 33 Figure 5-4 Type III HDI Construction with Stacked
Microvias (Caution: Unbalanced
9 HOLES/INTERCONNECTIONS .............................. 35 constructions may result in warp & twist.) ....... 17
9.1 Microvias ........................................................... 35 Figure 5-5 Type III HDI Construction with Staggered
Microvias (Caution: Unbalanced
9.1.1 Microvia Formation ........................................... 36 constructions may result in warp & twist.) ....... 17
9.2 Via Interconnect Variations ............................... 37 Figure 5-6 Type III HDI with Variable Depth Blind Vias .... 17
9.2.1 Stacked Microvias ............................................. 37 Figure 5-7 Type IV HDI Construction ................................ 18
9.2.2 Stacked Vias ....................................................... 38 Figure 5-8 Coreless Type V HDI Construction .................. 18
9.2.3 Staggered Microvias .......................................... 38 Figure 5-9 Type VI Construction ....................................... 18
9.2.4 Staggered Vias ................................................... 38 Figure 6-1 Bump Electrical Path (Redistributed Chip) ...... 20
9.2.5 Variable Depth Vias/Microvias .......................... 39 Figure 6-2 Final Metal Trace and Underlying
Traces (Cross Section) .................................... 20
10 GENERAL CIRCUIT FEATURE Figure 7-1 HDI Thermal Path Relationships ..................... 22
REQUIREMENTS .................................................. 41
Figure 7-2 Thermal Management of Chip Scale
10.1 Conductor Characteristics .................................. 41 and Flip Chip Parts Mounted on HDI .............. 22
10.1.1 Balanced Conductors ......................................... 41 Figure 7-3 Bump Interconnect Equivalent Model .............. 23
10.2 Land Characteristics .......................................... 41 Figure 7-4 Wire Bond Example ......................................... 24
10.3 Determining the Number of Conductors .......... 41 Figure 7-5 Approximate Thermal Model for Wire Bond .... 24
10.4 Wiring Factor (Wf) ............................................ 41 Figure 7-6 Flip Chip Example ............................................ 25

10.4.1 Localized Escape Calculations .......................... 41 Figure 7-7 Approximate Thermal Model for Flip Chip ....... 25

10.4.2 Wiring Between Tightly Linked Components .. 43 Figure 7-8 Chip Underfill Example .................................... 25
Figure 7-9 Approximate Thermal Model for
10.4.3 Total Wiring Requirements ............................... 43
Chip Underfill ................................................... 25
10.5 Via and Land Density ........................................ 44 Figure 7-10 Thermal Paste Example .................................. 25
10.6 Trade Off Process .............................................. 44 Figure 7-11 Approximate Thermal Model for
10.6.1 Wiring Factor Process ....................................... 44 Thermal Paste ................................................. 26

10.6.2 Input/Output (I/O) Variables .............................. 44 Figure 7-12 Thermal Resistance ......................................... 26
Figure 7-14 Metallic Thermal Properties ............................. 26
11 DOCUMENTATION ............................................... 45 Figure 7-13 Parallel Resistances ........................................ 26
12 QUALITY ASSURANCE ....................................... 45 Figure 8-1 Flip Chip Connection ....................................... 27
Figure 8-2 Mechanical and Electrical Connections ........... 27
Figures Figure 8-3 Joined Chip and Chip Underfill ........................ 27
Figure 8-4 Example Layouts ............................................. 28
Figure 1-1 Color Key ........................................................... 2
Figure 8-5 Suggested Direct Chip Attach Grid Pitch
Figure 3-1 Staggered Via .................................................... 3
(250 µm [9,843 µin] Grid; 150 µm
Figure 3-2 Staggered Microvias .......................................... 3 [5,906 µin] Bumps) ........................................... 30
Figure 3-3 Package Size and I/O Count ............................. 6 Figure 8-6 Type of CSP ..................................................... 31
Figure 3-4 Feature Pitch and Feature Size Defining Figure 8-7 Chip Scale Peripheral Package ....................... 32
Channel Width ................................................... 6
Figure 8-8 Printed Board Flip Chip or Grid Array
Figure 3-5 Routing and Via Grid for BGA Package ............ 7 Land Patterns .................................................. 32
Figure 3-6 Feature Pitch and Conductor Per Channel Figure 8-9 MSMT Land Drawing and Dimensions ............ 33
Combinations ..................................................... 8
Figure 8-10 Standard Grid Structure ................................... 34
Figure 4-1 PCB-HDI/Microvia Substrate (Application H) ... 11
Figure 8-11 Bump Footprint Planning ................................. 34
Figure 4-2 IC Carrier on HDI/Microvia Substrate
Figure 8-12 Redundant Footprint ........................................ 34
(Application I) ................................................... 11
Figure 8-13 Design Shrink Footprint ................................... 35
Figure 4-3 BGA Package on MCM-L Substrate Using
HDI-PCB Technology (Application I) ................ 11 Figure 8-14 Signal and Power Distribution Position ........... 35
Figure 5-1 Type I HDI Construction .................................. 15 Figure 8-15 Nested I/O Footprint ........................................ 35
Figure 5-2 Type II HDI Construction ................................. 16 Figure 9-1 Summary of the Manufacturing Processes
for PIDs, Laser and Plasma Methods of
Figure 5-3 Type III HDI Construction (Caution:
Unbalanced constructions may result in Via Generation ................................................. 36
warp & twist.) ................................................... 16 Figure 9-2 Microvia Manufacturing Processes .................. 37

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IPC-2226 April 2003

Figure 9-3 Cross-Sectional Views of Methods to Table 5-2 Minimum Drilled Hole
Make HDI with Microvias ................................. 37 Size for Plated-Through Hole Vias ................... 15
Figure 9-4 Four Typical Constructions that Employ Table 6-1 Final Metal Signal Trace (30 µm [1,181 µin])
Lasers for Via Generation ................................ 38 Resistances (example) ...................................... 21
Figure 9-5 Four Typical Constructions Utilizing Table 6-2 Final Metal Power Trace (60 µm [0.00236 in])
Etched or Mechanically Formed Vias .............. 38 Resistances (example) ...................................... 21
Figure 9-6 Four Commercially Produced PID Boards ...... 39 Table 7-1 Typical Thermal Resistance for Variable
Figure 9-7 Four New HDI Boards that Employ Bump Options (Triple Layer Chip) .................... 23
Conductive Pastes as Vias .............................. 39 Table 7-2 Typical Bump (150 µm) [5,906 µin]
Figure 9-8 Stacked Microvias ............................................ 39 Thermal Resistance Multilayer Metal Chips ..... 23

Figure 9-9 Stacked Vias .................................................... 40 Table 8-1 Pitch Dimensions .............................................. 28

Figure 9-10 Staggered Microvias ........................................ 40 Table 8-2 Examples of Fixed Square Body Size
Showing Maximum I/O Capability ..................... 29
Figure 9-11 Isometric View of Staggered Vias ................... 40
Table 8-3 Example of Fixed Rectangular Body Size ........ 30
Figure 9-12 Variable Depth Vias/Microvias ......................... 41
Table 8-4 Bump Diameter and Minimum Pitch Options ... 30
Figure 10-1 Wiring Factor Model for Tightly
Coupled Components ...................................... 44 Table 8-5 Chip Edge Seal Dimensions (Typical) .............. 33

Figure 10-2 Wiring Process Flow Chart .............................. 45 Table 10-1 Number of Conductors for Gridded Router
When Feature Pitch is 2,500 µm [98,425 µin] .. 42
Table 10-2 Number of Conductors for Gridded Router
When Feature Pitch is 1,250 µm [49,213 µin] .. 42
Table 10-3 Number of Conductors for Gridded Router
Tables When Feature Pitch is 650 µm [25,591 µin] ..... 42
Table 10-4 Number of Conductors for Gridded Router
Table 3-1 PCB Design/Performance Tradeoff Checklist ..... 3 When Feature Pitch is 500 µm [19,685 µin] ..... 42
Table 4-1 Sample Dielectric Insulator Designation ............. 9 Table 10-5 Number of Conductors for Gridded Router
Table 4-2 Sample Conductor Designation .......................... 9 When Feature Pitch is 250 µm [9,843 µin] ....... 43
Table 4-3 Dielectric with Conductor Designations .............. 9 Table 10-6 Pad Rows that can Escape per HDI Layer
Table 5-1 Typical Feature Sizes for HDI Construction, for Different Feature Sizes ................................ 43
µm [mil] .............................................................. 14 Table 10-7 Efficiencies ........................................................ 44

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April 2003 IPC-2226

Sectional Design Standard for High

Density Interconnect (HDI) Printed Boards

1 SCOPE The designations in this section determine the HDI design

This standard establishes requirements and considerations type by defining the number and location of HDI layers
for the design of organic and inorganic high density inter- that may or may not be combined with a substrate (core [C]
connect (HDI) printed boards and its forms of component or passive [P]).
mounting and interconnecting structures. For instance, an HDI printed board with two layers of HDI
on one side of the core and one layer of HDI on the other
1.1 Purpose The requirements contained herein are side of the core would be 2 [C] 1.
intended to establish design principles and recommenda-
tions that shall be used in conjunction with the detailed The following definitions apply to all forms of HDI.
requirements of IPC-2221. In addition, when the core
TYPE I 1 [C] 0 or 1 [C] 1 - with through vias connecting
material reflects requirements identified in the sectional
the outer layers (see 5.2.1).
standards (IPC-2222, IPC-2223, IPC-2224 and IPC-2225),
that information becomes a mandatory part of this stan- TYPE II 1 [C] 0 or 1 [C] 1 - with buried vias in the core
dard. and may have through vias connecting the outer layers (see
The standard provides recommendations for signal, power, 5.2.2).
ground and mixed distribution layers, dielectric separation,
TYPE III ≥2 [C] ≥0 - may have buried vias in the core and
via formation and metallization requirements and other
may have through vias connecting the outer layers (see
design features that are necessary for HDI-advanced IC
5.2.3).
interconnection substrates. Included are trade-off analyses
required to match the mounting structure to the selected TYPE IV ≥1 [P] ≥0 - where P is a passive substrate with
chip set. no electrical connection (see 5.2.4).

1.2 Document Hierarchy Document hierarchy shall be TYPE V Coreless constructions using layer pairs (see
in accordance with the generic standard IPC-2221. 5.2.5).

TYPE VI Alternate constructions (see 5.2.6).

1.3 Presentation All dimensions and tolerances in this
standard are represented in SI (metric) units with Imperial 1.6 Via Formation Via formation may be different from
units following as a hard conversion for reference only that considered in IPC-2221 since additional methods for
(e.g., 0.01 cm [0.0039 in]). via formation, in addition to drilled vias, will be used. The
methods for via formation, lamination/coating and sequen-
1.4 Interpretation Interpretation shall be in accordance tial layer process are covered in 9.1.1.
with the generic standard IPC-2221.
1.7 Design Features Figure 1-1 provides a color key to
1.5 Classification of HDI Types Classification shall be be used with all of the figures within this standard.
by category in accordance with the requirements based on
2 APPLICABLE DOCUMENTS
end use and as stated in 1.5.1 and 1.5.2 of this standard.
The following documents form a mandatory part of this
standard and all requirements stated therein apply, unless
1.5.1 Core Types When HDI products utilize core inter-
modified in the section where they are invoked.
connections, the core type(s) and their materials shall be in
accordance with IPC-2222 for rigid and IPC-2223 for flex- The revision of the document in effect at the time of solici-
ible core interconnections. For passive or constraining core tation shall take precedence over the applicable section of
boards the materials shall be in accordance with IPC-2221. this document.

2.1 IPC1
1.5.2 HDI Types The design designation system of this
standard recognizes the six industry approved design types IPC-T-50 Terms and Definitions for Interconnecting and
(see 5.2) used in the manufacture of HDI printed boards. Packaging Electronic Circuits

1. www.ipc.org