Program Control Instructions: This group of instructions includes instruction

related to Stack Control and Branch Group.

Stack: It is group of memory locations in RAM defined by user. It stores data temporarily in
case there is shortage of available general purpose registers. To store the data in this stack we
push the contents of register on to stack and these register would be free to be used. After that
function is completed, the previous contents are popped from stack and stored in the register.
Similar to Program Counter, Stack Pointer (SP) is the memory pointer in the stack. It uses the
concept of LIFO. While Pushing the data in the stack area, the SP decrements after each write.
Similarly, while Poping increments the address first then pops the data.

I. PUSH Rp  e.g., PUSH B where B is the register pair BC. This instruction pushes the
contents of register pair on to the stack. The SP pushes the content of B register to the
address pointed by Stack Pointer.
Before Execution After Execution

A S Z AC P CY A x x x x xx xx
B=20 C=30 B=20 C=30
D E D E
H L H L
SP(FFFF) SP(FFFD)
PC PC

0000H 0000H

FFFDH 88 FFFDH 88
FFFEH 9A FFFEH 30
36 20
FFFFH FFFFH
II. POP Rp  e.g., POP D where D is the register pair DE. This instruction pop off the stack
contents to register pair. When this instruction is executed, the contents of the memory
location pointed by the stack pointer (SP) register are copied to the low order register
pair. The SP is incremented by one and the contents of that memory location are copied
to the higher order register of register pair. The SP is incremented by 1. The process of
POP is exactly opposite to that of PUSH. So, the contents stored by PUSH are taken back
using POP instructions.

Before Execution After Execution

A S Z AC P CY A x x x x xx xx
B C B C
D=01 E=02 D=30 E=20
H L H L
SP(FFFD) SP(FFFF)
PC PC

0000H 0000H

FFFDH 20 FFFDH 20
30 FFFEH 30
FFFEH
90 90
FFFFH FFFFH
III. SPHL: This instruction loads the stack pointer with HL register pair contents. When this
instruction is executed, the contents of HL pair are transferred to stack pointer register. H
register contents to high order 8-bits and L register contents to low order 8-bits. The
contents of H and L are not altered.

Before Execution After Execution

A S Z AC P CY A x x x x xx xx
B C B C
D E D E
H=01 L=09 H=01 L=09
SP(FFFD) SP(0109)
PC PC

IV. XTHL: This instruction exchanges the HL with top of stack. When this instruction is
executed, the contents of L register are exchanged with the stack location pointed by the
stack pointer. The contents of H register are exchanged with the next stack location
(SP+1). The contents of the stack pointer register are not altered. No flags are modified.

Before Execution After Execution

A S Z AC P CY A x x x x xx xx
B C B C
D E D E
H=01 L=20 H=06 L=05
SP(FFFD) SP(FFFD)
PC PC

0000H 0000H

FFFDH 05 FFFDH 20
FFFEH 06 FFFEH 01
90 90
FFFFH FFFFH
V. NOP: This instruction does no operation

When this instruction is executed no operation is performed. The instruction is fetched

and decoded, no operation is executed and microprocessor will go for the next instruction
after that. This instruction can be used as a small delay of 4T states or if you have to
delete any instruction from your program you can use NOP instead of that instruction.

VI. HLT: This instruction halts and enters wait state.

When this instruction is executed, the microprocessor completes the execution and halts
any further execution. The microprocessor enters the halt acknowledge machine cycle
and wait states are inserted in every clock period. The address and data bus are placed in
high impedance state. The contents of the registers are not modified in this state.

To come out of this state the microprocessor must be interrupted or resetted. If

interrupted, the microprocessor executes a call location. Because of call, PC contents are
stored on to stack i.e. the address of next instruction. Microprocessor completes
ISR(Interrupt Service Routine) and with return instruction it returns back to next
instruction after halt.

When the reset signal is applied, PC is loaded with 0000 and execution starts from 0000
address onwards. This instruction is generally used to terminate the program execution.
In multiple ending programs at each end this instruction can be used in order to avoid
unnecessary jumps to terminate the program.
 Branch Group:

The microprocessor executes machine codes in a sequential manner. It goes on executing

from one memory location to the next. Branch group of instruction instructs the
microprocessor to go to different memory location. It continues executing machine codes
from that new location. The address of the new memory location is either specified in the
instruction or supplied by the microprocessor or given by extra hardware. The branch
group can be divided as:

Jump Instruction:
I. JMP address
II. Conditional Jump Instructions
III. PCHL

Call and Return Instruction

I. CALL address
II. Conditional CALL instructions
III. RET
IV. Conditional RET instructions

Restart Instructions
I. RST N

I. JMP Address: This is an unconditional jump instruction where the address is specified in
the instruction. When this instruction is executed, it directs the microprocessor about the
jump and its address where the microprocessor has to transfer its control. The storing
format is Opcode, Low order address and Higher order address.

E.g: JMP C200H where JMP is the opcode, C200H is the 16-bit address.

II. Conditional JMP Instructions: In conditional jump instructions, when the condition is true
or satisfied then only the jump is made at the specified address. If the condition is false or
not satisfied it will just check and proceed further to execute the next instruction after it.
 Different available conditional jumps are as follows:

JC – Jump if carry flag is set.

JNC – Jump if carry flag is reset.
JZ – Jump if zero flag is set.
JNZ - Jump if zero flag is reset.
JP – Jump if positive i.e. sign flag is set.
JM – Jump if negative i.e. sign flag is reset.
JPE – Jump if parity even i.e. parity flag is set.
JPO – Jump if parity odd i.e. parity flag is reset.

Note: No Jump on auxiliary carry flag.

Example JZ C200 : This instruction checks the zero flag. If the zero flag is set, condition
is true and the program control is transferred to the address C200H. If zero flag is reset,
condition is false and the program control is not transferred instead it will execute the
next instruction after JZ C200.

III. PCHL: This instruction loads program counter with HL contents. The contents of H and
L registers are transferred to Program Counter. The H contents to high order 8-bits and L
contents to low order 8-bits of program counter. This instruction is equivalent to a 1byte
unconditional jump instruction. A program sequence can be changed to any location by
simply loading the H and L registers with address and by using this instruction.
Example: LXI H C200H
PCHL
The LXI H instruction initializes HL pair with C200 contents H=C2 and L=00. When
PCHL is executed HL contents are transferred to PC and PC=C200, so the next
instruction executed will be from C200 address.
IV. CALL Address: This instruction is an unconditional call subroutine. When this
instruction is executed the program sequence is transferred to the address specified in the
instruction. Before transferring the sequence the PC contents are stored on to stack i.e.
higher order byte and then lower order byte. The call instruction is used to call a
subroutine. To return back from the subroutine, the PC contents are stored on to the stack.

Before Execution After Execution

A S Z AC P CY A x x x x xx xx
B C B C
D E D=30 E=20
H L H L
SP(C7FF) SP(C7FD)
PC(C006) PC(C200)

0000H 0000H

C006H CD C006H CD
C007H 00 C007H 00

C200H C200H
C201H

X C7FDH
C7FFH C7FEH 06
C7FFH C0

Example: CALL C200H

C006H Opcode of Call

C007H 00H

C008H C2H

C009H Next Instruction

When this instruction is executed, program counter contents C009 will be stored on to the
stack and microprocessor starts executing instructions from C200H onwards.
 V. Condition Call Instructions: In conditional CALL instruction, when the condition is true,
then a CALL at new address is made. If the condition is false then it will not have a
CALL and will proceed for next instruction after it. Different conditional CALL
instructions available are:

CC – Call, if carry flag is set.

CNC – Call, if carry flag is reset.
CP – Call, if positive i.e. sign flag is reset.
CM - Call, if minus i.e. sign flag is set.
CPE – Call, if parity even i.e. parity flag is set.
CPO – Call, if parity odd i.e. parity flag is
reset. CZ – Call, if zero flag is set.
CNZ – Call, if zero flag is reset.

Example: CC C200H

Call if carry flag is set, the program written from address C200H onwards will be executed.
If carry flag is reset microprocessor will execute next instruction after CC C200H.
VI. RET: This instruction will return from the subroutine. When this instruction is executed
program sequence is transferred from subroutine to the calling program. The return
address is taken from stack (where the call instruction has stored its PC contents i.e.
return address) this address is loaded in PC and the program execution begins at address
taken from stack.

Before Execution After Execution

A S Z AC P CY A x x x x xx xx
B C B C
D E D=30 E=20
H L H L
SP(C7FD) SP(C7FF)
PC(C209) PC(C009)

0000H 0000H

C006H C008H
C009H
C200H
C208H
C209H
C209H RET Opcode RET Opcode
C7FDH 09
C7FEH C0
C7FDH 09 C7FFH X
C7FEH C0
VII. Conditional RET Instructions: In this type of instructions, when the condition is true, then
only the RET is made at the address given by the stack. If condition is false, it will
proceed further to execute the next instruction after it.

Different conditional RET’s available are:

RC – Return from subroutine, if carry flag is set.

RNC – Return from subroutine, if carry flag is reset.
RZ – Return from subroutine, if zero flag is set.
RNZ - Return from subroutine, if zero flag is reset.
RP - Return from subroutine, if positive i.e. if sign flag is reset.
RM - Return from subroutine, if minus i.e. if sign flag is set.
RPO- Return from subroutine, if odd parity i.e. if parity flag is reset.
RPE - Return from subroutine, if even parity i.e. if parity flag is set.

VIII. RST N: These instructions are equivalent to 1 byte CALL instruction at restart location.
The contents of the PC are saved on to stack and program jumps to the address. These
instructions can be used as software interrupts in a program to transfer program execution
to one of the 8 locations depending on which RST instruction is executed.

Restart instructions and its locations are as follows:

Instructions Restart Locations

RST 0 0000

RST 1 0008

RST 2 0010

RST 3 0018

RST 4 0020

RST 5 0028

RST 6 0030

RST 7 0038