Chapter 9. Controller Design: 9.2. Effect of Negative Feedback On The Network Transfer Functions
Chapter 9. Controller Design: 9.2. Effect of Negative Feedback On The Network Transfer Functions
Chapter 9. Controller Design: 9.2. Effect of Negative Feedback On The Network Transfer Functions
Controller Design
9.1. Introduction
9.2. Effect of negative feedback on the network transfer
functions
9.2.1. Feedback reduces the transfer function from disturbances
to the output
9.2.2. Feedback causes the transfer function from the reference
input to the output to be insensitive to variations in the gains
in the forward path of the loop
9.3. Construction of the important quantities 1/(1+T) and
T/(1+T) and the closed-loop transfer functions
9.4. Stability
9.4.1. The phase margin test
9.4.2. The relation between phase margin and closed-loop
damping factor
9.4.3. Transient response vs. damping factor
9.5. Regulator design
9.5.1. Lead (PD) compensator
9.5.2. Lag (PI) compensator
9.5.3. Combined (PID) compensator
9.5.4. Design example
Transistor
gate driver Switching converter
δ(t) δ(t) Pulse-width vc(t) v(t) = f(vg , iload , d)
modulator vg(t)
dTs Ts t
iload (t) } Disturbances
v(t)
d(t)
} Control input
Fundamentals of Power Electronics 4 Chapter 9: Controller design
The dc regulator application
Switching converter
Objective: maintain constant v(t) = f(vg , iload , d)
output voltage v(t) = V, in spite vg(t)
of disturbances in vg(t) and
iload(t).
Typical variation in vg(t): 100Hz
iload (t) } Disturbances
v(t)
So we cannot expect to set the duty cycle to a single value, and obtain
a given constant output voltage under all conditions.
Negative feedback: build a circuit that automatically adjusts the duty
cycle as necessary, to obtain the specified output voltage with high
accuracy, regardless of disturbances or component tolerances.
vg + v
–
Sensor
– H(s) gain
Transistor Error
gate driver signal
δ Pulse-width vc G (s) ve –+ Hv
modulator c
Compensator
Reference
input vref
Fundamentals of Power Electronics 7 Chapter 9: Controller design
Negative feedback
Switching converter
v(t) = f(vg , iload , d)
vg(t)
Error
signal
ve(t)
iload (t)
vc Pulse-width d(t)
} Disturbances
v(t)
vref +– Compensator
modulator
} Control input
Reference
input
Sensor
gain
1 : M(D)
+
–
+
–
Output voltage can be expressed as
v(s) = Gvd(s) d(s) + Gvg(s) vg(s) – Z out(s) i load(s)
where
v(s) v(s) v(s)
Gvd(s) = Gvg(s) = Z out(s) = –
d(s) vg = 0 vg(s) d=0 i load(s) d=0
i load = 0 i load = 0 vg = 0
e(s)d(s) Le
1 : M(D)
+
–
• Use small-signal +
converter model
vg(s) + j(s)d(s) C v(s) iload (s)
– R
• Perturb and
linearize remainder –
of feedback loop:
d(s)
Error
vref (t) = Vref + vref (t) signal
vref (s) +– ve (s) vc (s) 1
Gc (s)
ve(t) = Ve + ve(t) Reference
VM
input Compensator Pulse-width
etc. modulator
H(s)v(s)
H(s)
Sensor
gain
H(s) v(s)
H(s)
Sensor
gain
v(s) Z out(s)
=
– i load(s) vref = 0 1 + T(s)
vg = 0
If the loop gain is large in magnitude, i.e., || T || >> 1, then (1+T) ≈ T and
T/(1+T) ≈ T/T = 1. The transfer function then becomes
v(s)
≈ 1
vref (s) H(s)
V = 1 T(0)
≈ 1
Vref H(0) 1 + T(0) H(0)
Example
80 dB
1 + ωs
z
|| T || T(s) = T0
QdB 1+ s + s 2
1 + ωs
60 dB | T0 |dB Qω p1 ω p1 p2
fp1
40 dB
– 40 dB/decade
20 dB
fz
– 20 dB/decade
0 dB
fc fp2
–20 dB Crossover – 40 dB/decade
frequency
–40 dB
1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
T ≈ 1 for || T || >> 1
1+T T for || T || << 1
1 for || T || >> 1
1 ≈ T(s)
1+T(s) 1 for || T || << 1
80 dB
T ≈ 1 for || T || >> 1
1+T T for || T || << 1
60 dB
fp1 || T ||
40 dB
Crossover
20 dB frequency
fz
– 20 dB/decade fc
0 dB
T fp2
–20 dB 1+T – 40 dB/decade
–40 dB
1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
f
Fundamentals of Power Electronics 18 Chapter 9: Controller design
Example: analytical expressions for approximate
reference to output transfer function
80 dB
1 for || T || >> 1
60 dB | T0 |dB QdB 1 ≈ T(s)
1+T(s) 1 for || T || << 1
fp1
40 dB
|| T ||
– 40 dB/decade
20 dB
fz
– 20 dB/decade
0 dB
+ 20 dB/decade fc fp2
–20 dB
fz Crossover – 40 dB/decade
frequency
+ 40 dB/decade
–40 dB
– | T0 |dB fp1 1
1+T
–60 dB QdB
–80 dB
1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
f
Fundamentals of Power Electronics 20 Chapter 9: Controller design
Interpretation: how the loop rejects disturbances
–20 dB –90˚
ϕm
–40 dB –180˚
–270˚
∠T fp2 fc
0 dB 0˚
–20 dB –90˚
–40 dB –180˚
ϕm (< 0)
–270˚
40 dB || T || f0
|| T || ∠T
f
20 dB
– 20 dB/decade
f0
Consider the 0 dB
case where T(s) f2 f0 f2
–20 dB f2
can be well-
approximated in –40 dB 0˚
– 40 dB/decade
the vicinity of the ∠T – 90˚
f2 /10
–90˚
crossover f2
ϕm
frequency as –180˚
10f2
T(s) = 1
s 1 + ωs
–270˚
ω0 2 f
If
T(s) = 1
s 1 + ωs
ω0 2
Then
T(s) 1 1
= =
1 + T(s) 1+ 1 1 + s + s2
T(s) ω 0 ω 0ω 2
or,
T(s) 1
=
1 + T(s) 1 + s + ωs
2
Qωc c
where
ω ω0
ωc = ω0ω2 = 2π fc Q = ω0 = ω2
c
ω ω0
Q = ω0 =
c ω2 low-Q approximation: Q ωc = ω0 ωc
= ω2
Q
40 dB || T || f0
f
20 dB
– 20 dB/decade
fc = f0 f2
0 dB
T f0 Q = f0 / fc
1+T
–20 dB
f2
–40 dB f0 f2 – 40 dB/decade
f2
f
Fundamentals of Power Electronics 31 Chapter 9: Controller design
High-Q case
ω ω0
ωc = ω0ω2 = 2π fc Q = ω0 = ω2
c
60 dB f0
|| T || f
40 dB
– 20 dB/decade
20 dB f2
Q = f0 /fc
0 dB
T fc = f0 f2 f0
1+T
–20 dB
f0 f2 – 40 dB/decade
f2
–40 dB
f
Fundamentals of Power Electronics 32 Chapter 9: Controller design
Q vs. ϕm
cos ϕ m
Q=
sin ϕ m
1+ 1 + 4Q 4
ϕ m = tan -1
2Q 4
10 dB
5 dB
0 dB Q = 1 ⇒ 0 dB
ϕm = 52˚
–5 dB
Q = 0.5 ⇒ –6 dB
–10 dB ϕm = 76˚
–15 dB
–20 dB
0° 10° 20° 30° 40° 50° 60° 70° 80° 90°
ϕm
Fundamentals of Power Electronics 34 Chapter 9: Controller design
9.4.3. Transient response vs. damping factor
2Q e -ωct/2Q 4Q 2 – 1
v(t) = 1 + sin ωc t + tan -1 4Q 2 – 1 Q > 0.5
4Q 2 – 1 2Q
ω ω Q < 0.5
v(t) = 1 – ω –2ω e –ω1t – ω –1ω e –ω2t
2 1 1 2
ωc
ω 1, ω 2 = 1± 1 – 4Q 2
2Q
2
Q = 50
v(t) Q = 10
Q=4
1.5
Q=2
Q=1
1
Q = 0.75
Q = 0.5
Q = 0.3
Q = 0.2
0.5
Q = 0.1
Q = 0.05
Q = 0.01
0
0 5 10 15
ωc t, radians
Typical specifications:
• Effect of load current variations on output voltage regulation
This is a limit on the maximum allowable output impedance
• Effect of input voltage variations on the output voltage
regulation
This limits the maximum allowable line-to-output transfer
function
• Transient response time
This requires a sufficiently high crossover frequency
• Overshoot and ringing
An adequate phase margin must be obtained
The regulator design problem: add compensator network Gc(s) to
modify T(s) such that all specifications are met.
1 + ωs fp
z
Gc(s) = Gc0 Gc0
1 + ωs fz fp
p || Gc || Gc0
fϕmax
fz
= fz fp
Improves phase
margin
fp /10 10fz
+ 45˚/decade
fz /10
0˚ – 45˚/decade
∠ Gc
60˚
fp fz
–
45˚
fz fp
∠ Gc( fϕmax) = tan -1
2
30˚
15˚
fp 1 + sin θ
=
fz 1 – sin θ
0˚
1 10 100 1000 θ =-Gc( fϕmax)
fp / fz
To obtain the maximum improvement in phase margin, we should design our compensator so that the frequency fϕmax coincides with the loop gain crossover frequency fc
1 – sin θ fp
fz = fc Gc0
fz fp
1 + sin θ || Gc || Gc0
fϕmax
1 + sin θ fz
= fz fp
fp = fc
1 – sin θ
fp /10 10fz
If it is desired that the magnitude + 45˚/decade
of the compensator gain at fc be fz /10
0˚ – 45˚/decade
unity, then Gc0 should be chosen ∠ Gc
as
fz f
Gc0 =
fp
60 dB
T0
40 dB || T || T0 Gc0 Original gain
|| T || ∠T
20 dB
Compensated gain f0
0 dB fz
fc
–20 dB fp
Compensated phase asymptotes
0˚
–40 dB 0˚
∠T
Original phase asymptotes –90˚
ϕm
–180˚
–270˚
f
|| Gc ||
ω
Gc(s) = Gc∞ 1 + sL
– 20 dB /decade Gc∞
Improves low- fL
frequency loop gain
and regulation
10fL 0˚
∠ Gc
+ 45˚/decade
– 90˚
fL /10
original
|| T ||
(uncompensated) 40 dB
loop gain is Gc∞Tu0
Tu0 20 dB fL f0
Tu(s) =
1 + ωs || Tu || Tu0 fc
0 0 dB
f0
compensator: –20 dB 90˚
ω
Gc(s) = Gc∞ 1 + sL ∠ Tu
–40 dB 0˚
10fL
Design strategy:
–90˚
choose ∠T 10f0 ϕm
Gc∞ to obtain desired –180˚
crossover frequency
ωL sufficiently low to 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
maintain adequate f
phase margin
Fundamentals of Power Electronics 43 Chapter 9: Controller design
Example, continued
|| T ||
40 dB
Gc∞Tu0
20 dB fL f0
fc
0 dB
–20 dB fL f0
1 1
1+T G c∞ T u0
–40 dB
ω
1 + sL 1 + ωs
z
Gc(s) = Gcm
1 + ωs 1 + ωs
40 dB p1 p2
|| Gc || ∠ Gc
|| Gc || fp2
20 dB fp1
Gcm fc
0 dB
fL fz
–40 dB 0˚
fp1 /10
– 90˚/decade
– 90˚ 90˚/decade
fz /10 10 fp1 –90˚
∠ Gc fL /10
–180˚
f
Fundamentals of Power Electronics 45 Chapter 9: Controller design
9.5.4. Design example
L
50 µH
+
iload
vg(t) + C R
v(t)
28 V – 500 µF 3Ω
Sensor
– H(s) gain
fs = 100 kHz
Transistor Error
gate driver signal
δ Pulse-width vc G (s) ve –+ Hv
modulator c
VM = 4 V Compensator vref
5V
V d
D2 1:D
L
+
–
+
Error d(s)
signal
vref (= 0) + ve (s) vc (s) 1
– Gc(s) VM
T(s)
Compensator VM = 4 V
H(s) v(s)
H(s)
H=1
3
60 dBV
|| Gvd || ∠ Gvd
40 dBV || Gvd || Q0 = 9.5 ⇒ 19.5 dB
Gd0 = 28 V ⇒ 29 dBV
Gvd(s) = V 1
f0
D 1 + s L + s 2LC 20 dBV
R ∠ Gvd 10 –1/2Q 0 f0 = 900 Hz
0 dBV 0˚
standard form:
–20 dBV –90˚
Gvd(s) = Gd0 1
1+ s + s 2
–40 dBV –180˚
Q 0 ω0 ω0 10 1/2Q 0
f0 = 1.1 kHz
–270˚
salient features:
Gvg(s) = D 1
1 + s L + s 2LC
R
Gvg(s) = Gg0 1
1+ s + s 2
Q 0 ω0 ω0
Output impedance:
Z out(s) = R || 1 || sL = sL
sC 1 + s L + s 2LC
R
VM = 4 V –
vref ( = 0 ) + ve(s) vc(s) +
1 d(s) v(s)
– Gc(s) VM Gvd (s)
Duty cycle +
variation
Converter power stage
T(s)
H=1
3
H(s)
40 dB
|| Tu || ∠ Tu
20 dB Q0 = 9.5 ⇒ 19.5 dB
|| Tu || Tu0 2.33 ⇒ 7.4 dB
0 dB f0
1 kHz
–20 dB
With Gc = 1, the – 1
10 2Q f0 = 900 Hz
– 40 dB/decade
0˚
loop gain is –40 dB 0˚
∠ Tu
1+ s + s 2
Q 0 ω0 ω0 –180˚
1
10 2Q f0 = 1.1 kHz
Tu0 = H V = 2.33 ⇒ 7.4dB –270˚
D VM 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
f
fc = 1.8 kHz, ϕm = 5˚
40 dB
|| Gc || fp ∠ Gc
Gc0
fz fp
20 dB || Gc || Gc0
fc
0 dB
fz = fz fp
–180˚
1 + ωs
z
T(s) = Tu0 Gc0
1 + ωs s + s 2
1+ ω0
p Q 0 ω0
40 dB
|| T || Q0 = 9.5 ⇒ 19.5 dB
∠T
|| T || T0 = 8.6 ⇒ 18.7 dB
20 dB
f0
0 dB 1 kHz fz
1.7 kHz fc
–20 dB 5 kHz fp
900 Hz 14 kHz
0˚
–40 dB 0˚
∠T 170 Hz
–90˚
1.4 kHz 17 kHz
ϕm=52˚
1.1 kHz –180˚
–270˚
1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
f
Fundamentals of Power Electronics 55 Chapter 9: Controller design
1/(1+T), with lead compensator
40 dB
Q0 = 9.5 ⇒ 19.5 dB
• need more
20 dB
|| T || T0 = 8.6 ⇒ 18.7 dB low-frequency
f0 loop gain
0 dB fz
1 fc • hence, add
1+T 1/T0 = 0.12 ⇒ – 18.7 dB inverted zero
–20 dB fp
Q0 (PID controller)
–40 dB
ω
1 + ωs 1 + sL
z
Gc(s) = Gcm
1 + ωs
40 dB p
|| Gc || || Gc || ∠ Gc
20 dB fp
fc • add inverted
Gcm
0 dB
fL fz zero to PD
compensator,
–20 dB
10fL 10fz 90˚ without
45˚/decade – 45˚/dec changing dc
–40 dB 0˚ gain or corner
fp /10
∠ Gc – 90˚ 90˚/decade frequencies
fz /10 –90˚
fL /10
• choose fL to be
–180˚
fc/10, so that
phase margin
1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz is unchanged
f
Fundamentals of Power Electronics 57 Chapter 9: Controller design
T(s) and 1/(1+T(s)), with PID compensator
60 dB
40 dB || T ||
Q0
20 dB
fL f0
0 dB fz
fc
–20 dB fp
1 Q0
–40 dB 1+T
–60 dB
–80 dB
1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
f
Fundamentals of Power Electronics 58 Chapter 9: Controller design
Line-to-output transfer function
v 20 dB
vg Q0
0 dB Gvg(0) = D
Open-loop || Gvg || f0
–20 dB D
T u0G cm
fL fz
–40 dB
fc
20 dB/decade
–60 dB
G vg – 40 dB/decade
–80 dB Closed-loop
1+T
–100 dB
Block 1 Block 2
A
Z1(s)
+
T(s)
H(s)
Tm (s)
H(s)
measured gain is
vy(s)
Tm(s) = Tm(s) = G1(s) G2(s) H(s)
vx(s) vref = 0
vg = 0
Express Tm as function of T:
Z 1(s)
Tm(s) = T(s) 1 +
Z 2(s)
Block 1 – vz + Block 2
i(s)
Z1(s) Zs(s)
0 – +
+ –
Tv (s)
H(s)
Block 1 – vz + Block 2
i(s)
Network analyzer 0
Z1(s)
–
Zs(s)
+
measures vref (s) +– ve (s) G2 (s) vx (s) = v(s)
G1 (s) ve (s) + vy (s) vx (s) Z2(s)
–
vy(s)
Tv(s) = + –
vx(s) vref = 0
vg = 0 Tv (s)
H(s)
Solve block diagram:
ve(s) = – H(s) G2(s) vx(s)
Z 1(s)
(ii) T(s) >>
Z 2(s)
Block 1 Block 2
vz
50 Ω Z 1(s) = 50Ω
+
–
– + Z 2(s) = 500Ω
Z 1(s)
+ = 0.1 ⇒ – 20dB
– vy (s) vx (s) 500 Ω Z 2(s)
Z 1(s)
+ – 1+ = 1.1 ⇒ 0.83dB
Z 2(s)
100 dB
Z 1(s) Z (s)
Tv(s) = T(s) 1 + + 1
80 dB Z 2(s) Z 2(s)
60 dB || Tv ||
|| T ||
40 dB
20 dB
0 dB Z1
⇒ – 20 dB || Tv ||
Z2
–20 dB
|| T ||
–40 dB
10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz
f
i y(s)
Ti(s) =
i x(s) vref = 0
vg = 0
Block 1 Block 2
iy (s) ix (s)
Z1(s)
0 iz (s)
vref (s) +– ve (s) G2 (s) vx (s) = v(s)
G1 (s) ve (s) + Z2(s)
– Zs(s)
Ti (s)
H(s)
+ –
Tv (s)
H(s)