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Assignment

This document is about digital electronics and pulse technique lab assignment 5 submitted by M.K. Ataul Karim to Pranta Saha. It contains answers to 4 exercises involving implementing logic functions using multiplexers and converting between multiplexer representations. Exercise 1 involves a 3-input logic function implemented with a lookup table. Exercise 2 converts a 4-to-1 multiplexer truth table to a 2-to-1 multiplexer circuit. Exercise 3 similarly converts another 4-to-1 multiplexer truth table. Exercise 4 implements a 2-input logic function with a 2-to-1 multiplexer.

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92 views10 pages

Assignment

This document is about digital electronics and pulse technique lab assignment 5 submitted by M.K. Ataul Karim to Pranta Saha. It contains answers to 4 exercises involving implementing logic functions using multiplexers and converting between multiplexer representations. Exercise 1 involves a 3-input logic function implemented with a lookup table. Exercise 2 converts a 4-to-1 multiplexer truth table to a 2-to-1 multiplexer circuit. Exercise 3 similarly converts another 4-to-1 multiplexer truth table. Exercise 4 implements a 2-input logic function with a 2-to-1 multiplexer.

Uploaded by

M.K. Ataul Karim
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Assignment-5

Course Title: Digital Electronics and Pulse Technique Lab


Course Code: CSE 224

Submitted To: Pranta Saha


Lecturer
School of Science, Engineering and Technology

East Delta University, Chittagong

Submitted By:
M.K. Ataul Karim
ID: 163001112
Submission Date: 28th July, 2020.
Exercise 2.1: f= A’B’+AC+BC; Using this function, make a LUT in DSCH.
Snip and show at least one logic output while running the simulation.
Answer:
Here,
f= A’B’+AC+BC
According to this function the truth table will be:
A B C Output (f)
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

DSCH circuit diagram for this equation:


LUT properties:

Timing Diagram of this function:


Exercise 2.2: Observe the following truth table:

(i) Implement the truth table using a 4-to-1 MUX


(ii) (ii) Convert the 4-to-1 MUX into a 2-to-1 MUX logic circuit (DSCH
needed)

Answer:
(i) Implement the truth table using a 4-to-1 MUX:
w1 w2 w3 f

Select pin 0 0 0 0 f=0


00
0 0 1 0
Select pin 0 1 0 0 f=w3
01
0 1 1 1
Select pin 1 0 0 0 f=w3
10
1 0 1 1
Select pin 1 1 0 1 f=1
11
1 1 1 1
4-to-1 MUX representation diagram of this truth table:

(ii) Convert the 4-to-1 MUX into a 2-to-1 MUX logic circuit in DSCH:
When, select pin w1=0, f= w2.w3
when, select pin w1=1, f= w2+w3
Timing diagram of this circuit:

Exercise 2.3: Observe the following truth table:

(i) Implement the truth table using a 4-to-1 MUX


(ii) Convert the 4-to-1 MUX into a 2-to-1 MUX logic circuit (DSCH needed)
Answer:
(i) Implement the truth table using a 4-to-1 MUX:
w1 w2 w3 f

Select pin 0 0 0 0 f=w3


00
0 0 1 1
Select pin 0 1 0 1 f=w3’
01
0 1 1 0
Select pin 1 0 0 1 f=w3’
10
1 0 1 0
Select pin 1 1 0 0 f=w3
11
1 1 1 1

4-to-1 MUX representation diagram of this truth table:


(ii) Convert the 4-to-1 MUX into a 2-to-1 MUX logic circuit in DSCH:
When, select pin w1=0, f= w2 XOR w3
when, select pin w1=1, f= w2 XNOR w3

Timing diagram of this circuit:


Exercise 2.4: f= A’B+BC’. Implement the function using a 2-to-1 MUX where
A is the select switch. (DSCH + truth table needed)
Answer:
Here, the function is f= AB’+BC’.
From this function we find this truth table where A is the select pin,
A B C f

Select pin 0 0 0 0 f= B+C


A=0
0 0 1 1
0 1 0 1
0 1 1 1
Select pin 1 0 0 0 f= BC’
A=1
1 0 1 0
1 1 0 1
1 1 1 0

2-to-1 MUX circuit of this function in DSCH:


Timing diagram of this function:

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