Lab 1 –

Code Conversion.
a. Introduction

In this lab we design and built a code converter using VHDL programming on the Nexys
4 DDR board. We are dealing with the simple code converter BCD to Excess-3. Excess- 3 is
similar to BCD but only 3 is added to the number and each number is defined by 4bit in binary.
We can see the conversion in the table below.

And further in this lab we generated a universal code converter using the above
implementation, where we used a select input where it selects if we want to convert BCD to
Excess-3 or Excess-3 to BCD.

b. Procedure

As this was the first lab which was more over an introduction to VHDL programming and
the Vivado workspace. So, we discussed the creation of the workspace and the project. At first, we
need to create new project in Vivado, select a RTL project, and select the language as VHDL.
After that we need to add a source file and hit create file and on next screen, we need to select the
board we are working on so in our case we need to select xc7a100tcsg324-1. This will create a
source file where we can implement our code.

For the implementation part we just need to specify some libraries on top which are needed.

Then we defined an entity called SimpleCodeConv, where we specified the input and
output arrays.

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 And in the main architecture we just added the negation to the input and then wrote the code
conversion logis and get them in the output.

For the universal code converter we need to add one more input in the entity.

We used process with if else loop in it for the condition in the select bit where if 0 we
convert from BCD to Excess-3 and if selected 1 we convert form Excess-3 to BCD.

c. Results

For the results we need to specify the pins on the board before running the synthesis,
implementation and generating the bits for the board. For this we need to add a constrain source
file for the Nexys 4 DDR board, which has an extension of XDC and full name of the file is
“Nexys-4-DDR-Master.xdc”. after adding this constrain file, we assign the switches as the inputs
and the led as the output foe the code converter, and one more switch for the select bit for the
universal converted.

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 Simulation results for the converter is shown below. We can see that the input 5 is
converted to 8 which is the excess-3 equivalent of the BCD input 5.

Now we are ready to run the synthesis and the implementation part and after that we get
the schematic diagram for the VHDL program.

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 This is the schematic of BCD to Excess-3 converter.

This is the schematic of the universal converter using the select bit.

After that we generate the bitstream for the board and upload it to the Nexys 4 DDR board.
After this we just run some tests on the board by giving inputs and observed that if we get proper
results.

Test 1- We gave the inputs as 0111 and the output is 1010 we can verify that its true form the
truth table.

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 Test 2- We gave input as 0100 then the output is 0111 which is also true.

Test 3- Here we use the universal converter where the select bit is 1, so it will do the excess-
3 to BCD conversion. We gave input as 1000 and the output we got is 0101.

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d. Discussion

Form the above results for the schematics and the actual results from the board
are verified using the truth table for the converters shown in the procedure. And the
main point for the discussion is that the system is working to its best on the Nexys 4
DDR board. And we got the essential knowledge for further labs which we covered.

e. Conclusion

We have got brief knowledge about the Vivado and process of how to run
synthesis, implementation and generate bitstream for the board. We also
implemented the BCD to Excess-3 converter. And then converted it to a universal
code converter sing a select bit. We learnt the basics of the VHDL programming
such as how to write entity, architecture and the process.

f. Reference
“742 Lab experiment 1 Handon”

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 Lab 2 –
Four Bit Ripple Carry Adder Subtractor
a. Introduction

The main goal of this lab is to get knowledge about the modular design technique. for
understanding this we have to implement the example of the 4-bit ripple carry adder. So, all the
required procedures and the concepts will get clear at the end of this experiment.

For a four bit ripple carry adder we need a 4 simple full adders, due to this concept we are
using the modular design technique in this implementation. Using any number of full adders, we
can generate any bit ripple carry adder. This is the replication technique used for when we can
use a small set of result for getting the full set of results as required. VHDL has the effective and
simple hierarchical design on the circuit. As we can test a small module independently and then
can be used where ever we need.

For the simple full adder, the truth table is shown below.

C-in A B Sum C-out

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

For the implementation of the 4 bit ripple carry adder we need 4 full adders as shown in
the figure below. Total we get 8 bits as the input, each number has 4 bits and one as a cin and for
selecting the operation addition or subtraction. These bits are input to the full adder in single bit
to each full adder for performing addition including carry.

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b. Procedure

This lab was more focused on the modular programming, so for that we first design a 1 bit
full adder which performs single bit addition. And further use this entity as a component in our 4
bit ripple carry adder.

Just like previous lab we created a new project in Vivado workplace. Add a source file
called full adder and add .xdc file for port mapping. And write a logic for the full adder in it and
try simulating it for the required results and when results are accurate then move on to the 4 bit
ripple carry adder. We can verify our results from the truth table above for the full adder.

For the full adder implementation, we need libraries for numeric bit and standard logic as
shown below.

Then we create an entity for full adder with a, b, c_in as inputs and sum, c_out as output.

In the architecture we created some logical wire signals which are needed for the
implementation. in wire1 we got the results for “a XOR b”, in wire2 we got results “wire1 AND
c_in”, in wire3 we got “a AND b”. and in the end, we use these wire for getting sum and c_out
for the final results. Logic for sum would be “wire1 XOR c_in”, and for c_out would be “wire2
OR wire3”.

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 If the results are satisfied, we can move for further implementation of the 4 bit ripple carry
adder. So, we need to add one more source file for the 4 bit ripple carry adder in the same project
as we would be using the fulladder entity in this code.

For the implementation of the 4 bit ripple carry adder, we need the libraries as always.
Then we wrote a new entity for 4bit ripple carry adder and called it rcadder. In there we specified
a generic width of the adder as 4 bits and the 2 inputs of input 4 bit each for the addition and out
output called sum of 5 bits.

And in the architecture, we imported the entity of full adder as a component here, so we
need to match the in and out bits as the original code.

Then we apply logic for the 4 bit ripple carry adder using the 1 bit adder and run this
code in loop for 4 times by incrementing the bits in array on inputs a and b and store the result
in S as wcarry and sum from the logic we used.

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c. Results

For the results we specified the switches as the input and the led for the output. For this we
need to add constrain file required by the board which was provided to us. At first, we simulated
the full adder code and checked if it is working or not and got the schematic design for that entity
which we will be using for the 4 bit adder. The implemented schematic generated for the full
adder is shown below.

Then we wrote the code for 4 bit ripple carry adder as mention in the procedure so then
we run synthesis, implementation and obtain the schematic for the 4 bit ripple carry adder. After
this we got the schematic for the 4 bit ripple carry adder as shown below.

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 Then we generated the bit stream for full adder code and uploaded it on the board. And
gave input a as 1 and b as 1 but the c_in is 0. Therefore, the sum must be 0 and the c_out must be
1 which is the desired output for the 1 bit full adder.

Then we generated bit stream for the 4 bit adder and uploader it on the board. And for
testing the logic, we gave input a as 1111 and b as 1111 so the sum we should get is 1110 and the
c_out must be 1. We can observe this on the board as highlighted we got the accurate output.

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d. Discussion

All the results we got were accurate and were verified using the truth table provided
for full adder and the 4 bit ripple carry adder. We also get all the required knowledge
regarding the modular designing in VHDL which was the main goal as we need to implement
more such code using modular techniques. We tested many addition and subtraction
examples for verifying that every odd condition is also satisfied in our system and there is
not any exceptional case for this

e. Conclusion

We studied the modular design technique using the example of the 4 bit ripple carry
adder and using the full adder component in it. We also got the implementation requirements for
the component and how it imports everything from the original entity of the full adder. and in the
end, we added the operation selection bit which triggers the XOR gates and we get the one’s
complement which is sued for the subtraction operation.

f. Reference
“742 Lab experiment 2 Handon”

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 Lab 3 –
Traffic Light Controller
a. Introduction

In this lab we have to design a traffic light controller using the Nexys 4 DDR board.
The main challenge in this implementation is to generate the timing of the lights. And in
this lab, we have implemented 2 types of traffic light controller 1st is the simple traffic
controller and the 2nd is using the sensors on each side of the interaction.

Before the actual implementation we designed the state diagram and the SM chart
for the traffic controller as shown below.

This is the Flow chart for the simple traffic light controller

From the above flow chart, we can see that for the N/S the green light for 10 sec
and then the it goes to yellow for 1 sec and then goes to red for 8 sec and then in the end it
goes for the green again. Similarly, in backwards it works for the E/W.

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 And for the traffic light controller with sensor the Flow chart is as follows. This
integrates the sensor used on each side on the intersection. If any vehicle is sensed on the
road then the lights would get trigged and change as we want to implement.

b. Procedure

For this implementation we need to add the required libraries such as std logic
1164 and std logic arith.

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 Then we specified the entity with the clock as an input and red, green, yellow output
for the N/S and E/W and named that entity as trafficControlFSM.

Then we wrote process for the working of the clock which changes the state and
resets the timer when we specify it in the other processes.

Then we implemented the switch case for changing the states from s0 to s5 and also
turn on/off the required lights in those states. For example, s0 is shown below and similar
to that other states are implemented.

Then we implemented the process for getting into next state from s0 to s5. For
example, we need to change the state form s0 to s1 when the timer is equal to 10 and have
to reset the timer in each state otherwise stay in s0 only. Similarly, for other states we reset
the timer for each state and specified the timer as we need for each state. One such condition
is shown below.

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c. Results

For this lab we just simulated the VHDL program we implemented. The results for
the simulation is shown below. We can observer from the results that the lights are getting
on and off for time we specified in the program and states are changing according.

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d. Discussion

In the simulation results we can observe that the states are changing as we wish
lights are getting on and off at the specified clocks rising edge. This shows that everything
we implemented is working properly. For the second implementation we used sensor on
each side of the intersection for getting info if there is any vehicle, so for that we used a
push button on the board which acts as a sensor in the implementation. when pressed it
detects that there is a vehicle present on the road and the signal must go green after particular
amount of time and gets red after some time.

Traffic light controller using D-flipflop

green

red

e. Conclusion

We successfully implement the traffic light controller using VHDL programming.

We learnt how to use the when and case statement in the VHDL programming, this explored
us to more to the switching conditions and how to use them in our code. We also learnt how
to use the clocks rising edge for changing the state in the program and doing so we parallelly
change the signals at each ends of the intersection. This solves many issues on the
intersection of any road.

f. Reference
“742 Lab experiment 8 Handon”

“Lecture notes”

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 Lab 4 –
Data Encryption Using LFSRs
a. Introduction

In this lab we need to study concepts regarding the cryptography and encryption on
the Nexys DDR 4 board. We got a bunch of encrypted ASCII text and have to decrypt
them using the specified method.

In this lab we just encrypt the 8 bit block of data using 8 bit key sequence, which is
easy for implementation other than the complex cryptography algorithms. The main logic
behind the cryptography is around the XOR operation. The main working of the
encryption can be explained using the block diagram below.

This seem easy but if we use the key which is known anyone can crack it at any
time. So, for avoiding this we need to change various aspects of the key dynamically during
the encryption and decryption at both the ends sender and receivers. So that it will get more
secure and cannot be cracked by anyone.

For the generation of a random key we use the LFSR with XOR gates placed at
random places. This will make sure that the key generated is not guessed by any one and
cannot violets the privacy. The simple design for this LFSR is shown below.

For ensuring that both the receiving and sending side uses the same key we must
need to specify somethings such as number of shifts in sampled key and the starting value
of LFSR bits. This will let both the user to use the same key for the encryption and
decryption and also provides additional security rather than using simple increment.

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b. Procedure

For the implementation of data encryption, we need to create new project as we

did in previous labs and create a source file called encrypt inside the project where the
actual implementation is done. Here we specify the required libraries in this code like
standard logic and the unsigned standard logic.

Then we constructed an entity where we initialized all the inputs and outputs we
will be needing. The inputs in this project will be clock, input string, key value, set for
the lfsr, and output will be original key, current key, etc.

Inside the architecture we imported the component of the debounce for

manipulating the data into plain text or cipher text depending on out=r need.

Then we must provide the LFSR control signals before beginning the process of
encryption. And also port the inputs for the debounce component. This can be done as
shown below.

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 Then the actual implementation of encryption using LFSR is done in the process.
We created an if else loop, if the debounce is set then lfsr is the key and else we used the
above lfsr process we discussed in introduction for encryption and get the encrypted data
and stored the data as we need in the outputs we initialied in the entity.

For the debounce component in above code we need to specify what it does, so we
need to write separate source file for that which includes required libraries at first followed
by the entity of the debounce with clock and button as input and result as a output.

Then in the actual architecture for debounce we specified the required signals and
start new process with clock which performs the debouncing logic for us which we used in
the data encryption using lfsr.

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c. Results

We did the simulation of this data encryption and got the simulation results as
shown below in the timing diagram.

The output form the timing diagram matches with the desired output which was
provide in the lab manual.

We also tried to synthesis and implement this experiment and we got the schematic
for this data encryption using lfsr system which is shown below. But we were not able to
generate bitstream for this so we didn’t uploaded this on the board for getting the results.

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d. Discussion

As security is the main concern while transferring data from source to destination.
We implemented an encryption algorithm for data security. We use LFSR for the
generation of random key sequence which would be used for the encryption process. We
got to know that the key must not be easy to detect and should be changing dynamically.
And for the results the output was matched as we need if for the inputs we provided. So
the encryption of the data is done as mentioned in the lab manual since the results are
matching to the provided results in the manual.

Data encryption using linear shift register and implemented on d-flipflops –

e. Conclusion

In this lab we studied how to encrypt and decrypt data using the lfsr. We also learnt
many aspects regarding the data security such as we cannot use same key always for the
encryption as anyone can hack into it, same key must be used at both the end of sending and
receiving. For lfsr we need to specify the starting point and the number of shifts in the key
value. Considering all this security issues we implemented a secure data encryption
algorithm.

f. Reference
“742 Lab experiment 9 Handon”

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