Stick diagram and Layout

Diagram
 INTRODUCTION

• Objectives:
– To know MOS layers
– To understand the stick diagrams
– To learn design rules
– To understand layout and symbolic diagrams

• Outcome:
– At the end of this, will be able draw the stick
diagram, layout and symbolic diagram for simple
MOS circuits

UNIT – II CIRCUIT DESIGN PROCESSES

 MOS LAYERS

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

• Objectives:
– To know what is meant by stick diagram.
– To understand the capabilities and limitations of
stick diagram.
– To learn how to draw stick diagrams for a given
MOS circuit.

• Outcome:
– At the end of this module the students will be able
draw the stick diagram for simple MOS circuits.

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

• VLSI design aims to translate circuit concepts

onto silicon.
• Stick diagrams are a means of capturing
topography and layer information using simple
diagrams.
• Stick diagrams convey layer information
through color codes (or monochrome
encoding).
• Acts as an interface between symbolic circuit
and the actual layout.
UNIT – II CIRCUIT DESIGN PROCESSES
 STICK DIAGRAMS

• Does show all components/vias.

– Via is used to connect higher level metals from metal connection

• It shows relative placement of components.

• Goes one step closer to the layout
• Helps plan the layout and routing

A stick diagram is a cartoon of a layout.

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

• Does not show

– Exact placement of components
– Transistor sizes
– Wire lengths, wire widths, tub boundaries
– Any other low level details such as
parasitics

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Stick Diagrams – Notations

Metal 1

poly
ndiff

pdiff
Can also draw
in shades of
gray/line style.
Buried Contact

Contact Cut

UNIT – II CIRCUIT DESIGN PROCESSES

STICK DIAGRAMS

NMOS ENCODING
UNIT – II CIRCUIT DESIGN PROCESSES
STICK DIAGRAMS

CMOS
ENCODING

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Stick Diagrams – Some Rules

Rule 1:
When two or more ‘sticks’ of the same type cross or touch
each other that represents electrical contact.

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Stick Diagrams – Some Rules

Rule 2:
When two or more „sticks‟ of different type cross or touch each
other there is no electrical contact.
(If electrical contact is needed we have to show the connection
explicitly)

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Stick Diagrams – Some Rules

Rule 3:
When a poly crosses diffusion it represents a transistor.

Note: If a contact is shown then it is not a transistor.

UNIT – II CIRCUIT DESIGN PROCESSES
 STICK DIAGRAMS

Stick Diagrams – Some Rules

Rule 4:
In CMOS a demarcation line is drawn to avoid touching of p-diff
with n-diff. All PMOS must lie on one side of the line and all
NMOS will have to be on the other side.

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

Vdd = 5V Vdd = 5V

pMOS
Vin Vout Vin Vout
nMOS

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

VDD
VDD
X

X
x x x
x X

Gnd Gnd

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

* Note the depletion mode device

Vdd = 5V

Vout
Vin

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

NOR gate and NAND using NMOS Transistors

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

f= [(xy) +z]‟ using NMOS Transistors

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

• Why we use design rules?

– Interface between designer and process engineer

• Historically, the process technology referred to the

length of the silicon channel between the source and
drain terminals in field effect transistors.
• The sizes of other features are generally derived as a
ratio of the channel length, where some may be larger
than the channel size and some smaller.
– For example, in a 90 nm process, the length of the channel may be 90
nm, but the width of the gate terminal may be only 50 nm.

UNIT – II CIRCUIT DESIGN PROCESSES

DESIGN RULES

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

• Allow translation of circuits (usually in stick

diagram or symbolic form) into actual
geometry in silicon
• Interface between circuit designer and
fabrication engineer
• Compromise
– designer - tighter, smaller
– fabricator - controllable, reproducible

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

• Design rules define ranges for features

– Examples:
• min. wire widths to avoid breaks
• min. spacing to avoid shorts
• minimum overlaps to ensure complete overlaps
– Measured in microns
– Required for resolution/tolerances of masks

• Fabrication processes defined by minimum channel

width
– Also minimum width of poly traces
– Defines “how fast” a fabrication process is

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

• Two major approaches:

– “Micron” rules: stated at micron resolution.
–  rules: simplified micron rules with limited
scaling attributes.
• Design rules represents a tolerance which insures
very high probability of correct fabrication
– scalable design rules: lambda parameter
– absolute dimensions (micron rules)

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

“Micron” rules

• All minimum sizes and spacing specified in

microns.
• Rules don't have to be multiples of λ.
• Can result in 50% reduction in area over λ
based rules
• Standard in industry.

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

Lambda-based Design Rules

• Lambda-based (scalable CMOS) design rules define

scalable rules based on  (which is half of the
minimum channel length)

– classes of MOSIS SCMOS rules: SUBMICRON, DEEPSUBMICRON

• Stick diagram is a draft of real layout, it serves as an

abstract view between the schematic and layout.

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

Lambda-based Design Rules

• Circuit designer in general want tighter, smaller layouts
for improved performance and decreased silicon area.
• On the other hand, the process engineer wants design
rules that result in a controllable and reproducible
process.
• Generally we find there has to be a compromise for a
competitive circuit to be produced at a reasonable cost.
• All widths, spacing, and distances are written in the
form
•  = 0.5 X minimum drawn transistor length

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

Lambda-based Design Rules

• Design rules based on single parameter, λ
• Simple for the designer
• Wide acceptance
• Provide feature size independent way of setting out
mask
• If design rules are obeyed, masks will produce working
circuits
• Minimum feature size is defined as 2 λ
• Used to preserve topological features on a chip
• Prevents shorting, opens, contacts from slipping out of
area to be contacted
UNIT – II CIRCUIT DESIGN PROCESSES
 DESIGN RULES
• Minimum width of PolySi and diffusion line 2
• Minimum width of Metal line 3 as metal lines run over a
more uneven surface than other conducting layers to ensure
their continuity

Metal

Diffusion
3

2 2 Polysilicon

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES
• PolySi – PolySi space 2
• Metal - Metal space 2
• Diffusion – Diffusion space 3 To avoid the possibility of
their associated regions overlapping and conducting
current

Metal
2
Diffusion

2 3 Polysilicon

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES
• Diffusion – PolySi space  To prevent the lines overlapping
to form unwanted capacitor
• Metal lines can pass over both diffusion and polySi without
electrical effect. Where no separation is specified, metal
lines can overlap or cross

Metal

Diffusion

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES
• Metal lines can pass over both diffusion and polySi without
electrical effect
• It is recommended practice to leave  between a metal edge
and a polySi or diffusion line to which it is not electrically
connected

Metal


Polysilicon

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

• Recall

– poly-poly spacing 2

– diff-diff spacing 3 (depletion regions tend to spread outward)

– metal-metal spacing 2

– diff-poly spacing 

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES
Butting Contact
The gate and source of a depletion device can be connected by a
method known as butting contact. Here metal makes contact to
both the diffusion forming the source of the depletion transistor
and to the polySi forming this device‟s gate.

Advantage:
No buried contact mask required and avoids associated processing.

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES
Buried Contact
Here gate length is depend upon the alignment of the buried
contact mask relative to the polySi and therefore vary by .

PolySi

 2  Channel length 

Buried contact 2

Diffusion
UNIT – II CIRCUIT DESIGN PROCESSES
 DESIGN RULES
Contact Cut
• Metal connects to polySi/diffusion by contact cut.
• Contact area: 2  X 2 
• Metal and polySi or diffusion must overlap this contact
area by l so that the two desired conductors encompass the
contact area despite any mis-alignment between
conducting layers and the contact hole

4

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES
Contact Cut
• Contact cut – any gate: 2  apart
• Why? No contact to any part of the gate.

4

2

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES
Contact Cut
• Contact cut – contact cut: 2  apart
• Why? To prevent holes from merging.

2

UNIT – II CIRCUIT DESIGN PROCESSES

DESIGN RULES

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

3
6

6

2
2

All device mask dimensions are based on multiples of , e.g., polysilicon minimum
width = 2. Minimum metal to metal spacing = 3

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES
Thinox

Metal 1
n-diffusion p-diffusion
3λ
2λ
3λ 3λ
2λ 3λ

Metal 2
2λ
4λ
2λ
2λ 4λ
Polysilicon
4λ

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

• Wells must surround transistors by 6 

– Implies 12  between opposite transistor flavors
– Leaves room for one wire track

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

• A wiring track is the space required for a wire

– 4  width, 4  spacing from neighbour = 8  pitch
• Transistors also consume one wiring track

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS

• Layer Types
– p-substrate
– n-well
– n+
– p+
– Gate oxide
– Gate (polysilicon)
– Field Oxide
• Insulated glass
• Provide electrical isolation

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS

N+ N+

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS
Top view of the FET pattern

NMOS NMOS PMOS PMOS

n+ n+ n+ n+ p+ p+ p+ p+

n-well

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS
Designing MOS Arrays
A B C

x y

A B C

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS
Parallel Connected MOS Patterning
x x
A B
A B

X X X
y
y

X X
A B
A B
X X

y y
UNIT – II CIRCUIT DESIGN PROCESSES
 LAYOUTS
The CMOS NOT Gate
Contact
Cut
Vp Vp
X n-well

X
x x
X
x
X
Gnd

Gnd

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS
The CMOS NAND Gate

Vp Vp

X X X
a.b

Gnd
a.b
a b
X X

a b
Gnd

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS
The CMOS NAND Gate

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS
The CMOS NOR Gate

UNIT – II CIRCUIT DESIGN PROCESSES