Verilog
Verilog
COMS W4995-02
f
b
sel
Multiplexer Built with Always
module mux(f, a, b, sel);
output f;
input a, b, sel; A reg behaves like
reg f; memory: holds its value
until imperatively
always @(a or b or sel)
if (sel) f = a; assigned otherwise
else f = b;
endmodule Body of an always block
contains traditional
a
imperative code
f
b
sel
Mux with Continuous Assignment
module mux(f, a, b, sel);
output f;
input a, b, sel;
assign f = sel ? a : b;
LHS is always set to
endmodule the value on the RHS
f
b
sel
Mux with User-Defined Primitive
primitive mux(f, a, b, sel);
output f;
input a, b, sel; Behavior defined using
table a truth table that
1?0 : 1; includes “don’t cares”
0?0 : 0; This is a less pessimistic than
?11 : 1;
?01 : 0; others: when a & b match, sel is
11? : 1; ignored; others produce X
00? : 0;
endtable a
endprimitive
f
b
sel
How Are Simulators Used?
Testbench generates stimulus and checks response
Coupled to model of the system
Pair is run simultaneously
Stimulus
Response
Result checker
Structural Modeling
When Verilog was first developed (1984) most logic
simulators operated on netlists
Netlist: list of gates and how they’re connected
A natural representation of a digital logic circuit
Not the most convenient way to express test benches
Behavioral Modeling
A much easier way to write testbenches
Also good for more abstract models of circuits
• Easier to write
• Simulates faster
More flexible
Provides sequencing
Verilog succeeded in part because it allowed both the
model and the testbench to be described together
How Verilog Is Used
Virtually every ASIC is designed using either Verilog or
VHDL (a similar language)
Behavioral modeling with some structural elements
“Synthesis subset” can be translated using Synopsys’
Design Compiler or others into a netlist
Design written in Verilog
Simulated to death to check functionality
Synthesized (netlist generated)
Static timing analysis to check timing
Two Main Components of Verilog:
Behavioral
Concurrent, event-triggered processes (behavioral)
Initial and Always blocks
Imperative code that can perform standard data
manipulation tasks (assignment, if-then, case)
Processes run until they delay for a period of time or wait
for a triggering event
Two Main Components of Verilog:
Structural
Structure (Plumbing)
Verilog program build from modules with I/O interfaces
Modules may contain instances of other modules
Modules contain local signals, etc.
Module configuration is static and all run concurrently
Two Main Data Types: Nets
Nets represent connections between things
Do not hold their value
Take their value from a driver such as a gate or other
module
Cannot be assigned in an initial or always block
Two Main Data Types: Regs
Regs represent data storage
Behave exactly like memory in a computer
Hold their value until explicitly assigned in an initial or
always block
Never connected to something
Can be used to model latches, flip-flops, etc., but do not
correspond exactly
Actually shared variables with all their attendant problems
Discrete-event Simulation
Basic idea: only do work when something changes
Centered around an event queue that contains events
labeled with the simulated time at which they are to be
executed
Basic simulation paradigm
• Execute every event for the current simulated time
• Doing this changes system state and may schedule
events in the future
• When there are no events left at the current time
instance, advance simulated time soonest event in the
queue
Four-valued Data
Verilog’s nets and registers hold four-valued data
0, 1: Obvious
Z: Output of an undriven tri-state driver. Models case
where nothing is setting a wire’s value
X: Models when the simulator can’t decide the value
• Initial state of registers
• When a wire is being driven to 0 and 1 simultaneously
• Output of a gate with Z inputs
Four-valued Logic
Logical operators work on three-valued logic
0 1 X Z
Outputs 0 if either
0 0 0 0 0
input is 0
1 0 1 X X
X 0 X X X Outputs X if both
Z 0 X X X inputs are gibberish
Structural Modeling
Nets and Registers
Wires and registers can be bits, vectors, and arrays
endmodule
Instantiating a Module
Instances of
module mymod(y, a, b);
look like
mymod mm1(y1, a1, b1); // Connect-by-position
mymod (y2, a1, b1),
(y3, a2, b2); // Instance names omitted
// Connect-by-name
mymod mm2(.a(a2), .b(b2), .y(c2));
Gate-level Primitives
Verilog provides the following:
always begin
wait(i);
a = 0;
wait(˜i);
a = 1;
end
Procedural Assignment
Inside an initial or always block:
sum = a + b + cin;
case (op)
2’b00: y = a + b;
2’b01: y = a - b;
2’b10: y = a ˆ b;
default: y = ’hxxxx;
endcase
For Loops
Example generates an increasing sequence of values on
an output
i = 0;
while (i <= 15) begin
output = i;
#10 i = i + 1;
end
Modeling A Flip-Flop With Always
Very basic: an edge-sensitive flip-flop
reg q;
while (˜ready)
count = count + 1;
Instead, use
wait(ready);
Simulation Behavior
Race conditions abound in Verilog
These can execute in either order: final value of a
undefined:
Delays
• May be in the Verilog source, but are simply ignored
Sequential:
reg q;
always @(d or clk)
q only assigned
if (clk) q = d;
when clk is 1
Register Inference
A common mistake is not completely specifying a case
statement
This implies a latch:
always @(a or b)
case ({a, b})
2’b00 : f = 0;
2’b01 : f = 1;
2’b10 : f = 1;
f is not assigned when
endcase
{a,b}= 2’b11
Register Inference
The solution is to always have a default case
always @(a or b)
case ({a, b})
2’b00 : f = 0;
2’b01 : f = 1;
2’b10 : f = 1;
default : f = 0; f is always assigned
endcase
Inferring Latches with Reset
Latches and Flip-flops often have reset inputs
Can be synchronous or asynchronous
Asynchronous positive reset: