Photovoltaic Energy Harvesting for Hybrid/Electric

Vehicles
Topology Comparison and Optimisation of a Discrete Power Stage for European Efficiency

Miodrag Nikolić, Horst Zimmermann

Institute of Electrodynamics, Microwave and Circuit Engineering (EMCE)
Vienna University of Technology (TU WIEN)
Gusshausstrasse 25/354, 1040 Vienna, Austria
{miodrag.nikolic, horst.zimmermann}@tuwien.ac.at

Abstract—This paper presents a topology comparison of a hybrid integrated power stage, controlled by maximum power point
low-voltage step-up dc-dc converter in terms of European tracking algorithms implemented using a microcontroller, DSP,
Efficiency. Such converters are suited to be integrated with solar or done in a custom ASIC [2], [3], [4], [5]. For instance, [3]
cells, thus forming a photovoltaic energy harvesting architecture gives a design example of photovoltaic powered portable
dedicated for an integrated realisation of a solar range extender system performing image processing and wireless
for electric vehicles. Except of a discrete power stage realisation, communication tasks. Reference [2] discusses fully
the rest of a system, such as control, time and power autonomous converter with an input power range spanning
management, shall be monolithically integrated in the AMS from 5 μW up to 10 mW, fabricated in a commercial TSMC
0.35μm HV CMOS process. Developed efficiency model allows
0.25 μm CMOS process with 5 metal layers and using one
straightforward comparison of different converter topologies, as
compact SMD inductor of 1 mH. Another example of
shown on an example of the dc-dc converter which supplies the
electric vehicle auxiliary board net (12 V) with photovoltaic integrated energy harvesting architecure is [4], where an
power up to 40 W from a stack of 9-10 solar cells. Optimisation of inductor-less on-chip micro power management system for
the design variables: the external power switches, and the light energy harvesting applications was designed and
converter switching frequency is outlined on a given example. implemented using an AMS 0.35 μm CMOS process.
Opposite to the latter examples which dealt with extremely
Keywords: dc-dc converter; boost converter; synchronous
low power processing (up to mW range), in the cases when
rectifier; energy harvesting; European Efficiency; renewable
energy; photovoltaics.
much higher photovoltaic-obtained electric power (an order of
value: several tens of Watts) has to be processed it turns out to
be very expensive to integrate power switches. Since it is
certainly the case in the discussed application, this paper
I. INTRODUCTION investigates solutions with a discrete power stage. An overview
of the essential research results of photovoltaic (PV) power
Effective use of photovoltaic energy resources is limited by generators installations, both grid-connected and stand-alone
power capacity of the solar cells, their orientation and applications is given in [5]. As well as the latter reference, also
incliniation angle in respect to sun, as well as by geographic- commercially available products of photovoltaic panels [6], [7]
dependent weather conditions. In order to maintain effective concentrate primarily to photovoltaic inverter realisations, i.e.
utilisation of solar energy for a priori defined photovoltaic- dc-ac converters. On the other hand, this work discusses a dc-
area, and given type of solar cells, the design goal is to keep dc converter being part of a photovoltaic conversion chain.
power processing of photovoltaic-obtained electric energy
highly efficient. Therefore, contributing to the European targets Conventional solutions in processing solar energy are not
for reducing CO2 emission, fossil fuel liquids consumption and suited for vehicle integration as they encounter two common
the development of “green technologies”, novel on board problems: (1) cell-mismatch loss in series-connected solar cell
integrated solar power generators are proposed within the stack due to shadowing of any single cell, (2) an impedance
Energy Efficient Electrical Car (E3Car) project [1] to provide mismatch between solar panel on a micro-level and load, which
an auxiliary way of charging hybrid/electric vehicles, and to has as a consequence non-maximal energy transfer. In order to
improve energy efficiency providing optimum utilisation of overcome the first issue, state-of-the-art photovoltaic panels
photovoltaic energy. use output bypass diodes [6], which should guide available
current around “weaker” groups of cells (input photovoltage
Up to now much work has been done in the field of the per group: 15-40 V). In that way, energy of such cell-groups
photovoltaics. A wide variety of applications have been remains unused and the rest of the cells might run out of the
considered, such as powering wireless devices [2], or satellite maximum power point of operation. The second issue is only
systems, emergency telephones, remote sensors, sun-powered partially handled by module-level maximum power point
radios, and space vehicles, according to [3]. Different tracking [7], dividing the whole photovoltaic panel in several
implementations were proposed, with either a discrete or

978-1-4673-1591-3/12/$31.00 ©2012 IEEE

planar (540×315 mm2) modules, which are individually MOSFET must be controlled such that it operates in the on
tracked. state when the diode (Fig. 2) would normally conduct, and in
the off state when the diode would be reverse-biased [8]. Since
Partial shadowing and varying inclinations of solar cells to n-channel components are smaller and less expensive in terms
the incident solar irradiation due to vehicle motion and the
curvature of the sunroof surface, which is additionally limited EV Auxiliary Board Net
to only about 1.5 m2, depending on vehicle type [1], are the (12V Board Net)
main reasons of non-suitability of these solutions in automotive
sector. Hence, in this work novel photovoltaic energy
GND
harvesting architecture for automotive applications is proposed. Active Electronic Circuit at Cell Stack Level
In comparison to fixed installations angular misadjustments
and dynamics caused by vehicle motion limits its potential to
receive irradiated solar energy. However, according to [1] in
order to consider different deviative conditions European
Switching
Efficiency is still a key figure of merit for a photovoltaic EV DC Bus
DC-DC
generator on the vehicle roof. Therefore, in-depth modelling (12V Board Net)
Converter
and characterisation of hybrid step-up dc-dc converters for PV Cell
European Efficiency is presented, thereby considering different Stack
converter topologies. Finally, numerical optimisation Control
methodology, suitable for topology comparison, is briefly Input

introduced. Feedforward Maximum Power Point Feedback

Tracking Controller

II. PHOTOVOLTAIC ENERGY HARVESTING ARCHITECTURE Reference

In order to tackle the obstacles specific for automotive
applications in harvesting photovoltaic energy, a novel power
electronic architecure depicted in Fig. 1, and proposed in the Figure 1. Novel photovoltaic energy harvesting architecture: one converter
E3Car project [1] is hereby introduced. It is based on an active for 10 solar cells in one stack.
integrated electronic circuit at cell stack level (very small group
of solar cells; ~9-10 cells per group) maintaining continuous
impedance matching between the source and the load, i.e. iIN L1 X SD1 iOUT
Maximum Power Point Tracking (MPPT). Such circuits are
 
suited to be directly integrated into the active solar cells to VDDH
properly interface them with the Electric Vehicle (EV) dc bus  IN d  OUT
and the grid. Hence, the photovoltaic area is split into small cell ML
groups, with one converter per group. The converters are in Cinternal C1
 low-side 
turn arranged in parallel connection to the EV auxiliary board
net (12 V) (Fig. 1) in order to maintain a low voltage at the driver 12V net
output. In that way maximum available power is further PV cell stack  EV auxiliary board net 
transferred from each cell group and power of no cell group is
lost. Described power conditioning is addressed using dc-dc Figure 2. Conventional boost converter as the active electronic circuit at cell
converters as active electronic circuits at cell stack level. stack level (Topology 1).

The nominal value of the input voltage of the low-voltage

solar-powered converter is around 5 V, which was chosen to be  BOOT
compatible with the power MOSFETs, while it pushes the d
power from the solar cells into the board net (Fig. 1) with the MH
nominal voltage of 12 V (lead acid battery in automotive Cbootstrap
high-side
applications – 14.4 V) [1]. The energy flow between the input
driver
solar stack and the 12 V board net of the electric vehicle is iIN L1 X iOUT
managed and directed by use of the MPPT controller which
sets the duty cycle of internal switches of the converter based  
VDDH
on Pulse Width Modulation (PWM) control algorithm (or any
 IN d  OUT
other, in principle). Meeting safety standards regarding ML
electrical protection, it is not necessary to use an isolated dc-dc Cinternal C1
 low-side 
converter for this application [1]. Therefore, the conventional
boost dc-dc converter topology (Fig. 2), and the synchronous- driver 12V net
rectified boost dc-dc converter topology (Fig. 3) are proposed, PV cell stack  EV auxiliary board net 
due to the minimal number of switches and reactive
components, as potential realisation of the low-voltage solar-
powered converter, i.e. of the active electronic circuit at cell Figure 3. Synchronous-rectified boost converter as the active electronic
circuit at cell stack level (Topology 2).
stack level. In the latter case, the synchronous rectifier
of process complexity [9], they are preferred for the high-side TABLE I. WEIGHTING COEFFICIENTS FOR EUROPEAN EFFICIENCY
switch implementation. For both topologies, the cell internal k 1 2 3 4 5 6
capacitance Cinternal , which has value of about 40 μF, is PIN [k ]
[%] 5 10 20 30 50 100
foreseen for keeping the solar voltage constant. PIN max
A[k ] 0.03 0.06 0.13 0.10 0.48 0.20
Making a step forward toward a system miniaturisation of
solar regenerative energy solutions in automotive applications,
efficiency for several operating points expressed by the
but still keeping a chip area small – roughly 0.5-1 mm², the percentages of the total rated power [1], [10], [11]
integration of the power stage is regarded not to be
advantageous, as a very large area of about 30 mm² would be 6

consumed by switches integrated in the 0.35μm HV CMOS EURO   A k

 k
. (1)
k 1
process for up to 8 A photocurrent. Hence, power stage will be
realised in a fully discrete way, with integrated MPPT control. The weights A k
, k  1,...,6 are normalised, so that
6
Principal differences in terms of power losses between
these two topologies are reflected in the two opposite ways.
 A k
 1 .
k 1
(2)

On the one hand, conduction loss could be reduced if a diode They are shown in Table I alongside with the respective
is replaced by a synchronous rectifier, while on the other hand data points, i.e. the conversion efficiencies indexed by a
this increases the gate charge loss, since there is an additional percentage of the total rated power of the photovoltaic
active switch. Other differences are pronounced in terms of generator. These weighting factors reflect the statistical
the number of external devices. In a low-side driver, an input working time of each operating point [8]. If further the
low voltage CMOS logic signal is transformed in a logic constant input voltage VIN is assumed, then operating points
signal swinging from ground to the voltage VDDH are defined by input currents
( VDDH  VIN ). Opposite of low-side drivers, which drive a P k

I IN k
 IN . (3)
power MOSFET whose source is connected to ground (Fig. 2 VIN
and 3), high-side drivers (Fig. 3) have to make use of power
limited auxiliary voltage supplies for proper overdriving [9]. This is a reasonable assumption for photovoltaic applications
In any case, the two control signals should be pseudo- and will be used throughout the text. Averaging given by (1)
complementary to each other in order to eliminate shoot- could be applied to three different quantities: dc-dc converter
efficiency, static tracking efficiency of the MPPT tracker, and
through effect, i.e. some predefined time should elapse before
total efficiency, which is the product of the previous two.
turning on one of the two power devices after the turn off of
Here, only the dc-dc converter efficiency will be discussed.
the other power device in order to avoid cross-conduction
currents.
IV. EFFICIENCY MODELLING OF THE POWER STAGES
Hence, synchronous rectification is more complicated from A real converter contains a large number of dissipative
the converter control point of view. All solutions for elements. Inductor copper loss, and inductor core loss (due to
delivering a gate voltage adequately higher than the positive hysteresis and eddy current losses in the magnetic core) are
power supply rail, which is usually not available at board or just one type of losses that occur in the converter.
Semiconductor conduction losses (due to semiconductor
system level, and which is necessary for high-side drivers,
device forward voltage drops) and semiconductor switching
could be classified in two different categories [9]: (1)
losses (due to turn-on and turn-off transitions of
bootstrap techniques, and (2) charge pump techniques. semiconductor devices and charging/discharging of gate
However, for integrated/hybrid converters any of these capacitances) are further examples of converter losses [8]. The
solutions is already drawback since it requires use of power needed to operate the control circuitry is in milliwatt
additional external devices such as capacitors and diodes, range and hence negligible in this application. In the first
making boost topology with synchronous rectifier less approximation of the analysis to be presented, it will be
favourable. assumed that converters operate in the Continuous Conduction
Mode (CCM), and that stages are realised with use of external
devices – a discrete power stage. Also, inductor core loss,
III. EUROPEAN EFFICIENCY which is proportional to frequency, will be neglected.
In order to consider the deviation from the nominal
conditions in the solar system's efficiency characterisation, i.e. A. Conventional Boost DC-DC Converter Topology
for specific latitudes and variable weather conditions, in-plane (Topology 1)
sun irradiance, module temperature, a suitable figure of merit
The conduction loss in the case of the conventional boost
is the European Efficiency EURO which is based on annual converter topology is given by
statistical analysis of these conditions optimised for Central
Europe [1]. It is the weighted mean value of the converter Pres  I IN
2
RON , ML D  I INVF 1  D   I IN
2
RL (4)
where D is the duty cycle, I IN the average input current of converter switching frequency. The transistor turn-on and
the converter, RL the inductor series resistance, VF the diode turn-off times are tON , ML and tOFF , ML , respectively.
forward voltage, and RON , ML the power MOSFET on-resistance. Therefore, the total loss in a particular operating point is
The diode forward voltage VF in principle depends on the expressed by
diode current. However, in datasheets it is usually provided for PLOSS  Pdrv  Poverlap  Pres . (10)
one current value or it is characterised by its maximal value
[12], [13], [14]. Graphical current-voltage dependencies of the In order to calculate the European Efficiency, the dc-dc
diodes are also provided [12], [13], [14], but from them it is converter efficiency  in different operating points given by
difficult to extract analytical models of these dependencies, Table I should be considered and finally averaged employing
especially to obtain the unified model. Hence, it is assumed (1). Thus, for the k -th, k  1,...,6 operating point holds
that the diode forward voltage VF remains roughly constant.
POUT k
PLOSS k

Applying volt-second balance on the inductor voltage  k

  1 (11)
PIN k
PIN k

VIN  I IN RL  I IN RON , ML  D 
, (5) which after simplification, using (3), (4), and (7)-(10), yields
 VIN  I IN RL  VF  VOUT 1  D   0
 I IN k
1  D   fV
the duty cycle D could be obtained  k
 1   RL  VF   s DDH QG , ML 
 V I k

 VIN VIN  IN IN
VIN  I IN  RL  RON , ML  . (12)
D  1 , (6) f sVOUT DI IN k

VOUT  VF  I IN RON , ML   tON ,ML  tOFF , ML   RON , ML  
2VIN VIN  
which, having neglected second-order terms1, simplifies to
The European Efficiency is then given by employing (1) to
V expression (12), using additionally (2), which brings
D 1  IN . (7)
VOUT
EURO  1  FHSSW  FIND  FLSSW
, (13)
The switching loss is, on the other hand, given through
transition-loss mechanisms in a power MOSFET and a diode. 1  D 
FHSSW  VF (14)
A diode recovery loss during turn-off transitions could be VIN
eliminated by using Schottky diodes which are majority-
6
carrier devices [8]. The energy provided by the gate driver to
charge and discharge the low-side MOSFET gate-to-source  A k
I k

k 1
IN
I IN max
capacitance during turn-on and turn-off transitions in each FIND  RL 0.5035 RL (15)
switching cycle represents the part of the converter switching VIN VIN
loss caused by a driver circuit. It is approximately given by f sVDDH QG , ML 6 A k
f sVOUT
Pdrv  QG , MLVDDH f s . (8)
FLSSW 
VIN
 I k
 2VIN
 tON ,ML  tOFF ,ML 
k 1 IN

Here, QG , ML is the gate charge of the low-side switch, DRON , ML 6


VIN
 A k
I k
IN
VDDH the gate-to-source voltage for turning on the power k 1
(16)
fV fV
3.3433 s DDH QG , ML  s OUT  tON , ML  tOFF , ML 
MOSFET, i.e. the driver supply voltage, and f s is the
converter switching frequency. The remaining part of the VIN I IN max 2VIN
switching loss is due to the voltage/current overlaps during DI IN max
switching transitions. When switching is performed with a  0.5035 RON , ML
clamped inductive load and assuming other loss sources to be VIN
annulated [9], this part of the loss is given by
PIN max
where I IN max  is the maximum rated input current.
1
Poverlap  VOUT I IN  tON , ML  tOFF , ML  f s , (9) VIN
2 Approximative expressions are obtained using values from
where VOUT is the converter output voltage, I IN is the average Table I.
inductor current in a certain operating point, and f s is the Hence, European Efficiency depends on three factors –
high-side switch, inductor, and low-side switch nonidealities –
and each of them should be (independently) minimised in
1
This approximation is normally not introduced at this stage. However, this order to maximise the efficiency. The term FHSSW shows that
provides easiness in determing dominant influences on the efficiency, since
expressions to be averaged later by (1) are greatly simplified, although not the maximum European Efficiency of the conventional boost
loosing much on the accuracy. Note that this is application-dependant and topology is directly limited by the high-side switch, i.e. by
should be checked whether it is justified under some other numerical
forward voltage of the diode VF . Similar limitation by the
conditions.
series resistance of the inductor RL is given through the term turn-off transitions in each switching cycle
FIND . Ordinary rectifier diodes are not recommended because Pdrv  QG, MLVDDH f s  QG, MHVDDH f s . (20)
of a higher forward voltage and the slow recovery time which
would compromise efficiency. Therefore, a Schottky diode Here, QG , MH is the gate charge of the high-side switch, and the
with the minimal forward voltage that can sustain a required other parameters are kept with the unchanged meaning. The
blocking voltage should be selected. Also, an inductor which remaining part of the switching loss, due to the voltage/current
has the minimal series resistance is required, although a overlaps during switching transitions, is again given by (9).
smaller inductor winding resistance means a larger, heavier, Namely, similar expression to (9) holds for the high-side
and more expensive inductor [8]. On the other hand, a discrete switch, where instead of the converter output voltage VOUT the
transistor could be characterised through its on-resistance forward voltage of the high-side transistor’s body diode
RON , ML and gate charge QG , ML . Both these factors should be should be taken into account. Since it is much smaller than
held as low as possible in order to have a higher efficiency. VOUT , the sum of the two approximates to (9). In this topology
Also, its turn-on time tON , ML and turn-off time tOFF , ML should also exists a loss due to the body diode, which occurs during a
be kept minimal. However, the transistor turn-on and turn-off dead-time. It includes reverse recovery and forward
times are not listed in the datasheets [12], [13], [14] – they conduction losses [15]. However, it is supposed that this time
depend on how fast the driver is able to charge and discharge could be kept small, so that the latter loss is negligible. Also, a
the gate. So, from a given set of discrete transistors, one that reverse recovery charge is not a primary design parameter.
minimises the term FLSSW should be selected, i.e. the one that The total loss in a particular operating point is again
provides an optimal combination of the pair ( RON , ML , QG , ML ). expressed by (10), this time using (17) and (20) therein instead
of (4) and (8). Further, the averaging procedure in calculating
B. Synchronous-Rectified Boost DC-DC Converter Topology European Efficiency is carried out in the similar way. The
(Topology 2) converter efficiency fot the k -th operating point is given by
(21), whereas the European Efficiency is again represented
The conduction loss in the case of the synchronous- with (13)-(16), up to the difference that instead of (14) holds
rectified boost converter topology is given by same expression (22). For maximisation of the European Efficiency, similar
as for the conventional boost converter topology (4), up to the comments as for the conventional boost converter topology
fact that a high-side switch is now realised as a synchronous are valid. In that sense, the high-side switch has an influence
rectifier MH, with the on-resistance RON , MH . This leads to of an active switch type.

Pres  I IN
2
RON , ML D  I IN
2
RON , MH 1  D   I IN
2
RL . (17) C. Topology Comparison for European Efficiency

The other parameters have the same meaning as previously, if

Table II illustrates the influence of the inductor series
we notice that the duty cycle D for the synchronous-rectified
resistance on the converter European Efficiency, valid for both
boost converter topology could be, having neglected second-
topologies, for several typical values obtained using (15).
order terms, again simplified to the same expression as (7). It
is, in fact, obtained from volt-second balance applied on the The only difference between these two topologies which
inductor voltage affects European Efficiency comes from the realisation of a
high-side switch. Fig. 4 illustrates a current-voltage
V  I R  I R  D 
IN IN L IN ON , ML characteristic of the high-side switch depending on its
, (18)
 V  I R  I R  V  1  D   0
realisation. It could be observed that for a given current,
IN IN L IN ON , MH OUT synchronous rectifier has a smaller conduction loss than diode,
and the duty cycle is, in full sense, given by as far as this current is small (compare, for example, points A
and B) – a limiting value is the crosspoint C. The on-
VIN  I IN  RL  RON , ML  resistance could be decreased by use of a larger MOSFET, so
D  1 . (19)
VOUT  I IN  RON , MH  RON , ML 
the conduction loss could be reduced as low as desired.
However, it would increase the switching loss (proportionally
The part of the switching loss due to driver circuits is in to frequency). So, optimal solution depends on the
thic case given by the energy provided by gate drivers to application-driven specifications. Therefore, to provide a fair
charge and discharge both the low-side and high-side comparison numerical simulation was performed in the
MOSFETs’ gate-to-source capacitance during turn-on and integrated circuit design environment, Cadence [16], impleme-

 f sVDDH fV DI k
 1  D   fV DI k

 k
 1   QG , MH  s OUT  tON , ML  tOFF , ML   IN RON , MH   VF +  s DDH QG , ML  IN RON , ML   ,
  
 VIN I IN k
2VIN VIN  VIN  VIN I IN k
VIN  
k  1,...,6 (21)
f sVDDH QG , MH 6 A k
DRON , MH 6
fV DI IN max
FHSSW 
VIN
 I k

k 1 VIN
 A k
I k
3.3433 V I
k 1
IN
s DDH
QG , MH  0.5035
VIN
RON , MH (22)
IN IN IN max
TABLE II. INFLUENCE OF DIFFERENT INDUCTOR SERIES RESISTANCES ON determine the European efficiency for pre-selected discrete
THE EUROPEAN EFFICIENCY
transistors and Schottky diodes [12], [13], [14] listed in Tab.
RL [mΩ] 10 25 50 75 100 III and IV, respectively, and forming a discrete design space.

1  FIND [%]
In the first step, with a specific setup of the topology 1:
99.19 97.99 95.97 93.96 91.94
certain simple driver (without level shifting stage), diode–
“STPS5L25B”, L  10 μH , C  100 nF , esr  50 m˟ , and
iHSSW
neglecting inductor-based losses, efficiency simulations were
100% I IN max performed at different frequencies, so as to choose an
appropriate low-side switch. The best results were provided by
diode the part “IPD135N03L G”. Therefore, in the following step,
already selecting that transistor for both topologies (as they
synchronous should have the same optimal solution), further optimisation is
done in order to select an optimal high-side switch. Fig. 5
rectifier
C shows the results for the topology 1, and Fig. 6 for the
topology 2. Applied dead time amounts 1% of the switching
50% I IN max
period. Table V summarises the post-layout simulation results
obtained with the optimised low-side gate driver, designed in
the AMS 0.35μm HV CMOS process, and with the
30% I IN max
A B combination of external semiconductor switches which
20% I IN max provide the best European Efficiency at the specified
10% I IN max frequencies.
5% I IN max Not surprisingly, the two-MOSFET converter using the
VF  HSSW largest MOSFETs gives the highest efficiency at 200 kHz. As
0
switching frequency becomes higher, switching losses
increase proportionally and advantage of synchronous
Figure 4. Comparison of high-side switch realisations. Arbitrary mutual rectification dissapears. So, there is a limitting switching
dependence is shown (illustration). Current values, i.e. operating points, used
in the definition of European Efficiency are highlighted.
frequency up to which synchronous rectification is a preferred
topology. Also, it is noticeable (Fig. 6) that the optimal
nting .lib models of commercially available external transistor at higher frequencies is not the same as the one at
semiconductor switches in readable form for the targeted 200 kHz. Although having more than two times larger on-
software. Specifications of the dc-dc converter are: nominal resistance (Tab. IV), it has a (slightly) smaller gate charge. It
input voltage 5 V, output voltage 12 V, and maximal input means that at higher frequencies the gate charge becomes
power 40 W. Circuit simulations were performed to obtain the more and more important factor.
converter efficiency graphs versus input current and to

TABLE III. DISCRETE N-CHANNEL MOSFET TRANSISTORS FOR EFFICIENCY COMPARISON (WORST-CASE VALUES)
Drain-Source On-resistance
Drain Current
Part Number Breakdown [mΩ]×Gate Package Manufacturer
(continuous) [A]
Voltage [V] Charge [nC]
BSO330N02K G 20 6.5 30×4.9 PG-DSO-8 Infineon
STP22NF03L 30 22 60×9 TO-220 ST Microelectronics
BSO300N03S 30 7.2 45×4.6 P-DSO-8 Infineon
BSO350N03 30 6 52×3.7 P-DSO-8 Infineon
STS15N4LLF3 40 15 7×28 SO-8 ST Microelectronics
STS6NF20V 20 6 40×11.5 SO-8 ST Microelectronics
IPD135N03L G 30 30 20.5×6.4 PG-TO252-3 Infineon
IPP147N03L G 30 20 21.7×4.8 PG-TO220-3-1 Infineon

TABLE IV. DISCRETE SCHOTTKY DIODES FOR EFFICIENCY COMPARISON

Blocking Voltage Avg. Forward Forward
Part Number Package Manufacturer
[V] Current [A] Voltage [V]
2
STPS10L25D/G 25 10 0.35 TO-220AC, D PAK ST Microelectronics
STPS15L25D/G 25 15 0.35 TO-220AC, D2PAK ST Microelectronics
STPS20L15D/G 15 20 0.33 TO-220AC, D2PAK ST Microelectronics
STPS5L25B/B-1 25 5 0.35 DPAK, IPAK ST Microelectronics
MBRB2515L 15 25 0.38 D2PAK ON Semiconductor
STPS8L30B/H 30 8 0.40 DPAK, IPAK ST Microelectronics
 could be drawn. Hence, availability of discrete semiconductor
switches, either diodes or MOSFETs, which satisfy
specifications, and maximise the efficiency is a deciding
factor. In a presented example, an advantage was given to the
conventional boost converter because of a simpler realisation
of control circuitry, and less number of external devices. As a
result of compromise, 500 kHz was chosen for the converter
switching frequency, thus enabling smaller reactive
components to be used.

ACKNOWLEDGEMENT

Financial funding from the Austrian BMVIT via FFG and the
ENIAC joint undertaking in the project E3Car is appreciated.
Figure 5. Comparison of high-side switches, 500 kHz (Topology 1). The authors especially thank to Mr. Paolo D’Abramo and Mr.
Harald Gall from austriamicrosystems AG for their support.

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