Working T13

Draft 1153D
Revision 18
19 August 1998

Information Technology -
AT Attachment
with Packet Interface Extension
(ATA/ATAPI-4)

This is an internal working document of T13, a Technical Committee of Accredited Standards Committee
NCITS. As such, this is not a completed standard and has not been approved. The contents may be
modified by the T13 Technical Committee. This document is made available for review and comment only.

Permission is granted to members of NCITS, its technical committees, and their associated task groups to
reproduce this document for the purposes of NCITS standardization activities without further permission,
provided this notice is included. All other rights are reserved. Any commercial or for-profit replication or
republication is prohibited.

ASC T13 Technical Editor:

Peter T. McLean
Maxtor Corporation
2190 Miller Drive
Longmont, CO 80501-6744
USA

Tel: 303-678-2149
Fax: 303-682-4811
Email: [email protected]

Reference number
ANSI X3.*** - 199x
Printed August, 20, 1998 9:50AM
T13/1153D revision 18

Other Points of Contact:

T13 Chair T13 Vice-Chair

Gene Milligan Pete McLean
Seagate Technology Maxtor Corporation
OKM 251 2190 Miller Drive
10323 West Reno (West Dock) Longmont, CO 80501
P.O. Box 12313 Tel: 303-678-2149
Oklahoma City, OK 73157-2313 Fax: 303-682-4811
Tel: 405-324-3070
Fax: 405-324-3794

NCITS Secretariat
Administrator Standards Processing
1250 Eye Street, NW Suite 200
Washington, DC 20005
Tel: 202-737-8888
Fax: 202-638-4922
Email: [email protected]

T13 Reflector
Internet address for subscription to the T13 reflector: [email protected]
Send email to above account and include in BODY of text, on a line by itself the following:
"subscribe T13 [your email address]"
Internet address for distribution via T13 reflector: [email protected]

T13 Anonymous FTP Site

fission.dt.wdc.com
T13 directory is: "/ t13 "

T13 mailings
Global Engineering
15 Inverness Way East
Englewood, CO 80112-5704
Tel: 303-792-2181 or 800-854-7179
Fax: 303-792-2192
 T13/1153D revision 18

DOCUMENT STATUS

Revision 0 - 5 February 1996

Document created from ATA3-r6 (X3T10/2008Dr6) with new frontmatter and the content of AT Attachment
Packet Interface (X3T10/1120Dr2) added.

Revision 1 - 18 March 1996

Per 2/21-23/96 working group meeting:

• Changed document name
• Removed term ATA from text of document
• Added output table to each command, moved table 6, and equivalent ATAPI table to Annex E
• Filled in na (not applicable) in command input and output tables
• Added PACKET bit descriptions in register descriptions clause 6.
• Added new clause 7.1 and rearranged clause 7.
• Made other text changes requested during page by page review.

Revision 2 - 5 April 1996

Per 3/27-29/96 working group meeting:

• Eliminated phrase “not used”/”not to be used”.
• Added “signature” the definitions and Protocol clause.
• Added SFF8020 reference and in bibliography.
• Swapped clauses 6 and 7.
• Reworded new clause 7, Register definitions to contains only material common to all
commands.
• Added subclauses to clause 8, Commands.
• Made text changes requested during page-by-page review.

Revision 3 - 3 May 1996

Per 4/24-25/96 working group meeting:

• Modified PACKET protocol flowcharts as requested
• Added proposal D96102R2, Pins A-D on 44-pin connector
• Made text changes requested during review
• Added ATA3 letter ballot comment resolution

Revision 4 - 10 June 1996

Added revisions per page-by-page review at 5/22-24/96 working group meeting

Revision 5 - 28 June 1996

Added proposals:
• D96125R5 Vendor specific and optional commands
• D96137R0 Protected area proposal
• D96131R1 SMART change proposal
Added register transfer timing.
Added revisions per page-by-page review at 6/19-21/96 working group meeting.
T13/1153D revision 18

Revision 6 - 6 September 1996

Added editorial changes from the ATA-3 ANSI pre-edit.

Added proposal D96106r1, FLUSH CACHE, as modified at the 7/31/96 working group meeting.
Added ATA/ATAPI-4 revision 6 to revisions list in IDENTIFY DEVICE response.
IORDY description in clause 5.2.11 changed to allow only tristate drivers.
Added description of invalid register address in Interface register definitions and descriptions clause.
Made “a” power management feature mandatory in the Power Management feature set.
Moved timing conventions to Conventions clause.

Revision 7 - 3 October 1996

Per September 25-26 working group meeting:

Added Feature Status Reporting, D96103R2 with revisions.
Added PACKET feature set queuing from D96104R8.
Added Removing Redundant Information proposal, D96114R1, except for timing diagram changes.
Added unitized connectors, D96126R1 and D96149R0.
Added modified reset protocol, D96142R6.
Added changes per page-by-page review.

Revision 8 - 3 December 1996

Per October 23-24 and November 13-15 working group meetings:

Added READ/WRITE DMA O/Q commands (D96104R9).
Added new timing diagrams (D96114R2).
Added reset changes (D96157R0).
Added changes per page by page reviews.

Revision 9 - 10 February 1997

Removed Removable Media feature set

Added register access restrictions proposal (D97102R0)
Added SET MAX ADDRESS addition (D97106R1)
Added enhanced security erase proposal (D96156R2)
Added Ultra DMA proposal (D96153R3)
Made changes requested by page by page review through clause 8.9.

Revision 10 - 7 March 1997

Made changes requested by page-by-page review at February meeting.

Modified protocol flowcharts in clause 9.

Revision 11 - 1 April 1997

Added Ultra DMA changes from D96153R4.

Modified protocol flow charts as requested at March meeting.
Made changes per change bar review at March meeting.

Revision 12 - 2 May 1997

Added CFA feature set per D97116R2.

Modified protocol flowcharts per April meeting review.
Made changes per change bar review at April meeting.
 T13/1153D revision 18

Revision 13 - 30 May 1997

Added Advanced Power Management per D97126R2.

Modified clauses 5.2.9, 6.6, and 6.7 to eliminate overlap/queue race.
Modified protocol flowcharts per May meeting.
Made changes per change bar review at May meeting.

Revision 14 - 26 June 1997

Made WRITE VERIFY command obsolete.

Added Removable Media Status Notification proposal per D97120R2.
Added 80-conductor assembly proposal per D97121R1.
Added new SET MAX/NATIVE MAX description per D97119R3.
Modified signature and persistence clause per D97139R0.
Modified protocol flowcharts per June meeting.
Made changes per change bar review at June meeting.

Revision 15 - 1 August 1997

Added Cleanup proposal per D97139R1.

Modified Annex B per D97138R3.
Modified Annex C per D97128R2.
Made changes per change bar review at July meeting.

Revision 16 - 25 August 1997

Added C/H/S and LBA calculation rules per D97145R3.

Made changes per change bar review at August meeting.

Revision 17 - 30 October 1997

Added changes per resolution of letter ballot comments, D97152R1.

Revision 18 - 19 August 1998

Added editorial changes per D98121r1.

T13/1153D revision 18

Page left intentionally blank

 T13/1153D revision 18

ANSI®
X3.****-199x

American National Standard

for Information Systems 

AT Attachment
with Packet Interface Extension  (ATA/ATAPI-4)

Secretariat
Information Technology Industry Council

Approved mm dd yy

American National Standards Institute, Inc.

Abstract

This standard specifies the AT Attachment Interface between host systems and storage devices. It provides
a common attachment interface for systems manufacturers, system integrators, software suppliers, and
suppliers of intelligent storage devices. It includes the Packet Command feature set implemented by
devices commonly known as ATAPI devices.

This standard maintains a high degree of compatibility with the AT Attachment-3 Interface (ATA-3), X3.298-
1997, and while providing additional functions, is not intended to require changes to presently installed
devices or existing software.
T13/1153D revision 18

Approval of an American National Standard requires verification by ANSI that the

American requirements for due process, consensus, and other criteria for approval have
National been met by the standards developer. Consensus is established when, in the
judgment of the ANSI Board of Standards Review, substantial agreement has
Standard been reached by directly and materially affected interests. Substantial agreement
means much more than a simple majority, but not necessarily unanimity.
Consensus requires that all views and objections be considered, and that effort be
made towards their resolution.

The use of American National Standards is completely voluntary; their existence

does not in any respect preclude anyone, whether he has approved the standards
or not, from manufacturing, marketing, purchasing, or using products, processes,
or procedures not conforming to the standards.

The American National Standards Institute does not develop standards and will in
no circumstances give interpretation on any American National Standard.
Moreover, no person shall have the right or authority to issue an interpretation of
an American National Standard in the name of the American National Standards
Institute. Requests for interpretations should be addressed to the secretariat or
sponsor whose name appears on the title page of this standard.

CAUTION NOTICE: This American National Standard may be revised or

withdrawn at any time. The procedures of the American National Standards
Institute require that action be taken periodically to reaffirm, revise, or withdraw
this standard. Purchasers of American National Standards may receive current
information on all standards by calling or writing the American National Standards
Institute.

CAUTION: The developers of this standard have requested that holders of patents that may be
required for the implementation of the standard, disclose such patents to the publisher. However,
neither the developers nor the publisher have undertaken a patent search in order to identify
which, if any, patents may apply to this standard.

As of the date of publication of this standard and following calls for the identification of patents that
may be required for the implementation of the standard, notice of one or more such claims has
been received.

By publication of this standard, no position is taken with respect to the validity of this claim or of
any rights in connection therewith. The patent holders have, however, filed a statement of
willingness to grant a license under these rights on reasonable and nondiscriminatory terms and
conditions to applicants desiring to obtain such a license. Details may be obtained from the
publisher.

No further patent search is conducted by the developer or the publisher in respect to any standard
it processes. No representation is made or implied that licenses are not required to avoid
infringement in the use of this standard.

Published by
American National Standards Institute
11 West 42nd Street, New York, New York 10036
Copyright 199n by American National Standards Institute
All rights reserved.
 T13/1153D revision 18

Contents Page
Foreword .............................................................................................................................................v
Introduction .........................................................................................................................................ix
1 Scope ...............................................................................................................................................1
2 Normative references .......................................................................................................................2
2.1 Approved references...............................................................................................................2
2.2 References under development ..............................................................................................2
2.3 Other references.....................................................................................................................2
3 Definitions, abbreviations, and conventions ......................................................................................3
3.1 Definitions and abbreviations ..................................................................................................3
3.2 Conventions............................................................................................................................5
4 Interface physical and electrical requirements ...................................................................................9
4.1 Cable configuration .................................................................................................................9
4.2 I/O cable .................................................................................................................................10
4.3 Electrical characteristics .........................................................................................................10
5 Interface signal assignments and descriptions ..................................................................................13
5.1 Signal summary ......................................................................................................................13
5.2 Signal descriptions..................................................................................................................14
6 General operational requirements .....................................................................................................19
6.1 Command delivery ..................................................................................................................19
6.2 Register delivered data transfer command sector addressing .................................................19
6.3 General feature set .................................................................................................................21
6.4 Ultra DMA feature set .............................................................................................................22
6.5 PACKET Command feature set ..............................................................................................24
6.6 Overlapped feature set ...........................................................................................................25
6.7 Queued feature set .................................................................................................................26
6.8 Power Management feature set ..............................................................................................27
6.9 Advanced Power Management feature set ..............................................................................29
6.10 Security Mode feature set .....................................................................................................30
6.11 Self-monitoring, analysis, and reporting technology feature set .............................................34
6.12 Host Protected Area feature set ............................................................................................35
6.13 CFA feature Set ....................................................................................................................36
6.14 Removable Media Status Notification and Removable Media feature sets ............................37
7 Interface register definitions and descriptions ...................................................................................39
7.1 Device addressing considerations ...........................................................................................39
7.2 I/O register descriptions ..........................................................................................................39
7.3 Alternate Status register..........................................................................................................41
7.4 Command register ..................................................................................................................41
7.5 Cylinder High register .............................................................................................................42
7.6 Cylinder Low register ..............................................................................................................42
7.7 Data register ...........................................................................................................................43
7.8 Data port.................................................................................................................................43
7.9 Device Control register ...........................................................................................................44
7.10 Device/Head register ............................................................................................................45
7.11 Error register.........................................................................................................................46
7.12 Features register...................................................................................................................46
7.13 Sector Count register ............................................................................................................47
7.14 Sector Number register .........................................................................................................47
7.15 Status register.......................................................................................................................48
8 Command descriptions .....................................................................................................................52
8.1 CFA ERASE SECTORS .........................................................................................................54
8.2 CFA REQUEST EXTENDED ERROR CODE .........................................................................56

Page i
T13/1153D revision 18

8.3 CFA TRANSLATE SECTOR...................................................................................................59

8.4 CFA WRITE MULTIPLE WITHOUT ERASE ...........................................................................61
8.5 CFA WRITE SECTORS WITHOUT ERASE ...........................................................................63
8.6 CHECK POWER MODE .........................................................................................................65
8.7 DEVICE RESET .....................................................................................................................67
8.8 DOWNLOAD MICROCODE ...................................................................................................69
8.9 EXECUTE DEVICE DIAGNOSTIC..........................................................................................71
8.10 FLUSH CACHE ....................................................................................................................73
8.11 GET MEDIA STATUS...........................................................................................................75
8.12 IDENTIFY DEVICE ...............................................................................................................77
8.13 IDENTIFY PACKET DEVICE ................................................................................................95
8.14 IDLE .....................................................................................................................................105
8.15 IDLE IMMEDIATE.................................................................................................................108
8.16 INITIALIZE DEVICE PARAMETERS.....................................................................................110
8.17 MEDIA EJECT......................................................................................................................113
8.18 MEDIA LOCK .......................................................................................................................115
8.19 MEDIA UNLOCK ..................................................................................................................117
8.20 NOP .....................................................................................................................................119
8.21 PACKET ...............................................................................................................................121
8.22 READ BUFFER ....................................................................................................................127
8.23 READ DMA...........................................................................................................................129
8.24 READ DMA QUEUED...........................................................................................................132
8.25 READ MULTIPLE .................................................................................................................136
8.26 READ NATIVE MAX ADDRESS ...........................................................................................139
8.27 READ SECTOR(S) ...............................................................................................................141
8.28 READ VERIFY SECTOR(S) .................................................................................................144
8.29 SECURITY DISABLE PASSWORD ......................................................................................147
8.30 SECURITY ERASE PREPARE.............................................................................................149
8.31 SECURITY ERASE UNIT .....................................................................................................151
8.32 SECURITY FREEZE LOCK ..................................................................................................154
8.33 SECURITY SET PASSWORD ..............................................................................................156
8.34 SECURITY UNLOCK............................................................................................................159
8.35 SEEK....................................................................................................................................161
8.36 SERVICE..............................................................................................................................164
8.37 SET FEATURES...................................................................................................................165
8.38 SET MAX ADDRESS............................................................................................................170
8.39 SET MULTIPLE MODE.........................................................................................................173
8.40 SLEEP..................................................................................................................................175
8.41 SMART.................................................................................................................................177
8.42 STANDBY.............................................................................................................................195
8.43 STANDBY IMMEDIATE ........................................................................................................197
8.44 WRITE BUFFER...................................................................................................................199
8.45 WRITE DMA .........................................................................................................................201
8.46 WRITE DMA QUEUED .........................................................................................................204
8.47 WRITE MULTIPLE ...............................................................................................................208
8.48 WRITE SECTOR(S) .............................................................................................................211
9 Protocol ............................................................................................................................................214
9.1 Signature and persistence.......................................................................................................214
9.2 Power on and hardware resets................................................................................................215
9.3 Software reset.........................................................................................................................219
9.4 DEVICE RESET protocol ........................................................................................................223
9.5 EXECUTE DEVICE DIAGNOSTIC protocol ............................................................................224
9.6 Device selection protocol ........................................................................................................227
9.7 PIO data in command protocol................................................................................................228
9.8 PIO data out command protocol .............................................................................................231
9.9 Non-data command protocol ...................................................................................................235

Page ii
 T13/1153D revision 18

9.10 DMA command protocol .......................................................................................................237

9.11 PACKET command protocol .................................................................................................239
9.12 READ/WRITE DMA QUEUED command protocol ................................................................253
9.13 Ultra DMA data in commands ...............................................................................................257
9.14 Ultra DMA data out commands .............................................................................................259
9.15 Ultra DMA CRC rules ............................................................................................................262
9.16 Single device configurations .................................................................................................265
10 Timing ............................................................................................................................................266
10.1 Deskewing ............................................................................................................................266
10.2 Transfer timing......................................................................................................................266

Tables Page

1 Byte order........................................................................................................................................8
2 DC characteristics............................................................................................................................10
3 AC characteristics............................................................................................................................10
4 Driver types and required termination ..............................................................................................11
5 Typical series termination for Ultra DMA ...........................................................................................12
6 Interface signal name assignments ..................................................................................................13
7 Security mode command actions .....................................................................................................33
8 Extended error codes........................................................................................................................57
9 CFA TRANSLATE SECTOR information ..........................................................................................60
10 Diagnostic codes ...........................................................................................................................72
11 Identify device information .............................................................................................................79
12 Minor revision number ...................................................................................................................90
13 Identify packet device information .................................................................................................97
14 Automatic standby timer periods ....................................................................................................105
15 Security password content .............................................................................................................148
16 SECURITY ERASE UNIT password................................................................................................153
17 SECURITY SET PASSWORD data content...................................................................................157
18 Identifier and security level bit interaction ......................................................................................158
19 SET FEATURES register definitions ..............................................................................................167
20 Transfer/mode values ....................................................................................................................168
21 Advanced power management levels .............................................................................................168
22 SMART Feature register values ......................................................................................................177
23 Device SMART data structure........................................................................................................189
24 Off-line data collection status byte values ......................................................................................189
25 BSY and DRDY timing for power on and hardware resets ..............................................................219
26 BSY and DRDY timing for software reset .......................................................................................223
27 BSY and DRDY timing for diagnostic command .............................................................................226
28 Equations for parallel generation of a CRC polynomial ...................................................................263
29 Register transfer to/from device .....................................................................................................268
30 PIO data transfer to/from device ....................................................................................................270
31 Multiword DMA data transfer..........................................................................................................272
32 Ultra DMA data burst timing requirements ......................................................................................274

Page iii
T13/1153D revision 18

Figures Page

1 Interface cabling diagram ................................................................................................................9

2 Ultra DMA termination with pull-up or pull-down ................................................................................12
3 PDIAG- example using an 80-conductor cable assembly ..................................................................16
4 Cable select example ......................................................................................................................17
5 Alternate cable select example .........................................................................................................18
6 Power management modes .............................................................................................................29
7 Security mode flow ..........................................................................................................................32
8 BSY and DRDY timing for power on and hardware resets ................................................................218
9 BSY and DRDY timing for software reset .........................................................................................222
10 BSY and DRDY timing for diagnostic command .............................................................................226
11 Device selection protocol ................................................................................................................227
12 PIO data in command protocol .......................................................................................................228
13 PIO data out command protocol .....................................................................................................231
14 Non-data command protocol ...........................................................................................................236
15 DMA command protocol .................................................................................................................237
16 PACKET non-data and PIO data command protocol .......................................................................239
17 PACKET DMA command protocol ..................................................................................................246
18 READ/WRITE DMA QUEUED command protocol .........................................................................253
19 Example parallel CRC generator ....................................................................................................263
20 Register transfer to/from device .....................................................................................................267
21 PIO data transfer to/from device ....................................................................................................269
22 Multiword DMA data transfers ........................................................................................................271
23 Initiating an Ultra DMA data in burst................................................................................................273
24 Sustained Ultra DMA data in burst ..................................................................................................276
25 Host pausing an Ultra DMA data in burst.........................................................................................277
26 Device terminating an Ultra DMA data in burst ...............................................................................278
27 Host terminating an Ultra DMA data in burst ...................................................................................279
28 Initiating an Ultra DMA data out burst .............................................................................................280
29 Sustained Ultra DMA data out burst ................................................................................................281
30 Device pausing an Ultra DMA data out burst ...................................................................................282
31 Host terminating an Ultra DMA data out burst .................................................................................283
32 Device terminating an Ultra DMA data out burst .............................................................................284

Annexes Page

A Connectors.......................................................................................................................................285
B Identify device data for devices with more than 1024 logical cylinders .............................................295
C Signal integrity .................................................................................................................................298
D Bibliography .....................................................................................................................................323
E ATA command set summary ............................................................................................................324
F Command packet format example ....................................................................................................329

Page iv
 T13/1153D revision 18

Foreword
(This foreward is not part of American National Standard X3.***-199*.)

This AT Attachment with Packet Interface Extension (ATA/ATAPI-4) standard is designed to maintain a
high degree of compatibility with the AT Attachment-3 Interface (ATA-3) standard and the packet command
feature set implemented by devices commonly known as ATAPI devices while providing the advantages of
additional features and functions.

This standard was developed by the ATA ad hoc working group of Accredited Standards Committee NCITS
during 1995-97. The standards approval process started in 1997. This document includes annexes that are
informative and are not considered part of the standard.

Requests for interpretation, suggestions for improvement and addenda, or defect reports are welcome. They
should be sent to the NCITS Secretariat, Information Technology Industry Council, 1250 Eye Street, NW,
Suite 200, Washington, DC 20005-3922.

This standard was processed and approved for submittal to ANSI by Accredited Standards Committee on
Information Processing Systems, NCITS. Committee approval of the standard does not necessarily imply
that all committee members voted for approval. At the time it approved this standard, the NCITS Committee
had the following members:

James D. Converse, Chair

Donald C. Loughry, Vice-Chair

Joanne M. Flanagan, Secretary

Organization Represented ....................................................................... Name of Representative

American Nuclear Society ....................................................................... Geraldine C. Main
Sally Hartzell (Alt.)
AMP, Inc ................................................................................................. Edward Kelly
Charles Brill (Alt.)
Apple Computer ...................................................................................... Karen Higginbottom
Association of the Institute for Certification of Professionals (AICCP) ...... Kennath Zemrowski
AT&T/NCR .............................................................................................. Thomas W. Kern
Thomas F. Frost (Alt.)
Boeing Company ..................................................................................... Catherine Howells
Andrea Vanosdoll (Alt.)
Bull HN Information Systems, Inc. ........................................................... William George
Compaq Computer Corporation ............................................................... James Barnes
Digital Equipment Corporation ................................................................. Delbert Shoemaker
Kevin Lewis (Alt.)
Eastman Kodak ....................................................................................... James D. Converse
Michael Nier (Alt.)
GUIDE International ................................................................................ Frank Kirshenbaum
Harold Kuneke (Alt.)
Hewlett-Packard ...................................................................................... Donald C. Loughry
Hitachi America, Ltd. ............................................................................... John Neumann
Kei Yamashita (Alt.)
Hughes Aircraft Company........................................................................ Harold L. Zebrack
IBM Corporation ...................................................................................... Joel Urman
Mary Anne Lawler (Alt.)
National Communication Systems ........................................................... Dennis Bodson
National Institute of Standards and Technology ....................................... Robert E. Roundtree
Michael Hogan (Alt.)
Northern Telecom, Inc. ............................................................................ Mel Woinsky
Subhash Patel (Alt.)
Neville & Associates ................................................................................ Carlton Neville

Page v
T13/1153D revision 18

Recognition Technology Users Association.............................................. Herbert P. Schantz

G. Edwin Hale (Alt.)
Share, Inc................................................................................................ Gary Ainsworth
David Thewlis (Alt.)
Sony Corporation..................................................................................... Michael Deese
Storage Technology Corporation ............................................................. Joseph S. Zajaczkowski
Samuel D. Cheatham (Alt.)
Sun Microsystems ................................................................................... Scott Jameson
Gary Robinson (Alt.)
3M Company ........................................................................................... Eddie T. Morioka
Paul D. Jahnke (Alt.)
Unisys Corporation .................................................................................. John L. Hill
Stephen P. Oksala (Alt.)
U.S. Department of Defense.................................................................... William C. Rinehuls
C. J. Pasquariello (Alt.)
U.S. Department of Energy...................................................................... Alton Cox
Lawrence A. Wasson (Alt.)
U.S. General Services Administration ...................................................... Douglas Arai
Larry L. Jackson (Alt.)
Wintergreen Information Services ........................................................... Joun Wheeler
Xerox Corporation ................................................................................... Dwight McBain
Roy Peirce (Alt.)

Subcommittee T13 on ATA Interfaces, that reviewed this standard, had the following members:

Gene Milligan, Chairman

Pete McLean, Vice-Chairman

Larry Lamers, Secretary

I. Dal Allan Paul Raikunen Richard Harcourt (Alt.)

Charles Brill Yogi Schaffner Pat LaVarre (Alt.)
Darrin Bulik J. R. Sims LeRoy Leach (Alt.)
Ben Chang Victor Siu Raymond Liang (Alt.)
Dan Colegrove Ron Stephens John Masiewicz (Alt.)
Greg Elkins Curtis Stevens Christopher Mayne (Alt.)
Mark Evans Tokuyuki Totani James McGrath (Alt.)
Lance Flake Anthony Yang Patrick Mercer (Alt.)
Tony Goodfellow Carl Bonke (Alt.) Marc Noblitt (Alt.)
Tom Hanan Joe Chen (Alt.) Ron Roberts (Alt.)
Richard Kalish Mike Christensen (Alt.) Yasuyuki Suemori (Alt.)
Kenichi Kojima David Evans (Alt.) Don Vohar (Alt.)
Hale Landis Stephen Finch (Alt.) Devon Worrell (Alt.)
Robert Liu Robert Griffith (Alt.)

ATA/ATAPI ad hoc Working Group, that developed this standard, had the following additional participants:

Evgeny Berzon Shinichi Kobayashi Norihiko Oshita

George Blattner Eric Kvamme Steven Peng
Jeff Cousins Tony Kwan Duncan Penman
Lang Dennis Bill Mable Jerry Saltzman
Farbod Falakfars John Mallory Andrew Shu
Robin Freeze Kent Manabe Trent Thomas
Gregg Goldman John Mangan Irv Tjomsland
Yoshihito Higashitsutsumi Terry Miller Ron Werbow
Son Ho Masa Morizumi Mike Winchell
Paul Jackson Kazou Nakashima Jauher Zaidi
Earle Jennings Jay Neer

Page vi
 T13/1153D revision 18

Introduction
This standard encompasses the following:

Clause 1 describes the scope.

Clause 2 provides normative references.

Clause 3 provides definitions, abbreviations, and conventions used within this document.

Clause 4 contains the electrical and mechanical characteristics; covering the interface cabling
requirements of the interface and DC cables and connectors.

Clause 5 contains the signal descriptions of the AT Attachment Interface.

Clause 6 describes the general operating requirements of the AT Attachment Interface.

Clause 7 contains descriptions of the registers of the AT Attachment Interface.

Clause 8 contains descriptions of the commands of the AT Attachment Interface.

Clause 9 contains the protocol of the AT Attachment Interface.

Clause 10 contains the interface timing diagrams.

Page vii
T13/1153D revision 18

(This page intentionally blank)

Page viii
 T13/1153D revision 18

AMERICAN NATIONAL STANDARD X3.****-199n

American National Standard

for Information Systems 

Information Technology
 (ATA/ATAPI-4)
AT Attachment with Packet Interface Extension

1 Scope
This standard specifies the AT Attachment Interface between host systems and storage devices. It provides
a common attachment interface for systems manufacturers, system integrators, software suppliers, and
suppliers of intelligent storage devices.

The application environment for the AT Attachment Interface is any host system that has storage devices
contained within the processor enclosure.

This standard defines the connectors and cables for physical interconnection between host and storage
device, as well as, the electrical and logical characteristics of the interconnecting signals. It also defines the
operational registers within the storage device, and the commands and protocols for the operation of the
storage device.

This standard maintains a high degree of compatibility with the AT Attachment-3 Interface standard (ATA-3),
X3.298-1997, and while providing additional functions, is not intended to require changes to presently
installed devices or existing software.

Page 1
T13/1153D revision 18

2 Normative references

The following standards contain provisions that, through reference in the text, constitute provisions of this
standard. At the time of publication, the editions indicated were valid. All standards are subject to revision,
and parties to agreements based on this standard are encouraged to investigate the possibility of applying
the most recent editions of the standards listed below.

Copies of the following documents can be obtained from ANSI: Approved ANSI standards, approved and
draft international and regional standards (ISO, IEC, CEN/CENELEC, ITUT), and approved and draft foreign
standards (including BSI, JIS, and DIN). For further information, contact ANSI Customer Service
Department at 212-642-4900 (phone), 212-302-1286 (fax) or via the World Wide Web at
http://www.ansi.org.

Additional availability contact information is provided below as needed.

2.1 Approved references

The following approved ANSI standards, approved international and regional standards (ISO, IEC,
CEN/CENELEC, ITUT), may be obtained from the international and regional organizations who control
them.

SCSI-3 Primary Commands (SPC) [NCITS 301:1997] (PACKET command feature set device types)
SCSI-3 Multimedia Commands (MMC) [NCITS 304:1997] (PACKET command feature set sense codes)

To obtain copies of these documents, contact Global Engineering or NCITS.

2.2 References under development

At the time of publication, the following referenced standards were still under development. For information
on the current status of the document, or regarding availability, contact the relevant standards body or other
organization as indicated.

Multimedia Commands - 2 (MMC-2) [T10/1228-D] (PACKET command feature set commands)

For more information on the current status of the above documents, contact NCITS. To obtain copies of
these documents, contact Global Engineering or NCITS.

2.3 Other references

The following standard and specifications were also referenced.

Power Connector Pin Dimensions [SFF8012]

2 1/2” Drives with 50-pin Connector [SFF 8212]
Unitized ATA 2-plus Connector [SFF8057]
Unitized ATA 3-in-1 Connector [SFF8058]
ATA 40-pin Connector [SFF8059]
80-conductor ATA Cable Assembly [SFF8049]
PC Card Standard , February 1995, PCMCIA (68-pin Connector)

For documents published by the SFF committee, contact SFF at 408-867-6630 or FaxAccess at 408-741-
1600. For the PC Card Standard published by the Personal Computer Memory Card International
Association, contact PCMCIA at 408-433-2273.

Page 2
 T13/1153D revision 18

3 Definitions, abbreviations, and conventions

3.1 Definitions and abbreviations

For the purposes of this American National Standard, the following definitions apply:

3.1.1 ATA (AT Attachment): ATA defines the physical, electrical, transport, and command
protocols for the internal attachment of storage devices.

3.1.2 ATA-1 device: A device that complies with ANSI X3.221-1994, the AT Attachment Interface for Disk
Drives.

3.1.3 ATA-2 device: A device that complies with ANSI X3.279-1996, the AT Attachment Interface with
Extensions.

3.1.4 ATA-3 device:A device that complies with ANSI X3.298-1997, the AT Attachment-3 Interface.

3.1.5 ATAPI (AT Attachment Packet Interface) device: A device implementing the Packet Command
feature set.

3.1.6 bus release: For devices implementing overlap, the term bus release is the act of clearing both DRQ
and BSY to zero before the action requested by the command is completed to allow the host to
select the other device.

3.1.7 byte count: The value placed in the Byte Count register by the device to indicate the number of bytes
to be transferred under this DRQ assertion when executing a PACKET command.

3.1.8 byte count limit: The value placed in the Byte Count register by the host as input to a PACKET
command to indicate the maximum byte count that may be transferred under a single DRQ
assertion.

3.1.9 CFA: The CompactFlash Association that created the specification for compact flash memory that
uses the ATA interface.

3.1.10 check condition: For devices implementing the PACKET Command feature set, this indicates an
exception condition has occurred that needs to be reported to the host.

3.1.11 CHS (cylinder-head-sector): This term defines the addressing of the device as being by cylinder
number, head number, and sector number.

3.1.12 command aborted: Command completion with ABRT set to one in the Error register and ERR set to
one in the Status register.

3.1.13 command acceptance: A command is considered accepted whenever the currently selected device
has its BSY bit equal to zero and the host writes to the Command register. An exception exists for
the EXECUTE DEVICE DIAGNOSTIC and DEVICE RESET command (see 8.9).

3.1.14 Command Block registers: Interface registers used for delivering commands to the device or
posting status from the device.

3.1.15 command completion: Command completion is the completion by the device of the action
requested by the command or the termination of the command with an error, the placing of the
appropriate error bits in the Error register, the placing of the appropriate status bits in the Status
register, the clearing of both BSY and DRQ to zero, and the asserting of INTRQ if nIEN is cleared
to zero and the command protocol specifies that INTRQ be asserted.

Page 3
T13/1153D revision 18

3.1.16 command packet: A command packet is a data structure transmitted to the device by a PACKET
command that includes the command and command parameters.

3.1.17 Control Block registers:Interface registers used for device control and to post alternate status.

3.1.18 CRC: Cyclical Redundancy Check used for the Ultra DMA protocol to check the validity of the data
that has been transferred during the last Ultra DMA burst.

3.1.19 data block: This term describes a unit of data words transferred using PIO data transfer. A data
block is transferred between the host and the device as a complete unit. A data block is a sector,
except for data blocks of a READ MULTIPLE and WRITE MULTIPLE commands. In the cases of
READ MULTIPLE and WRITE MULTIPLE commands, the size of the data block may be changed
in multiples of sectors by the SET MULTIPLE MODE command.

3.1.20 device: Device is a storage peripheral. Traditionally, a device on the interface has been a hard disk
drive, but any form of storage device may be placed on the interface provided it adheres to this
standard.

3.1.21 device selection: A device is selected when the DEV bit of the Device/Head register is equal to the
device number assigned to the device by means of a Device 0/Device 1 jumper or switch, or use
of the CSEL signal.

3.1.22 DMA (direct memory access): A means of data transfer between device and host memory without
host processor intervention.

3.1.23 LBA (logical block address): This term defines the addressing of the device as being by the linear
mapping of sectors.

3.1.24 master: In ATA-1, Device 0 has also been referred to as the master. Throughout this document the
term Device 0 is used.

3.1.25 native max address: The highest address a device accepts in the factory default condition, which is
the highest address that is accepted by the SET MAX ADDRESS command. The capacity defined
by native max address may be different in CHS and LBA translations.

3.1.26 overlap: Overlap is a protocol that allows devices that require extended command time to perform a
bus release so that commands may be executed by the other device on the bus.

3.1.27 packet delivered command: A command that is delivered to the device using the PACKET
command via a command packet that contains the command and the command parameters.

3.1.28 PIO (programmed input/output): A means of accessing device registers. PIO is also used to
describe one form of data transfers. PIO data transfers are performed by the host processor
utilizing PIO register accesses to the Data register.

3.1.29 queued: Command queuing allows the host to issue concurrent commands to the same device. Only
commands included in the Overlapped feature set may be queued.

3.1.30 register delivered command: A command that is delivered to the device by placing the command
and all of the parameters for the command in the device Command Block registers.

3.1.31 released: Indicates that a signal is not being driven. For tri-state drivers, this means that the driver is
in the high impedance state. For open-collector drivers, the driver is not asserted.

3.1.32 sector: A uniquely addressable set of 256 words (512 bytes).

Page 4
 T13/1153D revision 18

3.1.33 signature: A unique set of values placed in the Command Block registers by the device to allow the
host to distinguish between register delivered command devices and packet delivered command
devices.

3.1.34 slave: In ATA-1, Device 1 has also been referred to as the slave. Throughout this document the
term Device 1 is used.

3.1.35 SMART: Self-Monitoring, Analysis, and Reporting Technology for prediction of device degradation
and/or faults. Throughout this document this is noted as SMART.

3.1.36 Ultra DMA burst: An Ultra DMA burst is defined as the period from an assertion of DMACK- to the
subsequent negation of DMACK- when Ultra DMA has been enabled by the host.

3.1.37 unit attention condition: A state that a device implementing the PACKET Command feature set
maintains while it has asynchronous status information to report to the host.

3.1.38 unrecoverable error: An unrecoverable error is defined as having occurred at any point when the
device sets either the ERR bit or the DF bit to one in the Status register at command completion.

3.1.39 VS (vendor specific): This term is used to describe bits, bytes, fields, and code values that are
reserved for vendor specific purposes. These bits, bytes, fields, and code values are not
described in this standard, and may vary among vendors. This term is also applied to levels of
functionality whose definition is left to the vendor.

NOTE − Industry practice could result in conversion of a Vendor Specific bit, byte, field, or
code value into a defined standard value in a future standard.

3.2 Conventions
Lowercase is used for words having the normal English meaning. Certain words and terms used in this
American National Standard have a specific meaning beyond the normal English meaning. These words
and terms are defined either in clause 3 or in the text where they first appear.

The names of abbreviations, commands, fields, and acronyms used as signal names are in all uppercase
(e.g., IDENTIFY DEVICE). Fields containing only one bit are usually referred to as the "name" bit instead of
the "name" field. (see 3.2.5 for the naming convention used for naming bits.)

Names of device registers begin with a capital letter (e.g., Cylinder Low register).

3.2.1 Precedence

If there is a conflict between text, figures, and tables, the precedence shall be tables, figures, then text.

3.2.2 Keywords

Several keywords are used to differentiate between different levels of requirements and optionality.

3.2.2.1 expected: A keyword used to describe the behavior of the hardware or software in the design
models assumed by this standard. Other hardware and software design models may also be implemented.

3.2.2.2 mandatory:A keyword indicating items to be implemented as defined by this standard.

3.2.2.3 may: A keyword that indicates flexibility of choice with no implied preference.

3.2.2.4 obsolete: A keyword used to describe bits, bytes, fields, and code values that no longer have
consistent meaning or functionality from one implementation to another. However, some degree of
functionality may be required for items designated as “obsolete” to provide for backward compatibility. An

Page 5
T13/1153D revision 18

obsolete bit, byte, field, or command shall never be reclaimed for any other use in any future standard. Bits,
bytes, fields, and code values that had been designated as “obsolete” in previous standards may have been
reclassified as “retired” in this standard based on the definitions herein for “obsolete” and “retired”.

Obsolete commands should not be used by the host. Commands defined as obsolete in previous standards
may be command aborted by devices conforming to this standard. However, if a device does not command
abort an obsolete command but performs no operation in response to that command, the minimum that is
required by the device in response to the command is command completion without performing the action
requested by the command and without error indication.

3.2.2.5 optional: A keyword that describes features that are not required by this standard. However, if any
optional feature defined by the standard is implemented, it shall be done in the way defined by the standard.

3.2.2.6 retired: A keyword indicating that the designated bits, bytes, fields, and code values that had been
defined in previous standards are not defined in this standard and may be reclaimed for other uses in future
standards. If retired bits, bytes, fields, or code values are utilized before they are reclaimed, they shall have
the meaning or functionality as described in previous standards.

3.2.2.7 reserved: A keyword indicating reserved bits, bytes, words, fields, and code values that are set
aside for future standardization. Their use and interpretation may be specified by future extensions to this
or other standards. A reserved bit, byte, word, or field shall be set to zero, or in accordance with a future
extension to this standard. The recipient shall not check reserved bits, bytes, words, or fields. Receipt of
reserved code values in defined fields shall be treated as a command parameter error and reported by
returning command aborted.

3.2.2.8 shall: A keyword indicating a mandatory requirement. Designers are required to implement all such
mandatory requirements to ensure interoperability with other standard conformant products.

3.2.2.9 should: A keyword indicating flexibility of choice with a strongly preferred alternative. Equivalent to
the phrase “it is recommended”.

3.2.3 Numbering

Numbers that are not immediately followed by a lowercase "b" or "h" are decimal values. Numbers that are
immediately followed by a lowercase "b" (e.g., 01b) are binary values. Numbers that are immediately
followed by a lowercase "h" (e.g., 3Ah) are hexadecimal values.

3.2.4 Signal conventions

Signal names are shown in all uppercase letters.

All signals are either high active or low active signals. A dash character (-) at the end of a signal name
indicates it is a low active signal. A low active signal is true when it is below ViL, and is false when it is
above ViH. No dash at the end of a signal name indicates it is a high active signal. A high active signal is
true when it is above V iH, and is false when it is below ViL.

Asserted means that the signal is driven by an active circuit to its true state. Negated means that the signal
is driven by an active circuit to its false state. Released means that the signal is not actively driven to any
state (see 4.3.1). Some signals have bias circuitry that pull the signal to either a true state or false state
when no signal driver is actively asserting or negating the signal.

Control signals that may be used for more than one mutually exclusive functions are identified with their
function names separated by a colon (e.g., DIOW-:STOP).

3.2.5 Bit conventions

Bit names are shown in all uppercase letters except where a lowercase n precedes a bit name. If there is no
preceding n, then when BIT is set to one the meaning of the bit is true, and when BIT is cleared to zero the

Page 6
 T13/1153D revision 18

meaning of the bit is false. If there is a preceding n, then when nBIT is cleared to zero the meaning of the
bit is true and when nBIT is set to one the meaning of the bit is false.

True False
TEST
Bit setting=1
Bit setting=0

True False
nTEST
Bit setting=0
Bit setting=1

3.2.6 Timing conventions

Certain symbols are used in the timing diagrams. These symbols and their respective definitions are listed
below.

or - signal transition (asserted or negated)

or - data transition (asserted or negated)

- data valid

- undefined but not necessarily released

- asserted, negated or released

- released

- the “other ” condition if a sig nal is shown with no change

All signals are shown with the asserted condition facing to the top of the page. The negated condition is
shown towards the bottom of the page relative to the asserted condition.

The interface uses a mixture of negative and positive signals for control and data. The terms asserted and
negated are used for consistency and are independent of electrical characteristics.

In all timing diagrams, the lower line indicates negated, and the upper line indicates asserted. The following
illustrates the representation of a signal named TEST going from negated to asserted and back to negated,
based on the polarity of the signal.

Assert Negate
TEST
> V iH
< V iL

Assert Negate
TEST-
< V iL
> V iH

3.2.7 Byte ordering for data transfers

Assuming a block of data contains "n" bytes of information, the bytes are labeled Byte(0) through Byte(n-1),
where Byte(0) is first byte of the block, and Byte(n-1) is the last byte of the block. Table 1 shows the order
the bytes shall be presented in when such a block of data is transferred on the interface (see 8.12.8 and
8.13.8).

Page 7
T13/1153D revision 18

Table 1 − Byte order

DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
First transfer Byte (1) Byte (0)
Second transfer Byte (3) Byte (2)
........
Last transfer Byte (n-1) Byte (n-2)

NOTE − The above description is for data on the interface. Host systems and/or host
adapters may cause the order of data, as seen in the memory of the host, to be different.

Page 8
 T13/1153D revision 18

4 Interface physical and electrical requirements

Connectors are documented in annex A.

4.1 Cable configuration

This standard defines an interface containing a single host or host adapter and one or two devices. If two
devices are connected to the interface, they are connected in a daisychained configuration. One device is
configured as Device 0 and the other device as Device 1.

The designation of a device as Device 0 or Device 1 may be made in a number of ways including but not
limited to:

− a switch or a jumper on the device;

− use of the Cable Select (CSEL) pin.

The host shall be placed at one end of the cable.

Host or
adapter

Device Device

Host or
adapter

Device

Host or
adapter

Device
See note

NOTE − If a single device configuration is implemented with the device

in the middle, a cable stub results that may cause degradation of
signals (also see 5.2.13).

Figure 1 − Interface cabling diagram

Page 9
T13/1153D revision 18

4.2 I/O cable

The cable specification affects system integrity and the maximum length that shall be supported in any
application.

Cable total length shall not exceed 0.46 m (18 in).

Cable capacitance shall not exceed 35 pf.

4.3 Electrical characteristics

Table 2 defines the DC characteristics of the interface signals. Table 3 defines the AC characteristics.

Table 2 − DC characteristics
Description Min Max
IoL Driver sink current (see note 1) 4 mA
IoH Driver source current (see note 2) 400 µA
ViH Voltage input high 2.0 VDC
ViL Voltage input low 0.8 VDC
VoH Voltage output high (I oH = -400 µA) 2.4 VDC
VoL Voltage output low (IoL = 12 ma) 0.5 VDC
NOTES −
1 IoL for DASP shall be 12 mA minimum to meet legacy timing and signal integrity.
2 IoH value at 400 µA is insufficient in the case of DMARQ that is typically pulled low by a
5.6 kΩ resistor.

Table 3 − AC characteristics
Description Min Max
tRISE Rise time for any signal on AT interface (see note) 5 ns
tFALL Fall time for any signal on AT interface (see note) 5 ns
Cin Host input capacitance 25 pf
Cout Host output capacitance 25 pf
Cin Device input capacitance 20 pf
Cout Device output capacitance 20 pf
NOTE − tRISE and tFALL are measured from 10-90% of full signal amplitude with a total
capacitive load of 40 pf.

Page 10
 T13/1153D revision 18

4.3.1 Driver types and required termination

Table 4 − Driver types and required termination

Signal Source Driver type Host Device Notes
(see note (see note 2) (see note 2)
1)
RESET Host TP
DD (15:0) Bidir TS 3
DMARQ Device TS 5.6 kΩ PD 4
DIOR-:HDMARDY- Host TS
:HSTROBE
DIOW-:STOP Host TS
IORDY:DDMARDY- Device TS 1.0 kΩ PU 7,11
:DSTROBE
CSEL Host Ground 10 kΩ PU 5, 7
DMACK- Host TP
INTRQ Device TS 10 kΩ 6
DA (2:0) Host TP
PDIAG-:CBLID- Device TS 10 kΩ PU 7,8,9
CS0- CS1- Host TP
DASP- Device OC 10 kΩ PU 7,10
NOTES −
1 TS=Tri-state; OC=Open Collector; TP=Totem-pole; PU=Pull-up; PD=Pull-down.
2 All resistor values are minimum (lowest) allowed.
3 Devices shall not have a pull-up resistor on DD7. The host shall have a 10 kΩ pull-down
resistor and not a pull-up resistor on DD7 to allow a host to recognize the absence of a
device at power-up.
4 DMARQ shall be driven from its first assertion at the beginning of a DMA transfer until it
is negated after the last word is transferred. This signal shall be tri-stated at all other
times.
5 When used as CSEL, this line is grounded at the Host and a 10 kΩ pull-up is required
at both devices.
6 A 10 kΩ pull-down or pull-up, depending upon the level sensed, should be required at
the host.
7 Pull-up values are based on +5 v Vcc.
8 The host shall not connect to the PDIAG- signal.
9 CBLID- shall be used only for 80-conductor cable assemblies and shall be connected to
the ground pins in the host-side connectors for all of those assemblies.
10 The host shall not drive DASP-. If the host connects to DASP- for any purpose, the
host shall ensure that the signal level detected on the interface for DASP- shall maintain
VoH and VoL compatibility, given the I oH and IoL requirements of the DASP- device drivers.
11 Values greater than 1 kΩ may improve noise margin.

4.3.2 Electrical characteristics for Ultra DMA

4.3.2.1 Cable configuration

In a dual cable configuration (shared primary and secondary ports), DMACK- shall not be shared. DIOR-,
DIOW-, and IORDY should not be shared.

4.3.2.2 Series termination required for Ultra DMA

Series termination resistors are required at both the host and the device for operation in any of the Ultra
DMA modes. Table 5 describes typical values for series termination at the host and the device.

Page 11
T13/1153D revision 18

Table 5 − Typical series termination for Ultra DMA

Signal Host Termination Device Termination
DIOR-:HDMARDY- 22 ohm 82 ohm
:HSTROBE
DIOW-:STOP 22 ohm 82 ohm
CS0-, CS1- 33 ohm 82 ohm
DA0, DA1, DA2 33 ohm 82 ohm
DMACK- 22 ohm 82 ohm
DD15 through DD0 33 ohm 33 ohm
DMARQ 82 ohm 22 ohm
INTRQ 82 ohm 22 ohm
IORDY:DDMARDY- 82 ohm 22 ohm
:DSTROBE
RESET- 33 ohm 82 ohm
NOTE − Only those signals requiring termination are listed in this table. If
a signal is not listed, series termination is not required for operation in an
Ultra DMA mode. Figure 2 shows signals also requiring a pull-up or pull-
down resistor at the host. The actual termination values should be selected
to compensate for transceiver and trace impedance to match the
characteristic cable impedance.

VCC

IORDY DMARQ

DD 7

Figure 2 − Ultra DMA termination with pull-up or pull-down

Page 12
 T13/1153D revision 18

5 Interface signal assignments and descriptions

5.1 Signal summary

The physical interface consists of receivers and drivers communicating through a set of conductors using
an asynchronous interface protocol. Table 6 defines the signal names. For connector descriptions see
annex A. For driver and termination definition see 4.3.1. For signal protocol and timing see clause 9 and
clause 10.

Table 6 − Interface signal name assignments

Description Host Dir Dev Acronym
Cable select (see note) CSEL
Chip select 0 → CS0-
Chip select 1 → CS1-
Data bus bit 0 ↔ DD0
Data bus bit 1 ↔ DD1
Data bus bit 2 ↔ DD2
Data bus bit 3 ↔ DD3
Data bus bit 4 ↔ DD4
Data bus bit 5 ↔ DD5
Data bus bit 6 ↔ DD6
Data bus bit 7 ↔ DD7
Data bus bit 8 ↔ DD8
Data bus bit 9 ↔ DD9
Data bus bit 10 ↔ DD10
Data bus bit 11 ↔ DD11
Data bus bit 12 ↔ DD12
Data bus bit 13 ↔ DD13
Data bus bit 14 ↔ DD14
Data bus bit 15 ↔ DD15
Device active or slave (Device 1) present (see note) DASP-
Device address bit 0 → DA0
Device address bit 1 → DA1
Device address bit 2 → DA2
DMA acknowledge → DMACK-
DMA request ← DMARQ
Interrupt request ← INTRQ
I/O read → DIOR-
DMA ready during Ultra DMA data in bursts → HDMARDY-
Data strobe during Ultra DMA data out bursts → HSTROBE
I/O ready ← IORDY
DMA ready during Ultra DMA data out bursts ← DDMARDY-
Data strobe during Ultra DMA data in bursts ← DSTROBE
I/O write → DIOW-
Stop during Ultra DMA data bursts → STOP
Passed diagnostics (see note) PDIAG-
Cable assembly type identifier (see note) CBLID-
Reset → RESET-
NOTE − See signal descriptions and annex A for information on source of these signals

Page 13
T13/1153D revision 18

5.2 Signal descriptions

5.2.1 CS (1:0)- (Chip select)

These are the chip select signals from the host used to select the Command Block registers (see 7.2). When
DMACK- is asserted, CS0- and CS1- shall be negated and transfers shall be 16-bits wide.

5.2.2 DA (2:0) (Device address)

This is the 3-bit binary coded address asserted by the host to access a register or data port in the device
(see 7.2).

5.2.3 DASP- (Device active, device 1 present)

This is a time-multiplexed signal that indicates that a device is active, or that Device 1 is present.

NOTE − The indication that the device is active may be unsynchronized with the execution
of the command.

5.2.4 DD (15:0) (Device data)

This is an 8- or 16-bit bi-directional data interface between the host and the device. The lower 8 bits are
used for 8-bit register transfers. Data transfers are 16-bits wide.

5.2.5 DIOR-:HDMARDY-:HSTROBE (Device I/O read:Ultra DMA ready:Ultra DMA data strobe)

DIOR- is the strobe signal asserted by the host to read device registers or the data port.

HDMARDY- is a flow control signal for Ultra DMA data in bursts. This signal is asserted by the host to
indicate to the device that the host is ready to receive Ultra DMA data in bursts. The host may negate
HDMARDY- to pause an Ultra DMA data in burst.

HSTROBE is the data out strobe signal from the host for an Ultra DMA data out burst. Both the rising and
falling edge of HSTROBE latch the data from DD(15:0) into the device. The host may stop generating
HSTROBE edges to pause an Ultra DMA data out burst.

5.2.6 DIOW-:STOP (Device I/O write:Stop Ultra DMA burst)

DIOW- is the strobe signal asserted by the host to write device registers or the data port

DIOW- shall be negated by the host prior to initiation of an Ultra DMA burst. STOP shall be negated by the
host before data is transferred in an Ultra DMA burst. Assertion of STOP by the host during an Ultra DMA
burst signals the termination of the Ultra DMA burst.

5.2.7 DMACK- (DMA acknowledge)

This signal shall be used by the host in response to DMARQ to initiate DMA transfers.

5.2.8 DMARQ (DMA request)

This signal, used for DMA data transfers between host and device, shall be asserted by the device when it is
ready to transfer data to or from the host. For Mulitword DMA transfers, the direction of data transfer is
controlled by DIOR- and DIOW-. This signal is used in a handshake manner with DMACK-, i.e., the device
shall wait until the host asserts DMACK- before negating DMARQ, and re-asserting DMARQ if there is more
data to transfer.

Page 14
 T13/1153D revision 18

When a DMA operation is enabled, CS0- and CS1- shall not be asserted and transfers shall be 16-bits wide.

5.2.9 INTRQ (Device interrupt)

This signal is used by the selected device to interrupt the host system. When the nIEN bit is cleared to zero,
and the device is selected, INTRQ shall be enabled through a tri-state buffer and shall be driven either
asserted or negated. When the nIEN bit is set to one, or the device is not selected, the INTRQ signal shall
be in a high impedance state.

When asserted, this signal shall be negated by the device within 400 ns of the negation of DIOR- that reads
the Status register. When asserted, this signal shall be negated by the device within 400 ns of the negation
of DIOW- that writes the Command register.

When the device is selected by writing to the Device/Head register while an interrupt is pending, INTRQ
shall be asserted within 400 ns of the negation of DIOW- that writes the Device/Head register. When the
device is deselected by writing to the Device/Head register while an interrupt is pending, INTRQ shall be
negated within 400 ns of the negation of DIOW- that writes the Device/Head register.

For devices implementing the Overlapped feature set, if interrupts are being disabled using nIEN at the
same instant that the device asserts INTRQ, the minimum pulse width of INTRQ should be at least 40 ns.

5.2.10 IORDY:DDMARDY-:DSTROBE (I/O channel ready:Ultra DMA ready:Ultra DMA data strobe)

This signal is negated to extend the host transfer cycle of any host register access (Read or Write) when the
device is not ready to respond to a data transfer request.

If the device requires to extend the host transfer cycle time at PIO modes 3 and above, the device shall
utilize IORDY. Hosts that use PIO modes 3 and above shall support IORDY.

DDMARDY- is a flow control signal for Ultra DMA data out bursts. This signal is asserted by the device to
indicate to the host that the device is ready to receive Ultra DMA data out bursts. The device may negate
DDMARDY- to pause an Ultra DMA data out burst.

DSTROBE is the data in strobe signal from the device for an Ultra DMA data in burst. Both the rising and
falling edge of DSTROBE latch the data from DD(15:0) into the host. The device may stop generating
DSTROBE edges to pause an Ultra DMA data in burst.

5.2.11 PDIAG-:CBLID- (Passed diagnostics:Cable assembly type identifier)

PDIAG- shall be asserted by Device 1 to indicate to Device 0 that it has completed diagnostics (see clause
9).

The host may sample CBLID- after a power-on or hardware reset in order to detect the presence or absence
of an 80-conductor cable assembly by performing the following steps:

a) The host shall wait until the power on or hardware reset sequence is complete for all devices on
the cable;
b) If Device 1 is present, the host should issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE
and use the returned data to determine that Device 1 is compliant with ATA-3 or subsequent
standards. Any device compliant with ATA-3 or subsequent standards releases PDIAG- no later
than after the first command following a power on or hardware reset sequence.

NOTE − Older devices not in compliance with this standard or ATA-3 may continue to
assert this signal providing a false indication of the cable type. Issuing IDENTIFY DEVICE
or IDENTIFY PACKET DEVICE not only provides the host with the information required to
verify that the devices are compliant with these standards, but also provides a command
resulting in the release of this signal.

Page 15
T13/1153D revision 18

If the host detects that CBLID- is connected to ground, then an 80-conductor cable assembly is installed in
the system. If the host detects that this signal is not connected to ground, then an 80-conductor cable
assembly is not installed in the system.

Open PDIAG- conductor

CBLID-

Host Device 1 Device 0

NOTE − CBLID- is grounded in the 80-conductor cable assembly host connector for the
purpose of indicating to the host that the cable assembly being used is an 80-conductor
assembly not a 40-conductor assembly.

Figure 3 − PDIAG- example using an 80-conductor cable assembly

5.2.12 RESET- (Hardware reset)

This signal, referred to as hardware reset, shall be used by the host to reset the device (see 9.2).

5.2.13 CSEL (Cable select)

The device is configured as either Device 0 or Device 1 depending upon the value of CSEL:

− If CSEL is negated then the device address is 0;

− If CSEL is asserted then the device address is 1.

NOTE − Special cabling may be used to selectively ground CSEL e.g., CSEL of Device 0 is
connected to the CSEL conductor in the cable, and is grounded, thus allowing the device to
recognize itself as Device 0. CSEL of Device 1 is not connected to CSEL because the
conductor is removed, thus the device recognizes itself as Device 1. It should be recognized
that if a single device is configured at the end of the cable using CSEL, a device 1 only
configuration results.

Page 16
 T13/1153D revision 18

CSEL conductor

Open
Ground

Host Device 0 Device 1

CSEL conductor

Open
Ground

Host Device 1

CSEL conductor

See note Open

Ground

Host Device 0

NOTE − If a single device configuration is implemented with the device in the middle, a cable
stub results that may cause degradation of signals.
Figure 4 − Cable select example

NOTE − For designated cable assemblies (including all 80-conductor cable assemblies):
these assemblies are constructed so that CSEL is connected from the host connector to the
connector at the opposite end of the cable from the host. Therefore, Device 0 shall be at the
opposite end of the cable from the host. It should be recognized that if a single device is
configured at the connector not at the end of the cable, a Device 1 only configuration
results.

Page 17
T13/1153D revision 18

CSEL conductor
Open
Ground

Host Device 1 Device 0

CSEL conductor
Open
Ground

Host Device 0

CSEL conductor

See note Open

Ground

Host Device 1

NOTE − If a single device configuration is implemented with the device in the middle, a cable
stub results that may cause degradation of signals.
Figure 5 − Alternate cable select example

Page 18
 T13/1153D revision 18

6 General operational requirements

6.1 Command delivery

Commands may be delivered in two forms. For devices that do not implement the PACKET Command
feature set, all commands and command parameters are delivered by writing the device Command Block
registers. Such commands are defined as register delivered commands.

Devices that implement the PACKET Command feature set utilize packet delivered commands as well as
some register delivered commands.

All register delivered commands and the PACKET command are described in clause 8.

NOTE − The content of command packets delivered by the PACKET command are not
described in this specification.

6.2 Register delivered data transfer command sector addressing

For register delivered data transfer commands all addressing of data sectors recorded on the device's
media is by a logical sector address. There is no implied relationship between logical sector addresses and
the actual physical location of the data sector on the media.

Devices shall support translations as described below:

− All devices shall support LBA translation.

− If the device’s capacity is greater than or equal to one sector and less than or equal to
16,514,064 sectors the device shall support CHS translation.
− If the device’s capacity is greater than 16,514,064 sectors, then the device may support CHS
translation.
− If a device supports CHS translation, then, following a power-on or hardware reset, the CHS
translation enabled by the device shall be known as the default translation.
− If a device supports CHS translation, then a device may allow a host to use the INITIALIZE
DEVICE PARAMETERS command to select other CHS translations.
− If a device supports CHS translation, then IDENTIFY DEVICE words 1,3, and 6 shall describe
the default translation, and words 53-58 shall describe the current translation.

A CHS address is made up of three fields: the sector number, the head number, and the cylinder number.
Sectors are numbered from 1 to the maximum value allowed by the current CHS translation but shall not
exceed 255. Heads are numbered from 0 to the maximum value allowed by the current CHS translation but
shall not exceed 15. Cylinders are numbered from 0 to the maximum value allowed by the current CHS
translation but cannot exceed 65,535.

When the host selects a CHS translation using the INITIALIZE DEVICE PARAMETERS command, the host
requests the number of sectors per logical track and the number of heads per logical cylinder. The device
then computes the number of logical cylinders available in requested translation.

A device shall not change the addressing method specified by the command and shall return status
information utilizing the addressing method specified for the command.

1) The host may select either the currently selected CHS translation addressing or LBA addressing on
a command-by-command basis by using the LBA bit in the Device/Head register;

2) The device shall support LBA addressing for all media access commands.;

Page 19
T13/1153D revision 18

3) Logical sectors on the device shall be linearly mapped with the first LBA addressed sector (sector 0)
being the same sector as the first logical CHS addressed sector (cylinder 0, head 0, sector 1).
Irrespective of the logical CHS translation currently in effect, the LBA address of a given logical
sector does not change. The following is always true for LBA numbers less than or equal to
16,514,064 for devices supporting the current CHS translation:

LBA = ((cylinder * heads_ per_ cylinder + heads ) * sectors_ per_ track )+ sector − 1

where heads_per_cylinder and sectors_per_track are the current translation values.

6.2.1 Definitions and value ranges of IDENTIFY DEVICE words(see 8.12)

1) Word 1 shall contain the number of user-addressable logical cylinders in the default CHS translation. If
the content of words (61:60) is less than 16,514,064 then the content of word 1 shall be greater than or
equal to one and less than or equal to 65,535. If the content of words (61:60) is greater than or equal to
16,514,064 then the content of word 1 shall be equal to 16,383.
2) Word 3 shall contain the number of user-addressable logical heads in the default CHS translation. The
content of word 3 shall be greater than or equal to one and less than or equal to 16. For compatibility
with some BIOSs, the content of word 3 may be equal to 15 if the content of word 1 is greater than
8192.
3) Word 6 shall contain the number of user-addressable logical sectors in the default CHS translation. The
content of word 6 shall be greater than or equal to one and less than or equal to 63.
4) [(The content of word 1) * (the content of word 3) * (the content of word 6)] shall be less than or equal to
16,514,064.
5) Word 54 shall contain the number of user-addressable logical cylinders in the current CHS translation.
The content of word 54 shall be greater than or equal to one and less than or equal to 65,535. After
power-on or after a hardware reset the content of word 54 shall be equal to the content of word 1.
6) Word 55 shall contain the number of user-addressable logical heads in the current CHS translation. The
content of word 55 shall be greater than or equal to one and less than or equal to 16. After power-on or
after a hardware reset the content of word 55 shall be equal to the content of word 3.
7) Word 56 shall contain the number of user-addressable logical sectors in the current CHS translation.
The content of word 56 should be equal to 63 for compatibility with all BIOSs. However, the content of
word 56 may be greater than or equal to one and less than or equal to 255. At power-on or after a
hardware reset the content of word 56 shall equal the content of word 6.
8) Words (58:57) shall contain the user-addressable capacity in sectors for the current CHS translation.
The content of words (58:57) shall equal [(the content of word 54) * (the content of word 55) * (the
content of word 56)]. The content of words (58:57) shall be less than or equal to 16,514,064. The
content of words (58:57) shall be less than or equal to the content of words (61:60).
9) The content of words 54, 55, 56, and (58:57) may be affected by the host issuing an INITIALIZE
DEVICE PARAMETERS command (see 8.16).
10) If the content of words (61:60) is greater than 16,514,064 and if the device does not support CHS
addressing, then the content of words 1, 3, 6, 54, 55, 56, and (58:57) shall equal zero. If the content of
word 1, word 3, or word 6 equals zero, then the content of words 1, 3, 6, 54, 55, 56, and (58:57) shall
equal zero.
11) Words (61:60) shall contain the total number of user-addressable sectors. The content of words (61:60)
shall be greater than or equal to one and less than or equal to 268,435,456.
12) The content of words 1, 54, (58:57), and (61:60) may be affected by the host issuing a SET MAX
ADDRESS command (see 8.38).

6.2.2 Addressing constraints and error reporting

1) Devices may access any address in the current CHS translation if [(the requested cylinder +1) * (the
requested head + 1) * (the requested sector)] is less than or equal to the content of words (61:60).
2) Devices may respond with an “ID NOT FOUND” or a command aborted error to any command with a
CHS address request where one or more of the following are true:
3) The requested cylinder value is greater than [(the content of word 54) - 1]
4) The requested head value is greater than [(the content of word 55) - 1]

Page 20
 T13/1153D revision 18

5) The requested sector value is zero or greater than the content of word 56
6) Devices shall respond with an “ID NOT FOUND” or a command aborted error to any command with an
LBA address request where the requested LBA number is greater than or equal to the content of words
(61:60).

6.3 General feature set

The General feature set defines the common commands implemented by devices.

6.3.1 General feature set for devices not implementing the PACKET command feature set

The following General feature set commands are mandatory for all devices not implementing the PACKET
command feature set:
− EXECUTE DEVICE DIAGNOSTIC
− IDENTIFY DEVICE
− INITIALIZE DEVICE PARAMETERS
− READ DMA
− READ MULTIPLE
− READ SECTOR(S)
− READ VERIFY SECTOR(S)
− SEEK
− SET FEATURES
− SET MULTIPLE MODE
− WRITE DMA
− WRITE MULTIPLE
− WRITE SECTOR(S)

The following General feature set commands are optional for devices not implementing the PACKET
command feature set:
− DOWNLOAD MICROCODE
− FLUSH CACHE
− NOP
− READ BUFFER
− WRITE BUFFER

Read only devices shall return command aborted in response to write commands.

The following General feature set command is prohibited for use by devices not implementing the PACKET
command feature set:
− DEVICE RESET

The following resets are mandatory for devices not implementing the PACKET command feature set:

− Power On Reset: Executed at power on, the device executes a series of electrical circuitry
diagnostics, spins up the HDA, tests speed and other mechanical parametrics, and sets default
values (see 9.2).
− Hardware Reset: Executed in response to the assertion of the RESET- signal the device
executes a series of electrical circuitry diagnostics, and resets to default values (see 9.2).
− Software Reset: Executed in response to the setting of the SRST bit in the Device Control
register the device resets the interface circuitry (see 9.3).

Page 21
T13/1153D revision 18

6.3.2 General feature set for devices implementing the PACKET command feature set

The following General feature set commands are mandatory for all devices implementing the PACKET
command feature set:
− DEVICE RESET
− EXECUTE DEVICE DIAGNOSTIC
− IDENTIFY DEVICE
− IDENTIFY PACKET DEVICE
− NOP
− READ SECTOR(S)
− SET FEATURES

The following General command set commands are optional for devices implementing the PACKET
command feature set:
− FLUSH CACHE

The following General command set commands are prohibited for use by devices implementing the
PACKET command feature set.
− DOWNLOAD MICROCODE
− INITIALIZE DEVICE PARAMETERS
− READ BUFFER
− READ DMA
− READ MULTIPLE
− READ VERIFY
− SEEK
− SET MULTIPLE MODE
− WRITE BUFFER
− WRITE DMA
− WRITE MULTIPLE
− WRITE SECTOR(S)

The following resets are mandatory for devices implementing the PACKET command feature set:
− Power On Reset: Executed at power on, the device executes a series of electrical circuitry
diagnostics, spins up the HDA, tests speed and other mechanical parametrics, and sets default
values (see 9.2).
− Hardware Reset: Executed in response to the assertion of the RESET- signal the device
executes a series of electrical circuitry diagnostics, and resets to default values (see 9.2).
− Software Reset: Executed in response to the setting of the SRST bit in the Device Control
register the device resets the interface circuitry (see 9.3).
− Device Reset: Executed in response to the DEVICE RESET command the device resets the
interface circuitry (see 8.7).

6.4 Ultra DMA feature set

6.4.1 Overview

Ultra DMA is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED,
WRITE DMA QUEUED, and PACKET commands. When this protocol is enabled it shall be used instead of
the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the
Ultra DMA data burst only. When this protocol is used there are no changes to other elements of the ATA
protocol (e.g., Command Block Register access).

Several signal lines are redefined to provide new functions during an Ultra DMA burst. These lines assume
these definitions when:
1) an Ultra DMA mode is selected, and

Page 22
 T13/1153D revision 18

2) a host issues a READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED, or a PACKET
command requiring data transfer, and
3) the host asserts DMACK-.
These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation of
DMACK- by the host at the termination of an Ultra DMA burst. All of the control signals are unidirectional.
DMARQ and DMACK- retain their standard definitions.

With the Ultra DMA protocol, the control signal (STROBE) that latches data from DD(15:0) is generated by
the same agent (either host or device) that drives the data onto the bus. Ownership of DD(15:0) and this
data strobe signal are given either to the device during an Ultra DMA data in burst or to the host for an Ultra
DMA data out burst.

During an Ultra DMA burst a sender shall always drive data onto the bus, and, after a sufficient time to allow
for propagation delay, cable settling, and setup time, the sender shall generate a STROBE edge to latch the
data. Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the
same frequency as the data. The highest fundamental frequency on the cable shall be 16.67 million
transitions per second or 8.33 MHz (the same as the maximum frequency for PIO mode 4 and DMA mode
2).

Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA modes
the device is capable of supporting. The Set transfer mode subcommand in the SET FEATURES command
shall be used by a host to select the Ultra DMA mode at which the system operates. The Ultra DMA mode
selected by a host shall be less than or equal to the fastest mode of which the device is capable. Only one
Ultra DMA mode shall be selected at any given time. All timing requirements for a selected Ultra DMA
mode shall be satisfied. Devices supporting Ultra DMA mode 2 shall also support Ultra DMA modes 0 and
1. Devices supporting Ultra DMA mode 1 shall also support Ultra DMA mode 0.

An Ultra DMA capable device shall retain its previously selected Ultra DMA mode after executing a
Software reset sequence or the sequence caused by receipt of a DEVICE RESET command. An Ultra DMA
capable device shall clear any previously selected Ultra DMA mode and revert to its default non-Ultra DMA
modes after executing a Power on or hardware reset.

Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA
burst the host sends the its CRC data to the device. The device compares its CRC data to the data sent
from the host. If the two values do not match the device reports an error in the error register at the end of
the command. If an error occurs during one or more Ultra DMA bursts for any one command, at the end of
the command, the device shall report the first error that occurred.

6.4.2 Phases of operation

An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts. Each
Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and
the Ultra DMA burst termination phase. In addition, an Ultra DMA burst may be paused during the data
transfer phase (see 9.13 and 9.14 for the detailed protocol descriptions for each of these phases, 10.2.4
defines the specific timing requirements). In the following rules DMARDY- is used in cases that could apply
to either DDMARDY- or HDMARDY-, and STROBE is used in cases that could apply to either DSTROBE or
HSTROBE. The following are general Ultra DMA rules.

1) An Ultra DMA burst is defined as the period from an assertion of DMACK- by the host to the subsequent
negation of DMACK-.
2) A recipient shall be prepared to receive at least two data words whenever it enters or resumes an Ultra
DMA burst.

6.4.2.1 Ultra DMA burst initiation phase rules

1) An Ultra DMA burst initiation phase begins with the assertion of DMARQ by a device and ends when the
sender generates a STROBE edge to transfer the first data word.
2) An Ultra DMA burst shall always be requested by a device asserting DMARQ.

Page 23
T13/1153D revision 18

3) A host indicates it is ready to initiate the requested Ultra DMA burst by asserting DMACK-.
4) A host shall never assert DMACK- without first detecting that DMARQ is asserted.
5) For Ultra DMA data in bursts: a device may begin driving DD(15:0) after detecting that DMACK- is
asserted, STOP negated, and HDMARDY- is asserted.
6) After asserting DMARQ or asserting DDMARDY- for an Ultra DMA data out burst, a device shall not
negate either signal until the first STROBE edge is generated.
7) After negating STOP or asserting HDMARDY- for an Ultra DMA data in burst, a host shall not change
the state of either signal until the first STROBE edge is generated.

6.4.2.2 Data transfer phase rules

1) The data transfer phase is in effect from after Ultra DMA burst initiation until Ultra DMA burst
termination.
2) A recipient pauses an Ultra DMA burst by negating DMARDY- and resumes an Ultra DMA burst by
reasserting DMARDY-.
3) A sender pauses an Ultra DMA burst by not generating STROBE edges and resumes by generating
STROBE edges.
4) A recipient shall not signal a termination request immediately when the sender stops generating
STROBE edges. In the absence of a termination from the sender the recipient shall always negate
DMARDY- and wait the required period before signaling a termination request.
5) A sender may generate STROBE edges at greater than the minimum period specified by the enabled
Ultra DMA mode. The sender shall not generate STROBE edges at less than the minimum period
specified by the enabled Ultra DMA mode. A recipient shall be able to receive data at the minimum
period specified by the enabled Ultra DMA mode.

6.4.2.3 Ultra DMA burst termination phase rules

1) Either a sender or a recipient may terminate an Ultra DMA burst.

2) Ultra DMA burst termination is not the same as command completion. If an Ultra DMA burst termination
occurs before command completion, the command shall be completed by initiation of a new Ultra DMA
burst at some later time or aborted by the host issuing a hardware or software reset to the device.
3) An Ultra DMA burst shall be paused before a recipient requests a termination.
4) A host requests a termination by asserting STOP. A device acknowledges a termination request by
negating DMARQ.
5) A device requests a termination by negating DMARQ. A host acknowledges a termination request by
asserting STOP.
6) Once a sender requests a termination, it shall not change the state of STROBE until the recipient
acknowledges the request. Then, if STROBE is not in the asserted state, the sender shall return
STROBE to the asserted state. No data shall be transferred on this transition of STROBE.
7) A sender shall return STROBE to the asserted state whenever it detects a termination request from the
recipient. No data shall be transferred nor CRC calculated on this edge of DSTROBE.
8) Once a recipient requests a termination, it shall not change DMARDY from the negated state for the
remainder of an Ultra DMA burst.
9) A recipient shall ignore a STROBE edge when DMARQ is negated or STOP is asserted.

6.5 PACKET Command feature set

The PACKET Command feature set provides for devices that require command parameters that are too
extensive to be expressed in the Command Block registers. Devices implementing the PACKET Command
feature set exhibit responses different from that exhibited by devices not implementing this feature set.

The commands unique to the PACKET Command feature set are:

− PACKET
− IDENTIFY PACKET DEVICE

Page 24
 T13/1153D revision 18

6.5.1 Identification of PACKET Command feature set devices

When executing a power on, hardware, DEVICE RESET, or software reset, a device implementing the
PACKET Command feature set performs the same reset protocol as other devices but leaves the registers
with a signature unique to PACKET Command feature set devices (see 9.1).

In addition, the IDENTIFY DEVICE command shall not be executed but shall be command aborted and shall
return a signature unique to devices implementing the PACKET Command feature set. The IDENTIFY
PACKET DEVICE command is used by the host to get identifying parameter information for a device
implementing the PACKET Command feature set (see 8.12.5.2 and 8.13).

6.5.2 PACKET Command feature set resets

Devices implementing the PACKET Command feature set respond to power-on, hardware, and software
resets as any other device except for the resulting contents in the device registers as described above.
However, software reset should not be issued while a PACKET command is in progress. PACKET
commands utilized by some devices do not terminate if a software reset is issued.

The DEVICE RESET command is provided to allow the device to be reset without effecting the other device
on the bus.

6.5.3 The PACKET command

The PACKET command allows a host to send a command to the device via a command packet. The
command packet contains the command and command parameters that the device is to execute.

Upon receipt of the PACKET command the device sets BSY to one and prepares to receive the command
packet. When ready, the device sets DRQ to one and clears BSY to zero. The command packet is then
transferred to the device by PIO transfer. When the last word of the command packet is transferred, the
device sets BSY to one, and clears DRQ to zero (see 8.21 and 9.11).

6.6 Overlapped feature set

Overlap allows devices that require extended command time to perform a bus release so that the other
device on the bus may be used. To perform a bus release the device shall clear both DRQ and BSY to zero.
When selecting the other device during overlapped operations, the host shall disable interrupts via the nIEN
bit on the currently selected device before writing the Device/Head register to select the other device.

The only commands that may be overlapped are:

− NOP (with 01h subcommand code)

− PACKET
− READ DMA QUEUED
− SERVICE
− WRITE DMA QUEUED

For the PACKET command, overlap is indicated by the OVL bit in the Features register when the PACKET
command is issued.

If the device supports PACKET command overlap, the OVL bit is set to one in the Features register and the
Release interrupt has been enabled via the SET FEATURES command, then the device shall perform a bus
release when the command packet has been received. This allows the host to select the other device to
execute commands if desired. When the device is ready to continue the command, the device sets SERV to
one, and asserts INTRQ if selected and interrupts are enabled. The host then issues the SERVICE
command to continue the execution of the command

If the device supports PACKET command overlap, the OVL bit is set to one in the Features register and the
Release interrupt has been disabled via the SET FEATURES command, then the device may or may not

Page 25
T13/1153D revision 18

perform a bus release. If the device is ready to complete execution of the command, it may complete the
command immediately as described in the non-overlap case. If the device is not ready to complete
execution of the command, the device may perform a bus release and complete the command as described
in the previous paragraph.

For the READ DMA QUEUED and WRITE DMA QUEUED commands, the device may or may not perform
a bus release. If the device is ready to complete execution of the command, it may complete the command
immediately. If the device is not ready to complete execution of the command, the device may perform a
bus release and complete the command via a service request.

If a device has an outstanding command that has been released, it can only indicate that it requires to be
serviced when it is selected. This implies that the host has to poll each device to determine if a device is
requesting service. The polling can be performed at the host either by hardware or by a software routine.
The latter implies a considerable host processor overhead. Hardware polling is initiated by the NOP Auto
Poll command.

The NOP Auto Poll command is a host adapter function and is ignored by the device. The host software can
test for the support of this feature by issuing the NOP Auto Poll command and examining the Status
register. If the host adapter does not support this feature, the response received by the host will be from the
device with the ERR bit set to one. If the host adapter does support the command, the response will be from
the host adapter with the ERR bit cleared to zero. The only action taken by a device supporting the
Overlapped feature set will be to return the error indication in the Status register and to not abort any
outstanding commands.

6.7 Queued feature set

Command queuing allows the host to issue concurrent commands to the same device. Only commands
included in the overlapped feature set may be queued. If a queue exists when a non-queued command is
received, the non-queued command shall be command aborted and the commands in the queue shall be
discarded. The ending status shall be command aborted and the results are indeterminate.

The maximum queue depth supported by a device shall be indicated in word 75 of the IDENTIFY DEVICE
or IDENTIFY PACKET DEVICE response.

A queued command shall have a Tag provided by the host in the Sector Count register to uniquely identify
the command. When the device restores register parameters during the execution of the SERVICE
command, this Tag shall be restored so that the host may identify the command for which status is being
presented. If a queued command is issued with a Tag value that is identical to the Tag value for a command
already in the queue, the entire queue shall be aborted including the new command. The ending status shall
be command aborted and the results are indeterminate. If any error occurs, the command queue shall be
aborted.

When the device is ready to continue the processing of a bus released command and BSY and DRQ are
both cleared to zero, the device requests service by setting SERV to one, setting a pending interrupt, and
asserting INTRQ if selected and if nIEN is cleared to zero. SERV shall remain set until all commands ready
for service have been serviced. The pending interrupt shall be cleared and INTRQ negated by a Status
register read or a write to the Command register.

When the device is ready to continue the processing of a bus released command and BSY or DRQ is set to
one (i.e., the device is processing another command on the bus), the device requests service by setting
SERV to one. SERV shall remain set until all commands ready for service have been serviced. At command
completion of the current command processing (i.e., when both BSY and DRQ are cleared to zero), the
device shall process interrupt pending and INTRQ per the protocol for the command being completed. No
additional interrupt shall occur due to other commands ready for service until after the device’s SERV bit
has been cleared to zero.

When the device receives a new command while queued commands are ready for service, the device shall
execute the new command and process interrupt pending and INTRQ per the protocol for the new

Page 26
 T13/1153D revision 18

command. If the queued commands ready for service still exist at command completion of this command,
SERV remains set to one but no additional interrupt shall occur due to commands ready for service.

When queuing commands, the host shall disable interrupts via the nIEN bit before writing a new command
to the Command register and may re-enable interrupts after writing the command. When reading status at
command completion of a command, the host shall check the SERV bit since the SERV bit may be set
because the device is ready for service associated with another command. The host receives no additional
interrupt to indicate that a queued command is ready for service.

6.8 Power Management feature set

A device shall implement power management. A device implementing the PACKET Command feature set
may implement the power management as defined by the packet command set implemented by the device.
Otherwise, the device shall implement the Power Management feature set as described in this standard.

The Power Management feature set permits a host to modify the behavior of a device in a manner that
reduces the power required to operate. The Power Management feature set provides a set of commands
and a timer that enable a device to implement low power consumption modes. A register delivered
command device that implements the Power Management feature set shall implement the following
minimum set of functions:

− A Standby timer
− CHECK POWER MODE command
− IDLE command
− IDLE IMMEDIATE command
− SLEEP command
− STANDBY command
− STANDBY IMMEDIATE command

A device that implements the PACKET Command feature set and implements the Power Management
feature set shall implement the following minimum set of functions:

− A Standby timer
− CHECK POWER MODE command
− IDLE IMMEDIATE command
− SLEEP command
− STANDBY IMMEDIATE command

6.8.1 Power modes

In Active mode the device is capable of responding to commands. During the execution of a media access
command a device shall be in Active mode. Power consumption is greatest in this mode.

In Idle mode the device is capable of responding to commands but the device may take longer to complete
commands than when in the Active mode. Power consumption may be reduced from that of Active mode.

In Standby mode the device is capable of responding to commands but the device may take longer to
complete commands than in the Idle mode. The time to respond could be as long as 30 s. Power
consumption may be reduced from that of Idle mode.

In Sleep mode the device requires a hardware or software reset to be activated. The time to respond could
be as long as 30 s. Sleep mode provides the lowest power consumption of any mode.

6.8.2 Power management commands

Page 27
T13/1153D revision 18

The CHECK POWER MODE command allows a host to determine if a device is currently in, going to or
leaving Standby or Idle mode. The CHECK POWER MODE command shall not change the power mode or
affect the operation of the Standby timer.

The IDLE and IDLE IMMEDIATE commands move a device to Idle mode immediately from the Active or
Standby modes. The IDLE command also sets the Standby timer count and enables or disables the
Standby timer.

The SLEEP command moves a device to Sleep mode. The device's interface becomes inactive at
command completion of the SLEEP command. A hardware or software reset or DEVICE RESET command
is required to move a device out of Sleep mode.

After receiving a reset, the device should return to the power mode it was in before receiving the reset,
unless the device was in the Sleep mode. If the device was in the Sleep mode when receiving a reset, the
device should return to the Standby mode (This may be made a mandatory requirement in a future
standard).

The STANDBY and STANDBY IMMEDIATE commands move a device to Standby mode immediately from
the Active or Idle modes. The STANDBY command also sets the Standby timer count and enables or
disables the Standby timer.

6.8.3 Standby timer

The Standby timer provides a method for the device to automatically enter Standby mode from either Active
or Idle mode following a host programmed period of inactivity. If the Standby timer is enabled and if the
device is in the Active or Idle mode, the device waits for the specified time period and if no command is
received, the device automatically enters the Standby mode.

If the Standby timer is disabled, the device may not automatically enter Standby mode.

6.8.4 Idle mode transition

If a device accepts the IDLE IMMEDIATE command, the device shall transition to the Idle mode after
receipt of the command. If the device accepts the IDLE command it shall transition to the Idle mode as
described in 8.14.8. Some devices may perform internal power management and transition to the Idle
mode without host intervention.

6.8.5 Status

In Sleep mode, the device's interface is not active. The content of the Status register is invalid in this mode.

6.8.6 Power mode transitions

Figure 6 shows the minimum set of mode transitions that shall be implemented.

Page 28
 T13/1153D revision 18

1 Active 3
4 4
5
2
Idle Standby
3

5 Sleep 5

Resets 6 6

(see path 6)

Path 1: An IDLE command, IDLE IMMEDIATE command, or vendor specific

implementation moves the device to Idle mode.
Path 2: An IDLE command or IDLE IMMEDIATE command moves the device
to Idle mode.
Path 3: A STANDBY command, STANDBY IMMEDIATE command, vendor
specific implementation, or Standby timer expiration moves the
device to Standby mode.
Path 4: A Media access command moves the device to Active mode.
Path 5: A SLEEP command moves the device to Sleep mode.
Path 6: A reset, either hardware, software, or DEVICE RESET command
moves the device to Active, Idle or Standby as specified by the device
vendor.

Figure 6 − Power management modes

6.9 Advanced Power Management feature set

The Advanced Power Management feature set is an optional feature set that allows the host to select a
power management level. The power management level is a scale from the lowest power consumption
setting of 01h to the maximum performance level of FEh. Device performance may increase with increasing
power management levels. Device power consumption may increase with increasing power management
levels. The power management levels may contain discrete bands. For example, a device may implement
one power management method from level 80h to A0h and a higher performance, higher power
consumption method from level A1h to FEh. Advanced power management levels 80h and higher do not
permit the device to spin down to save power.

The Advanced Power Management feature set uses the following functions:
− A SET FEATURES subcommand to enable Advanced Power Management
− A SET FEATURES subcommand to disable Advanced Power Management

Advanced Power Management is independent of the Standby timer setting. If both Advanced Power
Management and the Standby timer are set, the device will go to the Standby state when the timer times out
or the device’s Advanced Power Management algorithm indicates that it is time to enter the Standby state.

The IDENTIFY DEVICE word 83, bit 3 indicates that Advanced Power Management is supported if set. word
86, bit 3 indicates that Advanced Power Management is enabled if set. Word 91, bits (7:0) contain the
current advanced power management level if Advanced Power Management is enabled.

Page 29
T13/1153D revision 18

6.10 Security Mode feature set

The Security Mode feature set allows a host to implement a security password system to prevent
unauthorized access to the internal disk drive.

A device that implements the Security Mode feature set shall implement the following minimum set of
commands:

− SECURITY SET PASSWORD

− SECURITY UNLOCK
− SECURITY ERASE PREPARE
− SECURITY ERASE UNIT
− SECURITY FREEZE LOCK
− SECURITY DISABLE PASSWORD

Support of the Security Mode feature set is indicated in IDENTIFY DEVICE word 128.

6.10.1 Security mode default setting

The Master password shall be set to a vendor specific value during manufacturing and the Lock mode
disabled.

The system manufacturer/dealer may set a new Master password using the SECURITY SET PASSWORD
command, without enabling or disabling the Lock mode.

6.10.2 Initial setting of the User password

When a User password is set, the device shall automatically enter Lock mode the next time the device is
powered-on or after a hardware reset.

6.10.3 Security mode operation from power-on or hardware reset

When Lock is enabled, the device rejects media access commands until a SECURITY UNLOCK command
is successfully completed.

6.10.4 Frozen mode

The SECURITY FREEZE LOCK command places the device in Frozen mode. This prevents accidental or
malicious password activation or setting. Table 7 lists the commands that the device shall execute when in
Frozen mode. The device shall exit Frozen mode on power off. All devices that support the Security Mode
feature set should be issued a SECURITY FREEZE LOCK command during system initialization.

6.10.5 User password lost

If the User password does not match and High level security is set, the device shall not allow the user to
access data. The device shall be unlocked using the Master password.

If the User password is lost and Maximum security level is set, data access shall not be allowed. However,
the SECURITY ERASE UNIT command shall unlock the device and shall erase all user data if the Master
password matches.

6.10.6 Attempt limit for SECURITY UNLOCK command

The device shall have an attempt limit counter. The purpose of this counter is to defeat repeated trial
attacks. After each failed User or Master password SECURITY UNLOCK command, the counter is
decremented. When the counter value reaches zero the EXPIRE bit (bit 4) of word 128 in the IDENTIFY
DEVICE information is set, and the SECURITY UNLOCK and SECURITY UNIT ERASE commands are

Page 30
 T13/1153D revision 18

command aborted until the device is powered off or hardware reset. The EXPIRE bit shall be cleared to zero
after power on or hardware reset. The counter shall be set to five after a power on or hardware reset.

Page 31
T13/1153D revision 18

Command received

Locked No Frozen No SECURITY Yes

mode? mode? FREEZE
LOCK
cmd?
Yes Yes
No
Yes Media Frozen Yes
access mode
cmd? Set frozen
cmd?
mode
No No

Yes SECURITY
UNLOCK
cmd?
No
User Yes
password
match
SECURITY No
No ERASE
UNIT
cmd?
Yes
No Mode High &
Master password Previous
match No command was
SECURITY
Yes ERASE
PREPARE

Yes

User or
master
No password
match

Yes

Erase unit Execute

command

Clear user password

Abort Set unlock mode

command

Command complete

Figure 7 − Security mode flow

Page 32
 T13/1153D revision 18

Table 7 − Security mode command actions

Command Locked mode Unlocked Frozen mode
mode
CHECK POWER MODE Executable Executable Executable
CFA REQUEST EXTENDED ERROR CODE Executable Executable Executable
CFA ERASE SECTORS Command aborted Executable Executable
CFA TRANSLATE SECTOR Executable Executable Executable
CFA WRITE MULTIPLE WITHOUT ERASE Command aborted Executable Executable
CFA WRITE SECTORS WITHOUT ERASE Command aborted Executable Executable
DEVICE RESET Executable Executable Executable
DOWNLOAD MICROCODE Executable Executable Executable
EXECUTE DEVICE DIAGNOSTIC Executable Executable Executable
FLUSH CACHE Command aborted Executable Executable
GET MEDIA STATUS Command aborted Executable Executable
IDENTIFY DEVICE Executable Executable Executable
IDENTIFY PACKET DEVICE Executable Executable Executable
IDLE Executable Executable Executable
IDLE IMMEDIATE Executable Executable Executable
INITIALIZE DEVICE PARAMETERS Executable Executable Executable
MEDIA EJECT Command aborted Executable Executable
MEDIA LOCK Command aborted Executable Executable
MEDIA UNLOCK Command aborted Executable Executable
NOP Executable Executable Executable
PACKET Command aborted Executable Executable
READ BUFFER Executable Executable Executable
READ DMA Command aborted Executable Executable
READ DMA QUEUED Command aborted Executable Executable
READ MULTIPLE Command aborted Executable Executable
READ NATIVE MAX ADDRESS Executable Executable Executable
READ SECTORS Command aborted Executable Executable
READ VERIFY SECTORS Command aborted Executable Executable
SECURITY DISABLE PASSWORD Command aborted Executable Command aborted
SECURITY ERASE PREPARE Executable Executable Executable
SECURITY ERASE UNIT Executable Executable Command aborted
SECURITY FREEZE LOCK Command aborted Executable Executable
SECURITY SET PASSWORD Command aborted Executable Command aborted
SECURITY UNLOCK Executable Executable Command aborted
SEEK Executable Executable Executable
SERVICE Command aborted Executable Executable
SET FEATURES Executable Executable Executable
SET MAX ADDRESS Command aborted Executable Executable
SET MULTIPLE MODE Executable Executable Executable
SLEEP Executable Executable Executable
SMART DISABLE OPERATIONS Executable Executable Executable
SMART ENABLE/DISABLE AUTOSAVE Executable Executable Executable
SMART ENABLE OPERATIONS Executable Executable Executable
SMART EXECUTE OFF-LINE IMMEDIATE Executable Executable Executable
SMART READ DATA Executable Executable Executable
SMART RETURN STATUS Executable Executable Executable
SMART SAVE ATTRIBUTE VALUES Executable Executable Executable
STANDBY Executable Executable Executable
STANDBY IMMEDIATE Executable Executable Executable
WRITE BUFFER Executable Executable Executable
WRITE DMA Command aborted Executable Executable
WRITE DMA QUEUED Command aborted Executable Executable
WRITE MULTIPLE Command aborted Executable Executable
WRITE SECTORS Command aborted Executable Executable

Page 33
T13/1153D revision 18

6.11 Self-monitoring, analysis, and reporting technology feature set

The intent of self-monitoring, analysis, and reporting technology (the SMART feature set) is to protect user
data and minimize the likelihood of unscheduled system downtime that may be caused by predictable
degradation and/or fault of the device. By monitoring and storing critical performance and calibration
parameters, SMART feature set devices attempt to predict the likelihood of near-term degradation or fault
condition. Providing the host system the knowledge of a negative reliability condition allows the host system
to warn the user of the impending risk of a data loss and advise the user of appropriate action. Support of
this feature set is indicated in bit 0 of IDENTIFY DEVICE word 82.

Devices that implement the PACKET Command feature set shall not implement the SMART feature set as
described in this subclause. Devices that implement the PACKET Command feature set and SMART shall
implement SMART as defined by the command packet set implemented by the device.

6.11.1 Device SMART data structure

SMART feature set capability and status information for the device are stored in the device SMART data
structure. The off-line data collection capability and status data stored herein may be useful to the host if the
SMART EXECUTE OFF-LINE IMMEDIATE command is implemented (see 8.41.4).

6.11.2 On-line data collection

Collection of SMART data in an “on-line” mode shall have no impact on device performance. The SMART
data that is collected or the methods by which data is collected in this mode may be different than those in
the off-line data collection mode for any particular device and may vary from one device to another.

6.11.3 Off-line data collection

The device shall use its off-line mode for data collection routines that have an impact on performance if the
device is required to respond to commands from the host while performing that data collection. This impact
on performance may vary from device to device. The data that is collected or the methods by which the
data is collected in this mode may be different than those in the on-line data collection mode for any
particular device and may vary from one device to another.

6.11.4 Threshold exceeded condition

This condition occurs when the device’s SMART reliability status indicates an impending degrading or fault
condition.

6.11.5 SMART feature set commands

These commands use a single command code and are differentiated from one another by the value placed
in the Features register (see 8.41).

If the SMART feature set is implemented, the following commands shall be implemented.

− SMART DISABLE OPERATIONS

− SMART ENABLE/DISABLE AUTOSAVE
− SMART ENABLE OPERATIONS
− SMART RETURN STATUS

If the SMART feature set is implemented, the following commands may be implemented.

− SMART EXECUTE OFF-LINE IMMEDIATE

− SMART READ DATA

Page 34
 T13/1153D revision 18

6.11.6 SMART operation with power management modes

When used with a host that has implemented the Power Management feature set, a SMART enabled device
should automatically save its accumulated SMART data upon receipt of an IDLE IMMEDIATE, STANDBY
IMMEDIATE, or SLEEP command or upon return to an Active or Idle mode from a Standby mode (see
8.41.5).

If a SMART feature set enabled device has been set to utilize its Standby timer, the device should
automatically save its accumulated SMART data prior to going from an Idle mode to the Standby mode or
upon return to an Active or Idle mode from a Standby mode.

A device shall not execute any routine to automatically save its accumulated SMART data while the device
is in a Standby or Sleep mode.

6.12 Host Protected Area feature set

A reserved area for data storage outside the normal operating system file system is required for several
specialized applications. Systems may wish to store configuration data or save memory to the device in a
location that the operating systems cannot change. The Host Protected Area feature set allows a portion of
the device to be reserved for such an area when the device is initially configured. A device that implements
the Host Protected Area feature set shall implement the following minimum set of commands:

− READ NATIVE MAX ADDRESS

− SET MAX ADDRESS
If the Host Protected Area feature set is supported, the device shall indicate so by setting bit 10 of
IDENTIFY DEVICE word 82.

The READ NATIVE MAX ADDRESS command allows the host to determine the maximum native address
space of the device even when a protected area has been allocated.

The SET MAX ADDRESS command allows the host to redefine the maximum address of the user
accessible address space. That is, when the SET MAX ADDRESS command is issued with a maximum
address less than the native maximum address, the device reduces the user accessible address space to
the maximum set, providing a protected area above that maximum address. The SET MAX ADDRESS
command shall be immediately preceded by a READ NATIVE MAX ADDRESS command. After the SET
MAX ADDRESS command has been issued, the device shall report only the reduced user address space in
response to an IDENTIFY DEVICE command in words 1, 54, 57, 58, 60, and 61. Any read or write
command to an address above the maximum address specified by the SET MAX ADDRESS command shall
cause command completion with the IDNF bit set to one and ERR set to one, or command aborted. A
volatility bit in the Sector Count register allows the host to specify if the maximum address set is preserved
across power-up or hardware reset cycles. On power up or hardware reset the device maximum address
returns to the last non-volatile address setting regardless of subsequent volatile SET MAX ADDRESS
commands. If the SET MAX ADDRESS command is issued with a value that exceeds the native maximum
address command aborted shall be returned.

Page 35
T13/1153D revision 18

Typical use of these commands would be:

On Reset
a) BIOS receives control after a system reset;
b) BIOS issues a READ NATIVE MAX ADDRESS command to find the max capacity of the
device;
c) BIOS issues a SET MAX ADDRESS command to the values returned by READ NATIVE MAX
ADDRESS;
d) BIOS reads configuration data from the highest area on the disk;
e) BIOS issues a READ NATIVE MAX ADDRESS command followed by a SET MAX ADDRESS
command to reset the device to the size of the file system.

On Save to Disk
a) BIOS receives control prior to shut down;
b) BIOS issues a READ NATIVE MAX ADDRESS command to find the max capacity of the
device;
c) BIOS issues a volatile SET MAX ADDRESS command to the values returned by READ NATIVE
MAX ADDRESS;
d) Memory is copied to the reserved area;
e) Shut down completes;
f) On power on or hardware reset the device max address returns to the last non-volatile setting.

These commands are intended for use only by system BIOS or other low level boot time process. The
process should select a single addressing translation, CHS or LBA, for all SET MAX ADDRESS and READ
NATIVE MAX ADDRESS commands. Using these commands outside BIOS controlled boot or shutdown
may result in damage to file systems on the device. Devices should command aborted a second non-
volatile SET MAX ADDRESS command after a power on or hardware reset

6.12.1 Host protected area orphan sectors

Issuing a SET MAX ADDRESS command with an LBA value may create orphan sectors just as an
INITIALIZE DEVICE PARAMETERS command may create such sectors (see B.3). If the SET MAX
ADDRESS LBA value does not correspond to a cylinder boundary, orphan sectors are created. The device
shall report the CHS boundary just below the requested LBA value in word 1. Sectors above this cylinder
boundary are orphan sectors and the device may or may not allow access to them in CHS translation.

6.13 CFA feature set

The CompactFlash Association (CFA) feature set provides support for solid state memory devices. The
commands provided for the CFA feature set are:
− CFA REQUEST EXTENDED ERROR CODE
− CFA WRITE SECTORS WITHOUT ERASE
− CFA ERASE SECTORS
− CFA WRITE MULTIPLE WITHOUT ERASE
− CFA TRANSLATE SECTOR

Devices reporting the value 848Ah in IDENTIFY DEVICE data word 0 or devices having bit 2 of IDENTIFY
DEVICE data word 83 set to one shall support the CFA feature Set. If the CFA feature set is implemented,
all five commands shall be implemented.

Support of DMA commands is optional for devices that support the CFA feature set.

The CFA ERASE SECTORS command preconditions the sector for a subsequent CFA WRITE SECTORS
WITHOUT ERASE or CFA WRITE MULTIPLE WITHOUT ERASE command to achieve higher performance
during the write operation. The CFA TRANSLATE SECTOR command provides information about a sector
such as the number of write cycles performed on that sector and an indication of the sector’s erased
precondition. The CFA REQUEST EXTENDED ERROR CODE command provides more detailed error
information.

Page 36
 T13/1153D revision 18

6.14 Removable Media Status Notification and Removable Media feature sets
This section describes two feature sets that secure the media in removable media storage devices using the
ATA/ATAPI interface protocols. First, the Removable Media Status Notification feature set is intended for
use in both devices implementing the PACKET command feature set and those not implementing the
PACKET command feature set. Second, the Removable Media feature set is intended for use only in
devices not implementing the PACKET command feature set. Only one of these feature sets is enabled at
any time. If the Removable Media Status Notification feature set is in use then the Removable Media
feature set is disabled and vice versa.

The reasons for implementing the Removable Media Status Notification feature Set or the Removable
Media feature set are:
− to prevent data loss caused by writing to new media while still referencing the previous media’s
information.
− to prevent data loss by locking the media until completion of a cached write.
− to prevent removal of the media by unauthorized persons.
6.14.1 Removable Media Status Notification feature set

The Removable Media Status Notification feature set is the preferred feature set for securing the media in
removable media storage devices. This feature set uses the SET FEATURES command to enable
Removable Media Status Notification. Removable Media Status Notification gives the host system
maximum control of the media. The host system determines media status by issuing the GET MEDIA
STATUS command and controls the device eject mechanism via the MEDIA EJECT command (for devices
not implementing the PACKET command feature set) or the START/STOP UNIT command (for devices
implementing the PACKET command feature set). While Removable Media Status Notification is enabled
devices not implementing the PACKET command feature set execute MEDIA LOCK and MEDIA UNLOCK
commands without changing the media lock state (no-operation). While Removable Media Status
Notification is enabled the eject button does not eject the media.

Removable Media Status Notification is persistent through medium removal and insertion and is only
disabled via the SET FEATURES command, hardware reset, software reset, the DEVICE RESET
command, the EXECUTE DEVICE DIAGNOSTIC command, or power on reset. Removable Media Status
Notification shall be re-enabled after any of the previous reset conditions occur. All media status is reset
when Removable Media Status Notification is disabled because a reset condition occurred. Any pending
media change or media change request is cleared when the Removable Media Status Notification reset
condition occurs.

The following task file commands are defined to implement the Removable Media Status Notification
feature set.
− GET MEDIA STATUS
− MEDIA EJECT
− SET FEATURES (Enable media status notification)
− SET FEATURES (Disable media status notification)

NOTE − Devices implementing the PACKET command feature set control the media eject
mechanism via the START/STOP UNIT packet command.

The preferred sequence of events to use the Removable Media Status Notification feature set is as follows:

a) Host system checks whether or not the device implements the PACKET command feature set via
the device signature in the task file registers.
b) Host system issues the IDENTIFY DEVICE command or the IDENTIFY PACKET DEVICE
command and checks word 0, bit 7 (removable media device) and word 83, bit 4 (Removable Media
Status Notification feature set supported).

Page 37
T13/1153D revision 18

c) Host system uses the SET FEATURES command to enable Media Status Notification that gives
control of the media to the host. At this time the host system checks the Cylinder High register to
determine if :
− the device is capable of locking the media.
− the device is capable of power ejecting the media.
− Media Status Notification was enabled prior to this command.
d) Host system periodically checks media status using the GET MEDIA STATUS command to
determine if any of the following events occurred:
− no media is present in the device (NM).
− media was changed since the last command (MC).
− a media change request has occurred (MCR).
− media is write protected (WP).
6.14.2 Removable Media feature set

The Removable Media feature set is intended only for devices not implementing the PACKET command
feature set. This feature set operates with Media Status Notification disabled. The MEDIA LOCK and
MEDIA UNLOCK commands are used to secure the media and the MEDIA EJECT command is used to
remove the media. While the media is locked the eject button does not eject the disk. Media status is
determined by checking the media status bits returned by the MEDIA LOCK and MEDIA UNLOCK
commands.

Power up reset, hardware reset, and the EXECUTE DEVICE DIAGNOSTIC command clear the Media Lock
(LOCK) state and the Media Change Request (MCR) state. Software reset clears the Media Lock (LOCK)
state, clears the Media Change Request (MCR) state, and preserves the Media Change (MC) state.

The following commands are defined to implement the Removable Media feature set.
− MEDIA EJECT
− MEDIA LOCK
− MEDIA UNLOCK

The preferred sequence of events to use the Removable Media feature set is as follows:

a) Host system checks whether or not the device implements the PACKET command feature set via
the device signature in the task file registers.
b) Host system issues the IDENTIFY DEVICE command and checks word 0, bit 7 (removable media
device) and word 82, bit 2 (Removable Media feature set supported).
c) Host system periodically issues MEDIA LOCK commands to determine if:
− no media is present in the device (NM) - media is locked if present.
− a media change request has occurred (MCR).

Page 38
 T13/1153D revision 18

7 Interface register definitions and descriptions

7.1 Device addressing considerations

In traditional controller operation, only the selected device receives commands from the host following
selection. In this standard, the register contents go to both devices (and their embedded controllers). The
host discriminates between the two by using the DEV bit in the Device/Head register.

Data is transferred in parallel either to or from host memory to the device's buffer under the direction of
commands previously transferred from the host. The device performs all of the operations necessary to
properly write data to, or read data from, the media. Data read from the media is stored in the device's
buffer pending transfer to the host memory and data is transferred from the host memory to the device's
buffer to be written to the media.

The devices using this interface shall be programmed by the host computer to perform commands and
return status to the host at command completion. When two devices are daisychained on the interface,
commands are written in parallel to both devices, and for all except the EXECUTE DEVICE DIAGNOSTIC
command, only the selected device executes the command. Both devices shall execute an EXECUTE
DEVICE DIAGNOSTIC command regardless of which device is selected, and Device 1 shall post its status
to Device 0 via PDIAG-. When the SRST bit in the Device Control register is set to one, both devices shall
perform the software reset protocol.

Devices are selected by the DEV bit in the Device/Head register (see 7.10). When the DEV bit is equal to
zero, Device 0 is selected. When the DEV bit is equal to one, Device 1 is selected. When devices are
daisy chained, one shall be set as Device 0 and the other as Device 1.

For register access protocols and timing see clauses 9 and 10.

7.2 I/O register descriptions

Communication to or from the device is through an I/O register that routes the input or output data to or
from registers addressed by the signals from the host (CS0-, CS1-, DA (2:0), DIOR-, and DIOW-). CS0-
and CS1- both asserted or negated is an invalid (not used) address except when both are negated during a
DMA data transfer. When CS0- and CS1- are both asserted or both negated and a DMA transfer is not in
progress, the device shall hold DD (15:00) in the released state and ignore transitions on DIOR- and DIOW-.
When CS0- is negated and CS1- is asserted only DA (2:0) with a value of 6h is valid. During invalid
combinations of assertion and negation of CS0-, CS1-, DA0, DA1, and DA2, a device shall keep DD(15:0) in
the high impedance state and ignore transitions on DIOR- and DIOW-. Valid register addresses are
described in the clauses defining the registers.

The Command Block registers are used for sending commands to the device or posting status from the
device. These registers include the Cylinder High, Cylinder Low, Device/Head, Sector Count, Sector
Number, Command, Status, Features, Error, and Data registers. The Control Block registers are used for
device control and to post alternate status. These registers include the Device Control and Alternate Status
registers.

Each register description in the following clauses contain the following format:

Address - the CS and DA address of the register.

Direction - indicates if the register is read/write, read only, or write only from the host.

Access restrictions - indicates when the register may be accessed.

Effect - indicates the effect of accessing the register.

Functional description - describes the function of the register.

Page 39
T13/1153D revision 18

Field/bit description - describes the content of the register.

Page 40
 T13/1153D revision 18

7.3 Alternate Status register

7.3.1 Address

CS1 CS0 DA2 DA1 DA0

A N A A N
A = asserted, N = negated

7.3.2 Direction

This register is read only. If this address is written to by the host, the Device Control register is written.

7.3.3 Access restrictions

When the BSY bit is set to one, the other bits in this register shall not be used. The entire contents of this
register are not valid while the device is in Sleep mode.

7.3.4 Effect

Reading this register shall not clear a pending interrupt.

7.3.5 Functional description

This register contains the same information as the Status register in the command block.

See 7.15 for definitions of the bits in this register.

7.4 Command register

7.4.1 Address

CS1 CS0 DA2 DA1 DA0

N A A A A
A = asserted, N = negated

7.4.2 Direction

This register is write only. If this address is read by the host, the Status register is read.

7.4.3 Access restrictions

For all commands except DEVICE RESET, this register shall only be written when BSY and DRQ are both
equal to zero and DMACK- is not asserted. The contents of this register is not valid while a device is in the
Sleep mode. If written when BSY or DRQ is set to one, the results of writing the Command register are
indeterminate except for the DEVICE RESET command.

7.4.4 Effect

Command processing begins when this register is written. The content of the Command Block registers
become parameters of the command when this register is written. Writing this register clears any pending
interrupt condition.

Page 41
T13/1153D revision 18

7.4.5 Functional description

This register contains the command code being sent to the device. Command execution begins
immediately after this register is written. The executable commands, the command codes, and the
necessary parameters for each command are summarized in the tables in informative annex E.

7.4.6 Field/bit description

7 6 5 4 3 2 1 0
Command Code

7.5 Cylinder High register

7.5.1 Address

CS1 CS0 DA2 DA1 DA0

N A A N A
A = asserted, N = negated

7.5.2 Direction

This register is read/write.

7.5.3 Access restrictions

This register shall be written only when both BSY and DRQ are cleared to zero and DMACK- is not asserted.
The contents of this register are valid only when BSY is cleared to zero. If this register is written when BSY
or DRQ is set to one, the result is indeterminate. The contents of the this register are not valid while a
device is in the Sleep mode.

7.5.4 Effect

The content of this register becomes a command parameter when the Command register is written.

7.5.5 Functional description

The content of this register is command dependent (see clause 8).

7.6 Cylinder Low register

7.6.1 Address

CS1 CS0 DA2 DA1 DA0

N A A N N
A = asserted, N = negated

7.6.2 Direction

This register is read/write.

7.6.3 Access restrictions

This register shall be written only when both BSY and DRQ are cleared to zero and DMACK- is not asserted.
The contents of this register are valid only when BSY is cleared to zero. If this register is written when BSY
or DRQ is set to one, the result is indeterminate. The contents of the this register are not valid while a
device is in the Sleep mode.

Page 42
 T13/1153D revision 18

7.6.4 Effect

The content of this register becomes a command parameter when the Command register is written.

7.6.5 Functional description

The content of this register is command dependent (see clause 8).

7.7 Data register

7.7.1 Address

CS1 CS0 DA2 DA1 DA0

N A N N N
A = asserted, N = negated

7.7.2 Direction

This register is read/write.

7.7.3 Access restrictions

This register shall be accessed for host PIO data only when DRQ is set to one and DMACK- is not asserted.
The contents of the this register are not valid while a device is in the Sleep mode.

7.7.4 Effect

PIO out data transfers are processed by a series of reads to this register, each read transferring the data
that follows the previous read. PIO in data transfers are processed by a series of writes to this register, each
write transferring the data that follows the previous write. The results of a read during a PIO in or a write
during a PIO out are indeterminate.

7.7.5 Functional description

The data register is 16-bits wide.

7.7.6 Field/bit description

15 14 13 12 11 10 9 8
Data(15:8)

7 6 5 4 3 2 1 0
Data(7:0)

7.8 Data port

7.8.1 Address

When DMACK- is asserted, CS0- and CS1- shall be negated and transfers shall be 16-bits wide.

Page 43
T13/1153D revision 18

CS1 CS0 DA2 DA1 DA0

N N X X X
A = asserted, N = negated, X = don’t care

7.8.2 Direction

This port is read/write.

7.8.3 Access restrictions

This port shall be accessed for host DMA data transfers only when DMACK- and DMARQ are asserted.

7.8.4 Effect

DMA out data transfers are processed by a series of reads to this port, each read transferring the data that
follows the previous read. DMA in data transfers are processed by a series of writes to this port, each write
transferring the data that follows the previous write. The results of a read during a DMA in or a write during a
DMA out are indeterminate.

7.8.5 Functional description

The data port is 16-bits in width.

7.8.6 Field/bit description

15 14 13 12 11 10 9 8
Data(15:8)

7 6 5 4 3 2 1 0
Data(7:0)

7.9 Device Control register

7.9.1 Address

CS1 CS0 DA2 DA1 DA0

A N A A N
A = asserted, N = negated

7.9.2 Direction

This register is write only. If this address is read by the host, the Alternate Status register is read.

7.9.3 Access restrictions

This register shall only be written when DMACK- is not asserted.

7.9.4 Effectiveness

The content of this register shall take effect when written.

Page 44
 T13/1153D revision 18

7.9.5 Functional description

This register allows a host to software reset attached devices and to enable or disable the assertion of the
INTRQ signal by a selected device.

7.9.6 Field/bit description

7 6 5 4 3 2 1 0
r r r r r SRST nIEN 0

− Bits 7 through 3 are reserved.

− SRST is the host software reset bit (see 9.3).
− nIEN is the enable bit for the device interrupt to the host. When the nIEN bit is cleared to zero, and
the device is selected, INTRQ shall be enabled through a tri-state buffer and shall be asserted r
negated by the device as appropriate. When the nIEN bit is set to one, or the device is not
selected, the INTRQ signal shall be in a high impedance state.
− Bit 0 shall be cleared to zero.

7.10 Device/Head register

7.10.1 Address

CS1 CS0 DA2 DA1 DA0

N A A A N
A = asserted, N = negated

7.10.2 Direction

This register is read/write.

7.10.3 Access restrictions

This register shall be written only when both BSY and DRQ are cleared to zero and DMACK- is not asserted.
The contents of this register are valid only when BSY is cleared to zero. If this register is written when BSY
or DRQ is set to one, the result is indeterminate. For devices not implementing the DEVICE RESET
command, the contents of this register are not valid while a device is in the Sleep mode. For devices
implementing the DEVICE RESET command, the contents of this register are valid while the device is in
Sleep mode.

7.10.4 Effect

The DEV bit becomes effective when this register is written by the host or the signature is set by the device.
All other bits in this register become a command parameter when the Command register is written.

7.10.5 Functional description

Bit 4, DEV, in this register selects the device. Other bits in this register are command dependent (see clause
8).

7.10.6 Field/bit description

7 6 5 4 3 2 1 0
obsolete # obsolete DEV # # # #

− obsolete - These bits are obsolete.

Page 45
T13/1153D revision 18

NOTE − Some hosts set these bits to one. Devices shall ignore these bits.

− # - The content of these bits is command dependent (see clause 8).

− DEV - Device select. Cleared to zero selects Device 0. Set to one selects Device 1.

7.11 Error register

7.11.1 Address

CS1 CS0 DA2 DA1 DA0

N A N N A
A = asserted, N = negated

7.11.2 Direction

This register is read only. If this address is written to, the Features register is written.

7.11.3 Access restrictions

The contents of this register shall be valid when BSY and DRQ equal zero and ERR equals one. The
contents of this register shall be valid upon completion of power on, or after a hardware or software reset, or
after command completion of an EXECUTE DEVICE DIAGNOSTICS or DEVICE RESET command. The
contents of this register are not valid while a device is in the Sleep mode.

7.11.4 Effect

None.

7.11.5 Functional description

This register contains status for the current command.

Following a power on, a hardware or software reset (see 9.2), or command completion of an EXECUTE
DEVICE DIAGNOSTIC (see 8.9) or DEVICE RESET command (see 8.7), this register contains a diagnostic
code .

At command completion of any command except EXECUTE DEVICE DIAGNOSTIC, the contents of this
register are valid when the ERR bit is equal to one in the Status register.

7.11.6 Field/bit description

7 6 5 4 3 2 1 0
# # # # # ABRT # #

− Bit 2 - ABRT (command aborted) is set to one to indicate the requested command has been
command aborted because the command code or a command parameter is invalid or some other
error has occurred.
− # -The content of this bit is command dependent (see clause 8).

7.12 Features register

Page 46
 T13/1153D revision 18

7.12.1 Address

CS1 CS0 DA2 DA1 DA0

N A N N A
A = asserted, N = negated

7.12.2 Direction

This register is write only. If this address is read by the host, the Error register is read.

7.12.3 Access restrictions

This register shall be written only when BSY and DRQ equal zero and DMACK- is not asserted. If this
register is written when BSY or DRQ is set to one, the result is indeterminate.

7.12.4 Effect

The content of this register becomes a command parameter when the Command register is written.

7.12.5 Functional description

The content of this register is command dependent (see clause 8).

7.13 Sector Count register

7.13.1 Address

CS1 CS0 DA2 DA1 DA0

N A N A N
A = asserted, N = negated

7.13.2 Direction

This register is read/write.

7.13.3 Access restrictions

This register shall be written only when both BSY and DRQ are zero and DMACK- is not asserted. The
contents of this register are valid only when both BSY and DRQ are zero. If this register is written when BSY
or DRQ is set to one, the result is indeterminate. The contents of the this register are not valid while a
device is in the Sleep mode.

7.13.4 Effect

The content of this register becomes a command parameter when the Command register is written.

7.13.5 Functional description

The content of this register is command dependent (see clause 8).

7.14 Sector Number register

Page 47
T13/1153D revision 18

7.14.1 Address

CS1 CS0 DA2 DA1 DA0

N A N A A
A = asserted, N = negated

7.14.2 Direction

This register is read/write.

7.14.3 Access restrictions

This register shall be written only when both BSY and DRQ are zero and DMACK- is not asserted. The
contents of this register are valid only when both BSY and DRQ are zero. If this register is written when BSY
or DRQ is set to one, the result is indeterminate. The contents of the this register are not valid while a
device is in the Sleep mode.

7.14.4 Effect

The content of this register becomes a command parameter when the Command register is written.

7.14.5 Functional description

The content of this register is command dependent (see clause 8).

7.15 Status register

7.15.1 Address

CS1 CS0 DA2 DA1 DA0

N A A A A
A = asserted, N = negated

7.15.2 Direction

This register is read only. If this address is written to by the host, the Command register is written.

7.15.3 Access restrictions

The contents of this register, except for BSY, shall be ignored when BSY is set equal to one. BSY is valid at
all times. The contents of this register are not valid while a device is in the Sleep mode.

7.15.4 Effect

Reading this register when an interrupt is pending causes the interrupt to be cleared (see 5.2.9). The host
should not read the Status register when an interrupt is expected as this may clear the interrupt before it can
be recognized by the host.

7.15.5 Functional description

This register contains the device status. The contents of this register are updated to reflect the current state
of the device and the progress of any command being executed by the device.

Page 48
 T13/1153D revision 18

7.15.6 Field/bit description

7 6 5 4 3 2 1 0
BSY DRDY # # DRQ obsolete obsolete ERR

7.15.6.1 BSY (Busy)

BSY is set to one to indicate that the device is busy. After the host has written the Command register the
device shall have either the BSY bit set to one, or the DRQ bit set to one, until command completion or the
device has performed a bus release for an overlapped command.

The BSY bit shall be set to one by the device:

1) after either the negation of RESET- or the setting of the SRST bit to one in the Device
Control register;
2) after writing the Command register if the DRQ bit is not set to one;
3) between blocks of a data transfer during PIO data in commands before the DRQ bit is
cleared to zero;
4) after the transfer of a data block during PIO data out commands before the DRQ bit is
cleared to zero;
5) during the data transfer of DMA commands either the BSY bit , the DRQ bit, or both
shall be set to one;
6) after the command packet is received during the execution of a PACKET command.

NOTE − The BSY bit may be set to one and then cleared to zero so quickly, that
host detection of the BSY bit being set to one is not certain.

When BSY is set to one, the device has control of the Command Block Registers and:
1) a write to a Command Block register by the host shall be ignored by the device except
for writing DEVICE RESET command;
2) a read from a Command Block register by the host will most likely yield invalid contents
except for the BSY bit itself.

The BSY bit shall be cleared to zero by the device:

1) after setting DRQ to one to indicate the device is ready to transfer data;
2) at command completion;
3) upon releasing the bus for an overlapped command;
4) when the device is ready to accept commands that do not require DRDY during a
power-on, hardware or software reset.

When BSY is cleared to zero, the host has control of the Command Block registers, the device
shall:
1) not set DRQ to one;
2) not change ERR bit;
3) not change the content of any other Command Block register;
4) set the SERV bit to one when ready to continue an overlapped command that has been
bus released.

7.15.6.2 DRDY (Device ready)

The DRDY bit shall be cleared to zero by the device:

1) when power-on, hardware, or software reset or DEVICE RESET or EXECUTE DEVICE
DIAGNOSTIC commands for devices implementing the PACKET command feature set.

When the DRDY bit is cleared to zero, the device shall accept and attempt to execute as described
in clause 8

The DRDY bit shall be set to one by the device:

Page 49
T13/1153D revision 18

1) when the device is capable of accepting all commands for devices not implementing the
PACKET command feature set;
2) prior to command completion except the DEVICE RESET or EXECUTE DEVICE
DIAGNOSTIC command for devices implementing the PACKET feature set.

When the DRDY bit is set to one:

1) the device shall accept and attempt to execute all implemented commands;
2) devices that implement the Power Management feature set shall maintain the DRDY bit
equal to one when they are in the Idle or Standby modes.

7.15.6.3 Command dependent

The use of bits marked with # are command dependent (see clause 8). Bit 4 was formerly the DSC (Device
Seek Complete) bit.

7.15.6.4 DRQ (Data request)

DRQ indicates that the device is ready to transfer a word of data between the host and the device. After the
host has written the Command register the device shall either set the BSY bit to one or the DRQ bit to one,
until command completion or the device has performed a bus release for an overlapped command.

The DRQ bit shall be set to one by the device:

1) when BSY is set to one and data is ready for PIO transfer;
2) during the data transfer of DMA commands either the BSY bit , the DRQ bit, or both
shall be set to one.

When the DRQ bit is set to one, the host may:

1) transfer data via PIO mode;
2) transfer data via DMA mode if DMARQ and DMACK- are asserted.

The DRQ bit shall be cleared to zero by the device:

1) when the last word of the data transfer occurs;
2) when the last word of the command packet transfer occurs for a PACKET command.

When the DRQ bit is cleared to zero, the host may:

1) transfer data via DMA mode if DMARQ and DMACK- are asserted and BSY is set to
one.

7.15.6.5 Obsolete bits

Some bits in this register were defined in previous ATA standards but have been declared obsolete in this
standard. These bits are labeled “obsolete”.

7.15.6.6 ERR (Error)

ERR indicates that an error occurred during execution of the previous command. For the PACKET and
SERVICE commands, this bit is defined as CHK and indicates that an exception conditions exists.

The ERR bit shall be set to one by the device:

1) when BSY or DRQ is set to one and an error occurs in the executing command.

When the ERR bit is set to one:

1) the bits in the Error register shall be valid;
2) the device shall not change the contents of the following registers until a new command
has been accepted, the SRST bit is set to one or RESET- is asserted:
− Error register;
− Cylinder High/Low registers;
− Sector Count register;

Page 50
 T13/1153D revision 18

− Sector Number register;

− Device/Head register.

The ERR bit shall be cleared to zero by the device:

1) when a new command is written to the Command register;
2) when the SRST bit is set to one;
3) when the RESET- signal is asserted.

When the ERR bit is cleared to zero at the end of a command:

1) the content of the Error register shall be ignored by the host.

Page 51
T13/1153D revision 18

8 Command descriptions
Commands are issued to the device by loading the pertinent registers in the command block with the
needed parameters and then writing the command code to the Command register.

Each command description in the following clauses contains the following subclauses:

Command code - Indicates the command code for this command.

Feature set - Indicates feature set and if the command is:

− Mandatory - Required to be implemented by devices as specified.
− Optional - Implementation is optional but if implemented shall be implemented as specified.

Protocol - Indicates which protocol is used by the command (see clause 9).

Inputs - Describes the Command Block register data that the host shall supply.

Register 7 6 5 4 3 2 1 0
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command Command Code
NOTE − na indicates the content of a bit or field is not applicable to the particular
command. obs indicates that the use of this bit is obsolete.

Normal outputs - Describes the Command Block register data returned by the device at the end of a
command.

Register 7 6 5 4 3 2 1 0
Error
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Status
NOTE − na indicates the content of a bit or field is not applicable to the particular
command. obs indicates that the use of this bit is obsolete.

Error outputs - Describes the Command Block register data that shall be returned by the device at command
completion with an unrecoverable error.

Page 52
 T13/1153D revision 18

Register 7 6 5 4 3 2 1 0
Error
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Status
NOTE − na indicates the content of a bit or field is not applicable to the particular
command. obs indicates that the use of this bit is obsolete.

Prerequisites - Any prerequisite commands or conditions that shall be met before the command is issued.

Description - The description of the command function(s).

Page 53
T13/1153D revision 18

8.1 CFA ERASE SECTORS

8.1.1 Command code

C0h

8.1.2 Feature set

CFA feature set.

− If the CFA feature set is implemented this command shall be implemented.

This command code is Vendor Specific for devices not implementing the CFA feature Set.

8.1.3 Protocol

Non-data command (see 9.9).

8.1.4 Inputs

The Cylinder Low, Cylinder High, Device/Head, and Sector Number specify the starting sector address to be
erased. The Sector Count register specifies the number of sectors to be erased.

Register 7 6 5 4 3 2 1 0
Features na
Sector Count Sector count
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs LBA obs DEV Head number or LBA
Command C0h

Sector Count -
number of sectors to be erased. A value of 00h indicates that 256 sectors are to be erased.
Sector Number -
starting sector number or LBA address bits (7:0).
Cylinder Low -
starting cylinder number bits (7:0) or LBA address bits (15:8).
Cylinder High -
starting cylinder number bits (15:8) or LBA address bits (23:16).
Device/Head -
bit 6 set to one if LBA address, cleared to zero if CHS address starting head number or LBA address
bits (27:24).

8.1.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector na
Number
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY na na na na na ERR

Page 54
 T13/1153D revision 18

Status register
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
ERR shall be cleared to zero.

8.1.6 Error outputs

The device shall return command aborted if the command is not supported. An unrecoverable error
encountered during execution of this command results in the termination of the command. The command
block registers contain the address of the sector where the first unrecovered error occurred.

Register 7 6 5 4 3 2 1 0
Error na na na IDNF na ABRT na MED
Sector Count na
Sector Sector number or LBA
Number
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs na obs DEV Head number or LBA
Status BSY DRDY DF na na na na ERR

Error Register -
IDNF shall be set to one if a user-accessible address could not be found and after an unsuccessful
INITIALIZE DEVICE PARAMETERS command until a valid CHS translation is established
(see 8.16.8). IDNF shall be set to one if an address outside of the range of user-accessible
addresses is requested if command aborted is not returned.
ABRT shall be set to one if the command is not supported. ABRT may be set to one if the device is
not able to complete the action requested by the command. ABRT shall be set to one if an
address outside of the range of user-accessible addresses is requested if IDNF is not set to
one.
MED shall be set to one if a media error is detected.
Sector Number, Cylinder Low, Cylinder High, Device/Head -
shall be written with the address of first unrecoverable error.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
ERR shall be set to one if an Error register bit is set to one.

8.1.7 Prerequisites

DRDY set equal to one.

8.1.8 Description

This command pre-erases and conditions from 1 to 256 sectors as specified in the Sector Count register.
This command should be issued in advance of a CFA WRITE SECTORS WITHOUT ERASE or a CFA
WRITE MULTIPLE WITHOUT ERASE command to increase the execution speed of the write operation.

Page 55
T13/1153D revision 18

8.2 CFA REQUEST EXTENDED ERROR CODE

8.2.1 Command code

03h

8.2.2 Feature set

CFA feature set.

− If the CFA feature set is implemented this command shall be implemented.

8.2.3 Protocol

Non-data command (see 9.9).

8.2.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Command 03h

8.2.5 Normal outputs

The extended error code written into the Error register is an 8-bit code. Table 8 defines these values.

Register 7 6 5 4 3 2 1 0
Error Extended error code
Sector Count Vendor specific
Sector Vendor specific
Number
Cylinder Low Vendor specific
Cylinder High Vendor specific
Device/Head obs na obs DEV Vendor specific
Status BSY DRDY na na na na na ERR

Error register -
Extended error code.
Sector Number, Cylinder Low, Cylinder High, Device/Head -
May contain additional information.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
ERR shall be cleared to zero.

Page 56
 T13/1153D revision 18

Table 8 − Extended error codes

Extended error code Description
00h No error detected / no additional information
01h Self test passed
03h Write / Erase failed
05h Self test or diagnostic failed
09h Miscellaneous error
0Bh Vendor specific
0Ch Corrupted media format
0D-0Fh Vendor specific
10h ID Not Found / ID Error
11h Uncorrectable ECC error
14h ID Not Found
18h Corrected ECC error
1Dh, 1Eh Vendor specific
1Fh Data transfer error / command aborted
20h Invalid command
21h Invalid address
22-23h Vendor specific
27h Write protect violation
2Fh Address overflow (address too large)
30-34h Self test or diagnostic failed
35h, 36h Supply or generated voltage out of tolerance
37h, 3Eh Self test or diagnostic failed
38h Corrupted media format
39h Vendor specific
3Ah Spare sectors exhausted
3Bh 3Ch, 3Fh Corrupted media format
3Dh Vendor specific
All other values Reserved

8.2.6 Error outputs

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector na
Number
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na na na na ERR

Error Register -
ABRT shall be set to one if the command is not supported. ABRT may be set to one if the device is
not able to complete the action requested by the command.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
ERR shall be set to one if an Error register bit is set to one.

Page 57
T13/1153D revision 18

8.2.7 Prerequisites

DRDY set equal to one.

8.2.8 Description

This command provides an extended error code which identifies the cause of an error condition in more
detail than is available with Status and Error register values. The CFA REQUEST EXTENDED ERROR
CODE command must be issued to the device immediately following the command which ended with an
error condition to obtain valid extended error code information.

Page 58
 T13/1153D revision 18

8.3 CFA TRANSLATE SECTOR

8.3.1 Command code

87h

8.3.2 Feature set

CFA feature set.

− If the CFA feature set is implemented this command shall be implemented.

This command code is Vendor Specific for devices not implementing the CFA feature Set.

8.3.3 Protocol

PIO data in command (see 9.7).

8.3.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs LBA obs DEV Head number or LBA
Command 87h

Sector Number -
sector number or LBA address bits (7:0).
Cylinder Low -
cylinder number bits (7:0) or LBA address bits (15:8).
Cylinder High -
cylinder number bits (15:8) or LBA address bits (23:16).
Device/Head -
bit 6 set to one if LBA address, cleared to zero if CHS address head number or LBA address bits
(27:24).

8.3.5 Normal outputs

A 512 byte information table is transferred to the host. Table 9 defines these values.

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector na
Number
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY na na na na na ERR

Page 59
T13/1153D revision 18

Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
ERR shall be cleared to zero.

Table 9 − CFA TRANSLATE SECTOR Information

Byte Description
00h Cylinder number MSB
01h Cylinder number LSB
02h Head number
03h Sector number
04h LBA bits (23:16)
05h LBA bits (15:8)
06h LBA bits (7:0)
07-12h Reserved
13h Sector erased flag (FFh = erased; 00h = not erased)
14-17h Reserved
18h Sector write cycles count bits (23:16)
19h Sector write cycles count bits (15:8)
1Ah Sector write cycles count bits (7:0)
1B-FFh Reserved

8.3.6 Error outputs

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector na
Number
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na na na na ERR

Error Register -
ABRT shall be set to one if the command is not supported. ABRT may be set to one if the device is
not able to complete the action requested by the command.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
ERR shall be set to one if an Error register bit is set to one.

8.3.7 Prerequisites

DRDY set equal to one.

8.3.8 Description

This command provides information related to a specific sector. The data indicates the erased or not erased
status of the sector, and the number of erase and write cycles performed on that sector. Devices may return
zero in fields that do not apply or that are not supported by the device.

Page 60
 T13/1153D revision 18

8.4 CFA WRITE MULTIPLE WITHOUT ERASE

8.4.1 Command code

CDh

8.4.2 Feature set

CFA feature set.

− If the CFA feature set is implemented this command shall be implemented.

8.4.3 Protocol

PIO data out command (see 9.8).

8.4.4 Inputs

The Cylinder Low, Cylinder High, Device/Head, and Sector Number specify the starting sector address to be
written. The Sector Count register specifies the number of sectors to be transferred.

Register 7 6 5 4 3 2 1 0
Features na
Sector Count Sector count
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs LBA obs DEV Head number or LBA
Command CDh

Sector Count -
number of sectors to be transferred. A value of 00h indicates that 256 sectors are to be transferred.
Sector Number -
starting sector number or LBA address bits (7:0).
Cylinder Low -
starting cylinder number bits (7:0) or LBA address bits (15:8).
Cylinder High -
starting cylinder number bits (15:8) or LBA address bits (23:16).
Device/Head -
bit 6 set to one if LBA address, cleared to zero if CHS address starting head number or LBA address
bits (27:24).

8.4.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector na
Number
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY na na na na na ERR

Page 61
T13/1153D revision 18

Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
ERR shall be cleared to zero.

8.4.6 Error outputs

The device shall return command aborted if the command is not supported. An unrecoverable error
encountered during execution of this command results in the termination of the command. The command
block registers contain the address of the sector where the first unrecovered error occurred. The amount of
data transferred is indeterminate.

Register 7 6 5 4 3 2 1 0
Error na na na IDNF na ABRT na MED
Sector Count na
Sector Sector number or LBA
Number
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs na obs DEV Head number or LBA
Status BSY DRDY DF na DRQ na na ERR

Error Register -
IDNF shall be set to one if a user-accessible address could not be found and after an unsuccessful
INITIALIZE DEVICE PARAMETERS command until a valid CHS translation is established
(see 8.16.8). IDNF shall be set to one if an address outside of the range of user-accessible
addresses is requested if command aborted is not returned.
ABRT shall be set to one if the command is not supported. ABRT may be set to one if the device is
not able to complete the action requested by the command. ABRT shall be set to one if an
address outside of the range of user-accessible addresses is requested if IDNF is not set to
one.
MED shall be set to one if a media error is detected
Sector Number, Cylinder Low, Cylinder High, Device/Head -
shall be written with the address of first unrecoverable error.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.4.7 Prerequisites

DRDY set equal to one. If bit 8 of IDENTIFY DEVICE word 59 is equal to zero, a successful SET MULTIPLE
MODE command shall precede a CFA WRITE MULTIPLE WITHOUT ERASE command.

8.4.8 Description

This command is similar to the WRITE MULTIPLE command. Interrupts are not generated on every sector,
but on the transfer of a block that contains the number of sectors defined by the SET MULTIPLE MODE.

Command execution is identical to the WRITE MULTIPLE operation except that the sectors are written
without an implied erase operation. The sectors should be pre-erased by a preceding CFA ERASE
SECTORS command.

Page 62
 T13/1153D revision 18

8.5 CFA WRITE SECTORS WITHOUT ERASE

8.5.1 Command code

38h

8.5.2 Feature set

CFA feature set.

− If the CFA feature set is implemented this command shall be implemented.

8.5.3 Protocol

PIO data out command (see 9.8).

8.5.4 Inputs

The Cylinder Low, Cylinder High, Device/Head, and Sector Number specify the starting sector address to be
written. The Sector Count register specifies the number of sectors to be transferred.

Register 7 6 5 4 3 2 1 0
Features na
Sector Count Sector count
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs LBA obs DEV Head number or LBA
Command 38h

Sector Count -
number of sectors to be transferred. A value of 00h indicates that 256 sectors are to be transferred.
Sector Number -
starting sector number or LBA address bits (7:0).
Cylinder Low -
starting cylinder number bits (7:0) or LBA address bits (15:8).
Cylinder High -
starting cylinder number bits (15:8) or LBA address bits (23:16).
Device/Head -
bit 6 set to one if LBA address, cleared to zero if CHS address starting head number or LBA address
bits (27:24).

8.5.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector na
Number
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY na na na na na ERR

Page 63
T13/1153D revision 18

Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
ERR shall be cleared to zero.

8.5.6 Error outputs

The device shall return command aborted if the command is not supported. An unrecoverable error
encountered during execution of this command results in the termination of the command. The command
block registers contain the address of the sector where the first unrecovered error occurred. The amount of
data transferred is indeterminate.

Register 7 6 5 4 3 2 1 0
Error na na na IDNF na ABRT na MED
Sector Count na
Sector Sector number or LBA
Number
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs na obs DEV Head number or LBA
Status BSY DRDY DF na DRQ na na ERR

Error Register -
IDNF shall be set to one if a user-accessible address could not be found and after an unsuccessful
INITIALIZE DEVICE PARAMETERS command until a valid CHS translation is established
(see 8.16.8). IDNF shall be set to one if an address outside of the range of user-accessible
addresses is requested if command aborted is not returned.
ABRT shall be set to one if the command is not supported. ABRT may be set to one if the device is
not able to complete the action requested by the command. ABRT shall be set to one if an
address outside of the range of user-accessible addresses is requested if IDNF is not set to
one.
MED shall be set to one if a media error is detected
Sector Number, Cylinder Low, Cylinder High, Device/Head -
shall be written with the address of first unrecoverable error.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault h as occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.5.7 Prerequisites

DRDY set equal to one.

8.5.8 Description

This command is similar to the WRITE SECTORS command. Command execution is identical to the
WRITE SECTORS operation except that the sectors are written without an implied erase operation. The
sectors should be pre-erased by a preceding CFA ERASE SECTORS command.

Page 64
 T13/1153D revision 18

8.6 CHECK POWER MODE

8.6.1 Command code

E5h

8.6.2 Feature set

Power Management feature set.

− Power Management feature set is mandatory when power management is not implemented by a
PACKET power management feature set.
− This command is mandatory when the Power Management feature set is implemented.

8.6.3 Protocol

Non-data command (see 9.9).

8.6.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command E5h

Device/Head register -
DEV shall indicate the selected device.

8.6.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count Result value
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Device/Head register -
DEV shall indicate the selected device.

Page 65
T13/1153D revision 18

Sector Count result value -

00h - device is in Standby mode.
80h - device is in Idle mode.
FFh - device is in Active mode or Idle mode.

8.6.6 Error outputs

The device shall return command aborted if the device does not support the Power Management feature
set.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if Power Management feature set is not supported. ABRT may be set to
one if the device is not able to complete the action requested by the command.

Device/Head register -
DEV shall indicate the selected device.

Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.6.7 Prerequisites

DRDY set equal to one.

8.6.8 Description

The CHECK POWER MODE command allows the host to determine the current power mode of the device.
The CHECK POWER MODE command shall not cause the device to change power or affect the operation
of the Standby timer.

Page 66
 T13/1153D revision 18

8.7 DEVICE RESET

8.7.1 Command code

08h

8.7.2 Feature set

General feature set

− Use prohibited when the PACKET Command feature set is not implemented.
− Mandatory when the PACKET Command feature set is implemented.

8.7.3 Protocol

Device reset (see 9.4 ).

8.7.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command 08h

Device/Head register -
DEV shall indicate the selected device.

8.7.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error Diagnostic results
Sector Count signature
Sector Number signature
Cylinder Low signature
Cylinder High signature
Device/Head 0 0 0 DEV 0 0 0 0
Status see 9.4

Error register -
The diagnostic code as described in 8.9 is placed in this register.
Sector Count, Sector Number, Cylinder low, Cylinder High -
Signature (see 9.1).
Device/Head register -
DEV shall indicate the selected device.
Status register -
see 9.4.

8.7.6 Error outputs

If supported, this command cannot end in an error condition. If this command is not supported and the
device has the BSY bit or the DRQ bit set to one when the command is written, the results of this command

Page 67
T13/1153D revision 18

are indeterminate. If this command is not supported and the device has the BSY bit and the DRQ bit cleared
to zero when the command is written, the device shall respond command aborted.

8.7.7 Prerequisites

This command shall be accepted when BSY or DRQ is set to one, DRDY is cleared to zero, or DMARQ is
asserted. This command shall be accepted when in Sleep mode.

8.7.8 Description

The DEVICE RESET command enables the host to reset an individual device without affecting the other
device.

Page 68
 T13/1153D revision 18

8.8 DOWNLOAD MICROCODE

8.8.1 Command code

92h

8.8.2 Feature set

General feature set

− Optional for devices not implementing the PACKET Command feature set.
− Use prohibited for devices implementing the PACKET Command feature set.

8.8.3 Protocol

PIO data out (see 9.8).

8.8.4 Inputs

The head bits of the Device/Head register shall always be cleared to zero. The Cylinder High and Low
registers shall be cleared to zero. The Sector Number and Sector Count registers are used together as a 16-
bit sector count value. The Feature register specifies the subcommand code.

Register 7 6 5 4 3 2 1 0
Features Subcommand code
Sector Count Sector count (low order)
Sector Number Sector count (high order)
Cylinder Low 00h
Cylinder High 00h
Device/Head obs na obs DEV 0 0 0 0
Command 92h

Device/Head register -
DEV shall indicate the selected device.

8.8.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.

Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 69
T13/1153D revision 18

8.8.6 Error outputs

The device shall return command aborted if the device does not support this command or did not accept the
microcode data. The device shall return command aborted if subcommand code is not a supported value.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if the device does not support this command or did not accept the
microcode data. ABRT may be set to one if the device is not able to complete the action
requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.8.7 Prerequisites

DRDY set equal to one.

8.8.8 Description

This command enables the host to alter the device’s microcode. The data transferred using the
DOWNLOAD MICROCODE command is vendor specific.

All transfers shall be an integer multiple of the sector size. The size of the data transfer is determined by
the contents of the Sector Number Register and the Sector Count register. The Sector Number Register
shall be used to extend the Sector Count register to create a sixteen bit sector count value. The Sector
Number Register shall be the most significant eight bits and the Sector Count register shall be the least
significant eight bits. A value of zero in both the Sector Number Register and the Sector Count register
shall indicate no data is to be transferred. This allows transfer sizes from 0 bytes to 33,553,920 bytes, in
512 byte increments.

The Features register shall be used to determine the effect of the DOWNLOAD MICROCODE command.
The values for the Feature Register are:

− 01h - download is for immediate, temporary use.

− 07h - save downloaded code for immediate and future use.

Either or both values may be supported. All other values are reserved.

Page 70
 T13/1153D revision 18

8.9 EXECUTE DEVICE DIAGNOSTIC

8.9.1 Command code

90h

8.9.2 Feature set

General feature set

− Mandatory for all devices.

8.9.3 Protocol

Device diagnostics (see 9.5 ).

8.9.4 Inputs

None. The device selection bit in the Device/Head register is ignored.

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs na na na na na
Command 90h

Device/Head register -
DEV shall indicate the selected device.

8.9.5 Normal outputs

The diagnostic code written into the Error register is an 8-bit code. Table 10 defines these values. The
values of the bits in the Error register are not as defined in 7.11.6.

Register 7 6 5 4 3 2 1 0
Error Diagnostic code
Sector Count Signature
Sector Number Signature
Cylinder Low Signature
Cylinder High Signature
Device/Head Signature
Status see 9.5

Error register -
Diagnostic code.
Sector Count, Sector number, Cylinder Low, Cylinder High, Device/Head registers -
device signature (see 9.1).
Device/Head register -
DEV shall indicate the selected device.
Status register -
see 9.5.

Page 71
T13/1153D revision 18

Table 10 − Diagnostic codes

Code (see note Description
1)
When this code is in the Device 0 Error register
01h Device 0 passed, Device 1 passed or not present
00h, 02h-7Fh Device 0 failed, Device 1 passed or not present
81h Device 0 passed, Device 1 failed
80h, 82h-FFh Device 0 failed, Device 1 failed
When this code is in the Device 1 Error register
01h Device 1 passed (see note 2)
00h,02h-7Fh Device 1 failed (see note 2)
NOTE −
1 Codes other than 01h and 81h may indicate additional information
about the failure(s).
2 If Device 1 is not present, the host may see the information from
Device 0 even though Device 1 is selected.

8.9.6 Error outputs

Table 10 shows the error information that is returned as a diagnostic code in the Error register.

8.9.7 Prerequisites

This command shall be accepted regardless of the state of DRDY.

8.9.8 Description
This command shall perform the internal diagnostic tests implemented by the device. The DEV bit in the
Device/Head register is ignored. Both devices, if present, shall execute this command regardless of which
device is selected.

If the host issues an EXECUTE DEVICE DIAGNOSTIC command while a device is in or going to a power
management mode except Sleep, then the device shall execute its EXECUTE DEVICE DIAGNOSTIC
sequence.

Page 72
 T13/1153D revision 18

8.10 FLUSH CACHE

8.10.1 Command code

E7h

8.10.2 Feature set

General feature set

− Optional for all devices.

8.10.3 Protocol

Non-data command (see 9.9).

8.10.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command E7h

Device/Head register -
DEV shall indicate the selected device.

8.10.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.10.6 Error outputs

If the command is not supported, the device shall return command aborted. An unrecoverable error
encountered during execution of writing data results in the termination of the command and the Command
Block registers contain the sector address of the sector where the first unrecoverable error occurred. The

Page 73
T13/1153D revision 18

sector is removed from the cache. Subsequent FLUSH CACHE commands continue the process of flushing
the cache.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs na obs DEV Head number or LBA
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if device does not support this command. ABRT may be set to one if the
device is not able to complete the action requested by the command.
Sector Number, Cylinder Low, Cylinder High, Device/Head -
shall be written with the address of the first unrecoverable error.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.10.7 Prerequisites

DRDY set equal to one.

8.10.8 Description

This command is used by the host to request the device to flush the write cache. If the write cache is to be
flushed, all data cached shall be written to the media. The BSY bit shall remain set to one until all data has
been successfully written or an error occurs. The device should use all error recovery methods available to
ensure the data is written successfully. The flushing of write cache may take several seconds to complete
depending upon the amount of data to be flushed and the success of the operation.

NOTE − This command may take longer than 30 s to complete.

Page 74
 T13/1153D revision 18

8.11 GET MEDIA STATUS

8.11.1 Command code

DAh

8.11.2 Feature set

Removable Media Status Notification feature set

− Mandatory for devices implementing the Removable Media Status Notification feature set.

Removable Media feature set

− Optional for devices implementing the Removable Media feature set.
8.11.3 Protocol

Non-data command (see 9.9).

8.11.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command DAh

Device/Head register -
DEV shall indicate the selected device.

8.11.5 Normal outputs

Normal outputs are returned if Media Status Notification is disabled or if no bits are set to one in the Error
register.

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 75
T13/1153D revision 18

8.11.6 Error outputs

If the device does not support this command, the device shall return command aborted.

Register 7 6 5 4 3 2 1 0
Error na WP MC na MCR ABRT NM obs
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if device does not support this command. ABRT may be set to one if the
device is not able to complete the action requested by the command.
NM (No Media) shall be set to one if no media is present in the device. This bit shall be set to one
for each execution of GET MEDIA STATUS until media is inserted into the device.
MCR (Media Change Request) shall be set to one if the eject button is pressed by the user and
detected by the device. The device shall reset this bit after each execution of the GET
MEDIA STATUS command and only set the bit again for subsequent eject button presses.
MC (Media Change) shall be set to one when the device detects media has been inserted. The
device shall reset this bit after each execution of the GET MEDIA STATUS command and
only set the bit again for subsequent media insertions.
WP (Write Protect) shall be set to one for each execution of GET MEDIA STATUS while the media
is write protected.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.11.7 Prerequisites

DRDY set equal to one.

8.11.8 Description

This command returns media status bits WP, MC, MCR, and NM, as defined above. When Media Status
Notification is disabled this command returns zeros in the WP, MC, MCR, and NM bits.

Page 76
 T13/1153D revision 18

8.12 IDENTIFY DEVICE

8.12.1 Command code

ECh

8.12.2 Feature set

General feature set

− Mandatory for all devices.
− Devices implementing the PACKET Command feature set (see 8.12.5.2).

8.12.3 Protocol

PIO data in (see 9.7).

8.12.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command ECh

Device/Head register -
DEV shall indicate the selected device.

8.12.5 Outputs

8.12.5.1 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 77
T13/1153D revision 18

8.12.5.2 Outputs for PACKET Command feature set devices

In response to this command, devices that implement the PACKET Command feature set shall post
command aborted and place the PACKET Command feature set signature in the Command Block registers
(see 9.1).

8.12.6 Error outputs

Devices not implementing the PACKET Command feature set shall not report an error.

8.12.7 Prerequisites

DRDY set equal to one.

8.12.8 Description

The IDENTIFY DEVICE command enables the host to receive parameter information from the device.

Some devices may have to read the media in order to complete this command.

When the command is issued, the device sets the BSY bit to one, prepares to transfer the 256 words of
device identification data to the host, sets the DRQ bit to one, clears the BSY bit to zero, and asserts INTRQ
if nIEN is cleared to zero. The host may then transfer the data by reading the Data register. Table 11
defines the arrangement and meaning of the parameter words in the buffer. All reserved bits or words shall
be zero.

Some parameters are defined as a 16-bit value. A word that is defined as a 16-bit value places the most
significant bit of the value on bit DD15 and the least significant bit on bit DD0.

Some parameters are defined as 32-bit values (e.g., words 57 and 58). Such fields are transferred using
two successive word transfers. The device shall first transfer the least significant bits, bits 15 through 0 of
the value, on bits DD (15:0) respectively. After the least significant bits have been transferred, the most
significant bits, bits 31 through 16 of the value, shall be transferred on DD (15:0) respectively.

Some parameters are defined as a string of ASCII characters. ASCII data fields shall contain only graphic
codes (i.e., code values 20h through 7Eh). For the string “Copyright”, the character “C” is the first byte, the
character “o” is the 2nd byte, etc. When such fields are transferred, the order of transmission is:

the 1st character (“C”) is on bits DD (15:8) of the first word,

the 2nd character (“o”) is on bits DD (7:0) of the first word,
the 3rd character (“p”) is on bits DD (15:8) of the second word,
the 4th character (“y”) is on bits DD (7:0) of the second word,
etc.

Page 78
 T13/1153D revision 18

Table 11 − IDENTIFY DEVICE information

Word F/V
0 General configuration bit-significant information:
F 15 0=ATA device
F 14-8 retired
F 7 1=removable media device
F 6 1=not removable controller and/or device
F 5-1 retired
F 0 Reserved
1 V Number of logical cylinders
2 R Reserved
3 F Number of logical heads
4-5 X retired
6 F Number of logical sectors per logical track
7-9 X retired
10-19 F Serial number (20 ASCII characters)
20-21 X retired
22 F obsolete
23-26 F Firmware revision (8 ASCII characters)
27-46 F Model number (40 ASCII characters)
47 X 15-8 80h
R 7-0 00h =Reserved
F 01h-FFh = Maximum number of sectors that shall be transferred
per interrupt on READ/WRITE MULTIPLE commands
48 R Reserved
49 Capabilities
R 15-14 Reserved for the IDENTIFY PACKET DEVICE command.
F 13 1=Standby timer values as specified in this standard are supported
0=Standby timer values shall be managed by the device
R 12 Reserved for the IDENTIFY PACKET DEVICE command.
F 11 1=IORDY supported
0=IORDY may be supported
F 10 1=IORDY may be disabled
R 9 Shall be set to one. Utilized by IDENTIFY PACKET DEVICE command.
R 8 Shall be set to one. Utilized by IDENTIFY PACKET DEVICE command.
X 7-0 retired
50 F Capabilities
15 Shall be cleared to zero.
14 Shall be set to one.
13-1 Reserved.
0 Shall be set to one to indicate a device specific Standby timer value
minimum.
51 F 15-8 PIO data transfer mode number
X 7-0 retired
52 R retired
53 R 15-3 Reserved
F 2 1=the fields reported in word 88 are valid
0=the fields reported in word 88 are not valid
F 1 1=the fields reported in words 64-70 are valid
0=the fields reported in words 64-70 are not valid
V 0 1=the fields reported in words 54-58 are valid
0=the fields reported in words 54-58 may be valid
54 V Number of current logical cylinders
(continued)

Page 79
T13/1153D revision 18

Table 11 − IDENTIFY DEVICE information(continued)

Word F/V
55 V Number of current logical heads
56 V Number of current logical sectors per track
57-58 V Current capacity in sectors
59 R 15-9 Reserved
V 8 1=Multiple sector setting is valid
V 7-0 xxh=Current setting for number of sectors that shall be
transferred per interrupt on R/W Multiple command
60-61 F Total number of user addressable sectors (LBA mode only)
62 R retired
63 R 15-11 Reserved
V 10 1= Multiword DMA mode 2 is selected
0= Multiword DMA mode 2 is not selected
V 9 1= Multiword DMA mode 1 is selected
0= Multiword DMA mode 1 is not selected
V 8 1= Multiword DMA mode 0 is selected
0= Multiword DMA mode 0 is not selected
R 7-3 Reserved
F 2 1= Multiword DMA mode 2 and below are supported
F 1 1= Multiword DMA mode 1 and below are supported
F 0 1= Multiword DMA mode 0 is supported
64 R 15-8 Reserved
F 7-0 Advanced PIO modes supported
65 Minimum Multiword DMA transfer cycle time per word
F 15-0 Cycle time in nanoseconds
66 Manufacturer’s recommended Multiword DMA transfer cycle time
F 15-0 Cycle time in nanoseconds
67 Minimum PIO transfer cycle time without flow control
F 15-0 Cycle time in nanoseconds
68 Minimum PIO transfer cycle time with IORDY flow control
F 15-0 Cycle time in nanoseconds
69-70 R Reserved (for future command overlap and queuing)
71-74 R Reserved for IDENTIFY PACKET DEVICE command.
75 F Queue depth
15-5 Reserved
4-0 Maximum queue depth
76-79 R Reserved
80 F Major version number
0000h or FFFFh = device does not report version
15 Reserved
14 Reserved for ATA/ATAPI-14
13 Reserved for ATA/ATAPI-13
12 Reserved for ATA/ATAPI-12
11 Reserved for ATA/ATAPI-11
10 Reserved for ATA/ATAPI-10
9 Reserved for ATA/ATAPI-9
8 Reserved for ATA/ATAPI-8
7 Reserved for ATA/ATAPI-7
6 Reserved for ATA/ATAPI-6
5 Reserved for ATA/ATAPI-5
4 1=supports ATA/ATAPI-4
3 1=supports ATA-3
2 1=supports ATA-2
1 1=supports ATA-1
0 Reserved
(continued)

Page 80
 T13/1153D revision 18

Table 11 − IDENTIFY DEVICE information(continued)

Word F/V
81 F Minor version number
0000h or FFFFh=device does not report version
0001h-FFFEh=see 8.12.44
82 F Command set supported. If words 82 and 83 =0000h or FFFFh command set
notification not supported.
15 Obsolete
14 1=NOP command supported
13 1=READ BUFFER command supported
12 1=WRITE BUFFER command supported
11 Obsolete
10 1=Host Protected Area feature set supported
9 1=DEVICE RESET command supported
8 1=SERVICE interrupt supported
7 1=release interrupt supported
6 1=look-ahead supported
5 1=write cache supported
4 1=supports PACKET Command feature set
3 1=supports Power Management feature set
2 1=supports Removable Media feature set
1 1=supports Security Mode feature set
0 1=supports SMART feature set
83 F Command sets supported. If words 82 and 83 =0000h or FFFFh command set
notification not supported.
15 Shall be cleared to zero
14 Shall be set to one
13-5 Reserved
4 1=Removable Media Status Notification feature set supported
3 1=Advanced Power Management feature set supported
2 1=CFA feature set supported
1 1=READ/WRITE DMA QUEUED supported
0 1=DOWNLOAD MICROCODE command supported
84 F Command set/feature supported extension. If words 82, 83, and 84 = 0000h or FFFFh
command set notification extension is not supported.
15 Shall be cleared to zero
14 Shall be set to one
13-0 Reserved
85 V Command set/feature enabled. If words 85, 86, and 87 = 0000h or FFFFh command
set enabled notification is not supported.
15 Obsolete
14 1=NOP command supported
13 1=READ BUFFER command supported
12 1=WRITE BUFFER command supported
11 Obsolete
10 1=Host Protected Area feature set supported
9 1=DEVICE RESET command supported
8 1=SERVICE interrupt enabled
7 1=release interrupt enabled
6 1=look-ahead enabled
5 1=write cache enabled
4 1=supports PACKET Command feature set
3 1=supports Power Management feature set
2 1=supports Removable Media feature set
1 1= Security Mode feature set enabled
0 1= SMART feature set enabled
(continued)

Page 81
T13/1153D revision 18

Table 11 − IDENTIFY DEVICE information(concluded)

Word F/V
86 V Command set/feature enabled. If words 85, 86, and 87 = 0000h or FFFFh command
set enabled notification is not supported.
15-5 Reserved
4 1=Removable Media Status Notification feature set enabled
3 1=Advanced Power Management feature set enabled
2 1=CFA feature set supported
1 1=READ/WRITE DMA QUEUED command supported
0 1=DOWNLOAD MICROCODE command supported
87 V Command set/feature default. If words 85, 86, and 87 = 0000h or FFFFh command
set default notification is not supported.
15 Shall be cleared to zero
14 Shall be set to one
13-0 Reserved
88 R 15-11 Reserved
V 10 1=Ultra DMA mode 2 is selected
0=Ultra DMA mode 2 is not selected
V 9 1=Ultra DMA mode 1 is selected
0=Ultra DMA mode 1 is not selected
V 8 1=Ultra DMA mode 0 is selected
0=Ultra DMA mode 0 is not selected
R 7-3 Reserved
F 2 1=Ultra DMA mode 2 and below are supported
F 1 1=Ultra DMA mode 1 and below are supported
F 0 1=Ultra DMA mode 0 is supported
89 F Time required for security erase unit completion
90 F Time required for Enhanced security erase completion
91 V Current advanced power management value
92-126 R Reserved
127 F Removable Media Status Notification feature set support
15-2 Reserved
1-0 00=Removable Media Status Notification feature set not supported
01=Removable Media Status Notification feature supported
10=Reserved
11=Reserved
128 V Security status
15-9 Reserved
8 Security level 0=High, 1=Maximum
7-6 Reserved
5 1=Enhanced security erase supported
4 1=Security count expired
3 1=Security frozen
2 1=Security locked
1 1=Security enabled
0 1=Security supported
129-159 X Vendor specific
160-255 R Reserved
Key:
F = the content of the word is fixed and does not change. For removable media devices, these values may
change when media is removed or changed.
V = the contents of the word is variable and may change depending on the state of the device or the
commands executed by the device.
X = the content of the word is vendor specific and may be fixed or variable.
R = the content of the word is reserved and shall be zero.

Page 82
 T13/1153D revision 18

8.12.9 Word 0: General configuration

Devices that conform to this standard shall clear bit 15 to zero.

Devices reporting a value of 848Ah in this word shall support the CFA feature set.

8.12.10 Word 1: Number of cylinders

This word contains the number of user-addressable logical cylinders in the default CHS translation (see 6.2).

8.12.11 Word 2: Reserved.

8.12.12 Word 3: Number of logical heads

This word contains the number of user-addressable logical heads per logical cylinder in the default CHS
translation (see 6.2).

8.12.13 Word 4-5: Retired.

8.12.14 Word 6: Number of logical sectors per logical track

This word contains the number of user-addressable logical sectors per logical track in the default CHS
translation (see 6.2).

8.12.15 Words 7-9: Retired.

8.12.16 Words 10-19: Serial number

This field contains the serial number of the device. The contents of this field is an ASCII character string of
twenty bytes. The device shall pad the character string with spaces (20h), if necessary, to ensure that the
string is the proper length. The combination of Serial number (words 10-19) and Model number (words 27-
46) shall be unique for a given manufacturer.

8.12.17 Word 20-21: Retired.

8.12.18 Word 22: Obsolete.

8.12.19 Word 23-26: Firmware revision

This field contains the firmware revision number of the device. The contents of this field is an ASCII
character string of eight bytes. The device shall pad the character string with spaces (20h), if necessary, to
ensure that the string is the proper length.

8.12.20 Words 27-46: Model number

This field contains the model number of the device. The contents of this field is an ASCII character string of
forty bytes. The device shall pad the character string with spaces (20h), if necessary, to ensure that the
string is the proper length. The combination of Serial number (words 10-19) and Model number (words 27-
46) shall be unique for a given manufacturer.

8.12.21 Word 47: READ/WRITE MULTIPLE support.

Bits 7-0 of this word define the maximum number of sectors per block that the device supports for
READ/WRITE MULTIPLE commands.

8.12.22 Word 48: Reserved.

Page 83
T13/1153D revision 18

8.12.23 Word 49-50: Capabilities

Bits 15 and 14 of word 49 are reserved for use in the IDENTIFY PACKET DEVICE command response.

Bit 13 of word 49 is used to determine whether a device utilizes the Standby timer values as defined in this
standard. Table 14 specifies the Standby timer values utilized by the device if bit 13 is set to one. If bit 13 is
cleared to zero, the timer values shall be vendor specific.

Bit 12 of word 49 is reserved for use in the IDENTIFY PACKET DEVICE command response.

Bit 11 of word 49 is used to determine whether a device supports IORDY. If this bit is set to one, then the
device supports IORDY operation. If this bit is zero, the device may support IORDY. This ensures
backward compatibility. If a device supports PIO mode 3 or higher, then this bit shall be set to one.

Bit 10 of word 49 is used to indicate a device’s ability to enable or disable the use of IORDY. If this bit is set
to one, then the device supports the disabling of IORDY. Disabling and enabling of IORDY is accomplished
using the SET FEATURES command.

Bits 9 and 8 of word 49 shall be set to one for backward compatibility. These bits are defined for use in the
IDENTIFY PACKET DEVICE command response.

Bits 7 through 0 of word 49 are retired.

Bit 15 of word 50 shall be cleared to zero to indicate that the contents of word 50 are valid.

Bit 14 of word 50 shall be set to one to indicate that the contents of word 50 are valid.

Bits 13 through 1 of word 50 are reserved.

Bit 0 of word 50 set to one indicates that the device has a minimum Standby timer value that is device
specific.

8.12.24 Word 51: PIO data transfer mode number

The PIO transfer timing for each device falls into modes that have unique parametric timing specifications
that are specified in 10.2.2. The value returned in Bits 15-8 shall be 00h for mode 0, 01h for mode 1, or 02h
for mode 2. Values 03h through FFh are reserved.

8.12.25 Word 52: Retired

8.12.26 Word 53: Field validity

If bit 0 of word 53 is set to one, the values reported in words 54 through 58 are valid. If this bit is cleared to
zero, the values reported in words 54 through 58 may be valid. If bit 1 of word 53 is set to one, the values
reported in words 64 through 70 are valid. If this bit is cleared to zero, the values reported in words 64-70
are not valid. Any device that supports PIO mode 3 or above, or supports Multiword DMA mode 1 or above,
shall set bit 1 of word 53 to one and support the fields contained in words 64 through 70. If the device
supports Ultra DMA and the values reported in word 88 are valid, then bit 2 of word 53 shall be set to one. If
the device does not support Ultra DMA and the values reported in word 88 are not valid, then this bit is
cleared to zero.

8.12.27 Word 54: Number of current logical cylinders

This field contains the number of user-addressable logical cylinders in the current CHS translation (see 6.2).

Page 84
 T13/1153D revision 18

8.12.28 Word 55: Number of current logical heads

This field contains the number of user-addressable logical heads per logical cylinder in the current CHS
translation (see 6.2).

8.12.29 Word 56: Number of current logical sectors per logical track

This field contains the number of user-addressable logical sectors per logical track in the current CHS
translation (see 6.2).

8.12.30 Word (58:57): Current capacity in sectors

This field contains the current capacity in sectors in the current CHS translation (see 6.2).

8.12.31 Word 59: Multiple sector setting

If bit 8 is set to one, bits 7-0 reflect the number of sectors currently set to transfer on a READ/WRITE
MULTIPLE command. If word 47 bits 7-0 are zero then word 59 bits 8-0 shall also be zero. This field may
default to the preferred value for the device.

8.12.32 Word (61:60): Total number of user addressable sectors

This field contains the total number of user addressable sectors (see 6.2).

8.12.33 Word 62: Retired

8.12.34 Word 63: Multiword DMA transfer

Word 63 indentifies the Multiword DMA transfer modes supported by the device and indicates the mode that
is currently selected.

8.12.34.1 Reserved

Bits 15 though 11 of word 63 are reserved.

8.12.34.2 Multiword DMA mode 2 selected

If bit 10 of word 63 is set to one, then Multiword DMA mode 2 is selected. If this bit is cleared to zero, then
Multiword DMA mode 2 is not selected. If bit 9 is set to one or if bit 8 is set to one, then this bit shall be
cleared to zero.

8.12.34.3 Multiword DMA mode 1 selected

If bit 9 of word 63 is set to one, then Multiword DMA mode 1 is selected. If this bit is cleared to zero then
Multiword DMA mode 1 is not selected. If bit 10 is set to one or if bit 8 is set to one, then this bit shall be
cleared to zero.

8.12.34.4 Multiword DMA mode 0 selected

If bit 8 of word 63 is set to one, then Multiword DMA mode 0 is selected. If this bit is cleared to zero then
Multiword DMA mode 0 is not selected. If bit 10 is set to one or if bit 9 is set to one, then this bit shall be
cleared to zero.

8.12.34.5 Reserved

Bits 7 through 3 of word 63 are reserved.

Page 85
T13/1153D revision 18

8.12.34.6 Multiword DMA mode 2 supported

If bit 2 of word 63 is set to one, then Multiword DMA modes 2 and below are supported. If this bit is cleared
to zero, then Multiword DMA mode 2 is not supported. If Multiword DMA mode 2 is supported, then
Multiword DMA modes 1 and 0 shall also be supported. If this bit is set to one, bits 1 and 0 shall be set to
one.

8.12.34.7 Multiword DMA mode 1 supported

If bit 1 of word 63 is set to one, then Multiword DMA modes 1 and below are supported. If this bit is cleared
to zero, then Multiword DMA mode 1 is not supported. If Multiword DMA mode 1 is supported, then
Multiword DMA mode 0 shall also be supported. If this bit is set to one, bit 0 shall be set to one.

8.12.34.8 Multiword DMA mode 0 supported

If bit 0 of word 63 is set to one, then Multiword DMA mode 0 is supported.

8.12.35 Word 64: PIO transfer modes supported

Bits 7 through 0 of word 64 of the Identify Device parameter information is defined as the advanced PIO
data transfer supported field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit
significant. Any number of bits may be set to one in this field by the device to indicate the advanced PIO
modes it is capable of supporting.

Of these bits, bits 7 through 2 are Reserved for future advanced PIO modes. Bit 0, if set to one, indicates
that the device supports PIO mode 3. Bit 1, if set to one, indicates that the device supports PIO mode 4.

8.12.36 Word 65: Minimum Multiword DMA transfer cycle time per word

Word 65 of the parameter information of the IDENTIFY DEVICE command is defined as the minimum
Multiword DMA transfer cycle time per word. This field defines, in nanoseconds, the minimum cycle time
that the device supports when performing Multiword DMA transfers on a per word basis.

If this field is supported, bit 1 of word 53 shall be set to one. Any device that supports Multiword DMA mode
1 or above shall support this field, and the value in word 65 shall not be less than the minimum cycle time
for the fastest DMA mode supported by the device.

If bit 1 of word 53 is set to one because a device supports a field in words 64-70 other than this field and the
device does not support this field, the device shall return a value of zero in this field.

8.12.37 Word 66: Device recommended Multiword DMA cycle time

Word 66 of the parameter information of the IDENTIFY DEVICE command is defined as the device
recommended Multiword DMA transfer cycle time. This field defines, in nanoseconds, the minimum cycle
time per word during a single sector host transfer while performing a multiple sector READ DMA or WRITE
DMA command for any location on the media under nominal conditions. If a host runs at a faster cycle rate
by operating at a cycle time of less than this value, the device may negate DMARQ for flow control. The
rate at which DMARQ is negated could result in reduced throughput despite the faster cycle rate. Transfer
at this rate does not ensure that flow control will not be used, but implies that higher performance may
result.

If this field is supported, bit 1 of word 53 shall be set to one. Any device that supports Multiword DMA mode
1 or above shall support this field, and the value in word 66 shall not be less than the value in word 65.

If bit 1 of word 53 is set to one because a device supports a field in words 64-70 other than this field and the
device does not support this field, the device shall return a value of zero in this field.

Page 86
 T13/1153D revision 18

8.12.38 Word 67: Minimum PIO transfer cycle time without flow control

Word 67 of the parameter information of the IDENTIFY DEVICE command is defined as the minimum PIO
transfer without flow control cycle time. This field defines, in nanoseconds, the minimum cycle time that, if
used by the host, the device guarantees data integrity during the transfer without utilization of flow control.

If this field is supported, Bit 1 of word 53 shall be set to one.

Any device that supports PIO mode 3 or above shall support this field, and the value in word 67 shall not be
less than the value reported in word 68.

If bit 1 of word 53 is set to one because a device supports a field in words 64-70 other than this field and the
device does not support this field, the device shall return a value of zero in this field.

8.12.39 Word 68: Minimum PIO transfer cycle time with IORDY

Word 68 of the parameter information of the IDENTIFY DEVICE command is defined as the minimum PIO
transfer with IORDY flow control cycle time. This field defines, in nanoseconds, the minimum cycle time
that the device supports while performing data transfers while utilizing IORDY flow control.

If this field is supported, Bit 1 of word 53 shall be set to one.

Any device that supports PIO mode 3 or above shall support this field, and the value in word 68 shall be the
fastest defined PIO mode supported by the device.

If bit 1 of word 53 is set to one because a device supports a field in words 64-70 other than this field and the
device does not support this field, the device shall return a value of zero in this field.

8.12.40 Words 69-74: Reserved

8.12.41 Word 75: Queue depth

Bits 4 through 0 of word 75 indicate the maximum queue depth supported by the device. If bit 1 of word 83
is cleared to zero indicating that the device does not support READ/WRITE DMA QUEUED commands, the
value in this field shall be 00h. If bit 1 of word 83 is set to one, bits 4 through 0 indicate the maximum queue
depth supported. A device may support READ/WRITE DMA QUEUED commands to provide overlap only
(i.e., queuing not supported), in this case, bit 1 of word 83 shall be set to one and the queue depth shall be
set to 00h.

8.12.42 Words 76-79: Reserved

8.12.43 Word 80: Major version number

If not 0000h or FFFFh, the device claims compliance with the major version(s) as indicated by bits 1 through
4 being equal to one. Values other than 0000h and FFFFh are bit significant. Since ATA standards maintain
downward compatibility, it is allowed for a device to set more than one bit.

8.12.44 Word 81: Minor version number

If an implementor claims that the revision of the standard they used to guide their implementation does not
need to be reported or if the implementation was based upon a standard prior to the ATA-3 standard, word
81 shall be 0000h or FFFFh.

Table 12 defines the value that may optionally be reported in word 81 to indicate the revision of the standard
that guided the implementation.

Page 87
T13/1153D revision 18

Table 12 − Minor version number

Value Minor revision
0001h ATA (ATA-1) X3T9.2 781D prior to revision 4
0002h ATA-1 published, ANSI X3.221-1994
0003h ATA (ATA-1) X3T10 781D revision 4
0004h ATA-2 published, ANSI X3.279-1996
0005h ATA-2 X3T10 948D prior to revision 2k
0006h ATA-3 X3T10 2008D revision 1
0007h ATA-2 X3T10 948D revision 2k
0008h ATA-3 X3T10 2008D revision 0
0009h ATA-2 X3T10 948D revision 3
000Ah ATA-3 published, ANSI X3.298-199x
000Bh ATA-3 X3T10 2008D revision 6
000Ch ATA-3 X3T13 2008D revision 7 and 7a
000Dh ATA/ATAPI-4 X3T13 1153D revision 6
000Eh ATA/ATAPI-4 T13 1153D revision 13
000Fh ATA/ATAPI-4 X3T13 1153D revision 7
0010h Reserved
0011h ATA/ATAPI-4 T13 1153D revision 15
0012h-0013h Reserved
0014h ATA/ATAPI-4 T13 1153D revision 14
0015h-0016h Reserved
0017h ATA/ATAPI-4 T13 1153D revision 17
0018h-FFFFh Reserved

8.12.45 Words 82-84: Features/command sets supported

Words 82, 83, and 84 shall indicate features/command sets supported. The value 0000h or FFFFh was
placed in each of these words by devices prior to ATA-3 and shall be interpreted by the host as meaning
that features/command sets supported are not indicated. Bits 1 through 13 of word 83 and bits 0 through 13
of word 84 are reserved. Bit 14 of word 83 and word 84 shall be set to one and bit 15 of word 83 and word
84 shall be cleared to zero to provide indication that the features/command sets supported words are valid.

If bit 0 of word 82 is set to one, the SMART feature set is supported.

If bit 1 of word 82 is set to one, the Security Mode feature set is supported.

If bit 2 of word 82 is set to one, the Removable Media feature set is supported.

If bit 3 of word 82 is set to one, the Power Management feature set is supported.

If bit 4 of word 82 is set to one, the PACKET Command feature set is supported.

If bit 5 of word 82 is set to one, write cache is supported.

If bit 6 of word 82 is set to one, look-ahead is supported.

If bit 7 of word 82 is set to one, release interrupt is supported.

If bit 8 of word 82 is set to one, SERVICE interrupt is supported.

If bit 9 of word 82 is set to one, the DEVICE RESET command is supported.

If bit 10 of word 82 is set to one, the Host Protected Area feature set is supported.

Bit 11 of word 82 is obsolete.

Page 88
 T13/1153D revision 18

If bit 12 of word 82 is set to one, the device supports the WRITE BUFFER command.

If bit 13 of word 82 is set to one, the device supports the READ BUFFER command.

If bit 14 of word 82 is set to one, the device supports the NOP command.

Bit 15 of word 82 is obsolete.

If bit 0 of word 83 is set to one, the device supports the DOWNLOAD MICROCODE command.

If bit 1 of word 83 is set to one, the device supports the READ DMA QUEUED and WRITE DMA QUEUED
commands.

If bit 2 of word 83 is set to one, the device supports the CFA feature set.

If bit 3 of word 83 is set to one, the device supports the Advanced Power Management feature set.

If bit 4 of word 83 is set to one, the device supports the Removable Media Status feature set.

8.12.46 Words 85-87: Features/command sets enabled

Words 85, 86, and 87 shall indicate features/command sets enabled. The value 0000h or FFFFh was placed
in each of these words by devices prior to ATA-4 and shall be interpreted by the host as meaning that
features/command sets enabled are not indicated. Bits 1 through 15 of word 86 are reserved. Bits 0-13 of
word 87 are reserved. Bit 14 of word 87 shall be set to one and bit 15 of word 87 shall be cleared to zero to
provide indication that the features/command sets enabled words are valid.

If bit 0 of word 85 is set to one, the SMART feature set has been enabled via the SMART ENABLE
OPERATIONS command.

If bit 1 of word 85 is set to one, the Security Mode feature set has been enabled via the SECURITY SET
PASSWORD command.

If bit 2 of word 85 is set to one, the Removable Media feature set is supported.

If bit 3 of word 85 is set to one, the Power Management feature set is supported.

If bit 4 of word 85 is set to one, the PACKET Command feature set is supported.

If bit 5 of word 85 is set to one, write cache has been enabled via the SET FEATURES command (see
8.37.9).

If bit 6 of word 85 is set to one, look-ahead has been enabled via the SET FEATURES command (see
8.37.13).

If bit 7 of word 85 is set to one, release interrupt has been enabled via the SET FEATURES command (see
8.37.14).

If bit 8 of word 85 is set to one, SERVICE interrupt has been enabled via the SET FEATURES command
(see 8.37.15).

If bit 9 of word 85 is set to one, the DEVICE RESET command is supported.

If bit 10 of word 85 is set to one, the Host Protected Area feature set is supported.

Bit 11 of word 85 is obsolete.

Page 89
T13/1153D revision 18

If bit 12 of word 85 is set to one, the device supports the WRITE BUFFER command.

If bit 13 of word 85 is set to one, the device supports the READ BUFFER command.

If bit 14 of word 85 is set to one, the device supports the NOP command.

Bit 15 of word 85 is obsolete.

If bit 0 of word 86 is set to one, the device supports the DOWNLOAD MICROCODE command.

If bit 1 of word 86 is set to one, the device supports the READ DMA QUEUED and WRITE DMA QUEUED
commands.

If bit 2 of word 86 is set to one, the device supports the CFA feature set.

If bit 3 of word 86 is set to one, the Advanced Power Management feature set has been enabled via the
SET FEATURES command.

If bit 4 of word 86 is set to one, the Removable Media Status feature set has been enabled via the SET
FEATURES command.

8.12.47 Word 88: Ultra DMA modes

Only one Ultra DMA mode shall be selected at any time. If an Ultra DMA mode is enabled, no Multiword
DMA mode shall be enabled. If a Multiword DMA mode is enabled, no Ultra DMA mode shall be enabled.

8.12.47.1 Reserved

Bits 15 though 11 of word 88 are reserved.

8.12.47.2 Ultra DMA mode 2 selected

If bit 10 of word 88 is set to one, then Ultra DMA mode 2 is selected. If this bit is cleared to zero, then Ultra
DMA mode 2 is not selected. If bit 9 is set to one or if bit 8 is set to one, then this bit shall be cleared to
zero.

8.12.47.3 Ultra DMA mode 1 selected

If bit 9 of word 88 is set to one, then Ultra DMA mode 1 is selected. If this bit is cleared to zero then Ultra
DMA mode 1 is not selected. If bit 10 is set to one or if bit 8 is set to one, then this bit shall be cleared to
zero.

8.12.47.4 Ultra DMA mode 0 selected

If bit 8 of word 88 is set to one, then Ultra DMA mode 0 is selected. If this bit is cleared to zero then Ultra
DMA mode 0 is not selected. If bit 10 is set to one or if bit 9 is set to one, then this bit shall be cleared to
zero.

8.12.47.5 Reserved

Bits 7 through 3 of word 88 are reserved.

8.12.47.6 Ultra DMA mode 2 supported

If bit 2 of word 88 is set to one, then Ultra DMA modes 2 and below are supported. If this bit is cleared to
zero, then Ultra DMA mode 2 is not supported. If Ultra DMA mode 2 is supported, then Ultra DMA modes 1
and 0 shall also be supported. If this bit is set to one, bits 1 and 0 shall be set to one.

Page 90
 T13/1153D revision 18

8.12.47.7 Ultra DMA mode 1 supported

If bit 1 of word 88 is set to one, then Ultra DMA modes 1 and below are supported. If this bit is cleared to
zero, then Ultra DMA mode 1 is not supported. If Ultra DMA mode 1 is supported, then Ultra DMA mode 0
shall also be supported. If this bit is set to one, bit 0 shall be set to one.

8.12.47.8 Ultra DMA mode 0 supported

If bit 0 of word 88 is set to one, then Ultra DMA mode 0 is supported. If this bit is cleared to zero, then Ultra
DMA is not supported.

8.12.48 Word 89: Time required for Security erase unit completion

Word 89 specifies the time required for the SECURITY ERASE UNIT command to complete.

Value Time
0 Value not specified
1-254 (Value*2) minutes
255 >508 minutes

8.12.49 Word 90: Time required for Enhanced security erase unit completion

Word 90 specifies the time required for the ENHANCED SECURITY ERASE UNIT command to complete.

Value Time
0 Value not specified
1-254 (Value*2) minutes
255 >508 minutes

8.12.50 Word 91: Advanced power management level value

Bits 7-0 of word 91 contain the current Advanced Power Management level setting.

8.12.51 Words 92-126: Reserved

8.12.52 Word 127: Removable Media Status Notification feature set support

If bit 0 of word 127 is set to one and bit 1 of word 127 is cleared to zero, the device supports the Removable
Media Status Notification feature set. Bits 15 through 2 shall be cleared to zero.

8.12.53 Word 128: Security status

Bit 8 of word 128 indicates the security level. If security mode is enabled and the security level is high, bit 8
shall be cleared to zero. If security mode is enabled and the security level is maximum, bit 8 shall be set to
one. When security mode is disabled, bit 8 shall be cleared to zero.

Bit 5 of word 128 indicates the Enhanced security erase unit feature is supported. If bit 5 is set to one, the
Enhanced security erase unit feature set is supported.

Bit 4 of word 128 indicates that the security count has expired. If bit 4 is set to one, the security count is
expired and SECURITY UNLOCK and SECURITY ERASE UNIT are command aborted until a power-on
reset or hard reset.

Bit 3 of word 128 indicates security Frozen. If bit 3 is set to one, the security is Frozen.

Bit 2 of word 128 indicates security locked. If bit 2 is set to one, the security is locked.

Page 91
T13/1153D revision 18

Bit 1 of word 128 indicates security enabled. If bit 1 is set to one, the security is enabled.

Bit 0 of word 128 indicates the Security Mode feature set supported. If bit 0 is set to one, security is
supported.

8.12.54 Words 129-159: Vendor specific.

8.12.55 Words 160-255: Reserved.

Page 92
 T13/1153D revision 18

8.13 IDENTIFY PACKET DEVICE

8.13.1 Command code

A1h

8.13.2 Feature set

PACKET Command feature set

− Use prohibited for devices not implementing the PACKET Command feature set.
− Mandatory for devices implementing the PACKET Command feature set.

8.13.3 Protocol

PIO data in (see 9.7).

8.13.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command A1h

Device/Head register -
DEV shall indicate the selected device.

8.13.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.13.6 Error outputs

The device shall return command aborted if the device does not implement this command, otherwise, the
device shall not report an error.

Page 93
T13/1153D revision 18

8.13.7 Prerequisites

This command shall be accepted regardless of the state of DRDY.

8.13.8 Description

The IDENTIFY PACKET DEVICE command enables the host to receive parameter information from a
device that implements the PACKET Command feature set.

Some devices may have to read the media in order to complete this command.

When the command is issued, the device sets the BSY bit to one, prepares to transfer the 256 words of
device identification data to the host, sets the DRQ bit to one, clears the BSY bit to zero, and asserts INTRQ
if nIEN is cleared to zero. The host may then transfer the data by reading the Data register. Table 13
defines the arrangement and meanings of the parameter words in the buffer. All reserved bits or words shall
be zero.

Some parameters are defined as a group of bits. A word that is defined as a set of bits is transmitted with
indicated bits on the respective data bus bit (e.g., bit 15 appears on DD15).

Some parameters are defined as a 16-bit value. A word that is defined as a 16-bit value places the most
significant bit of the value on bit DD15 and the least significant bit on bit DD0.

Some parameters are defined as 32-bit values (e.g., words 57 and 58). Such fields are transferred using
two word transfers. The device shall first transfer the least significant bits, bits 15 through 0 of the value, on
bits DD (15:0) respectively. After the least significant bits have been transferred, the most significant bits,
bits 31 through 16 of the value, shall be transferred on DD (15:0) respectively.

Some parameters are defined as a string of ASCII characters. For the string “Copyright”, the character “C” is
the first byte, the character “o” is the 2nd byte, etc. When such fields are transferred, the order of
transmission is:

the 1st character (“C”) is on bits DD (15:8) of the first word,

the 2nd character (“o”) is on bits DD (7:0) of the first word,
the 3rd character (“p”) is on bits DD (15:8) of the second word,
the 4th character (“y”) is on bits DD (7:0) of the second word,
etc.

Page 94
 T13/1153D revision 18

Table 13 − IDENTIFY PACKET DEVICE information(continued)

Word F/V
0 General configuration bit-significant information:
F 15-14 10=ATAPI device
11=reserved
R 13 reserved
F 12-8 Field indicates command packet set used by device
F 7 1=removable media device
F 6-5 00=Device shall set DRQ to one within 3 ms of receiving PACKET
command.
01=Device shall assert INTRQ when DRQ is set to one after receiving
PACKET.
10=Device shall set DRQ to one within 50 µs of receiving PACKET
R 4-2 command.
F 1-0 11=reserved
reserved
00=12 byte command packet
01=16 byte command packet
1x=reserved
1-9 R Reserved
10-19 F Serial number (20 ASCII characters)
20-22 R Reserved
23-26 F Firmware revision (8 ASCII characters)
27-46 F Model number (40 ASCII characters)
47-48 R Reserved
49 Capabilities
F 15 1=interleaved DMA supported
F 14 1=command queuing supported
F 13 1=overlap operation supported
F 12 1=ATA software reset required (obsolete)
F 11 1=IORDY supported
F 10 1=IORDY may be disabled
F 9 1=LBA supported
F 8 1=DMA supported
X 7-0 Vendor specific
50 R Reserved
51 F 15-8 PIO data transfer mode number
X 7-0 Vendor specific
52 R Reserved
53 R 15-3 Reserved
F 2 1=the fields reported in word 88 are valid
0=the fields reported in word 88 are not valid
F 1 1=the fields reported in words 64-70 are valid
0=the fields reported in words 64-70 are not valid
V 0 1=the fields reported in words 54-58 are valid
0=the fields reported in words 54-58 may be valid
54-62 R Reserved
(continued)

Page 95
T13/1153D revision 18

Table 13 − IDENTIFY PACKET DEVICE information

(continued)
Word F/V
63 R 15-11 Reserved
V 10 1= Multiword DMA mode 2 is selected
0= Multiword DMA mode 2 is not selected
V 9 1= Multiword DMA mode 1 is selected
0= Multiword DMA mode 1 is not selected
V 8 1= Multiword DMA mode 0 is selected
0= Multiword DMA mode 0 is not selected
R 7-3 Reserved
F 2 1= Multiword DMA mode 2 and below are supported
F 1 1= Multiword DMA mode 1 and below are supported
F 0 1= Multiword DMA mode 0 is supported Multiword DMA mode selected
64 R 15-8 Reserved
F 7-0 Advanced PIO transfer modes supported
65 Minimum Multiword DMA transfer cycle time per word
F 15-0 Cycle time in nanoseconds
66 Manufacturer’s recommended Multiword DMA transfer cycle time
F 15-0 Cycle time in nanoseconds
67 Minimum PIO transfer cycle time without flow control
F 15-0 Cycle time in nanoseconds
68 Minimum PIO transfer cycle time with IORDY flow control
F 15-0 Cycle time in nanoseconds
69-70 R Reserved (for future command overlap and queuing)
71 F Typical time in ns from receipt of PACKET command to bus release.
72 F Typical time in ns from receipt of SERVICE command to BSY cleared to zero
73-74 R Reserved
75 F Queue depth
15-5 Reserved
4-0 Maximum queue depth supported
76-79 R Reserved
80 F Major version number
0000h or FFFFh = device does not report version
15 Reserved
14 Reserved for ATA/ATAPI-14
13 Reserved for ATA/ATAPI-13
12 Reserved for ATA/ATAPI-12
11 Reserved for ATA/ATAPI-11
10 Reserved for ATA/ATAPI-10
9 Reserved for ATA/ATAPI-9
8 Reserved for ATA/ATAPI-8
7 Reserved for ATA/ATAPI-7
6 Reserved for ATA/ATAPI-6
5 Reserved for ATA/ATAPI-5
4 1=supports ATA/ATAPI-4
3 1=supports ATA-3
2 1=supports ATA-2
1 1=supports ATA-1
0 Reserved
81 F Minor version number
0000h or FFFFh=device does not report version
0001h-FFFEh=see 8.12.44
(continued)

Page 96
 T13/1153D revision 18

Table 13 − IDENTIFY PACKET DEVICE information(continued)

Word F/V
82 F Command set supported. If words 82 and 83 =0000h or FFFFh command set
notification not supported.
15 Obsolete
14 1=NOP command supported
13 1=READ BUFFER command supported
12 1=WRITE BUFFER command supported
11 Obsolete
10 1=Host Protected Area feature set supported
9 1=DEVICE RESET command supported
8 1=SERVICE interrupt supported
7 1=release interrupt supported
6 1=look-ahead supported
5 1=write cache supported
4 1=supports PACKET Command feature set
3 1=supports Power Management feature set
2 1=supports Removable Media feature set
1 1=supports Security Mode feature set
0 1=supports SMART feature set
83 F Command sets supported. If words 82 and 83 =0000h or FFFFh command set
notification not supported.
15 Shall be cleared to zero
14 Shall be set to one
13-5 Reserved
4 1=Removable Media Status Notification feature set supported
3-1 Reserved
0 1=DOWNLOAD MICROCODE command supported
84 F Command set/feature supported extension. If words 82, 83, and 84 = 0000h or FFFFh
command set notification extension is not supported.
15 Shall be cleared to zero
14 Shall be set to one
13-0 Reserved
85 V Command set/feature enabled. If words 85, 86, and 87 = 0000h or FFFFh command
set enabled notification is not supported.
15 Obsolete
14 1=NOP command supported
13 1=READ BUFFER command supported
12 1=WRITE BUFFER command supported
11 Obsolete
10 1=Host Protected Area feature set supported
9 1=DEVICE RESET command supported
8 1=SERVICE interrupt enabled
7 1=release interrupt enabled
6 1=look-ahead enabled
5 1=write cache enabled
4 1=supports PACKET Command feature set
3 1=supports Power Management feature set
2 1=supports Removable Media feature set
1 1= Security Mode feature set enabled
0 1= SMART feature set enabled
(continued)

Page 97
T13/1153D revision 18

Table 13 − IDENTIFY PACKET DEVICE information(concluded)

Word F/V
86 V Command set/feature enabled. If words 85, 86, and 87 = 0000h or FFFFh command
set enabled notification is not supported.
15-5 Reserved
4 1=Removable Media Status Notification feature set enabled via the SET
FEATURES command.
3-1 Reserved
0 1=DOWNLOAD MICROCODE command supported
87 V Command set/feature default. If words 85, 86, and 87 = 0000h or FFFFh command
set default notification is not supported.
15 Shall be cleared to zero
14 Shall be set to one
13-0 Reserved
88 R 15-11 Reserved
V 10 1=Ultra DMA mode 2 is selected
0=Ultra DMA mode 2 is not selected
V 9 1=Ultra DMA mode 1 is selected
0=Ultra DMA mode 1 is not selected
V 8 1=Ultra DMA mode 0 is selected
0=Ultra DMA mode 0 is not selected
R 7-3 Reserved
F 2 1=Ultra DMA mode 2 and below are supported
F 1 1=Ultra DMA mode 1 and below are supported
F 0 1=Ultra DMA mode 0 is supported
89-126 R Reserved
127 F Removable Media Status Notification feature set support
15-2 Reserved
1-0 00=Removable Media Status Notification feature set not supported
01=Removable Media Status Notification feature set supported
10=Reserved
11=Reserved
128 V Security status
15-9 Reserved
8 Security level 0=High, 1=Maximum
7-6 Reserved
5 1=Enhanced security erase supported
4 1=Security count expired
3 1=Security frozen
2 1=Security locked
1 1=Security enabled
0 1=Security supported
129-159 X Vendor specific
160-255 R Reserved
Key:
F = the content of the word is fixed and does not change. For removable media devices, these values may
change when media is removed or changed.
V = the contents of the word is variable and may change depending on the state of the device or the
commands executed by the device.
X = the content of the word is vendor specific and may be fixed or variable.
R = the content of the word is reserved and shall be zero.

Page 98
 T13/1153D revision 18

8.13.9 Word 0: General configuration

Bits 15 and 14 of word 0 indicate the type of device. If bit 15 is cleared to zero the device does not
implement the PACKET Command feature set. If bit 15 is set to one and bit 14 is cleared to zero, the device
implements the PACKET Command feature set. The value bit 15 and bit 14 both set to one is reserved.

Bits 12 through 8 of word 0 indicate the command packet set implemented by the device. This value follows
the peripheral device type value as defined in X3T10/995D, SCSI-3 Primary Commands.

Value Description
00h Direct-access device
01h Sequential-access device
02h Printer device
03h Processor device
04h Write-once device
05h CD-ROM device
06h Scanner device
07h Optical memory device
08h Medium changer device
09h Communications device
0A-0Bh Reserved for ACS IT8
0Ch Array controller device
0D-1Eh Reserved
1Fh Unknown or no device type

Bit 7 if set to one indicates that the device has removable media.

Bits 6 and 5 of word 0 indicates the DRQ response time when a PACKET command is received. A value of
00b indicates a maximum time of 3 ms from receipt of PACKET to the setting of DRQ to one. A value of
01b indicates that INTRQ shall be asserted when DRQ is set to one and that this action will occur within 10
ms of the receipt of PACKET. A value of 10b indicates a maximum time of 50 µs from the receipt of
PACKET to the setting of DRQ to one. The value 11b is reserved.

Bits 1 and 0 of word 0 indicate the packet size the device supports. A value of 00b indicates that a 12 byte
packet is supported; a value of 01b indicates a 16 byte packet. The values 10b and 11b are reserved.

8.13.10 Words 1-9: Reserved

8.13.11 Words 10-19: Serial number

The use of these words is optional. If not implemented, the content shall be zeros. If implemented, the
content shall be as described in words 10-19 of the IDENTIFY DEVICE command (see 8.12.16).

8.13.12 Words 20-22: Reserved

8.13.13 Words 23-26: Firmware revision

Words 23 through 26 shall have the content described for words 23 through 26 of the IDENTIFY DEVICE
command.

8.13.14 Words 27-46: Model number

Words 27 through 46 shall have the content described for words 27 through 46 of the IDENTIFY DEVICE
command.

8.13.15 Words 47-48: Reserved

Page 99
T13/1153D revision 18

8.13.16 Word 49: Capabilities

Bit 15 of word 49 is used to indicated that the device supports interleaved DMA data transfer for overlapped
DMA commands.

Bit 14 of word 49 is used to indicated that the device supports command queuing for overlapped commands.
If bit 14 is set to one, bit 13 shall be set to one.

Bit 13 of word 49 is used to indicated that the device supports command overlap operation.

Bit 12 of word 49 indicates that the device requires a software reset to reset the device when BSY is set to
one. Some devices produced before this standard are unable to process a DEVICE RESET when the BSY
bit is set to one. The use of this bit is obsolete.

Bit 11 of word 49 is used to determine whether a device supports IORDY. If this bit is set to one, then the
device supports IORDY operation. If this bit is zero, the device may support IORDY. This ensures
backward compatibility. If a device supports PIO mode 3 or higher, then this bit shall be set to one.

Bit 10 of word 49 is used to indicate a device’s ability to enable or disable the use of IORDY. If this bit is set
to one, then the device supports the disabling of IORDY. Disabling and enabling of IORDY is accomplished
using the SET FEATURES command.

Bit 9 of word 49 indicates that an LBA translation is supported

Bits 8 of word 49 indicates that DMA is supported.

8.13.17 Word 50: Reserved

8.13.18 Word 51: PIO data transfer mode number

Word 51 shall have the content described for word 51 of the IDENTIFY DEVICE command.

8.13.19 Word 52: Reserved

8.13.20 Word 53: Field validity

Word 53 shall have the content described for word 53 of the IDENTIFY DEVICE command.

8.13.21 Words 54-62: Reserved

8.13.22 Word 63: Multiword DMA transfer

Word 63 shall have the content described for word 63 of the IDENTIFY DEVICE command.

8.13.23 Word 64: PIO transfer mode supported

Word 64 shall have the content described for word 64 of the IDENTIFY DEVICE command.

8.13.24 Word 65: Minimum multiword DMA transfer cycle time per word

Word 65 shall have the content described for word 65 of the IDENTIFY DEVICE command.

8.13.25 Word 66: Device recommended multiword DMA cycle time

Word 66 shall have the content described for word 66 of the IDENTIFY DEVICE command.

8.13.26 Word 67: Minimum PIO transfer cycle time without flow control

Page 100
 T13/1153D revision 18

Word 67 shall have the content described for word 67 of the IDENTIFY DEVICE command.

8.13.27 Word 68: Minimum PIO transfer cycle time with IORDY

Word 68 shall have the content described for word 68 of the IDENTIFY DEVICE command.

8.13.28 Word 69-70: Reserved

8.13.29 Word 71: PACKET to bus release time

Word 71 shall contain the typical time (99.7 % of the time) in microseconds from the receipt of a PACKET
command until the device performs a bus release.

8.13.30 Word 72: SERVICE to bus release time

Word 72 shall contain the typical time (the mean plus three standard deviations) in microseconds from the
receipt of a SERVICE command until the device performs a bus release.

8.13.31 Word 73-74: Reserved

8.13.32 Word 75: Queue depth

Bits 4 through 0 of word 75 shall have the content described for word 75 of the IDENTIFY DEVICE
command.

8.13.33 Words 76-79: Reserved

8.13.34 Word 80: Major revision number

Word 80 shall have the content described for word 80 of the IDENTIFY DEVICE command.

8.13.35 Word 81: Minor revision number

Word 81 shall have the content described for word 81 of the IDENTIFY DEVICE command.

8.13.36 Words 82-84: Features/command sets supported

Words 82, 83, and 84 shall have the content described for words 82, 83, and 84 of the IDENTIFY DEVICE
command.

8.13.37 Words 85-87: Features/command sets enabled

Words 85, 86, and 87 shall have the content described for words 85, 86, and 87 of the IDENTIFY DEVICE
command.

8.13.38 Word 88:Ultra DMA modes

Word 88 shall have the content described for word 88 of the IDENTIFY DEVICE command.

8.13.39 Word 89: Time required for Security erase unit completion

Word 89 shall have the content described for word 89 of the IDENTIFY DEVICE command.

8.13.40 Word 90: Time required for Enhanced security erase unit completion

Word 90 shall have the content described for word 90 of the IDENTIFY DEVICE command.

Page 101
T13/1153D revision 18

8.13.41 Word 127: Removable Media Status Notification feature set support

Word 127 shall have the content described for word 127 of the IDENTIFY DEVICE command.

8.13.42 Word 128: Security status

Word 128 shall have the content described for word 128 of the IDENTIFY DEVICE command.

8.13.43 Words 129-255: Reserved

Page 102
 T13/1153D revision 18

8.14 IDLE

8.14.1 Command code

E3h

8.14.2 Feature set

Power Management feature set.

− Power Management feature set is mandatory when power management is not implemented by a
PACKET power management feature set.
− This command is mandatory when the Power Management feature set is implemented.

8.14.3 Protocol

Non-data command (see 9.9).

8.14.4 Inputs

Values other than zero in the Sector Count register when the IDLE command is issued shall determine the
time period programmed into the Standby timer. Table 14 defines these values.

Register 7 6 5 4 3 2 1 0
Features na
Sector Count Timer period value
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command E3h

Device/Head register -
DEV shall indicate the selected device.

Table 14 − Automatic Standby timer periods

Sector Count register Corresponding timeout period
contents
0 (00h) Timeout disabled
1-240 (01h-F0h) (value * 5) s
241-251 (F1h-FBh) ((value - 240) * 30) min
252 (FCh) 21 min
253 (FDh) Period between 8 and 12 hrs
254 (FEh) Reserved
255 (FFh) 21 min 15 s
NOTE − Times are approximate.

Page 103
T13/1153D revision 18

8.14.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.14.6 Error outputs

The device shall return command aborted if the device does not support the Power Management feature
set.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if Power Management feature set is not supported. ABRT may be set to
one if the device is not able to complete the action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.14.7 Prerequisites

DRDY set equal to one.

8.14.8 Description

The IDLE command allows the host to place the device in the Idle mode using the Standby timer. INTRQ
may be asserted even though the device may not have fully transitioned to Idle mode.

Page 104
 T13/1153D revision 18

If the Sector Count register is non-zero then the Standby timer shall be enabled. The value in the Sector
Count register shall be used to determine the time programmed into the Standby timer (see 6.8). If the
Sector Count register is zero then the Standby timer is disabled.

Page 105
T13/1153D revision 18

8.15 IDLE IMMEDIATE

8.15.1 Command code

E1h

8.15.2 Feature set

Power Management feature set.

− Power Management feature set is mandatory when power management is not implemented by a
PACKET power management feature set.
− This command is mandatory when the Power Management feature set is implemented.

8.15.3 Protocol

Non-data command (see 9.9).

8.15.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command E1h

Device/Head register -
DEV shall indicate the selected device.

8.15.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 106
 T13/1153D revision 18

8.15.6 Error outputs

The device shall return command aborted if the device does not support the Power Management feature
set.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if Power Management feature set is not supported. ABRT may be set to
one if the device is not able to complete the action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.15.7 Prerequisites

DRDY set equal to one.

8.15.8 Description

The IDLE IMMEDIATE command allows the host to immediately place the device in the Idle mode. INTRQ
may be asserted even though the device may not have fully transitioned to Idle mode (see 6.8).

Page 107
T13/1153D revision 18

8.16 INITIALIZE DEVICE PARAMETERS

8.16.1 Command code

91h

8.16.2 Feature set

General feature set

− Mandatory for devices not implementing the PACKET Command feature set if a CHS
translation is supported.
− Not mandatory for devices not implementing the PACKET command feature set if the device
capacity is greater then 8 Gbytes and only LBA translation is supported.
− Use prohibited for devices implementing the PACKET Command feature set.

8.16.3 Protocol

Non-data (see 9.9).

8.16.4 Inputs

The Sector Count register specifies the number of logical sectors per logical track, and the Device/Head
register specifies the maximum head number.

Register 7 6 5 4 3 2 1 0
Features na
Sector Count Logical sectors per logical track
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV Max head
Command 91h

Device/Head register -
DEV shall indicate the selected device.

8.16.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY na DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 108
 T13/1153D revision 18

8.16.6 Error outputs

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY na DF na DRQ na na ERR

Error register -
ABRT shall be set to one if the device does not support the requested CHS translation. ABRT may
be
set to one if the device is not able to complete the action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.16.7 Prerequisites

This command shall be accepted regardless of the state of DRDY.

8.16.8 Description

This command enables the host to set the number of logical sectors per track and the number of logical
heads minus 1, per logical cylinder for the current CHS translation mode.

If the capacity of the device is less than 16,514,064 sectors, a device shall support the CHS translation
described in words 1, 3, and 6 of the IDENTIFY DEVICE information. Support of other CHS translations is
optional.

If the host requests a CHS translation that is not supported by the device, the device shall return command
aborted. The device shall also clear bit 0 of word 53 in the IDENTIFY DEVICE data to zero, and the content
of words 54, 55, 56, and (58:57) may be zero until a supported translation is requested by the host.

If the requested CHS translation is not supported, the device shall fail all media access commands with an
ID Not Found error until a valid CHS translation is established.

After a successful INITIALIZE DEVICE PARAMETERS command the content of all IDENTIFY DEVICE
words shall comply with 6.2.1 in addition to the following:
1) The content of words 1, 3, 6, and (61:60) shall be unchanged.
2) The content of word 55 shall equal the (Max head value requested by the host + 1).
3) The content of word 56 shall equal the (Logical sectors per logical track value requested by the host).
4) If the content of word (61:60) is less than or equal to 16,514,064, then word 54 shall equal the whole
number result of [[(the content of words (61:60)) ÷ [(the new content of word 55 as determined by the
successful INITIALIZE DEVICE PARAMETERS command) * (the new content of word 56 as determined
by the successful INITIALIZE DEVICE PARAMETERS command)]], or 65,535 whichever is less.
5) If the content of word (61:60) is greater than 16,514,064, then word 54 shall equal the whole number
result of [[(16,514,064) ÷ [(the new content of word 55 as determined by the successful INITIALIZE
DEVICE PARAMETERS command) * (the new content of word 56 as determined by the successful
INITIALIZE DEVICE PARAMETERS command)]] or 65,535 whichever is less.

Page 109
T13/1153D revision 18

6) Words (58:57) shall equal [(the new content of word 54) * (the new content of word 55) * (the new
content of word 56)].

Page 110
 T13/1153D revision 18

8.17 MEDIA EJECT

8.17.1 Command code

EDh

8.17.2 Feature set

Removable Media Status Notification feature set

− Mandatory for devices not implementing the PACKET command feature set and implementing
the Removable Media Status Notification feature set.
− Prohibited for devices implementing the PACKET command feature set.

Removable Media feature set

− Mandatory for devices not implementing the PACKET command feature set and implementing
the Removable Media feature set.
− Prohibited for devices implementing the PACKET command feature set.
8.17.3 Protocol

Non-data command (see 9.9).

8.17.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command EDh

Device/Head register -
DEV shall indicate the selected device.

8.17.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 111
T13/1153D revision 18

8.17.6 Error outputs

If the device does not support this command, the device shall return command aborted.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT NM obs
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if device does not support this command. ABRT may be set to one if the
device is not able to complete the action requested by the command.
NM (No Media) shall be set to one if no media is present in the device.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.17.7 Prerequisites

DRDY set equal to one.

8.17.8 Description

This command causes any pending operations to complete, spins down the device if needed, unlocks the
media if locked, and ejects the media. The device keeps track of only one level of media lock.

Page 112
 T13/1153D revision 18

8.18 MEDIA LOCK

8.18.1 Command code

DEh

8.18.2 Feature set

Removable Media Status Notification feature set

− Optional for devices not implementing the PACKET command feature set and implementing the
Removable Media Status Notification feature set.
− Prohibited for device implementing the PACKET command feature set.

Removable Media feature set

− Mandatory for devices not implementing the PACKET command feature set and implementing
the Removable Media feature set.
− Prohibited for devices implementing the PACKET command feature set.
8.18.3 Protocol

Non-data command (see 9.9).

8.18.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command DEh

Device/Head register -
DEV shall indicate the selected device.

8.18.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 113
T13/1153D revision 18

8.18.6 Error outputs

If the device does not support this command, the device shall return command aborted.

Register 7 6 5 4 3 2 1 0
Error na na na na MCR ABRT NM obs
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if device does not support this command. ABRT may be set to one if the
device is not able to complete the action requested by the command.
NM (No Media) shall be set to one if no media is present in the device.
MCR (Media Change Request) shall be set to one if the device is locked and a media change
request has been detected by the device.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.18.7 Prerequisites

DRDY set equal to one.

8.18.8 Description

This command can be used to lock the media, if Media Status Notification is disabled. If Media Status
Notification is enabled, this command will return good status (no ERR bit in the Status register) and perform
no action.

If the media is unlocked and media is present, the media shall be set to the LOCKED state and no Error
register bit shall be set to one. The device keeps track of only one level of media lock. Subsequent MEDIA
LOCK commands, while the media is in the LOCKED state, do not set additional levels of media locks.

If the media is locked, the status returned shall indicate whether a media change request has been detected
by the device. If a media change request has been detected, the MCR bit in the Error register and the ERR
bit in the Status register shall be set to one.

When media is in the LOCKED state, the device shall respond to the media change request button, by
setting the MCR bit in the Error register and the ERR bit in the Status register to one, until the media
LOCKED condition is cleared.

Page 114
 T13/1153D revision 18

8.19 MEDIA UNLOCK

8.19.1 Command code

DFh

8.19.2 Feature set

Removable Media Status Notification feature set

− Optional for devices not implementing the PACKET command feature set and implementing the
Removable Media Status Notification feature set.
− Prohibited for devices implementing the PACKET command feature set.

Removable Media feature set

− Mandatory for devices not implementing the PACKET command feature set and implementing
the Removable Media feature set.
− Prohibited for devices implementing the PACKET command feature set.
8.19.3 Protocol

Non-data command (see 9.9).

8.19.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command DFh

Device/Head register -
DEV shall indicate the selected device.

8.19.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 115
T13/1153D revision 18

8.19.6 Error outputs

If the device does not support this command, the device shall return command aborted.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT NM obs
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if device does not support this command. ABRT may be set to one if the
device is not able to complete the action requested by the command.
NM (No Media) shall be set to one if no media is present in the device.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.19.7 Prerequisites

DRDY set equal to one.

8.19.8 Description

This command can be used to unlock the device, if Media Status Notification is disabled. If Media Status
Notification is enabled, this command will return good status (no ERR bit in the Status register) and perform
no action.

If the media is present, the media shall be set to the UNLOCKED state and no Error register bit shall be set
to one. The device keeps track of only one level of media lock. A single MEDIA UNLOCK command unlocks
the media.

If a media change request has been detected by the device prior to the issuance of this command, the
media shall be ejected at MEDIA UNLOCK command completion.

Page 116
 T13/1153D revision 18

8.20 NOP

8.20.1 Command code

00h

8.20.2 Feature set

General feature set

− Optional for devices not implementing the PACKET Command feature set.
− Mandatory for devices implementing the PACKET Command feature set.
− Mandatory for devices implementing the Overlapped feature set.

8.20.3 Protocol

Non-data (see 9.9).

8.20.4 Inputs

Register 7 6 5 4 3 2 1 0
Features Subcommand code
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command 00h

Features register -

Subcommand code Description Action

00h NOP Return command aborted and abort any
outstanding queue.
01h NOP Auto Poll Return command aborted and do not abort any
outstanding queue.
02h-FFh Reserved Return command aborted and do not abort any
outstanding queue.

Device/Head register -
DEV shall indicate the selected device.

8.20.5 Normal outputs

This command always fails with an error.

8.20.6 Error outputs

The Command Block registers, other than the Error and Status registers, are not changed by this command.
This command always fails with the device returning command aborted.

Page 117
T13/1153D revision 18

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count Initial value
Sector Number Initial value
Cylinder Low Initial value
Cylinder High Initial value
Device/Head Initial value
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one.
Sector Count, Sector Number, Cylinder Low, Cylinder High, Device/Head -
value set by host is not changed.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one.

8.20.7 Prerequisites

DRDY set equal to one.

8.20.8 Description

The device shall respond with command aborted. For devices implementing the Overlapped feature set,
subcommand code 00h in the Features register shall abort any outstanding queue. Subcommand codes 01h
through FFh in the Features register shall not affect the status of any outstanding queue.

Page 118
 T13/1153D revision 18

8.21 PACKET

8.21.1 Command code

A0h

8.21.2 Feature set

PACKET Command feature set

− Use prohibited for devices not implementing the PACKET Command feature set.
− Mandatory for devices implementing the PACKET Command feature set.

8.21.3 Protocol

Packet (see 9.11).

8.21.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na na na na na na OVL DMA
Sector Count Tag na
Sector Number na
Byte count low Byte count limit (7-0)
(Cylinder Low)
Byte count high Byte count limit (15-8)
(Cylinder High)
Device/Head obs na obs DEV na na na na
Command A0h

Features register -
OVL - This bit is set to one to inform the device that the PACKET command is to be overlapped.
DMA - This bit is set to one to inform the device that the data transfer (not the command packet
transfer) associated with this command is via DMA or Ultra DMA mode.
Sector Count register -
Tag - If the device supports command queuing, this field contains the command Tag for the
command being delivered. If queuing is not supported, this field is not applicable.
Byte count low and Byte count high registers -
These registers are written by the host with the maximum byte count that is to be transferred in any
single DRQ assertion for PIO transfers. The byte count does not apply to the command PACKET
transfer. If the PACKET command does not transfer data, the byte count is ignored.

If the PACKET command results in a data transfer:

1) the host shall not set the byte count limit to zero. If the host sets the byte count limit to zero
the device shall return command aborted;
2) the value set into the byte count limit shall be even if the total requested data transfer length
is greater than the byte count limit;
3) the value set into the byte count limit may be odd if the total requested data transfer length
is equal to or less than the byte count limit;
4) the value FFFFh is interpreted by the device as though it were FFFEh.
Device/Head register -
DEV shall indicate the selected device.

Page 119
T13/1153D revision 18

8.21.5 Normal outputs

8.21.5.1 Awaiting command

When the device is ready to accept the command packet from the host the register content shall be as
shown below.

Register 7 6 5 4 3 2 1 0
Error na
Interrupt reason Tag REL I/O C/D
(Sector Count)
Sector Number na
Byte count low Byte count (7:0)
(Cylinder Low)
Byte count high Byte count (15:8)
(Cylinder High)
Device/Head obs na obs DEV na na na na
Status BSY DRDY DMRD SERV DRQ na na CHK

Byte count High/Low - shall reflect the value set by the host when the command was issued.
Interrupt reason register -
Tag - If the device supports command queuing and overlap is enabled, this field contains the
command Tag for the command. If the device does not support command queuing or overlap is
disabled, this field is not applicable.
REL - Shall be cleared to zero.
I/O - Shall be cleared to zero indicating transfer to the device.
C/D - Shall be set to one indicating the transfer of a command packet.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY - Shall be cleared to zero.
DRDY - na.
DMRD (DMA ready) - Shall be cleared to zero.
SERV (Service) - Shall be set to one if another command is ready to be serviced. If overlap is not
supported, this bit is command specific.
DRQ - Shall be set to one.
CHK - Shall be cleared to zero.

8.21.5.2 Data transmission

When the device is ready to transfer data requested by a data transfer command, the device sets the
following register content to initiate the data transfer.

Register 7 6 5 4 3 2 1 0
Error na
Interrupt reason Tag REL I/O C/D
(Sector Count)
Sector Number na
Byte count low Byte count (7:0)
(Cylinder Low)
Byte count high Byte count (15:8)
(Cylinder High)
Device/Head obs na obs DEV na na na na
Status BSY DRDY DMRD SERV DRQ na na CHK

Byte count High/Low - If the transfer is to be in PIO mode, the byte count of the data to be transferred for
this DRQ assertion shall be presented.

Page 120
 T13/1153D revision 18

Valid byte count values are as follows:

1) the byte count shall be less than or equal to the byte count limit value from the host;
2) the byte count shall not be zero;
3) the byte count shall be less than or equal to FFFEh;
4) the byte count shall be even except for the last transfer of a command;
5) if the byte count is odd, the last valid byte transferred is on DD[7:0] and the data on
DD[15:8] is a pad byte of undefined value;
6) if the last transfer of a command has a pad byte, the byte count shall be odd.
Interrupt reason register -
Tag - If the device supports command queuing and overlap is enabled, this field contains the
command Tag for the command. If the device does not support command queuing or overlap is
disabled, this field is not applicable.
REL - Shall be cleared to zero.
I/O - Shall be cleared to zero if the transfer is to the device. Shall be set to one if the transfer is to
the host.
C/D - Shall be cleared to zero indicating the transfer of data.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY - Shall be cleared to zero.
DRDY - na.
DMRD (DMA ready) - Shall be set to one if the transfer is to be a DMA or Ultra DMA transfer and
the device supports overlap DMA.
SERV (Service) - Shall be set to one if another command is ready to be serviced. If overlap is not
supported, this bit is command specific.
DRQ - Shall be set to one.
CHK - Shall be cleared to zero.

8.21.5.3 Bus release (overlap feature set only)

After receiving the command packet, the device sets BSY to one and clears DRQ to zero. If the command
packet requires a data transfer, the OVL bit is set to one, and the device is not prepared to immediately
transfer data, the device may perform a bus release by placing the following register content. If the
command packet requires a data transfer, the OVL bit is set to one, and the Release interrupt is enabled,
the device shall perform a bus release by setting the register content as follows.

Register 7 6 5 4 3 2 1 0
Error na
Interrupt reason Tag REL I/O C/D
(Sector Count)
Sector Number na
Byte count low na
(Cylinder Low)
Byte count high na
(Cylinder High)
Device/Head obs na obs DEV na na na na
Status BSY DRDY DMRD SERV DRQ na na CHK

Byte count High/Low - na.

Interrupt reason register -
Tag - If the device supports command queuing and overlap is enabled, this field contains the
command Tag for the command. If the device does not support command queuing or overlap is
disabled, this field is not applicable.
REL - Shall be set to one.
I/O - Shall be cleared to zero.
C/D - Shall be cleared to zero.

Page 121
T13/1153D revision 18

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY - Shall be cleared to zero indicating bus release.
DRDY - na.
DMRD (DMA ready) - Shall be cleared to zero.
SERV (Service) - Shall be set to one if another command is ready to be serviced. If overlap is not
supported, this bit is command specific.
DRQ - Shall cleared to zero.
CHK - Shall be cleared to zero.

8.21.5.4 Service request (overlap feature set only)

When the device is ready to transfer data or complete a command after the command has performed a bus
release, the device shall set the SERV bit and not change the state of any other register bit (see 6.6).

8.21.5.5 Successful command completion

When the device has command completion without error, the device sets the following register content.

Register 7 6 5 4 3 2 1 0
Error na
Interrupt reason Tag REL I/O C/D
(Sector Count)
Sector Number na
Byte count low na
(Cylinder Low)
Byte count high na
(Cylinder High)
Device/Head obs na obs DEV na na na na
Status BSY DRDY DMRD SERV DRQ na na CHK

Byte count High/Low -na.

Interrupt reason register -
Tag - If the device supports command queuing and overlap is enabled, this field contains the
command Tag for the command. If the device does not support command queuing or
overlap is disabled, this field is not applicable.
REL - Shall be cleared to zero.
I/O - Shall be set to one.
C/D - Shall be set to one.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY - Shall be cleared to zero indicating command completion.
DRDY - Shall be set to one.
DMRD (DMA ready) - na.
SERV (Service) - Shall be set to one if another command is ready to be serviced. If overlap is not
supported, this bit is command specific.
DRQ - Shall be cleared to zero.
CHK - Shall be cleared to zero.

8.21.6 Error outputs

The device shall not terminate the PACKET command with an error before the last byte of the command
packet has been written (see 9.11).

Page 122
 T13/1153D revision 18

Register 7 6 5 4 3 2 1 0
Error Sense key na ABRT EOM ILI
Interrupt reason Tag REL I/O C/D
(Sector Count)
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF SERV DRQ na na CHK

Error register -
Sense Key is a command packet set specific error indication.
ABRT shall be set to one if the requested command has been command aborted because the
command code or a command parameter is invalid. ABRT may be set to one if the device is
not able to complete the action requested by the command.
EOM - the meaning of this bit is command set specific. See the appropriate command set standard
for its definition.
ILI - the meaning of this bit is command set specific. See the appropriate command set standard for
its definition.
Interrupt reason register -
Tag - If the device supports command queuing and overlap is enabled, this field contains the
command Tag for the command. If the device does not support command queuing or
overlap is disabled, this field is not applicable.
REL - Shall be cleared to zero.
I/O - Shall be set to one.
C/D - Shall be set to one.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
SERV (Service) - Shall be set to one if another command is ready to be serviced. If overlap is not
supported, this bit is command specific.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
CHK shall be set to one if an Error register sense key or code bit is set.

8.21.7 Prerequisites

This command shall be accepted regardless of the state of DRDY.

8.21.8 Description

The PACKET command is used to transfer a device command via a command packet. If the native form of
the encapsulated command is shorter than the packet size reported in bits 1 and 0 of word 0 of the
IDENTIFY PACKET DEVICE response, the encapsulated command shall begin at byte 0 of the packet.
Packet bytes beyond the end of the encapsulated command are reserved.

If the device supports overlap, the OVL bit is set to one in the Features register and the Release interrupt
has been disabled via the SET FEATURES command, the device may or may not perform a bus release. If
the device is ready for the data transfer, it may begin the transfer immediately as described in the non-
overlapped protocol (see 9.11). If the data is not ready, the device may perform a bus release and complete
the transfer after the execution of a SERVICE command.

Page 123
T13/1153D revision 18

8.22 READ BUFFER

8.22.1 Command code

E4h

8.22.2 Feature set

General feature set

− Optional for devices not implementing the PACKET Command feature set.
− Use prohibited for devices implementing the PACKET Command feature set.

8.22.3 Protocol

PIO data in (see 9.7).

8.22.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command E4h

Device/Head register -
DEV shall indicate the selected device.

8.22.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.22.6 Error outputs

The device shall return command aborted if the command is not supported.

Page 124
 T13/1153D revision 18

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if this command is not supported. ABRT may be set to one if the device is
not able to complete the action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.22.7 Prerequisites

DRDY set equal to one. A WRITE BUFFER command shall immediately proceed a READ BUFFER
command.

8.22.8 Description

The READ BUFFER command enables the host to read the current contents of the device’s sector buffer.

The READ BUFFER and WRITE BUFFER commands shall be synchronized such that sequential WRITE
BUFFER and READ BUFFER commands access the same 512 bytes within the buffer.

Page 125
T13/1153D revision 18

8.23 READ DMA

8.23.1 Command code

C8h or C9h

NOTE − The host should not use the C9h value.

8.23.2 Feature set

General feature set

− Mandatory for devices not implementing the PACKET Command feature set.
− Use prohibited for devices implementing the PACKET Command feature set.

8.23.3 Protocol

DMA (see 9.10).

8.23.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count Sector count
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs LBA obs DEV Head number or LBA
Command C8h or C9h

Sector Count -
number of sectors to be transferred. A value of 00h indicates that 256 sectors are to be transferred.
Sector Number -
starting sector number or LBA address bits (7:0).
Cylinder Low -
starting cylinder number bits (7:0) or LBA address bits (15:8).
Cylinder High -
starting cylinder number bits (15:8) or LBA address bits (23:16).
Device/Head -
bit 6 set to one if LBA address, cleared to zero if CHS address.
DEV shall indicate the selected device.
bits (3:0) starting head number or LBA address bits (27:24).

8.23.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Page 126
 T13/1153D revision 18

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.23.6 Error outputs

An unrecoverable error encountered during the execution of this command results in the termination of the
command. The Command Block registers contain the address of the sector where the first unrecoverable
error occurred. The amount of data transferred is indeterminate.

Register 7 6 5 4 3 2 1 0
Error ICRC UNC MC IDNF MCR ABRT NM obs
Sector Count na
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs na obs DEV Head number or LBA
Status BSY DRDY DF na DRQ na na ERR

Error register -
ICRC shall be set to one if an interface CRC error has occurred during an Ultra DMA data transfer.
The content of this bit is not applicable for Multiword DMA transfers.
UNC shall be set to one if data is uncorrectable
MC shall be set to one if the media in a removable media device changed since the issuance of the
last command. The device shall clear its internal media change detected state.
IDNF shall be set to one if a user-accessible address could not be found and after an unsuccessful
INITIALIZE DEVICE PARAMETERS command until a valid CHS translation is established
(see 8.16.8). IDNF shall be set to one if an address outside of the range of user-accessible
addresses is requested if command aborted is not returned.
MCR shall be set to one if a media change request has been detected by a removable media
device. This bit is only cleared by a GET MEDIA STATUS or a media access command.
ABRT shall be set to one if this command is not supported or if an error, including an ICRC error,
has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is
not able to complete the action requested by the command. ABRT shall be set to one if an
address outside of the range of user-accessible addresses is requested if IDNF is not set to
one.
NM shall be set to one if no media is present in a removable media device.
Sector Number, Cylinder Low, Cylinder High, Device/Head -
shall be written with the address of first unrecoverable error.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.23.7 Prerequisites

DRDY set equal to one. The host shall initialize the DMA channel.

Page 127
T13/1153D revision 18

8.23.8 Description

The READ DMA command allows the host to read data using the DMA data transfer protocol.

Page 128
 T13/1153D revision 18

8.24 READ DMA QUEUED

8.24.1 Command code

C7h

8.24.2 Feature set

Overlapped feature set

− Mandatory for devices implementing the Overlapped feature set but not implementing the PACKET
command feature set.
− Use prohibited for devices implementing the PACKET command feature set.

8.24.3 Protocol

DMA QUEUED (see 9.12).

8.24.4 Inputs

Register 7 6 5 4 3 2 1 0
Features Sector Count
Sector Count Tag na na na
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs LBA obs DEV Head number or LBA
Command C7h

Features -
number of sectors to be transferred. A value of 00h indicates that 256 sectors are to be transferred.
Sector count -
if the device supports command queuing, bits (7:3) contain the Tag for the command being
delivered. If queuing is not supported, this field is not applicable.
Sector number -
starting sector number or LBA address bits (7:0).
Cylinder Low -
starting cylinder number bits (7:0) or LBA address bits (15:8).
Cylinder High -
starting cylinder number bits (15:8) or LBA address bits (23:16).
Device/Head -
bit 6 set to one if LBA address, cleared to zero if CHS address.
DEV shall indicate the selected device.
bits (3:0) starting head number or LBA address bits (27:24).

8.24.5 Normal outputs

8.24.5.1 Release

If the device performs a bus release before transferring data for this command, the register content upon
performing a bus release shall be as shown below.

Page 129
T13/1153D revision 18

Register 7 6 5 4 3 2 1 0
Error na
Sector Count Tag REL I/O C/D
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF SERV DRQ na na ERR

Sector Count register -

Tag - If the device supports command queuing, this field shall contain the Tag of the command
being bus released. If the device does not support command queuing, this field shall be
zeros.
REL bit shall be set to one indicating that the device has bus released an overlap command.
I/O shall be zero.
C/D shall be zero.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating bus release.
DRDY shall be set to one.
SERV (Service) shall be cleared to zero when no other queued command is ready for service. It
shall be set to one when another queued command is ready for service. It shall be set to
one when the device has prepared this command for service.
DF (Device Fault) shall be cleared to zero
DRQ bit shall be cleared to zero.
ERR bit shall be cleared to zero.

8.24.5.2 Command completion

When the transfer of all requested data has occurred without error, the register content shall be as shown
below.

Register 7 6 5 4 3 2 1 0
Error 00h
Sector Count Tag REL I/O C/D
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF SERV DRQ na na ERR

Sector Count register -

Tag - If the device supports command queuing, this field shall contain the Tag of the completed
command. If the device does not support command queuing, this field shall be zeros.
REL shall be cleared to zero.
I/O shall be set to one.
C/D shall be set to one.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
SERV (Service) shall be cleared to zero when no other queued command is ready for service. It
shall be set to one when another queued command is ready for service.
DF (Device Fault) shall be cleared to zero.

Page 130
 T13/1153D revision 18

DRQ bit shall be cleared to zero.

ERR bit shall be cleared to zero.

8.24.6 Error outputs

The Sector Count register contains the Tag for this command if the device supports command queuing. The
device shall return command aborted if the command is not supported or if the device has not had
overlapped interrupt enabled. The device shall return command aborted if the device supports command
queuing and the Tag is invalid. An unrecoverable error encountered during the execution of this command
results in the termination of the command and the Command Block registers contain the sector where the
first unrecoverable error occurred. If a queue existed, the unrecoverable error shall cause the queue to
abort.

Register 7 6 5 4 3 2 1 0
Error ICRC UNC MC IDNF MCR ABRT NM obs
Sector Count Tag REL I/O C/D
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs na obs D Head number or LBA
Status BSY DRDY DF SERV DRQ na na ERR

Error register -
ICRC shall be set to one if an interface CRC error has occurred during an Ultra DMA data transfer.
The content of this bit is not applicable for Multiword DMA transfers.
UNC shall be set to one if data is uncorrectable.
MC shall be set to one if the media in a removable media device changed since the issuance of the
last command. The device shall clear its internal media change detected state.
IDNF shall be set to one if a user-accessible address could not be found and after an unsuccessful
INITIALIZE DEVICE PARAMETERS command until a valid CHS translation is established
(see 8.16.8). IDNF shall be set to one if an address outside of the range of user-accessible
addresses is requested if ABRT is not set to one.
MCR shall be set to one if a media change request has been detected by a removable media
device. This bit is only cleared by a GET MEDIA STATUS or a media access command.
ABRT shall be set to one if this command is not supported or if an error, including an ICRC error,
has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is
not able to complete the action requested by the command. ABRT shall be set to one if an
address outside of the range of user-accessible addresses is requested if IDNF is not set to
one.
NM shall be set to one if no media is present in a removable media device.
Sector Count register -
Tag - If the device supports command queuing, this field shall contain the Tag of the completed
command. If the device does not support command queuing, this field shall be zeros.
REL shall be cleared to zero.
I/O shall be set to one.
Bit 0 - C/D shall be set to one.
Sector Number, Cylinder Low, Cylinder High, Device/Head -
shall be written with the address of first unrecoverable error.
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
SERV (Service) shall be cleared to zero when no other queued command is ready for service. It
shall be set to one when another queued command is ready for service.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

Page 131
T13/1153D revision 18

8.24.7 Prerequisites
DRDY set to one. The host shall initialize the DMA channel.

8.24.8 Description
This command executes in a similar manner to a READ DMA command. The device may perform a bus
release or it may execute the data transfer without performing a bus release if the data is ready to transfer.

Page 132
 T13/1153D revision 18

8.25 READ MULTIPLE

8.25.1 Command code

C4h

8.25.2 Feature set

General feature set

− Mandatory for devices not implementing the PACKET Command feature set.
− Use prohibited for devices implementing the PACKET Command feature set.

8.25.3 Protocol

PIO data in (see 9.7).

8.25.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count Sector count
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs LBA obs DEV Head number or LBA
Command C4h

Sector Count -
number of sectors to be transferred. A value of 00h indicates that 256 sectors are to be transferred.
Sector Number -
starting sector number or LBA address bits (7:0).
Cylinder Low -
starting cylinder number bits (7:0) or LBA address bits (15:8).
Cylinder High -
starting cylinder number bits (15:8) or LBA address bits (23:16).
Device/Head -
bit 6 set to one if LBA address, cleared to zero if CHS address.
DEV shall indicate the selected device.
bits (3:0) starting head number or LBA address bits (27:24).

8.25.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.

Page 133
T13/1153D revision 18

DRDY shall be set to one.

DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.25.6 Error outputs

An unrecoverable error encountered during the execution of this command results in the termination of the
command. The Command Block registers contain the address of the sector where the first unrecoverable
error occurred. The amount of data transferred is indeterminate.

Register 7 6 5 4 3 2 1 0
Error na UNC MC IDNF MCR ABRT NM obs
Sector Count na
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs na obs DEV Head number or LBA
Status BSY DRDY DF na DRQ na na ERR

Error register -
UNC shall be set to one if data is uncorrectable.
MC shall be set to one if the media in a removable media device changed since the issuance of the
last command. The device shall clear its internal media change detected state.
IDNF shall be set to one if a user-accessible address could not be found and after an unsuccessful
INITIALIZE DEVICE PARAMETERS command until a valid CHS translation is established
(see 8.16.8). IDNF shall be set to one if an address outside of the range of user-accessible
addresses is requested if command aborted is not returned.
MCR shall be set to one if a media change request has been detected by a removable media
device. This bit is only cleared by a GET MEDIA STATUS or a media access command.
ABRT shall be set to one if this command is not supported or if an error, including an ICRC error,
has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is
not able to complete the action requested by the command. ABRT shall be set to one if an
address outside of the range of user-accessible addresses is requested if IDNF is not set to
one.
NM shall be set to one if no media is present in a removable media device.
Sector Number, Cylinder Low, Cylinder High, Device/Head -
shall be written with the address of first unrecoverable error.
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.25.7 Prerequisites

DRDY set equal to one. If bit 8 of IDENTIFY DEVICE word 59 is cleared to zero, a successful SET
MULTIPLE MODE command shall precede a READ MULTIPLE command.

8.25.8 Description

The READ MULTIPLE command performs similarly to the READ SECTOR(S) command. Interrupts are not
generated on every sector, but on the transfer of a block that contains the number of sectors defined by a
SET MULTIPLE MODE command or the default if no intervening SET MULTIPLE command has been
issued. Command execution is identical to the READ SECTOR(S) operation except that the number of

Page 134
 T13/1153D revision 18

sectors defined by a SET MULTIPLE MODE command are transferred without intervening interrupts. The
DRQ bit qualification of the transfer is required only at the start of the data block, not on each sector.

The block count of sectors to be transferred without intervening interrupts is programmed by the SET
MULTIPLE MODE command, that shall be executed prior to the READ MULTIPLE command. When the
READ MULTIPLE command is issued, the Sector Count register contains the number of sectors (not the
number of blocks or the block count) requested.

If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible
are transferred, followed by a final, partial block transfer. The partial block transfer shall be for n sectors,
where n = remainder (sector count/ block count).

If the READ MULTIPLE command is received when READ MULTIPLE commands are disabled, the READ
MULTIPLE operation shall be rejected with command aborted.

Device errors encountered during READ MULTIPLE commands are posted at the beginning of the block or
partial block transfer, but the DRQ bit is still set to one and the data transfer shall take place, including
transfer of corrupted data, if any. The contents of the Command Block Registers following the transfer of a
data block that had a sector in error are undefined. The host should retry the transfer as individual requests
to obtain valid error information.

Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All other
errors cause the command to stop after transfer of the block that contained the error.

Page 135
T13/1153D revision 18

8.26 READ NATIVE MAX ADDRESS

8.26.1 Command code

F8h

8.26.2 Feature set

Host Protected Area feature set.

− Mandatory when the Host Protected Area feature set is implemented.
− Use prohibited when Removable feature set is implemented.

8.26.3 Protocol

Non-data command (see 9.9).

8.26.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs LBA obs DEV na
Command F8h

Device/Head -
If LBA is set to one, the maximum address shall be reported as an LBA value.
If LBA is cleared to zero, the maximum address shall be reported as a CHS value.
DEV shall indicate the selected device.

8.26.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number Native max address sector number or LBA
Cylinder Low Native max address cylinder low or LBA
Cylinder High Native max address cylinder high or LBA
Device/Head obs na obs DEV Native max address head or
LBA
Status BSY DRDY DF na DRQ na na ERR

Sector Number -
maximum native sector number (IDENTIFY DEVICE word 6) or LBA bits (7:0) for native max
address on the device.
Cylinder Low -
maximum native cylinder number low or LBA bits (15:8) for native max address on the device.
Cylinder High -
maximum native cylinder number high or LBA bits (23:16) for native max address on device.
Device/Head -
maximum native head number (IDENTIFY DEVICE word 3 minus one) or LBA bits (27:24) for native
max address on the device.
DEV shall indicate the selected device.

Page 136
 T13/1153D revision 18

Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.26.6 Error outputs

If this command is not supported the device shall return command aborted. The device shall return
command aborted if a CHS address is requested and the device does not support a CHS translation.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY na na na na na ERR

Error register -
ABRT shall be set to one if this command is not supported. ABRT may be set to one if the device is
not able to complete the action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
ERR shall be set to one if an Error register bit is set to one.

8.26.7 Prerequisites

DRDY set equal to one.

8.26.8 Description

This command returns the native maximum address. The native maximum address is the highest address
accepted by the device in the factory default condition. The native maximum address is the maximum
address that is valid when using the SET MAX ADDRESS command.

Page 137
T13/1153D revision 18

8.27 READ SECTOR(S)

8.27.1 Command code

20h or 21h

NOTE − The host should not use the 21h value.

8.27.2 Feature set

General feature set

− Mandatory for all devices.
− PACKET Command feature set devices (see 8.27.5.2).

8.27.3 Protocol

PIO data in (see 9.7).

8.27.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count Sector count
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs LBA obs DEV Head number or LBA
Command 20h or 21h

Sector Count -
number of sectors to be transferred. A value of 00h indicates that 256 sectors are to be transferred.
Sector Number -
starting sector number or LBA address bits (7:0).
Cylinder Low -
starting cylinder number bits (7:0) or LBA address bits (15:8).
Cylinder High -
starting cylinder number bits (15:8) or LBA address bits (23:16).
Device/Head -
bit 6 set to one if LBA address, cleared to zero if CHS address.
DEV shall indicate the selected device.
bits (3:0) starting head number or LBA address bits (27:24).

Page 138
 T13/1153D revision 18

8.27.5 Outputs

8.27.5.1 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.27.5.2 Outputs for PACKET Command feature set devices

In response to this command, devices that implement the PACKET Command feature set shall post
command aborted and place the PACKET Command feature set signature in the Cylinder High and the
Cylinder Low register (see 9.1).

8.27.6 Error outputs

An unrecoverable error encountered during the execution of this command results in the termination of the
command. The Command Block registers contain the address of the sector where the first unrecoverable
error occurred. The amount of data transferred is indeterminate.

Register 7 6 5 4 3 2 1 0
Error na UNC MC IDNF MCR ABRT NM obs
Sector Count na
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs na obs DEV Head number or LBA
Status BSY DRDY DF na DRQ na na ERR

Error register -
UNC shall be set to one if data is uncorrectable.
MC shall be set to one if the media in a removable media device changed since the issuance of the
last command. The device shall clear its internal media change detected state.
IDNF shall be set to one if a user-accessible address could not be found and after an unsuccessful
INITIALIZE DEVICE PARAMETERS command until a valid CHS translation is established
(see 8.16.8). IDNF shall be set to one if an address outside of the range of user-accessible
addresses is requested if command aborted is not returned.
MCR shall be set to one if a media change request has been detected by a removable media
device. This bit is only cleared by a GET MEDIA STATUS or a media access command.
ABRT shall be set to one if this command is not supported or if an error, including an ICRC error,
has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is
not able to complete the action requested by the command. ABRT shall be set to one if an

Page 139
T13/1153D revision 18

address outside of the range of user-accessible addresses is requested if IDNF is not set to
one.
NM shall be set to one if no media is present in a removable media device.
Sector Number, Cylinder Low, Cylinder High, Device/Head -
shall be written with the address of first unrecoverable error.
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.27.7 Prerequisites

DRDY set equal to one.

8.27.8 Description

This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0
requests 256 sectors. The transfer shall begin at the sector specified in the Sector Number register.

The DRQ bit is always set to one prior to data transfer regardless of the presence or absence of an error
condition.

Page 140
 T13/1153D revision 18

8.28 READ VERIFY SECTOR(S)

8.28.1 Command code

40h or 41h

NOTE − The host should not use the 41h value.

8.28.2 Feature set

General feature set

− Mandatory for all devices not implementing the PACKET Command feature set.
− Use prohibited for devices implementing the PACKET Command feature set.

8.28.3 Protocol

Non-data (see 9.9).

8.28.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count Sector count
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs LBA obs DEV Head number or LBA
Command 40h or 41h

Sector Count -
number of sectors to be transferred. A value of 00h indicates that 256 sectors are to be transferred.
Sector Number -
starting sector number or LBA address bits (7:0).
Cylinder Low -
starting cylinder number bits (7:0) or LBA address bits (15:8).
Cylinder High -
starting cylinder number bits (15:8) or LBA address bits (23:16).
Device/Head -
bit 6 set to one if LBA address, cleared to zero if CHS address.
DEV shall indicate the selected device.
bits (3:0) starting head number or LBA address bits (27:24).

8.28.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Page 141
T13/1153D revision 18

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.28.6 Error outputs

An unrecoverable error encountered during the execution of this command results in the termination of the
command. The Command Block registers contain the address of the sector where the first unrecoverable
error occurred.

Register 7 6 5 4 3 2 1 0
Error na UNC MC IDNF MCR ABRT NM obs
Sector Count na
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs na obs DEV Head number or LBA
Status BSY DRDY DF na DRQ na na ERR

Error register -
UNC shall be set to one if data is uncorrectable.
MC shall be set to one if the media in a removable media device changed since the issuance of the
last command. The device shall clear its internal media change detected state.
IDNF shall be set to one if a user-accessible address could not be found and after an unsuccessful
INITIALIZE DEVICE PARAMETERS command until a valid CHS translation is established
(see 8.16.8). IDNF shall be set to one if an address outside of the range of user-accessible
addresses is requested if command aborted is not returned.
MCR shall be set to one if a media change request has been detected by a removable media
device. This bit is only cleared by a GET MEDIA STATUS or a media access command.
ABRT shall be set to one if this command is not supported or if an error, including an ICRC error,
has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is
not able to complete the action requested by the command. ABRT shall be set to one if an
address outside of the range of user-accessible addresses is requested if IDNF is not set to
one.
NM shall be set to one if no media is present in a removable media device.
Sector Number, Cylinder Low, Cylinder High, Device/Head -
shall be written with the address of first unrecoverable error.
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.28.7 Prerequisites

DRDY set equal to one.

8.28.8 Description

Page 142
 T13/1153D revision 18

This command is identical to the READ SECTOR(S) command, except that the DRQ bit is never set to one,
and no data is transferred to the host.

Page 143
T13/1153D revision 18

8.29 SECURITY DISABLE PASSWORD

8.29.1 Command code

F6h

8.29.2 Feature set

Security Mode feature set.

− Mandatory when the Security Mode feature set is implemented.

8.29.3 Protocol

PIO data out (see 9.8).

8.29.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command F6h

Device/Head register -
DEV shall indicate the selected device.

8.29.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.29.6 Error outputs

The device shall return command aborted if the command is not supported, the device is in Locked mode,
or the device is in Frozen mode.

Page 144
 T13/1153D revision 18

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if this command is not supported. ABRT may be set to one if the device is
not able to complete the action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.29.7 Prerequisites

DRDY set equal to one. Device shall be in Unlocked mode.

8.29.8 Description

The SECURITY DISABLE PASSWORD command requests a transfer of a single sector of data from the
host. Table 15 defines the content of this sector of information. If the password selected by word 0 matches
the password previously saved by the device, the device disables the Lock mode. This command does not
change the Master password that may be reactivated later by setting a User password (see 6.10).

Table 15 − Security password content

Word Content
0 Control word
Bit 0 Identifier 0=compare User password
1=compare Master password
Bit 1-15 Reserved
1-16 Password (32 bytes)
17-255 Reserved

Page 145
T13/1153D revision 18

8.30 SECURITY ERASE PREPARE

8.30.1 Command code

F3h

8.30.2 Feature set

Security Mode feature set.

− Mandatory when the Security Mode feature set is implemented.

8.30.3 Protocol

Non-data (see 9.9).

8.30.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command F3h

Device/Head register -
DEV shall indicate the selected device.

8.30.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.30.6 Error outputs

The device shall return command aborted if the command is not supported or the device is in Frozen mode.

Page 146
 T13/1153D revision 18

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if this command is not supported or device is in Frozen mode. ABRT may
be set to one if the device is not able to complete the action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.30.7 Prerequisites

DRDY set equal to one.

8.30.8 Description

The SECURITY ERASE PREPARE command shall be issued immediately before the SECURITY ERASE
UNIT command to enable device erasing and unlocking. This command prevents accidental erase of the
device.

Page 147
T13/1153D revision 18

8.31 SECURITY ERASE UNIT

8.31.1 Command code

F4h

8.31.2 Feature set

Security Mode feature set.

− Mandatory when the Security Mode feature set is implemented.

8.31.3 Protocol

PIO data out (see 9.8).

8.31.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command F4h

Device/Head register -
DEV shall indicate the selected device.

8.31.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 148
 T13/1153D revision 18

8.31.6 Error outputs

The device shall return command aborted if the command is not supported, the device is in Frozen mode,
not preceded by a SECURITY ERASE PREPARE command, or if the data area is not successfully
overwritten.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if this command is not supported, device is in Frozen mode, not preceded
by a SECURITY ERASE PREPARE command, or if the data area is not successfully
overwritten. ABRT may be set to one if the device is not able to complete the action
requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.31.7 Prerequisites

DRDY set equal to one. This command shall be immediately preceded by a SECURITY ERASE PREPARE
command.

8.31.8 Description

This command requests transfer of a single sector of data from the host. Table 16 defines the content of this
sector of information. If the password does not match the password previously saved by the device, the
device rejects the command with command aborted.

The SECURITY ERASE PREPARE command shall be completed immediately prior to the SECURITY
ERASE UNIT command. If the device receives a SECURITY ERASE UNIT command without an
immediately prior SECURITY ERASE PREPARE command, the device command aborts the SECURITY
ERASE UNIT command.

When normal erase mode is selected, the SECURITY ERASE UNIT command writes binary zeroes to all
user data areas. The enhanced erase mode is optional. When enhanced erase mode is selected, the device
writes predetermined data patterns to all user data areas. In enhanced mode, all previously written user data
is overwritten, including sectors that are no longer in use due to reallocation.

This command disables the device Lock mode, however, the Master password is still stored internally within
the device and may be reactivated later when a new User password is set.

Page 149
T13/1153D revision 18

Table 16 − SECURITY ERASE UNIT password

Word Content
0 Control word
Bit 0 Identifier 0=compare User password
1=compare Master password
Bit 1 Erase mode 0=Normal erase
1=Enhanced erase
Bit 2-15 Reserved
1-16 Password (32 bytes)
17-255 Reserved

Page 150
 T13/1153D revision 18

8.32 SECURITY FREEZE LOCK

8.32.1 Command code

F5h

8.32.2 Feature set

Security Mode feature set.

− Mandatory when the Security Mode feature set is implemented.

8.32.3 Protocol

Non-data (see 9.9).

8.32.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command F5h

Device/Head register -
DEV shall indicate the selected device.

8.32.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.32.6 Error outputs

The device shall return command aborted if the command is not supported, or the device is in Locked
mode.

Page 151
T13/1153D revision 18

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if this command is not supported or device is in locked mode. ABRT may
be set to one if the device is not able to complete the action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.32.7 Prerequisites

DRDY set equal to one.

8.32.8 Description

The SECURITY FREEZE LOCK command sets the device to Frozen mode. After command completion any
other commands that update the device Lock mode are rejected. Frozen mode is disabled by power off or
hardware reset. If SECURITY FREEZE LOCK is issued when the device is in Frozen mode, the command
executes and the device remains in Frozen mode.

Commands disabled by SECURITY FREEZE LOCK are:

− SECURITY SET PASSWORD
− SECURITY UNLOCK
− SECURITY DISABLE PASSWORD
− SECURITY ERASE UNIT

Page 152
 T13/1153D revision 18

8.33 SECURITY SET PASSWORD

8.33.1 Command code

F1h

8.33.2 Feature set

Security Mode feature set.

− Mandatory when the Security Mode feature set is implemented.

8.33.3 Protocol

PIO data out (see 9.8).

8.33.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command F1h

Device/Head register -
DEV shall indicate the selected device.

8.33.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.33.6 Error outputs

The device shall return command aborted if the command is not supported, the device is in Locked mode,
or the device is in Frozen mode.

Page 153
T13/1153D revision 18

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if this command is not supported, if device is in Frozen mode, or if device
is in locked mode. ABRT may be set to one if the device is not able to complete the action
requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.33.7 Prerequisites

DRDY set equal to one.

8.33.8 Description

This command requests a transfer of a single sector of data from the host. Table 17 defines the content of
this sector of information. The data transferred controls the function of this command. Table 18 defines the
interaction of the identifier and security level bits.

Table 17 − SECURITY SET PASSWORD data content

Word Content
0 Control word
Bit 0 Identifier 0=set User password
1=set Master password
Bits 1-7 Reserved
Bit 8 Security level 0=High
1=Maximum
Bits 9-15 Reserved
1-16 Password (32 bytes)
17-255 Reserved

Table 18 − Identifier and security level bit interaction

Identifier Level Command result
User High The password supplied with the command shall be saved as the new User password.
The Lock mode shall be enabled from the next power-on or hardware reset. The
device shall then be unlocked by either the User password or the previously set
Master password.
User Maximum The password supplied with the command shall be saved as the new User password.
The Lock mode shall be enabled from the next power-on or hardware reset. The
device shall then be unlocked by only the User password. The Master password
previously set is still stored in the device but shall not be used to unlock the device.
Master High or This combination shall set a Master password but shall not enable or disable the
Maximum Lock mode. The security level is not changed.

Page 154
 T13/1153D revision 18

8.34 SECURITY UNLOCK

8.34.1 Command code

F2h

8.34.2 Feature set

Security Mode feature set.

− Mandatory when the Security Mode feature set is implemented.

8.34.3 Protocol

PIO data out (see 9.8).

8.34.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command F2h

Device/Head register -
DEV shall indicate the selected device.

8.34.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.34.6 Error outputs

The device shall return command aborted if the command is not supported, or the device is in Frozen mode.

Page 155
T13/1153D revision 18

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if this command is not supported or if device is in Frozen mode. ABRT
may
be set to one if the device is not able to complete the action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.34.7 Prerequisites

DRDY set equal to one.

8.34.8 Description

This command requests transfer of a single sector of data from the host. Table 15 defines the content of this
sector of information.

If the Identifier bit is set to Master and the device is in high security level, then the password supplied shall
be compared with the stored Master password. If the device is in maximum security level then the unlock
shall be rejected.

If the Identifier bit is set to user then the device compares the supplied password with the stored User
password.

If the password compare fails then the device returns command aborted to the host and decrements the
unlock counter. This counter is initially set to five and is decremented for each password mismatch when
SECURITY UNLOCK is issued and the device is locked. When this counter reaches zero then SECURITY
UNLOCK and SECURITY ERASE UNIT commands are command aborted until a power-on reset or a
hardware reset. SECURITY UNLOCK commands issued when the device is unlocked have no effect on the
unlock counter.

Page 156
 T13/1153D revision 18

8.35 SEEK

8.35.1 Command code

70h

8.35.2 Feature set

General feature set

− Mandatory for devices not implementing the PACKET Command feature set.
− Use prohibited for devices implementing the PACKET Command feature set.

8.35.3 Protocol

Non-data (see 9.9).

8.35.4 Inputs

The Cylinder High register, the Cylinder Low register, the head portion of Device/Head register, and the
Sector Number register contain the address of a sector that the host may request in a subsequent
command.

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs LBA obs DEV Head number or LBA
Command 70h

Sector Number -
sector number or LBA address bits (7:0).
Cylinder Low -
cylinder number bits (7:0) or LBA address bits (15:8).
Cylinder High -
cylinder number bits (15:8) or LBA address bits (23:16).
Device/Head -
bit 6 set to one if LBA address, cleared to zero if CHS address.
DEV shall indicate the selected device.
bits (3:0) head number or LBA address bits (27:24).

8.35.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF DSC DRQ na na ERR

Page 157
T13/1153D revision 18

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DSC (Device Seek Complete) shall be set to one concurrent with or after the setting of DRDY to
one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.35.6 Error outputs

Some devices may not report IDNF because they do not range check the address values requested by the
host.

Register 7 6 5 4 3 2 1 0
Error na na MC IDNF MCR ABRT NM na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
MC shall be set to one if the media in a removable media device changed since the issuance of the
last command. The device shall clear its internal media change detected state.
IDNF shall be set to one if a user-accessible address could not be found and after an unsuccessful
INITIALIZE DEVICE PARAMETERS command until a valid CHS translation is established
(see 8.16.8). IDNF shall be set to one if an address outside of the range of user-accessible
addresses is requested if command aborted is not returned.
MCR shall be set to one if a media change request has been detected by a removable media
device. This bit is only cleared by a GET MEDIA STATUS or a media access command.
ABRT shall be set to one if this command is not supported or if an error, including an ICRC error,
has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is
not able to complete the action requested by the command. ABRT shall be set to one if an
address outside of the range of user-accessible addresses is requested if IDNF is not set to
one.
NM shall be set to one if no media is present in a removable media device.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.35.7 Prerequisites

DRDY set equal to one.

8.35.8 Description

Page 158
 T13/1153D revision 18

This command allows the host to provide advanced notification that particular data may be requested by the
host in a subsequent command. DSC shall be set to one concurrent with or after the setting of DRDY to one
when updating the Status register for this command.

Page 159
T13/1153D revision 18

8.36 SERVICE

8.36.1 Command code

A2h

8.36.2 Feature set

Overlap and Queued feature sets

− Mandatory when the PACKET, Overlapped feature set is implemented.

8.36.3 Protocol

PACKET or READ/WRITE DMA QUEUED (see 9.11 and 9.12).

8.36.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command A2h

Device/Head register -
DEV shall indicate the selected device.

8.36.5 Outputs

Outputs as a result of a SERVICE command are described in the command description for the command for
which SERVICE is being requested.

8.36.6 Prerequisites

The device shall have performed a bus release for a previous overlap PACKET, READ DMA QUEUED, or
WRITE DMA QUEUED command and shall have set the SERV bit to one to request the SERVICE
command be issued to continue data transfer and/or provide command status (see 8.37.15).

8.36.7 Description

The SERVICE command is used to provide data transfer and/or status of a command that was previously
bus released.

Page 160
 T13/1153D revision 18

8.37 SET FEATURES

8.37.1 Command code

EFh

8.37.2 Feature set

General feature set

− Mandatory for all devices.
− Set transfer mode subcommand is mandatory.
− Enable/disable write cache subcommands are mandatory when a write cache is implemented.
− Enable/Disable Media Status Notification sub commands are mandatory if the Removable
Media feature set is implemented.
− All other subcommands are optional.

8.37.3 Protocol

Non-data (see 9.9).

8.37.4 Inputs

Table 19 defines the value of the subcommand in the Feature register. Some subcommands use other
registers, such as the Sector Count register to pass additional information to the device.

Register 7 6 5 4 3 2 1 0
Features Subcommand code
Sector Count Subcommand specific
Sector Number Subcommand specific
Cylinder Low Subcommand specific
Cylinder High Subcommand specific
Device/Head obs na obs DEV na na na na
Command EFh

Device/Head register -
DEV shall indicate the selected device.

8.37.5 Normal outputs

See the subcommand descriptions.

8.37.6 Error outputs

If any subcommand input value is not supported or is invalid, the device shall return command aborted.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Page 161
T13/1153D revision 18

Error register -
ABRT shall be set to one if this subcommand is not supported or if value is invalid. ABRT may be
set
to one if the device is not able to complete the action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.37.7 Prerequisites

DRDY shall be set to one.

8.37.8 Description

This command is used by the host to establish parameters that affect the execution of certain device
features. Table 19 defines these features.

At power on, or after a hardware reset, the default setting of the functions specified by the subcommands
are vendor specific.

Page 162
 T13/1153D revision 18

Table 19 − SET FEATURES register definitions

Value
(see note)
01h Retired
02h Enable write cache
03h Set transfer mode based on value in Sector Count register. Table 20 defines
values.
04h Obsolete
05h Enable advanced power management
31h Disable Media Status Notification
33h Obsolete
44h Obsolete
54h Obsolete
55h Disable read look-ahead feature
5Dh Enable release interrupt
5Eh Enable SERVICE interrupt
66h Disable reverting to power on defaults
77h Obsolete
81h Retired
82h Disable write cache
84h Obsolete
85h Disable advanced power management
88h Obsolete
95h Enable Media Status Notification
99h Obsolete
9Ah Obsolete
AAh Enable read look-ahead feature
ABh Obsolete
BBh Obsolete
CCh Enable reverting to power on defaults
DDh Disable release interrupt
DEh Disable SERVICE interrupt
NOTE − All values not shown are reserved for future definition.

8.37.9 Enable/disable write cache

Subcommand codes 02h and 82h allow the host to enable or disable write cache in devices that implement
write cache. When the subcommand disable write cache is issued, the device shall initiate the sequence to
flush cache to non-volatile memory before command completion (see 8.10).

8.37.10 Set transfer mode

A host selects the transfer mechanism by Set Transfer Mode, subcommand code 03h, and specifying a
value in the Sector Count register. The upper 5 bits define the type of transfer and the low order 3 bits
encode the mode value. One PIO mode and one DMA mode shall be selected at all times. The host may
change the selected modes by the SET FEATURES command.

Page 163
T13/1153D revision 18

Table 20 − Transfer mode values

Mode Bits (7:3) Bits (2:0)
PIO default mode 00000b 000b
PIO default mode, disable IORDY 00000b 001b
PIO flow control transfer mode 00001b mode
Retired 00010b na
Multiword DMA mode 00100b mode
Ultra DMA mode 01000b mode
Reserved 10000b na
mode = transfer mode number

If a device supports this standard, and receives a SET FEATURES command with a Set Transfer Mode
parameter and a Sector Count register value of “00000000b”, it shall set its default PIO mode. If the value
is “00000001b” and the device supports disabling of IORDY, then the device shall set its default PIO mode
and disable IORDY. A device shall support all PIO modes below the highest mode supported, e.g., if PIO
mode 1 is supported PIO mode 0 shall be supported.

Support of IORDY is mandatory when PIO mode 3 or above is the current mode of operation.

Devices reporting support for Multi Word DMA mode 1 shall also support Multi Word DMA mode 0. A device
shall support all Multi Word DMA modes below the highest mode supported, e.g., if Multi Word DMA mode
1 is supported Multi Word DMA mode 0 shall be supported.

A device shall support all Ultra DMA modes below the highest mode supported, e.g., if Ultra DMA mode 1 is
supported Ultra DMA mode 0 shall be supported.

If an Ultra DMA mode is enabled any previously enabled Multi Word DMA mode shall be disabled by the
device. If a Multiword DMA mode is enabled any previously enabled Ultra DMA mode shall be disabled by
the device.

8.37.11 Enable/disable advanced power management

Subcommand code 05h allows the host to enable Advanced Power Management. To enable Advanced
Power Management, the host writes the Sector Count register with the desired advanced power
management level and then executes a SET FEATURES command with subcommand code 05h. The
power management level is a scale from the lowest power consumption setting of 01h to the maximum
performance level of FEh. Table 21 shows these values.

Table 21 − Advanced power management levels

Level Sector Count value
Maximum performance FEh
Intermediate power management levels without Standby 81h-FDh
Minimum power consumption without Standby 80h
Intermediate power management levels with Standby 02h-7Fh
Minimum power consumption with Standby 01h
Reserved FFh
Reserved 00h

Device performance may increase with increasing power management levels. Device power consumption
may increase with increasing power management levels. The power management levels may contain
discrete bands. For example, a device may implement one power management method from 80h to A0h
and a higher performance, higher power consumption method from level A1h to FEh. Advanced power
management levels 80h and higher do not permit the device to spin down to save power.

Subcommand code 85h disables Advanced Power Management. Subcommand 85h may not be
implemented on all devices that implement SET FEATURES subcommand 05h.

Page 164
 T13/1153D revision 18

8.37.12 Enable/disable Media Status Notification

Subcommand code 31h disables Media Status Notification and leaves the media in an unlocked state. If
Media Status Notification is disabled when this subcommand is received, the subcommand has no effect.

Subcommand code 95h enables Media Status Notification and clears any previous media lock state. This
subcommand returns the device capabilities for media eject, media lock, previous state of Media Status
Notification and the current version of Media Status Notification supported in the Cylinder Low and Cylinder
High registers as described below.

Register 7 6 5 4 3 2 1 0
Cylinder Low VER
Cylinder High r r r r r PEJ LOCK PENA

Cylinder Low register -

VER shall contain the Media Status Notification version supported by the device (currently 0x00h)
Cylinder High register -
PENA shall be set to one if Media Status Notification was enabled prior to the receipt of this
command,
LOCK shall be set to one if the device is capable of locking the media preventing manual ejection.
PEJ shall be set to one if the device has a power eject mechanism that is capable of physically
ejecting the media when a MEDIA EJECT command is sent to the device. This bit must be set
to zero if the device only unlocks the media when it receives a MEDIA EJECT command.
r (reserved) shall be cleared to zero.

8.37.13 Enable/disable read look-ahead

Subcommand codes AAh and 55h allow the host to request the device to enable or disable read look-ahead.
Error recovery performed by the device is vendor specific.

8.37.14 Enable/disable release interrupt

Subcommand codes 5Dh and DDh allow a host to enable or disable the asserting INTRQ if nIEN is cleared
to zero when a device releases the bus for an overlapped PACKET command.

8.37.15 Enable/disable SERVICE interrupt

Subcommand codes 5Eh and DEh allow a host to enable or disable the asserting of an interrupt when DRQ
is set to one in response to a SERVICE command.

8.37.16 Enable/disable reverting to defaults

Subcommand codes CCh and 66h allow the host to enable or disable the device from reverting to power on
default values. A setting of 66h allows settings that may have been modified since power on to remain at the
same setting after a software reset.

Page 165
T13/1153D revision 18

8.38 SET MAX ADDRESS

8.38.1 Command code

F9h

8.38.2 Feature set

Host Protected Area feature set.

− Mandatory when the Host Protected Area feature set is implemented.
− Use prohibited when the Removable feature set is implemented.

8.38.3 Protocol

Non-data command (see 9.9).

8.38.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na VV
Sector Number Native max address sector number or set max
LBA
Cylinder Low Set max cylinder low or LBA
Cylinder High Set max cylinder high or LBA
Device/Head obs LBA obs DEV Native max address
head number or set
max LBA
Command F9h

Sector Count -
V V (Value volatile). If bit 0 is set to one, the device shall preserve the maximum values over power-
up or hardware reset. If bit 0 is cleared to zero, the device shall revert to the most recent non-
volatile maximum address value setting over power-up or hardware reset.
Sector Number -
contains the native max address sector number (IDENTIFY DEVICE word 6) or LBA bits (7:0) value
to be set.
Cylinder Low -
contains the maximum cylinder low or LBA bits (15:8) value to be set.
Cylinder High -
contains the maximum cylinder high or LBA bits (23:16) value to be set.
Device/Head -
if LBA is set to one, the maximum address value is an LBA value.
If LBA is cleared to zero, the maximum address value is a CHS value.
DEV shall indicate the selected device.
Bits (3:0) contain the native max address head number (IDENTIFY DEVICE word 3 minus one) or
LBA bits (27:24) value to be set.

Page 166
 T13/1153D revision 18

8.38.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number Native max sector number or max LBA
Cylinder Low Max cylinder low or LBA
Cylinder High Max cylinder high or LBA
Device/Head obs na obs DEV Native max head or max LBA
Status BSY DRDY DF na DRQ na na ERR

Sector Number -
maximum native sector number or LBA bits (7:0) set on the device.
Cylinder Low -
maximum cylinder number low or LBA bits (15:8) set on the device.
Cylinder High -
maximum cylinder number high or LBA bits (23:16) set on device.
Device/Head -
DEV shall indicate the selected device.
maximum native head number or LBA bits (27:24) set on the device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.38.6 Error outputs

If this command is not supported or the maximum value to be set exceeds the capacity of the device, the
device shall return command aborted.

Register 7 6 5 4 3 2 1 0
Error na na na IDNF na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY na na na na na ERR

Error register -
ABRT shall be set to one if this command is not supported, maximum value requested exceeds the
device capacity, the set max cylinder number is greater than 16,383, or the command is not
immediately preceded by a READ NATIVE MAX ADDRESS command. ABRT may be set to
one if the device is not able to complete the action requested by the command.
IDNF shall be set to one if the command was the second non-volatile SET MAX ADDRESS
command after power on or hardware reset.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
ERR shall be set to one if an Error register bit is set to one.

Page 167
T13/1153D revision 18

8.38.7 Prerequisites

DRDY set equal to one. A successful READ NATIVE MAX ADDRESS command shall immediately precede
a SET MAX ADDRESS command.

8.38.8 Description

This command allows the host to redefine the maximum address of the user-accessible address space in
either LBA translation or the current CHS translation. The host may either set a new maximum cylinder
number for CHS translation or a new maximum LBA address for LBA translation. After a successful SET
MAX ADDRESS command using a new maximum cylinder number value the content of all IDENTIFY
DEVICE words shall comply with 6.2.1 in addition to the following:
1) The content of words 3, 6, 55, and 56 are unchanged
2) The content of word 1 shall equal (the new Set max cylinder number + 1) or 16,383, whichever is less
3) The content of words (61:60) shall equal [(the new content of word 1 as determined by the successful
SET MAX ADDRESS command) * (the content of word 3) * (the content of word 6)]
4) If the content of words (61:60) as determined by a successful SET MAX ADDRESS command is less
than 16,514,064, then the content of word 54 shall be equal to [(the content of words (61:60)) ÷ ((the
content of IDENTIFY DEVICE word 55) * (the content of word 56)] or 65,535, whichever is less
5) If the content of word (61:60) as determined by a successful SET MAX ADDRESS command is greater
than 16,514,064, then word 54 shall equal the whole number result of [[(16,514,064) ÷ [(the content of
word 55) * (the content of word 56)]] or 65,535 whichever is less) The content of words (58:57) shall
be equal to [(the new content of word 54 as determined by the successful SET MAX ADDRESS
command) * (the content of word 55) * (the content of word 56)]

After a successful SET MAX ADDRESS command using a new maximum LBA address the content of all
IDENTIFY DEVICE words shall comply with 6.2.1 in addition to the following:
− The content of words (61:60) shall be equal to the new Maximum LBA address + 1.
− If the content of words (61:60) is greater than 16,514,064 and if the device does not support CHS
addressing, then the content of words 1, 3, 6, 54, 55, 56, and (58:57) shall equal zero.

If the device supports CHS addressing:

− The content of words 3, 6, 55, and 56 are unchanged.
− If the new content of words (61:60) is less than 16,514,064, then the content of word 1 shall be equal to
[(the new content of words (61:60)) ÷ [(the content of word 3) * (the content of word 6)]] or 65,535,
whichever is less.
− If the new content of words (61:60) is greater than or equal to 16,514,064, then the content of word 1
shall be equal to 16,383.
− If the new content of words (61:60) is less than 16,514,064, then the content of word 54 shall be equal to
[(the new content of words (61:60)) ÷ [(the content of word 55) * (the content of word 56)]].
− If the new content of words (61:60) is greater than or equal to 16,514,064, then the content of word 54
shall be equal to 16,383.
− Words (58:57) shall be equal to [(the content of word 54) * (the content of word 55) * (the content of
word 56).

After successful command completion, all read and write access attempts to addresses greater than
specified by the successful SET MAX ADDRESS command shall be rejected with an “ID Not Found” error.

Hosts should not issue more than one non-volatile SET MAX ADDRESS command after a power on or
hardware reset. Devices shall report an “ID Not Found” error upon receiving a second non-volatile SET
MAX ADDRESS command after a power on or hardware reset.

The contents of IDENTIFY DEVICE words shall not be changed if a SET MAX ADDRESS command fails for
any reason.

Page 168
 T13/1153D revision 18

8.39 SET MULTIPLE MODE

8.39.1 Command code

C6h

8.39.2 Feature set

General feature set

Mandatory for devices not implementing the PACKET Command feature set.
Use prohibited for devices implementing the PACKET Command feature set.

8.39.3 Protocol

Non-data (see 9.9).

8.39.4 Inputs

The Sector Count register contains number of sectors per block to use on all following READ/WRITE
MULTIPLE commands. The host shall set Sector Count values equal to 2, 4, 8, 16, 32, 64, or 128.

Register 7 6 5 4 3 2 1 0
Features na
Sector Count Sectors per block
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command C6h

Device/Head register -
DEV shall indicate the selected device.

8.39.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 169
T13/1153D revision 18

8.39.6 Error outputs

If a block count is not supported, the device shall return command aborted.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if the block count is not supported. ABRT may be set to one if the device
is
not able to complete the action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.39.7 Prerequisites

DRDY set equal to one.

8.39.8 Description

This command establishes the block count for READ MULTIPLE and WRITE MULTIPLE commands.

Devices shall support the block size specified in the IDENTIFY DEVICE parameter word 47, bits 7 through
0, and may also support smaller values.

Upon receipt of the command, the device checks the Sector Count register. If the Sector Count register
contains a valid value and the block count is supported, the value is used for all subsequent READ
MULTIPLE and WRITE MULTIPLE commands and their execution is enabled.

Page 170
 T13/1153D revision 18

8.40 SLEEP

8.40.1 Command code

E6h

8.40.2 Feature set

Power Management feature set.

− Power Management feature set is mandatory when power management is not implemented by a
PACKET power management feature set.
− This command is mandatory when the Power Management feature set is implemented.

8.40.3 Protocol

Non-data command (see 9.9).

8.40.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command E6h

Device/Head register -
DEV shall indicate the selected device.

8.40.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 171
T13/1153D revision 18

8.40.6 Error outputs

The device shall return command aborted if the device does not support the Power Management feature
set.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if the device does not support the Power Management feature set. ABRT
may be set to one if the device is not able to complete the action requested by the
command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.40.7 Prerequisites

DRDY set equal to one.

8.40.8 Description

This command is the only way to cause the device to enter Sleep mode.

This command causes the device to set the BSY bit to one, prepare to enter Sleep mode, clear the BSY bit
to zero and assert INTRQ. The host shall read the Status register in order to clear the interrupt and allow
the device to enter Sleep mode. In Sleep mode, the device only responds to the assertion of the RESET
signal and the writing of the SRST bit in the Device Control register and releases its driven signal lines. The
host shall not attempt to access the Command Block registers while the device is in Sleep mode.

Because some host systems may not read the Status register and clear the interrupt, a device may
automatically release INTRQ and enter Sleep mode after a vendor specific time period of not less than 2 s.

The only way to recover from Sleep mode is with a software reset, a hardware reset, or a DEVICE RESET
command.

A device shall not power on in Sleep mode nor remain in Sleep mode following a reset sequence.

Page 172
 T13/1153D revision 18

8.41 SMART
Individual SMART commands are identified by the value placed in the Feature register. Table 22 shows
these Feature register values.

Table 22 − SMART Feature register values

Value Command
00h-CFh reserved
D0h SMART READ DATA
D1h obsolete
D2h SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE
D3h SMART SAVE ATTRIBUTE VALUES
D4h SMART EXECUTE OFF-LINE IMMEDIATE
D5h-D6h reserved
D7h obsolete
D8h SMART ENABLE OPERATIONS
D9h SMART DISABLE OPERATIONS
DAh SMART RETURN STATUS
DBh obsolete
DCh-DFh reserved
E0h-FFh vendor specific

Page 173
T13/1153D revision 18

8.41.1 SMART DISABLE OPERATIONS

8.41.1.1 Command code

B0h with a Feature register value of D9h.

8.41.1.2 Feature set

SMART feature set.

− Mandatory when the SMART feature set is implemented.
− Use prohibited when the PACKET Command feature set is implemented.

8.41.1.3 Protocol

Non-data command (see 9.9).

8.41.1.4 Inputs

The Features register shall be set to D9h. The Cylinder Low register shall be set to 4Fh. The Cylinder High
register shall be set to C2h.

Register 7 6 5 4 3 2 1 0
Features D9h
Sector Count na
Sector Number na
Cylinder Low 4Fh
Cylinder High C2h
Device/Head obs na obs DEV na na na na
Command B0h

Device/Head register -
DEV shall indicate the selected device.

8.41.1.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 174
 T13/1153D revision 18

8.41.1.6 Error outputs

If the device does not support this command, if SMART is not enabled, or if the values in the Features,
Cylinder Low, or Cylinder High registers are invalid, the device shall return command aborted.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if this command is not supported, if SMART is not enabled, or if input
register values are invalid. ABRT may be set to one if the device is not able to complete the
action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.41.1.7 Prerequisites

DRDY set equal to one. SMART enabled.

8.41.1.8 Description

This command disables all SMART capabilities within the device including any and all timer and event count
functions related exclusively to this feature. After receipt of this command the device shall disable all
SMART operations. SMART data shall no longer be monitored or saved by the device. The state of SMART
(either enabled or disabled) shall be preserved by the device across power cycles.

After receipt of this command by the device, all other SMART commands (including SMART DISABLE
OPERATIONS commands), with the exception of SMART ENABLE OPERATIONS, are disabled and invalid
and shall be command aborted by the device.

Page 175
T13/1153D revision 18

8.41.2 SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE

8.41.2.1 Command code

B0h with a Feature register value of D2h.

8.41.2.2 Feature set

SMART feature set.

− Mandatory when the SMART feature set is implemented.
− Use prohibited when the PACKET Command feature set is implemented.

8.41.2.3 Protocol

Non-data command (see 9.9).

8.41.2.4 Inputs

The Features register shall be set to D2h. The Cylinder Low register shall be set to 4Fh. The Cylinder High
register shall be set to C2h. The Sector Count register is set to 00h to disable attribute autosave and a value
of F1h is set to enable attribute autosave.

Register 7 6 5 4 3 2 1 0
Features D2h
Sector Count 00h or F1h
Sector Number na
Cylinder Low 4Fh
Cylinder High C2h
Device/Head obs na obs DEV na na na na
Command B0h

Device/Head register -
DEV shall indicate the selected device.

8.41.2.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 176
 T13/1153D revision 18

8.41.2.6 Error outputs

If the device does not support this command, if SMART is disabled, or if the values in the Features, Cylinder
Low, or Cylinder High registers are invalid, the device shall return command aborted.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if this command is not supported, if SMART is disabled, or if the input
register values are invalid. ABRT may be set to one if the device is not able to complete the
action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.41.2.7 Prerequisites

DRDY set equal to one. SMART enabled.

8.41.2.8 Description

This command enables and disables the optional attribute autosave feature of the device. Depending upon
the implementation, this command may either allow the device, after some vendor specified event, to
automatically save its updated attribute values to non-volatile memory; or this command may cause the
autosave feature to be disabled. The state of the attribute autosave feature (either enabled or disabled) shall
be preserved by the device across power cycles.

A value of zero written by the host into the device’s Sector Count register before issuing this command shall
cause this feature to be disabled. Disabling this feature does not preclude the device from saving SMART
data to non-volatile memory during some other normal operation such as during a power-on or power-off
sequence or during an error recovery sequence.

A value of F1h written by the host into the device’s Sector Count register before issuing this command shall
cause this feature to be enabled. Any other meaning of this value or any other non-zero value written by the
host into this register before issuing this command may differ from device to device. The meaning of any
non-zero value written to this register at this time shall be preserved by the device across power cycles.

If this command is not supported by the device, the device shall return command aborted upon receipt from
the host.

During execution of the autosave routine the device shall not set BSY to one nor clear DRDY to zero. If the
device receives a command from the host while executing its autosave routine it shall respond to the host
within two seconds.

Page 177
T13/1153D revision 18

8.41.3 SMART ENABLE OPERATIONS

8.41.3.1 Command code

B0h with a Feature register value of D8h.

8.41.3.2 Feature set

SMART feature set.

− Mandatory when the SMART feature set is implemented.
− Use prohibited when the PACKET Command feature set is implemented.

8.41.3.3 Protocol

Non-data command (see 9.9).

8.41.3.4 Inputs

The Features register shall be set to D8h. The Cylinder Low register shall be set to 4Fh. The Cylinder High
register shall be set to C2h.

Register 7 6 5 4 3 2 1 0
Features D8h
Sector Count na
Sector Number na
Cylinder Low 4Fh
Cylinder High C2h
Device/Head obs na obs DEV na na na na
Command B0h

Device/Head register -
DEV shall indicate the selected device.

8.41.3.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 178
 T13/1153D revision 18

8.41.3.6 Error outputs

If the device does not support this command or if the values in the Features, Cylinder Low, or Cylinder High
registers are invalid, the device shall return command aborted.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if this command is not supported or if the input register values are invalid.
ABRT may be set to one if the device is not able to complete the action requested by the
command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.41.3.7 Prerequisites

DRDY set equal to one.

8.41.3.8 Description

This command enables access to all SMART capabilities within the device. Prior to receipt of this command
SMART data are neither monitored nor saved by the device. The state of SMART (either enabled or
disabled) shall be preserved by the device across power cycles. Once enabled, the receipt of subsequent
SMART ENABLE OPERATIONS commands shall not affect any SMART data or functions.

Page 179
T13/1153D revision 18

8.41.4 SMART EXECUTE OFF-LINE IMMEDIATE

8.41.4.1 Command code

B0h with the content of the Features register equal to D4h

8.41.4.2 Feature set

SMART feature set.

− Optional when the SMART feature set is implemented.
− Use prohibited when the PACKET Command feature set is implemented.

8.41.4.3 Protocol

Non-data command (see 9.9).

8.41.4.4 Inputs

The Features register shall be set to D4h. The Cylinder Low register shall be set to 4Fh. The Cylinder High
register shall be set to C2h.

Register 7 6 5 4 3 2 1 0
Features D4h
Sector Count na
Sector Number na
Cylinder Low 4Fh
Cylinder High C2h
Device/Head obs na obs DEV na
Command B0h

Device/Head register -
DEV shall indicate the selected device.

8.41.4.5 Normal Outputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one indicating that the device is capable of receiving any command.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 180
 T13/1153D revision 18

8.41.4.6 Error Outputs

If the device does not support this command, if SMART is disabled, or if the values in the Features, Cylinder
Low, or Cylinder High registers are invalid, the device shall return command aborted.

Register 7 6 5 4 3 2 1 0
Error na na na IDNF na ABRT na obs
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
IDNF shall be set to one if SMART data sector’s ID field could not be found.
ABRT shall be set to one if this command is not supported, if SMART is not enabled, or if register
values are invalid. ABRT may be set to one if the device is not able to complete the action
requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one indicating that the device is capable of receiving any command.
DF (Device Fault) shall be set to one indicating that a device fault has occurred.
DRQ shall be cleared to zero indicating that there is no data to be transferred.
ERR shall be set to one if any Error register bit is set to one.

8.41.4.7 Prerequisites

DRDY set to one. SMART enabled.

8.41.4.8 Description

This command causes the device to immediately initiate the optional set of activities that collect SMART
data in an off-line mode and then save this data to the device's non-volatile memory.

During execution of its off-line activities the device shall not set BSY nor clear DRDY.

If the device is in the process of performing its set of off-line data collection activities as a result of receiving
a SMART EXECUTE OFF-LINE IMMEDIATE command from the host and is interrupted by any new
command from the host except a SMART DISABLE OPERATIONS, SMART EXECUTE OFF-LINE
IMMEDIATE, or STANDBY IMMEDIATE command, the device shall suspend or abort its off-line data
collection activities and service the host within two seconds after receipt of the new command. After
servicing the interrupting command from the host the device may immediately re-initiate or resume its off-
line data collection activities without any additional commands from the host (see the definition for Bit 2 in
the Off-line data collection capability byte in 8.41.5).

If the device is in the process of performing its off-line data collection activities and is interrupted by a
STANDBY IMMEDIATE command from the host, the device shall suspend or abort its off-line data
collection activities, and service the host within two seconds after receipt of the command. After receiving a
new command that causes the device to exit a power saving mode, the device shall initiate or resume off-
line data collection activities without any additional commands from the host unless these activities were
aborted by the device (see 8.41.5.8).

If the device is in the process of performing its off-line data collection activities and is interrupted by a
SMART DISABLE OPERATIONS command from the host, the device shall suspend or abort its off-line data

Page 181
T13/1153D revision 18

collection activities and service the host within two seconds after receipt of the command. Upon receipt of
the next SMART ENABLE OPERATIONS command the device may, after the next vendor specified event,
either re-initiate its off-line data collection activities or resume those activities from where they had been
previously suspended.

If the device is in the process of performing its off-line data collection activities and is interrupted by a
SMART EXECUTE OFF-LINE IMMEDIATE command from the host, the device shall abort its off-line data
collection activities and service the host within two seconds after receipt of the command. The device shall
then re-initiate its off-line data collection activities in response to the new EXECUTE OFF-LINE IMMEDIATE
command.

Page 182
 T13/1153D revision 18

8.41.5 SMART READ DATA

8.41.5.1 Command code

B0h with the content of the Features register equal to D0h.

8.41.5.2 Feature set

SMART feature set.

− Optional when the SMART feature set is implemented.
− Use prohibited when the PACKET Command feature set is implemented.

8.41.5.3 Protocol

PIO data in (see 9.7).

8.41.5.4 Inputs

The Features register shall be set to D0h. The Cylinder Low register shall be set to 4Fh. The Cylinder High
register shall be set to C2h.

Register 7 6 5 4 3 2 1 0
Features D0h
Sector Count na
Sector Number na
Cylinder Low 4Fh
Cylinder High C2h
Device/Head obs na obs DEV na
Command B0h

Device/Head register -
DEV shall indicate the selected device.

8.41.5.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one indicating that the device is capable of receiving any command.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 183
T13/1153D revision 18

8.41.5.6 Error outputs

If the device does not support this command, if SMART is disabled, or if the values in the Features, Cylinder
Low, or Cylinder High registers are invalid, the device shall return command aborted.

Register 7 6 5 4 3 2 1 0
Error na UNC na IDNF na ABRT na obs
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
UNC shall be set to one if SMART data is uncorrectable.
IDNF shall be set to one if SMART data sector’s ID field could not be found or data structure
checksum occurred.
ABRT shall be set to one if this command is not supported, if SMART is not enabled, or if register
values are invalid. ABRT may be set to one if the device is not able to complete the action
requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one indicating that the device is capable of receiving any command.
DF (Device Fault) shall be set to one indicating that a device fault has occurred.
DRQ shall be cleared to zero indicating that there is no data to be transferred.
ERR shall be set to one if any Error register bit is set to one.

8.41.5.7 Prerequisites

DRDY set to one. SMART enabled.

8.41.5.8 Description

This command returns the Device SMART data structure to the host.

Table 23 defines the 512 bytes that make up the Device SMART data structure. All multi-byte fields shown
in this structure follow the byte ordering described in 3.2.7.

Page 184
 T13/1153D revision 18

Table 23 − Device SMART data structure

Byte F/V Descriptions
0-361 X Vendor specific
362 V Off-line data collection status
363 X Vendor specific
364-365 V Total time in seconds to complete off-line data collection activity
366 X Vendor specific
367 F Off-line data collection capability
368-369 F SMART capability
370-385 R Reserved
386-510 X Vendor specific
511 V Data structure checksum
Key:
F=the content of the byte is fixed and does not change.
V=the content of the byte is variable and may change depending on the state of the
device or the commands executed by the device.
X=the content of the byte is vendor specific and may be fixed or variable.
R=the content of the byte is reserved and shall be zero.

The value of the off-line data collection status byte defines the current status of the off-line activities of the
device. Table 24 lists the values and their respective definitions.

Table 24 − Off-line data collection status byte values

Value Definition
00h or 80h Off-line data collection activity was never started.
01h Reserved
02h or 82h Off-line data collection activity was completed without error.
03h Reserved
04h or 84h Off-line data collection activity was suspended by an interrupting command from
host.
05h or 85h Off-line data collection activity was aborted by an interrupting command from host.
06h or 86h Off-line data collection activity was aborted by the device with a fatal error.
07h-3Fh Reserved
40h-7Fh Vendor specific
81h Reserved
83h Reserved
87h-BFh Reserved
C0h-FFh Vendor specific

The total time in seconds to complete off-line data collection activity word specifies how many seconds the
device requires to complete its sequence of off-line data collection activity. Valid values for this word are
from 0001h to FFFFh.

Off-line data collection capability.

The following describes the definition for the off-line data collection capability bits. If the value of all of
these bits is equal to zero, then no off-line data collection is implemented by this device.

− Bit 0 (EXECUTE OFF-LINE IMMEDIATE implemented bit) - If the value of this bit equals one, then the
SMART EXECUTE OFF-LINE IMMEDIATE command is implemented by this device. If the value of
this bit equals zero, then the SMART EXECUTE OFF-LINE IMMEDIATE command is not implemented
by this device.

− Bit 1 (vendor specific).

Page 185
T13/1153D revision 18

− Bit 2 (abort/restart off-line by host bit) - If the value of this bit equals one, then the device shall abort all
off-line data collection activity initiated by an SMART EXECUTE OFF-LINE IMMEDIATE command
upon receipt of a new command. Off-line data collection activity must be restarted by a new SMART
EXECUTE OFF-LINE IMMEDIATE command from the host. If the value of this bit equals zero, the
device shall suspend off-line data collection activity after an interrupting command and resume off-line
data collection activity after some vendor-specified event.

− Bits 3-7 (reserved).

SMART capability

The following describes the definition for the SMART capabilities bits. If the value of all of these bits is
equal to zero, then automatic saving of SMART data is not implemented by this device.

− Bit 0 (power mode SMART data saving capability bit) - If the value of this bit equals one, the device
shall save its SMART data prior to going into a power saving mode (Idle, Standby, or Sleep) or
immediately upon return to Active or Idle mode from a Standby mode. If the value of this bit equals
zero, the device shall not save its SMART data prior to going into a power saving mode (Idle, Standby,
or Sleep) or immediately upon return to Active or Idle mode from a Standby mode.

− Bit 1 (SMART data autosave after event capability bit) - The value of this bit shall be equal to one for
devices complying with this standard.

− Bits 2-15 (reserved).

The data structure checksum is the two's compliment of the result of a simple eight-bit addition of the first
511 bytes in the data structure.

Page 186
 T13/1153D revision 18

8.41.6 SMART RETURN STATUS

8.41.6.1 Command code

B0h with a Feature register value of DAh.

8.41.6.2 Feature set

SMART feature set.

− Mandatory when the SMART feature set is implemented.
− Use prohibited when the PACKET Command feature set is implemented.

8.41.6.3 Protocol

Non-data command (see 9.9).

8.41.6.4 Inputs

The Features register shall be set to DAh. The Cylinder Low register shall be set to 4Fh. The Cylinder High
register shall be set to C2h.

Register 7 6 5 4 3 2 1 0
Features DAh
Sector Count na
Sector Number na
Cylinder Low 4Fh
Cylinder High C2h
Device/Head obs na obs DEV na na na na
Command B0h

Device/Head register -
DEV shall indicate the selected device.

8.41.6.5 Normal outputs

If the device has not detected a threshold exceeded condition, the device sets the Cylinder Low register to
4Fh and the Cylinder High register to C2h. If the device has detected a threshold exceeded condition, the
device sets the Cylinder Low register to F4h and the Cylinder High register to 2Ch.

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low 4Fh or F4h
Cylinder High C2h or 2Ch
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Cylinder Low -
4Fh if threshold not exceeded, F4h if threshold exceeded.
Cylinder High -
C2h if threshold not exceeded, 2Ch if threshold exceeded.
Device/Head register -
DEV shall indicate the selected device.

Page 187
T13/1153D revision 18

Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.41.6.6 Error outputs

If the device does not support this command, if SMART is disabled, or if the values in the Features, Cylinder
Low, or Cylinder High registers are invalid, the device shall return command aborted.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if this command is not supported, if SMART is disabled, or if the input
register values are invalid. ABRT may be set to one if the device is not able to complete the
action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.41.6.7 Prerequisites

DRDY set equal to one. SMART enabled.

8.41.6.8 Description

This command is used to communicate the reliability status of the device to the host at the host’s request. If
a threshold exceeded condition is not detected by the device, the device shall set the Cylinder Low register
to 4Fh and the Cylinder High register to C2h. If a threshold exceeded condition is detected by the device,
the device shall set the Cylinder Low register to F4h and the Cylinder High register to 2Ch.

Page 188
 T13/1153D revision 18

8.41.7 SMART SAVE ATTRIBUTE VALUES

8.41.7.1 Command code

B0h with a Feature register value of D3h.

8.41.7.2 Feature set

SMART feature set.

− Optional and not recommended when the SMART feature set is implemented.
− Use prohibited when the PACKET Command feature set is implemented.

8.41.7.3 Protocol

Non-data command (see 9.9).

8.41.7.4 Inputs

The Features register shall be set to D3h. The Cylinder Low register shall be set to 4Fh. The Cylinder High
register shall be set to C2h.

Register 7 6 5 4 3 2 1 0
Features D3h
Sector Count na
Sector Number na
Cylinder Low 4Fh
Cylinder High C2h
Device/Head obs na obs DEV na na na na
Command B0h

Device/Head register -
DEV shall indicate the selected device.

8.41.7.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 189
T13/1153D revision 18

8.41.7.6 Error outputs

If the device does not support this command, if SMART is disabled, or if the values in the Features, Cylinder
Low, or Cylinder High registers are invalid, the device shall return command aborted.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if this command is not supported, if SMART is disabled, or if the input
register values are invalid. ABRT may be set to one if the device is not able to complete the
action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero..
ERR shall be set to one if an Error register bit is set to one.

8.41.7.7 Prerequisites

DRDY set equal to one. SMART enabled.

8.41.7.8 Description

This command causes the device to immediately save any updated attribute values to the device’s non-
volatile memory regardless of the state of the attribute autosave timer.

Page 190
 T13/1153D revision 18

8.42 STANDBY

8.42.1 Command code

E2h

8.42.2 Feature set

Power Management feature set.

− Power Management feature set is mandatory when power management is not implemented by a
PACKET power management feature set.
− This command is mandatory when the Power Management feature set is implemented.

8.42.3 Protocol

Non-data command (see 9.9).

8.42.4 Inputs

The value in the Sector Count register when the STANDBY command is issued shall determine the time
period programmed into the Standby timer. Table 14 defines these values.

Register 7 6 5 4 3 2 1 0
Features na
Sector Count Time period value
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command E2h

Device/Head register -
DEV shall indicate the selected device.

8.42.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 191
T13/1153D revision 18

8.42.6 Error outputs

The device shall return command aborted if the device does not support the Power Management feature
set.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if the Power Management feature set is not supported. ABRT may be set
to
one if the device is not able to complete the action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.42.7 Prerequisites

DRDY set equal to one.

8.42.8 Description

This command causes the device to enter the Standby mode.

If the Sector Count register is non-zero then the Standby timer shall be enabled. The value in the Sector
Count register shall be used to determine the time programmed into the Standby timer (see Table 14).

If the Sector Count register is zero then the Standby timer is disabled.

Page 192
 T13/1153D revision 18

8.43 STANDBY IMMEDIATE

8.43.1 Command code

E0h

8.43.2 Feature set

Power Management feature set.

− Power Management feature set is mandatory when power management is not implemented by a
PACKET power management feature set.
− This command is mandatory when the Power Management feature set is implemented.

8.43.3 Protocol

Non-data command (see 9.9).

8.43.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command E0h

Device/Head register -
DEV shall indicate the selected device.

8.43.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

Page 193
T13/1153D revision 18

8.43.6 Error outputs

The device shall return command aborted if the device does not support the Power Management feature
set.

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if the Power Management feature set is not supported. ABRT may be set
to
one if the device is not able to complete the action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.43.7 Prerequisites

DRDY set equal to one.

8.43.8 Description

This command causes the device to immediately enter the Standby mode.

Page 194
 T13/1153D revision 18

8.44 WRITE BUFFER

8.44.1 Command code

E8h

8.44.2 Feature set

General feature set

− Optional for devices not implementing the PACKET Command feature set.
− Use prohibited for devices implementing the PACKET Command feature set.

8.44.3 Protocol

PIO data out (see 9.8).

8.44.4 Inputs

Register 7 6 5 4 3 2 1 0
Features na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Command E8h

Device/Head register -
DEV shall indicate the selected device.

8.44.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.44.6 Error outputs

The device shall return command aborted if the command is not supported.

Page 195
T13/1153D revision 18

Register 7 6 5 4 3 2 1 0
Error na na na na na ABRT na na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF na DRQ na na ERR

Error register -
ABRT shall be set to one if this command is not supported. ABRT may be set to one if the device is
not able to complete the action requested by the command.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.44.7 Prerequisites

DRDY set equal to one.

8.44.8 Description

This command enables the host to write the contents of one sector in the device’s buffer.

The READ BUFFER and WRITE BUFFER commands shall be synchronized within the device such that
sequential WRITE BUFFER and READ BUFFER commands access the same 512 bytes within the buffer.

Page 196
 T13/1153D revision 18

8.45 WRITE DMA

8.45.1 Command code

CAh or CBh

NOTE − The host should not use the CBh value.

8.45.2 Feature set

General feature set

Mandatory for devices not implementing the PACKET Command feature set.
Use prohibited for devices implementing the PACKET Command feature set.

8.45.3 Protocol

DMA (see 9.10).

8.45.4 Inputs

The Cylinder Low, Cylinder High, Device/Head, and Sector Number specify the starting sector address to be
written. The Sector Count register specifies the number of sectors to be transferred.

Register 7 6 5 4 3 2 1 0
Features na
Sector Count Sector count
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs LBA obs DEV Head number or LBA
Command CAh or CBh

Sector Count -
number of sectors to be transferred. A value of 00h indicates that 256 sectors are to be transferred.
Sector Number -
starting sector number or LBA address bits (7:0).
Cylinder Low -
starting cylinder number bits (7:0) or LBA address bits (15:8).
Cylinder High -
starting cylinder number bits (15:8) or LBA address bits (23:16).
Device/Head -
bit 6 set to one if LBA address, cleared to zero if CHS address.
DEV shall indicate the selected device.
bits (3:0) starting head number or LBA address bits (27:24).

Page 197
T13/1153D revision 18

8.45.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.45.6 Error outputs

An unrecoverable error encountered during the execution of this command results in the termination of the
command. The Command Block registers contain the address of the sector where the first unrecoverable
error occurred. The amount of data transferred is indeterminate.

Register 7 6 5 4 3 2 1 0
Error ICRC WP MC IDNF MCR ABRT NM obs
Sector Count na
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs na obs DEV Head number or LBA
Status BSY DRDY DF na DRQ na na ERR

Error register -
ICRC shall be set to one if an interface CRC error has occurred during an Ultra DMA data transfer.
The content of this bit is not applicable for Multiword DMA transfers.
WP shall be set to one if the media in a removable media device is write protected.
MC shall be set to one if the media in a removable media device changed since the issuance of the
last command. The device shall clear its internal media change detected state.
IDNF shall be set to one if a user-accessible address could not be found and after an unsuccessful
INITIALIZE DEVICE PARAMETERS command until a valid CHS translation is established
(see 8.16.8). IDNF shall be set to one if an address outside of the range of user-accessible
addresses is requested if command aborted is not returned.
MCR shall be set to one if a media change request has been detected by a removable media
device. This bit is only cleared by a GET MEDIA STATUS or a media access command.
ABRT shall be set to one if this command is not supported or if an error, including an ICRC error,
has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is
not able to complete the action requested by the command. ABRT shall be set to one if an
address outside of the range of user-accessible addresses is requested if IDNF is not set to
one.
NM shall be set to one if no media is present in a removable media device.
Sector Number, Cylinder Low, Cylinder High, Device/Head -
shall be written with address of first unrecoverable error.
DEV shall indicate the selected device.
Status register -

Page 198
 T13/1153D revision 18

BSY shall be cleared to zero indicating command completion.

DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.45.7 Prerequisites

DRDY set equal to one. The host shall initialize the DMA channel.

8.45.8 Description

The WRITE DMA command allows the host to write data using the DMA data transfer protocol.

Page 199
T13/1153D revision 18

8.46 WRITE DMA QUEUED

8.46.1 Command code

CCh

8.46.2 Feature set

Overlapped feature set

− Mandatory for devices implementing the Overlapped feature set but not implementing the
PACKET Command feature set.
− Use prohibited for devices implementing the PACKET Command feature set.

8.46.3 Protocol
DMA QUEUED (see 9.12).

8.46.4 Inputs

Register 7 6 5 4 3 2 1 0
Features Sector Count
Sector Count Tag na na na
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs LBA obs DEV Head number or LBA
Command CCh

Features -
number of sectors to be transferred. A value of 00h indicates that 256 sectors are to be transferred.
Sector count -
if the device supports command queuing, bits (7:3) contain the Tag for the command being
delivered. If queuing is not supported, this field is not applicable.
Sector number -
starting sector number or LBA address bits (7:0).
Cylinder Low -
starting cylinder number bits (7:0) or LBA address bits (15:8).
Cylinder High -
starting cylinder number bits (15:8) or LBA address bits (23:16).
Device/Head -
bit 6 set to one if LBA address, cleared to zero if CHS address.
DEV shall indicate the selected device.
bits (3:0) starting head number or LBA address bits (27:24).

8.46.5 Normal outputs

8.46.5.1 Bus release

If the device performs a bus release before transferring data for this command, the register content upon
performing a bus release shall be as shown below.

Page 200
 T13/1153D revision 18

Register 7 6 5 4 3 2 1 0
Error na
Sector Count Tag REL I/O C/D
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF SERV DRQ na na ERR

Sector Count register -

Tag - If the device supports command queuing, this field shall contain the Tag of the command
being bus released. If the device does not support command queuing, this field shall be
zeros.
REL bit shall be set indicating that the device has bus released an overlap command.
I/O shall be cleared to zero.
C/D shall be cleared to zero.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating bus release.
DRDY shall be set to one.
SERV (Service) shall be cleared to zero if no other queued command is ready for service. It shall be
set to one when another queued command is ready for service. This bit shall be set to one
when the device has prepared this command for service.
DF (Device Fault) shall be cleared to zero.
DRQ bit shall be cleared to zero.
ERR bit shall be cleared to zero.

8.46.5.2 Command completion

When the transfer of all requested data has occurred without error, the register content shall be as shown
below.

Register 7 6 5 4 3 2 1 0
Error 00h
Sector Count Tag RE I/O C/D
L
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na
Status BSY DRDY DF SERV DRQ na na ERR

Sector Count register -

Tag - If the device supports command queuing, this field shall contain the Tag of the completed
command. If the device does not support command queuing, this field shall be zeros.
REL shall be cleared to zero.
I/O shall be set to one.
C/D shall be set to one.
Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
SERV (Service) shall be cleared to zero when no other queued command is ready for service. It
shall be set to one when another queued command is ready for service.

Page 201
T13/1153D revision 18

DF (Device Fault) shall be cleared to zero.

DRQ bit shall be cleared to zero.
ERR bit shall be cleared to zero.

8.46.6 Error outputs

The Sector Count register contains the Tag for this command if the device supports command queuing. The
device shall return command aborted if the command is not supported or if the device has not had
overlapped interrupt enabled. The device shall return command aborted if the device supports command
queuing and the Tag is invalid. An unrecoverable error encountered during the execution of this command
results in the termination of the command and the Command Block registers contain the sector where the
first unrecoverable error occurred. If a queue existed, the unrecoverable error shall cause the queue to
abort. The device may remain BSY for some time when responding to these errors.

Register 7 6 5 4 3 2 1 0
Error ICRC WP MC IDNF MCR ABRT NM na
Sector Count Tag REL I/O C/D
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs na obs DEV Head number or LBA
Status BSY DRDY DF SERV DRQ na na ERR

Error register -
ICRC shall be set to one if an interface CRC error has occurred during an Ultra DMA data transfer.
The content of this bit is not applicable for Multiword DMA transfers.
WP shall be set to one if the media in a removable media device is write protected.
MC shall be set to one if the media in a removable media device changed since the issuance of the
last command. The device shall clear its internal media change detected state.
IDNF shall be set to one if a user-accessible address could not be found and after an unsuccessful
INITIALIZE DEVICE PARAMETERS command until a valid CHS translation is established
(see 8.16.8). IDNF shall be set to one if an address outside of the range of user-accessible
addresses is requested if command aborted is not returned.
MCR shall be set to one if a media change request has been detected by a removable media
device. This bit is only cleared by a GET MEDIA STATUS or a media access command.
ABRT shall be set to one if this command is not supported or if an error, including an ICRC error,
has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is
not able to complete the action requested by the command. ABRT shall be set to one if an
address outside of the range of user-accessible addresses is requested if IDNF is not set to
one.
NM shall be set to one if no media is present in a removable media device.
Sector Count register -
Tag - If the device supports command queuing, this field shall contain the Tag of the completed
command. If the device does not support command queuing, this field shall be zeros.
REL shall be cleared to zero.
I/O shall be set to one.
C/D shall be set to one.
Sector Number, Cylinder Low, Cylinder High, Device/Head -
shall be written with the address of first unrecoverable error.
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
SERV (Service) shall be cleared to zero when no other queued command is ready for service. It
shall be set to one when another queued command is ready for service.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

Page 202
 T13/1153D revision 18

8.46.7 Prerequisites
DRDY set to one. The host shall initialize the DMA channel.

8.46.8 Description
This command executes in a similar manner to a WRITE DMA command. The device may perform a bus
release the bus or it may execute the data transfer without performing a bus release if the data is ready to
transfer.

If the device performs a bus release, the host shall reselect the device using the SERVICE command.

Once the data transfer is begun, the device shall not perform a bus release until the entire data transfer has
been completed.

Page 203
T13/1153D revision 18

8.47 WRITE MULTIPLE

8.47.1 Command code

C5h

8.47.2 Feature set

General feature set

− Mandatory for devices not implementing the PACKET Command feature set.
− Use prohibited for devices implementing the PACKET Command feature set.

8.47.3 Protocol

PIO data out (see 9.8).

8.47.4 Inputs

The Cylinder Low, Cylinder High, Device/Head, and Sector Number specify the starting sector address to be
written. The Sector Count register specifies the number of sectors to be transferred.

Register 7 6 5 4 3 2 1 0
Features na
Sector Count Sector count
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs LBA obs DEV Head number or LBA
Command C5h

Sector Count -
number of sectors to be transferred. A value of 00h indicates that 256 sectors are to be transferred.
Sector Number -
starting sector number or LBA address bits (7:0).
Cylinder Low -
starting cylinder number bits (7:0) or LBA address bits (15:8).
Cylinder High -
starting cylinder number bits (15:8) or LBA address bits (23:16).
Device/Head -
bit 6 set to one if LBA address, cleared to zero if CHS address.
DEV shall indicate the selected device.
bits (3:0) starting head number or LBA address bits (27:24).

8.47.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Page 204
 T13/1153D revision 18

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.47.6 Error outputs

An unrecoverable error encountered during the execution of this command results in the termination of the
command. The Command Block registers contain the address of the sector where the first unrecoverable
error occurred. The amount of data transferred is indeterminate.

Register 7 6 5 4 3 2 1 0
Error na WP MC IDNF MCR ABRT NM na
Sector Count na
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs na obs DEV Head number or LBA
Status BSY DRDY DF na DRQ na na ERR

Error register -
WP shall be set to one if the media in a removable media device is write protected.
MC shall be set to one if the media in a removable media device changed since the issuance of the
last command. The device shall clear its internal media change detected state.
IDNF shall be set to one if a user-accessible address could not be found and after an unsuccessful
INITIALIZE DEVICE PARAMETERS command until a valid CHS translation is established
(see 8.16.8). IDNF shall be set to one if an address outside of the range of user-accessible
addresses is requested if command aborted is not returned.
MCR shall be set to one if a media change request has been detected by a removable media
device. This bit is only cleared by a GET MEDIA STATUS or a media access command.
ABRT shall be set to one if this command is not supported or if an error, including an ICRC error,
has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is
not able to complete action requested by the command. ABRT shall be set to one if an
address outside of the range of user-accessible addresses is requested if IDNF is not set to
one.
NM shall be set to one if no media is present in a removable media device.
Sector Number, Cylinder Low, Cylinder High, Device/Head -
shall be written with the address of first unrecoverable error.
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be set to one if a device fault has occurred.
DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.47.7 Prerequisites

DRDY set equal to one. If bit 8 of IDENTIFY DEVICE word 59 is equal to zero, a successful SET MULTIPLE
MODE command shall proceed a WRITE MULTIPLE command.

Page 205
T13/1153D revision 18

8.47.8 Description

This command is similar to the WRITE SECTOR(S) command. Interrupts are not generated on every
sector, but on the transfer of a block that contains the number of sectors defined by SET MULTIPLE MODE
or the default if no intervening SET MULTIPLE command has been issued.

Command execution is identical to the WRITE SECTOR(S) operation except that the number of sectors
defined by the SET MULTIPLE MODE command are transferred without intervening interrupts. The DRQ
bit qualification of the transfer is required only at the start of the data block, not on each sector.

The block count of sectors to be transferred without intervening interrupts is the default or programmed by
the SET MULTIPLE MODE command, that shall be executed prior to the WRITE MULTIPLE command.

When the WRITE MULTIPLE command is issued, the Sector Count register contains the number of sectors
(not the number of blocks or the block count) requested.

If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible
are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where:

n = Remainder (sector count/ block count).

If the WRITE MULTIPLE command is received when WRITE MULTIPLE commands are disabled, the Write
Multiple operation shall be rejected with command aborted.

Device errors encountered during WRITE MULTIPLE commands are posted after the attempted device
write of the block or partial block transferred. The Write command ends with the sector in error, even if it
was in the middle of a block. Subsequent blocks are not transferred in the event of an error.

The contents of the Command Block Registers following the transfer of a data block that had a sector in
error are undefined. The host should retry the transfer as individual requests to obtain valid error
information. Interrupts are generated when the DRQ bit is set to one at the beginning of each block or
partial block.

Page 206
 T13/1153D revision 18

8.48 WRITE SECTOR(S)

8.48.1 Command code

30h or 31h

NOTE − The host should not use the 31h value.

8.48.2 Feature set

General feature set

− Mandatory for devices not implementing the PACKET Command feature set.
− Use prohibited for devices implementing the PACKET Command feature set.

8.48.3 Protocol

PIO data out (see 9.8).

8.48.4 Inputs

The Cylinder Low, Cylinder High, Device/Head, and Sector Number specify the starting sector address to be
written. The Sector Count register specifies the number of sectors to be transferred.

Register 7 6 5 4 3 2 1 0
Features na
Sector Count Sector count
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs LBA obs DEV Head number or LBA
Command 30h or 31h

Sector Count -
number of sectors to be transferred. A value of 00h indicates that 256 sectors are to be transferred.
Sector Number -
starting sector number or LBA address bits (7:0).
Cylinder Low -
starting cylinder number bits (7:0) or LBA address bits (15:8).
Cylinder High -
starting cylinder number bits (15:8) or LBA address bits (23:16).
Device/Head -
bit 6 set to one if LBA address, cleared to zero if CHS address.
DEV shall indicate the selected device.
bits (3:0) starting head number or LBA address bits (27:24).

Page 207
T13/1153D revision 18

8.48.5 Normal outputs

Register 7 6 5 4 3 2 1 0
Error na
Sector Count na
Sector Number na
Cylinder Low na
Cylinder High na
Device/Head obs na obs DEV na na na na
Status BSY DRDY DF na DRQ na na ERR

Device/Head register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

8.48.6 Error outputs

An unrecoverable error encountered during the execution of this command results in the termination of the
command. The Command Block registers contain the address of the sector where the first unrecoverable
error occurred. The amount of data transferred is indeterminate.

Register 7 6 5 4 3 2 1 0
Error na WP MC IDNF MCR ABRT NM na
Sector Count na
Sector Number Sector number or LBA
Cylinder Low Cylinder low or LBA
Cylinder High Cylinder high or LBA
Device/Head obs na obs DEV Head number or LBA
Status BSY DRDY DF na DRQ na na ERR

Error register -
WP shall be set to one if the media in a removable media device is write protected.
MC shall be set to one if the media in a removable media device changed since the issuance of the
last command. The device shall clear its internal media change detected state.
IDNF shall be set to one if a user-accessible address could not be found and after an unsuccessful
INITIALIZE DEVICE PARAMETERS command until a valid CHS translation is established
(see 8.16.8). IDNF shall be set to one if an address outside of the range of user-accessible
addresses is requested if command aborted is not returned.
MCR shall be set to one if a media change request has been detected by a removable media
device. This bit is only cleared by a GET MEDIA STATUS or a media access command.
ABRT shall be set to one if this command is not supported or if an error, including an ICRC error,
has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is
not able to complete the action requested by the command. ABRT shall be set to one if an
address outside of the range of user-accessible addresses is requested if IDNF is not set to
one.
NM shall be set to one if no media is present in a removable media device.
Sector Number, Cylinder Low, Cylinder High, Device/Head -
shall be written with the address of first unrecoverable error.
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.

Page 208
 T13/1153D revision 18

DF (Device Fault) shall be set to one if a device fault has occurred.

DRQ shall be cleared to zero.
ERR shall be set to one if an Error register bit is set to one.

8.48.7 Prerequisites

DRDY set equal to one.

8.48.8 Description

This command writes from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0
requests 256 sectors.

Page 209
T13/1153D revision 18

9 Protocol
Commands are grouped into different classes according to the protocols followed for command execution.
The command classes with their associated protocols are defined below.

For all commands except DEVICE RESET, the host first checks if the BSY bit is equal to one, and should
proceed no further unless and until the BSY bit is equal to zero. For most commands, the host shall also
wait for the DRDY bit to be equal to one before proceeding.

Data transfers may be accomplished in more ways than are described below, but these sequences should
work with all known implementations of devices.

A device shall maintain either the BSY bit equal to one or the DRQ bit equal to one at all times until
command completion. The INTRQ signal is used by the device to signal most, but not all, times when the
BSY bit is changed from one to zero during command execution and command completion.

The result of writing to the Command register or a hardware or software reset while the BSY bit is equal to
one or the DRQ bit is equal to one may result in data corruption for commands that were queued or in
progress at the time.

9.1 Signature and persistence

A device not implementing the PACKET command feature set shall place the signature in the Command
Block registers listed below for power on reset, hardware reset, software reset, and the EXECUTE DEVICE
DIAGNOSTIC command.

If the device does not implement the PACKET command feature set, the signature shall be:
Sector Count 01h
Sector Number 01h
Cylinder Low 00h
Cylinder High 00h
Device/Head 00h

A device implementing the PACKET command feature set shall place the signature in the Command Block
registers listed below for power on reset, hardware reset, software reset, the EXECUTE DEVICE
DIAGNOSTIC command, and the DEVICE RESET command. The DEVICE RESET command shall not
change the value of the DEV bit when writing the signature into the Device/Head register for a device
implementing the PACKET command feature set. If the device implements the PACKET command feature
set, the signature is also written in the registers for the IDENTIFY DEVICE and READ SECTOR(S)
commands.

If the device implements the PACKET command feature set, the signature shall be:
Sector Count 01h
Sector Number 01h
Cylinder Low 14h
Cylinder High EBh
Device/Head 00h or 10h

If the PACKET command feature set is implemented by a device, then the signature values written by the
device in the Command Block registers following power on reset, hardware reset, software reset, or the
DEVICE RESET command shall not be changed by the device until the device receives a command that
sets DRDY to one. These commands are a PACKET command or an IDENTIFY PACKET DEVICE
command. Writes by the host to the Command Block registers that contain the signature values shall
overwrite the signature values and invalidate the signature.

Page 210
 T13/1153D revision 18

9.2 Power on and hardware resets

This clause describes the algorithm and timing relationships for Device 0 and Device 1 during the
processing of power on and hardware resets.

If the host asserts RESET- while a device is in or going to a power management mode, then the device shall
execute its hardware reset sequence.

If the host reasserts RESET- before devices have completed executing their power on or hardware reset
sequences, then the devices shall restart executing their hardware reset sequence at step (b).

The host should not set the SRST bit to one in the Device Control register or issue a DEVICE RESET
command while the BSY bit is set to one in either devices’ Status register as a result of executing a power
on or hardware reset sequence. If the host sets the SRST bit in the Device Control register to one or issues
a DEVICE RESET command before the devices have completed execution of their power on or hardware
reset sequences, then the devices shall ignore the software reset or DEVICE RESET command.

A host should issue an IDENTIFY DEVICE and/or IDENTIFY PACKET DEVICE command after a issuing a
software reset in order to correctly determine the current status of features implemented by the device(s).

If the device has not determined its device number, the device shall follow the protocol described in steps
(a) through (c) of 9.2.1 until the device number is determined.

The host shall not begin polling the Status register until at least 2 ms after RESET- is negated. The host
should only interpret bits 6 and 7 of the Status register to determine completion of the reset.

9.2.1 Power on and hardware resets - device 0

The following steps should occur sequentially as listed. Several of the steps may occur concurrently or
outside of the listed sequence when explicitly allowed so long as all timing relationships are satisfied, e.g.:
Device 0 may continue to sample DASP- after Device 0 has completed its hardware initialization and self-
diagnostic testing.

Steps (b) through (o) shall be completed within 31s from negation of RESET- by the host.

a) The host shall assert RESET- for a minimum of 25 µs after power to the device has stabilized within the
system’s specified tolerance. The device shall not recognize a signal assertion shorter than 20 ns as a
valid RESET signal. Devices may respond to any signal assertion greater than 20 ns and shall
recognize a signal equal to or greater than 25 us;
b) The device shall release PDIAG-, INTRQ, IORDY, DMARQ, and DD(15:0) no later than 400 ns after
RESET- is negated;
c) The device shall set the BSY bit to one no later than 400 ns after RESET- is negated;
d) The device shall determine that it is Device 0;
e) The device shall release DASP- no later than 1 ms after RESET- is negated;
f) Steps (b), (c), (d), and (e) shall be completed before continuing;
g) Device 0 shall sample DASP- for assertion by Device 1. Device 0 may sample DASP- at any
frequency. This sampling shall not begin until at least 1 ms after RESET- is negated. Device 0 may
stop sampling DASP- upon detection of its assertion. The last sample of DASP- by Device 0 shall occur
no sooner than 450 ms after RESET- is negated if assertion has not been detected before this time.
Device 0 shall not sample DASP- later than 5 s after RESET- is negated;
h) Step (g) shall be completed before executing the following: Device 0 shall store whether or not Device
1 was detected in step (g). This information is needed to process any future software reset or
EXECUTE DEVICE DIAGNOSTIC command. This information shall be saved by Device 0 until the
next power on or hardware reset;
i) Device 0 should begin performing its hardware initialization and self-diagnostic testing;
j) Device 0 may revert to its default condition (the device’s settings may now be in different conditions
than they were before RESET- was asserted by the host). All Ultra DMA modes shall be disabled;

Page 211
T13/1153D revision 18

k) Step (g) shall be completed before executing the following: if Device 0 did not detect that DASP- was
asserted by Device 1 during step (g) (i.e.: Device 1 is not present), then Device 0 shall clear bit 7 to
zero in the Error register and go to step (m);
l) Device 0 shall sample PDIAG- for assertion by Device 1. Device 0 may sample PDIAG- at any
frequency. This sampling shall not begin until at least 1 ms after RESET- is negated. Device 0 may
stop sampling PDIAG- upon detection of its assertion. The last sample of PDIAG- by Device 0 shall
occur no sooner than 450 ms after RESET- is negated if assertion has not been detected before this
time. Device 0 shall not sample PDIAG- later than 31 s after RESET- is negated;
1) If Device 0 detects that PDIAG- is asserted within 31 s after RESET- is negated, then Device 0 shall
clear bit 7 to zero in the Error register;
2) If Device 0 does not detect that PDIAG- is asserted within 31 s after RESET- is negated, then
Device 0 shall set bit 7 to one in the Error register;
m) If performed, the hardware initialization and self-diagnostic testing initiated in step (i) shall be completed
before executing the following: Device 0 shall write its self-diagnostic testing results to bits 6-0 in the
Error register. Table 10 defines results values;
n) Device 0 shall set its signature values (see 9.1) and clear SRST in the Device Control register to zero.
The effect on the Features register is undefined;
o) Clearing Status register bits:
1) If the PACKET command feature set is not implemented by Device 0, Device 0 shall clear to zero
bits 3, 2, and 0 of the Status register;
2) If the PACKET command feature set is implemented by Device 0, Device 0 shall clear to zero bits
5, 4, 3, 2, and 0 of the Status register;
p) Clearing BSY:
1) If the PACKET command feature set is not implemented by Device 0, then steps (h), (j), (k), (l) (as
required), (m), and (n) shall be completed before executing the following: Device 0 shall clear the
BSY bit to zero when ready to accept commands that do not require the DRDY bit to be equal to one;
2) If the PACKET command feature set is implemented by Device 0, then Device 0 shall return its
operating modes to their specified initial conditions: MODE SELECT conditions shall be restored to
their last saved values if saved values have been established; MODE SELECT conditions for which
no values have been saved shall be returned to their default values; then Device 0 shall clear the
BSY bit to zero when ready to accept commands;
q) Setting DRDY:
1) If the PACKET command feature set is not implemented by Device 0, then the DRDY bit shall be
set to one within 30 s after the BSY bit has been cleared to zero. Steps (p) (1) and (q) (1) may
occur at the same time;
2) If the PACKET command feature set is implemented by Device 0, then Device 0 shall not set DRDY
to one;

9.2.2 Power on and hardware resets - device 1

The following steps should occur sequentially as listed. Several of the steps may occur concurrently or
outside of the listed sequence when explicitly allowed so long as all timing relationships are satisfied.

Steps (b) through (m) shall be completed by Device 1 within 30 s from negation of RESET- by the host.

a) The host shall assert RESET- for a minimum of 25 µs after power to the device has stabilized within the
system’s specified tolerance. The device shall not recognize a signal assertion shorter than 20 ns as a
valid RESET signal. Devices may respond to any signal assertion greater than 20 ns and shall
recognize a signal equal to or greater than 25 us;
b) The device shall release INTRQ, IORDY, DMARQ, and DD(15:0) no later than 400 ns after RESET- is
negated;
c) The device shall set the BSY bit to one no later than 400 ns after RESET- is negated;
d) The device shall determine that it is Device 1;
e) Device 1 shall negate PDIAG- no later than 1 ms after RESET- is negated;
f) Steps (b), (c), (d), and (e) shall be completed before continuing;
g) Device 1 shall assert DASP- no later than 400 ms after RESET- is negated:
h) Device 1 should begin performing its hardware initialization and self-diagnostic testing;

Page 212
 T13/1153D revision 18

i) Device 1 may revert to its default condition (the device’s settings may now be in different conditions
than they were before the RESET- was asserted by the host). All Ultra DMA modes shall be disabled;
j) If performed, the hardware initialization and self-diagnostic testing initiated in step (h) shall be
completed before executing the following: Device 1 shall write its self-diagnostic testing results to the
Error register. Table 10 defines the results values;
k) Device 1 shall set its signature values (see 9.1) and clear SRST in the Device Control register to zero.
The effect on the Features register is undefined;
l) Clearing Status register bits:
1) If the PACKET command feature set is not implemented by Device 1, Device 1 shall clear to zero
bits 3, 2, and 0 of the Status register;
2) If the PACKET command feature set is implemented by Device 1, Device 1 shall clear to zero bits
5, 4, 3, 2, and 0 of the Status register;
m) Clearing BSY:
1) If the PACKET command feature set is not implemented by Device 1, then steps (g), (i), (j), and (k)
shall be completed before executing the following: Device 1 shall clear the BSY bit to zero when
ready to accept commands that do not require the DRDY bit to be equal to one;
2) If the PACKET command feature set is implemented by Device 1, then Device 1 shall return its
operating modes to their specified initial conditions: MODE SELECT conditions shall be restored to
their last saved values if saved values have been established; MODE SELECT conditions for which
no values have been saved shall be returned to their default values; then Device 1 shall clear the
BSY bit to zero when ready to accept commands;
n) Step (l) shall be completed before executing the following: If Device 1 passed its self-diagnostic testing,
then Device 1 shall assert PDIAG-;
o) Setting DRDY:
1) If the PACKET command feature set is not implemented by Device 1, then the DRDY bit shall be
set to one within 30 s after the BSY bit has been cleared to zero. Steps (m) (1), (n), and (o) (1) may
occur at the same time;
2) If the PACKET command feature set is implemented by Device 1, then Device 1 shall not set DRDY
to one;
p) Device 1 shall continue to assert DASP- and PDIAG- until after the first command is received from the
host or until at least 31 s after RESET- is negated or until detecting that the host has set the SRST bit to
one in the Device Control register, whichever comes first. Device 1 shall release PDIAG- no later than
command completion of the next command from the host except for the EXECUTE DEVICE
DIAGNOSTIC command.

Page 213
T13/1153D revision 18

t10
RESET-

t11
Device 0 BSY

Device 0 DRDY

Device 0 PDIAG- out

Device 0 DASP- out

t12

t13
Device 0 DASP- in

Device 0 PDIAG- in

t14
t15
Device 1 BSY

Device 1 DRDY
t16

Device 1 DASP- out

t17
t18
Device 1 PDIAG- out

Figure 8 − BSY and DRDY timing for power on and hardware resets

Page 214
 T13/1153D revision 18

Table 25 − BSY and DRDY timing for power on and hardware resets
RESET- timing parameters Min Max Note
t10 RESET- pulsewidth 25 µs 1
t11 Device 0 RESET- negation to BSY bit set to 400 ns
one, release PDIAG-
t12 Device 0 release DASP- 1 ms
t13 Device 0 sample of DASP- 1 ms 450 ms 2
t14 Device 0 sample of PDIAG- 1 ms 31 s 3
t15 Device 1 RESET- negation to BSY bit set to
one
t16 Device 1 assert DASP- 400 ms
t17 Device 1 negate PDIAG- if asserted 1 ms
t18 Device 1 assert PDIAG- 30 s 4
NOTES −
1 The device shall not recognize a RESET- assertion pulse width shorter than 20 ns as a
valid signal assertion.
2 Device 0 shall sample beginning 1 ms after RESET- is negated. Sampling shall
continue until DASP- assertion by Device 1 is sensed or 450 ms has elapsed indicating
no Device 1 present.
3 Device 0 shall sample beginning 1 ms after RESET- is negated. Sampling shall
continue until:
a) no DASP- assertion is sensed in 450 ms;
b) DASP- assertion is sensed in 450 ms and PDIAG- assertion is sensed;
c) or DASP- assertion is sensed in 450 ms and no PDIAG- assertion is sensed
in 31s.
When sampling is stopped, Device 0 shall clear the BSY bit to zero. DRDY shall be set to
one when Device 0 is ready to accept any command. No maximum time is specified but
a host should allow up to 30 s from the time RESET- is negated.
4 Upon completion of internal diagnostics, Device 1 shall clear BSY to zero, and if
diagnostics passed, assert PDIAG-. Internal diagnostics shall complete within 30 s of the
negation of RESET-.

9.3 Software reset

This clause describes the algorithm and timing relationships for Device 0 and Device 1 during the
processing of software resets.

If the host sets the SRST bit in the Device Control register to one while a device is in or going to a power
management mode, then the device shall execute its software reset sequence.

If the host asserts RESET- before devices have completed executing their software reset sequences, then
the devices shall start executing their hardware reset sequence at step (b).

The host should not set the SRST bit to one in the Device Control register while the BSY bit is set to one in
either devices’ Status register as a result of executing a software reset sequence. If the host sets the SRST
bit in the Device Control register to one before the devices have completed execution of their software reset
sequences, then the devices shall restart executing their software reset sequences at step (b).

A host should issue an IDENTIFY DEVICE and/or IDENTIFY PACKET DEVICE command after a issuing a
software reset in order to correctly determine the current status of features implemented by the device(s).

Some devices may take up to 2 ms to set BSY when coming out of Sleep mode. The host shall not begin
polling the Status register until at least 2 ms after the SRST bit has been set to one. The host should only
interpret bits 6 and 7 of the Status register to determine completion of the reset.

Page 215
T13/1153D revision 18

9.3.1 Software reset - device 0

The following steps should occur sequentially as listed. Several of the steps may occur concurrently or
outside of the listed sequence when explicitly allowed so long as all timing relationships are satisfied, e.g.,
Device 0 may continue to sample PDIAG- after Device 0 has completed writing the specified values to the
Sector Count, Sector Number, Cylinder Low, Cylinder High, and Device/Head registers.

Steps (g) through (k) shall be completed within 31 s from Device 0 detecting that the SRST bit is cleared to
zero.

a) The host shall set the SRST bit to one in the Device Control register. The host shall not clear the SRST
bit to zero until at least 5 µs after setting the bit to one. The host shall not set the SRST bit to one until
the bit has been cleared to zero for at least 5 µs;
b) The device shall release PDIAG-, INTRQ, IORDY, DMARQ, and DD(15:0) no later than 400 ns after
detecting that the SRST bit is equal to one;
c) Device 0 shall set the BSY bit to one no later than 400 ns after detecting that the SRST bit is equal to
one;
d) Hardware initialization and self-diagnostic testing:
1) If the PACKET command feature set is not implemented by the device, the device shall begin
performing its hardware and self-diagnostic testing;
2) If the PACKET command feature set is implemented by the device, the device may begin
performing its hardware and self-diagnostic testing and the device is not expected to stop any
background device activity (e.g., immediate command (see MMC and MMC2)) that was started
prior to the time that the SRST was set to one in step (a);
e) Reverting to default:
1) If the PACKET command feature set is not implemented by Device 0, then Device 0 may revert to
its default condition (the device’s settings may now be in different conditions than they were before
the SRST bit was set to one by the host). However, the condition of any Ultra DMA mode (either
enabled or disabled) shall not be affected by the host setting the SRST bit to one ;
2) If the PACKET command feature set is implemented by Device 0, then Device 0 shall not revert to
its default condition. However, the condition of any Ultra DMA mode (either enabled or disabled)
shall not be affected by the host setting the SRST bit to one;
f) Device 0 shall wait for the host to clear the SRST bit to zero before continuing;
g) If Device 0 did not detect that DASP- was asserted by Device 1 during the most recent power cycle or
hardware reset, then Device 0 shall clear bit 7 in the Error register to zero and go to step (i);
h) If Device 0 detected that DASP- was asserted by Device 1 during the most recent power cycle or
hardware reset, then Device 0 shall sample PDIAG- for assertion by Device 1. Device 0 may sample
PDIAG- at any frequency. This sampling shall not begin until at least 1 ms after SRST is cleared to
zero. Device 0 may stop sampling PDIAG- upon detection of assertion. Device 0 shall not sample
PDIAG- after the first command is received or later than 31 s after SRST is cleared to zero;
1) If Device 0 detects that PDIAG- is asserted within 31 s after SRST is cleared to zero, then Device 0
shall clear bit 7 to zero in the Error register;
2) If Device 0 does not detect that PDIAG- is asserted within 31 s after SRST is cleared to zero, then
Device 0 shall set bit 7 to one in the Error register;
i) If performed, the hardware initialization and self-diagnostic testing initiated in step (d) shall be
completed before executing the following: Device 0 shall write its self-diagnostic testing results to bits
6-0 in the Error register. Table 10 defines the results values;
j) Device 0 shall set its signature values (see 9.1). The effect on the Features register is undefined;
k) Clearing Status register bits:
1) If the PACKET command feature set is not implemented by Device 0, Device 0 shall clear to zero
bits 3, 2, and 0 of the Status register;
2) If the PACKET command feature set is implemented by Device 0, Device 0 shall clear to zero bits
5, 3, 2, and 0 of the Status register;

Page 216
 T13/1153D revision 18

l) Clearing BSY:
1) If the PACKET command feature set is not implemented by Device 0, then Steps (g), (h) (as
required), (i) and (j) shall be completed before executing the following: Device 0 shall clear the
BSY bit to zero when ready to accept commands that do not require the DRDY bit to be equal to
one.
2) If the PACKET command feature set is implemented by Device 0, then Device 0 shall return its
operating modes to their specified initial conditions: MODE SELECT conditions shall be restored to
their last saved values if saved values have been established; MODE SELECT conditions for which
no values have been saved shall be returned to their default values; then Device 0 shall clear the
BSY bit to zero when ready to accept commands;
m) Setting DRDY:
1) If the PACKET command feature set is not implemented by Device 0, then the DRDY bit shall be
set to one within 30 s after the BSY bit has been cleared to zero. Steps (l) (1) and (m) (1) may
occur at the same time;
2) If the PACKET command feature set is implemented by Device 0, then Device 0 shall not set
DRDY to one;

9.3.2 Software reset - device 1

The following steps should occur sequentially as listed. Several of the steps may occur concurrently or
outside of the listed sequence when explicitly allowed so long as all timing relationships are satisfied.

Steps (h) through (k) shall be completed within 30 s from Device 1 detecting that the SRST bit is cleared to
zero.

a) The host shall set the SRST bit to one in the Device Control register. The host shall not clear the SRST
bit to zero until at least 5 µs after setting the bit to one. The host shall not set the SRST bit to one until
the bit has been cleared to zero for at least 5 µs;
b) The device shall release INTRQ, IORDY, DMARQ, and DD(15:0) no later than 400 ns after detecting
that the SRST bit is equal to one;
c) Device 1 shall set the BSY bit to one no later than 400 ns after detecting that the SRST bit is equal to
one;
d) Device 1 shall negate PDIAG- no later than 1 ms after detecting that the SRST bit is equal to one;
e) Hardware initialization and self-diagnostic testing:
1) If the PACKET command feature set is not implemented by the device, the device shall begin
performing its hardware and self-diagnostic testing;
2) If the PACKET command feature set is implemented by the device, the device may begin
performing its hardware and self-diagnostic testing and the device is not expected to stop any
background device activity (e.g., immediate command (see MMC and MMC2)) that was started prior
to the time that the SRST was set to one in step (a);
f) Reverting to default:
1) If the PACKET command feature set is not implemented by Device 1, then Device 1 may revert to
its default condition (the device’s settings may now be in different conditions than they were before
the SRST bit was set to one by the host). However, the condition of any Ultra DMA mode (either
enabled or disabled) shall not be affected by the host setting the SRST bit to one;
2) If the PACKET command feature set is implemented by Device 1, then Device 1 shall not revert to
its default condition. However, the condition of any Ultra DMA mode (either enabled or disabled)
shall not be affected by the host setting the SRST bit to one;
g) Device 1 shall wait for the host to clear the SRST bit to zero before continuing;
h) If performed, the hardware initialization and self-diagnostic testing initiated in step (e) shall be
completed before executing the following: Device 1 shall write its self-diagnostic testing results to the
Error register. Table 10 defines the results values;
i) Device 1 shall set its signature values (see 9.1). The effect on the Features register is undefined;
j) Clearing Status register bits:
1) If the PACKET command feature set is not implemented by Device 1, Device 1 shall clear to zero
bits 3, 2, and 0 of the Status register;
2) If the PACKET command feature set is implemented by Device 1, Device 1 shall clear to zero bits
5, 3, 2, and 0 of the Status register;

Page 217
T13/1153D revision 18

k) Clearing BSY:
1) If the PACKET command feature set is not implemented by Device 1, then steps (h) and (i) shall be
completed before executing the following: Device 1 shall clear the BSY bit to zero when ready to
accept commands that do not require the DRDY bit to be equal to one;
2) If the PACKET command feature set is implemented by Device 1, then Device 1 shall return its
operating modes to their specified initial conditions: MODE SELECT conditions shall be restored to
their last saved values if saved values have been established; MODE SELECT conditions for which
no values have been saved shall be returned to their default values; then Device 1 shall clear the
BSY bit to zero when ready to accept commands;
l) Step (j) shall be completed before executing the following: If Device 1 passed its self-diagnostic testing,
then Device 1 shall assert PDIAG-;
m) Setting DRDY:
1) If the PACKET command feature set is not implemented by Device 1, then the DRDY bit shall be
set to one within 30 s after the BSY bit has been cleared to zero. Steps (k) (1), (l), and (m) (1) may
occur at the same time;
2) If the PACKET command feature set is implemented by Device 1, then Device 1 shall not set DRDY
to one;
n) Device 1 shall continue to assert PDIAG- until after the first command is received from the host or until
at least 31 s after detecting that SRST is cleared to zero or until detecting that the host has set the
SRST bit to one in the Device Control register, whichever comes first. Device 1 shall release PDIAG- no
later than command completion of the next command from the host except for the EXECUTE DEVICE
DIAGNOSTIC command.

t20
SRST

t21
Device 0 BSY

Device 0 DRDY

Device 0 PDIAG- out

Device 0 PDIAG- in

t22
t23
Device 1 BSY

Device 1 DRDY
t24
t25

Device 1 PDIAG- out

Figure 9 − BSY and DRDY timing for software reset

Page 218
 T13/1153D revision 18

Table 26 − BSY and DRDY timing for software reset

SRST timing parameters Min Max Note
t20 SRST bit set to one 5 µs
t21 Device 0 SRST set to one to BSY bit set to one, 400 ns
release PDIAG-
t22 Device 0 SRST cleared to zero to sample of PDIAG- 1 ms 31 s 1
t23 Device 1 SRST set to one to BSY set to one 400 ns
t24 Device 1 SRST cleared to zero to BSY bit cleared to 30 s 2
zero, PDIAG- asserted
t25 Device 1 negate PDIAG- if asserted 1 ms
NOTES −
1 Device 0 shall sample beginning 1 ms after SRST is cleared to zero. Sampling shall continue
until PDIAG- assertion by Device 1 is sensed or 31 s has elapsed indicating Device 1 failed
diagnostic.
2 Upon completion of internal diagnostics, Device 1 shall clear BSY to zero, and if diagnostics
passed, assert PDIAG-. Internal diagnostics shall complete within 30 s of the SRST being
cleared to zero.

9.4 DEVICE RESET protocol

If the host asserts RESET- before the device has completed executing a DEVICE RESET command, then
the device shall start executing its hardware reset sequence at step (b).

If the host sets the SRST bit to one before the device has completed executing a DEVICE RESET
command, the device shall start executing its software reset sequence at step (b).

The host should not issue a DEVICE RESET command while a DEVICE RESET command is in progress. If
the host issues a DEVICE RESET command while a DEVICE RESET command is in progress, the results
are indeterminate.

The following steps shall occur sequentially as listed.

Steps (b) through (i) shall be completed within 6 s from the device detecting that the command has been
written.

a) The host shall write the DEVICE RESET command in the Command register;
b) The selected device shall release INTRQ, IORDY, DMARQ, and DD(15:0) no later than 400 ns after
detecting that the command has been written;
c) The device shall set the BSY bit to one no later than 400 ns after detecting that the command has been
written;
d) The device should stop execution of any uncompleted command. The device is expected to end
background device activity (e.g., immediate commands (see MMC and MMC2));
e) The device should not revert to its default condition. If the device reverts to its default condition, the
device shall report a Unit Attention condition to a subsequent PACKET command;
f) The device shall clear bit 7 in the Error register to zero;
g) The device shall set its signature values (see 9.1). The effect on the Features register is undefined;
h) The device shall clear to zero bits 5, 3, 2, and 0 of the Status register;
i) MODE SELECT conditions shall not be altered;
j) The device shall clear the BSY bit to zero when ready to accept commands that do not require the
DRDY bit to be equal to one;
k) The device shall not set DRDY to one.

9.5 EXECUTE DEVICE DIAGNOSTIC protocol

The following steps should occur sequentially as listed. Several of the steps may occur concurrently or
outside of the listed sequence so long as all timing relationships are satisfied, e.g.: Device 0 may continue

Page 219
T13/1153D revision 18

to sample PDIAG- after Device 0 has completed writing the specified values to the Sector Count, Sector
Number, Cylinder Low, Cylinder High, and Device/Head registers.

If the host asserts RESET- before devices have completed executing their EXECUTE DEVICE
DIAGNOSTIC sequences, then the devices shall start executing their hardware reset sequence at step (b).

If the host sets the SRST bit in the Device Control register to one before the devices have completed
execution of their EXECUTE DEVICE DIAGNOSTIC sequences, then the devices shall start executing their
software reset sequences at step (b).

The host shall not begin polling the Status register until at least 2 ms after the EXECUTE DEVICE
DIAGNOSTIC command has been issued. The host should only interpret bits 6 and 7 of the Status register
to determine command completion.

9.5.1 EXECUTE DEVICE DIAGNOSTIC - Device 0

Device 0 performs the following operations for this command.

Steps (a) through (i) shall be completed within 6 s after the EXECUTE DEVICE DIAGNOSTIC command is
received:

a) The device shall release PDIAG-, INTRQ, IORDY, DMARQ, and DD(15:0) no later than 400 ns after the
EXECUTE DEVICE DIAGNOSTIC command is received;
b) Device 0 shall set the BSY bit to one no later than 400 ns after the EXECUTE DEVICE DIAGNOSTIC
command is received;
c) Device 0 should begin performing its self-diagnostic testing;
d) Steps (a), (b), and (c) shall be completed before continuing;
e) If Device 0 did not detect that DASP- was asserted by Device 1 during the most recent power cycle or
hardware reset, then Device 0 shall clear bit 7 to zero in the Error register and go to step (g);
f) If Device 0 detected that DASP- was asserted by Device 1 during the most recent power cycle or
hardware reset, then Device 0 shall sample PDIAG- for assertion by Device 1. Device 0 may sample
PDIAG- at any frequency. This sampling shall not begin until at least 1 ms after the EXECUTE DEVICE
DIAGNOSTIC command is received. Device 0 may stop sampling PDIAG- upon detection of assertion.
Device 0 shall not sample PDIAG- later than 6 s after the EXECUTE DEVICE DIAGNOSTIC command
is received after the next command is received;
1) If Device 0 detects that PDIAG- is asserted within 6 s after the EXECUTE DEVICE DIAGNOSTIC
command is received, then Device 0 shall clear bit 7 to zero in the Error register;
2) If Device 0 does not detect that PDIAG- is asserted within 6 s after the EXECUTE DEVICE
DIAGNOSTIC command is received, then Device 0 shall set bit 7 to one in the Error register;
g) If performed, the self-diagnostic testing initiated in step (c) shall be completed before executing the
following: Device 0 shall write its self-diagnostic testing results to bits 6-0 of the Error Register. Table
10 defines the results values;
h) Device 0 shall set its signature values (see 9.1). The effect on the Features register is undefined;
i) Clearing Status register bits:
1) If the PACKET command feature set is not implemented by Device 0, Device 0 shall clear to zero
bits 3, 2, and 0 of the Status register;
2) If the PACKET command feature set is implemented by Device 0, Device 0 shall clear to zero bits
5, 4, 3, 2, and 0 of the Status register;
j) Clearing BSY:
1) If the PACKET Command feature set is not implemented by Device 0, then Steps (e), (f) (as
required), (g) and (h) shall be completed before executing the following: Device 0 shall clear the
BSY bit to zero when ready to accept commands that do not require the DRDY bit to be equal to
one.
2) If the PACKET Command feature set is implemented by Device 0, then Device 0 shall return its
operating modes to their specified initial conditions: MODE SELECT conditions shall be restored to
their last saved values if saved values have been established; MODE SELECT conditions for which
no values have been saved shall be returned to their default values; then Device 0 shall clear the
BSY bit to zero when ready to accept commands;

Page 220
 T13/1153D revision 18

k) Setting DRDY:
1) If the PACKET Command feature set is not implemented by Device 0, then the DRDY bit shall be
set to one within 30 s after the BSY bit has been cleared to zero. Steps (i) (1) and (j) (1) may occur
at the same time;
2) If the PACKET Command feature set is implemented by Device 0, then Device 0 shall not set
DRDY to one;
l) After completing the above steps, Device 0 shall assert INTRQ if nIEN is cleared to zero.

9.5.2 EXECUTE DEVICE DIAGNOSTIC - Device 1

Device 1 performs the following operations for this command.

The following steps should occur sequentially as listed. Several of the steps may occur concurrently or
outside of the listed sequence so long as all timing relationships are satisfied.

Steps (a) through (i) shall be completed within 5 s after the EXECUTE DEVICE DIAGNOSTIC command is
received:

a) The device shall release INTRQ, IORDY, DMARQ, and DD(15:0) no later than 400 ns after the
EXECUTE DEVICE DIAGNOSTIC command is received;
b) Device 1 shall set the BSY bit to one no later than 400 ns after the EXECUTE DEVICE DIAGNOSTIC
command is received;
c) Device 1 shall negate PDIAG- no later than 1 ms after the EXECUTE DEVICE DIAGNOSTIC command
is received;
d) Device 1 should initiate performance of its self-diagnostic testing;
e) Steps (a), (b), (c), and (d) shall be completed before continuing.
f) If performed, the self-diagnostic testing initiated in step (d) shall be completed before executing the
following: Device 1 shall write its self-diagnostic testing results to the Error register. Table 10 defines
the results values;
g) Device 1 shall set its signature values (see 9.1). The effect on the Features register is undefined;
h) Clearing Status register bits:
1) If the PACKET command feature set is not implemented by Device 1, Device 1 shall clear to zero
bits 3, 2, and 0 of the Status register;
2) If the PACKET command feature set is implemented by Device 1, Device 1 shall clear to zero bits
5, 4, 3, 2, and 0 of the Status register;
i) Clearing BSY:
1) If the PACKET Command feature set is not implemented by Device 1, then steps (f) and (g) shall
be completed, , before executing the following: Device 1 shall clear the BSY bit to zero when ready
to accept commands that do not require the DRDY bit to be equal to one;
2) If the PACKET Command feature set is implemented by Device 1, then Device 1 shall return its
operating modes to their specified initial conditions: MODE SELECT conditions shall be restored to
their last saved values if saved values have been established; MODE SELECT conditions for which
no values have been saved shall be returned to their default values; then Device 1 shall clear the
BSY bit to zero when ready to accept commands;
j) Step (h) shall be completed before executing the following: If Device 1 passed its self-diagnostic testing
during step (d), then Device 1 shall assert PDIAG-;
k) Setting DRDY:
1) If the PACKET Command feature set is not implemented by Device 1, then the DRDY bit shall be
set to one within 30 s after the BSY bit has been cleared to zero. Steps (h) (1), (i), and (j) (1) may
occur at the same time;
2) If the PACKET Command feature set is implemented by Device 1, then Device 1 shall not set
DRDY to one;
l) Device 1 shall continue to assert PDIAG- until after the first command is received from the host or until
31 s after the EXECUTE DEVICE DIAGNOSTIC command is received or until detecting that the host
has set the SRST bit to one in the Device Control register, whichever comes first. Device 1 shall release
PDIAG- no later than command completion of the next command from the host except for the
EXECUTE DEVICE DIAGNOSTIC command.

Page 221
T13/1153D revision 18

EXECUTE DEVICE DIAGNOSTIC command received

t31
Device 0 BSY

Device 0 DRDY

Device 0 PDIAG- out

Device 0 PDIAG- in

t32
t33
Device 1 BSY

Device 1 DRDY
t34
t35

Device 1 PDIAG- out

Figure 10 − BSY and DRDY timing for diagnostic command

Table 27 − BSY and DRDY timing for diagnostic command

EXECUTE DEVICE DIAGNOSTIC timing parameters Min Max Note
t31 Device 0 command received to BSY bit set to one, 400 ns
release PDIAG-
t32 Device 0 command received to sample of PDIAG- 1 ms 6s 1
t33 Device 1 command received to BSY set to one 400 ns
t34 Device 1 command received to BSY bit cleared to 5s 2
zero, PDIAG- asserted
t35 Device 1 negate PDIAG- if asserted 1 ms
NOTES −
1 Device 0 shall sample beginning 1 ms after receipt of the command. Sampling shall
continue until PDIAG- assertion by Device 1 is sensed or 6 s has elapsed indicating
Device 1 failed diagnostic.
2 Upon completion of internal diagnostics, Device 1 shall clear BSY to zero, and if
diagnostics passed, assert PDIAG-. Internal diagnostics shall complete within 5 s of the
receipt of the command.

Page 222
 T13/1153D revision 18

9.6 Device selection protocol

Before issuing any command to a device except the DEVICE RESET command, the host shall insure that
the selected device is no longer busy, select the desired device, and insure that it is ready to accept a
command. Figure 11 describes the protocol for device selection.

Start

Host: Read Status or Alternate Status register

Host: No
BSY=0 &
DRQ=0?

Yes
Host: Write the Device/Head register with appropriate
DEV bit value (The host shall wait at least 400 ns before
reading the Status register to ensure the content is valid.)

Host: Read Status or Alternate Status register

Host: No
BSY=0 &
DRQ=0 ?

Yes

End

Figure 11 − Device selection protocol

Page 223
T13/1153D revision 18

9.7 PIO data in command protocol

This class includes:

− CFA TRANSLATE SECTOR

− IDENTIFY DEVICE
− IDENTIFY PACKET DEVICE
− READ BUFFER
− READ MULTIPLE
− READ SECTOR(S)
− SMART READ DATA

Execution of this class of command includes the transfer of one or more blocks of data from the device to
the host. Figure 12 describes the protocol of a PIO data in command. This description does not include all
possible error conditions.

Start

Host: Execute device selection

protocol described in 9.6

Host: Write any required command parameters to the

Features, Sector Count, Sector Number, Cylinder
High, Cylinder Low, and Device/Head registers

Host: Write command code to the Command register

(The host shall wait at least 400 ns before reading
the Status register to ensure the content is valid.)

Device: Set BSY=1 and begin command execution

Figure 12 − PIO data in command protocol(continued)

Page 224
 T13/1153D revision 18

Device: Yes
Error to Device: Set error status
report?
NOTE − Some devices
may assert DRQ at this
No time.
Device: When ready to transfer data block, set DRQ=1
Device:Clear BSY=0

Device: Clear BSY=0

B

Device: Yes
Device: Assert INTRQ
nIEN=0 ?

NOTE − This Host: Read Status

No
prevents register
polling host Host: Read Alternate Status
from reading register and ignore results
status before it
is valid. Device: Negate INTRQ
Host: Read Status register

NOTE − Status
register is read to
clear pending
interupt. Host: No
BSY=0 &
DRQ=1?

Yes

Host: Read Data register

No Device:
DRQ block
transfer
complete ?

Yes

Figure 12 − PIO data in command protocol(continued)

Page 225
T13/1153D revision 18

See 7.15.6.1
Device:
All data for No
Device: Set BSY=1
command
transferred?

Device: Clear DRQ=0

Yes

Device: Clear DRQ=0

A
NOTE − This
prevents Host: Read Alternate
polling host Status register and
from reading ignore results B
status before
it is valid
No
Host: Read of Status register Device:
recommended nIEN=0 ?

NOTE − Status Yes

register is read to
clear pending Device: Assert INTRQ
interupt.

Host: Read Status register

Device: Negate INTRQ

End

NOTE − Device: Command is complete (see 7.15.6.1 and 7.15.6.4).

Host: a) Should perform its error routine if an error is reported.
b) May issue another command to device.
c) May select other device and issue it a command.

Figure 12 − PIO data in command protocol(concluded)

Page 226
 T13/1153D revision 18

9.8 PIO data out command protocol

This class includes:

− CFA WRITE MULTIPLE WITHOUT ERASE

− CFA WRITE SECTORS WITHOUT ERASE
− DOWNLOAD MICROCODE
− SECURITY DISABLE PASSWORD
− SECURITY ERASE UNIT
− SECURITY SET PASSWORD
− SECURITY UNLOCK
− WRITE BUFFER
− WRITE MULTIPLE
− WRITE SECTOR(S)

Execution of this class of command includes the transfer of one or more blocks of data from the host to the
device. Figure 13 describes the protocol of a PIO data out command. This description does not include all
possible error conditions.

Start

Host: Execute device selection

protocol described in 9.6

Host: Write any required command parameters to the

Features, Sector Count, Sector Number, Cylinder
High, Cylinder Low, and Device/Head registers

Host: Write command code to the Command register

(The host shall wait at least 400 ns before reading
the Status register to ensure the content is valid.)

Device: Set BSY=1 and begin command execution

Device: Yes
Device: Set error status
Error ?

No D

Figure 13 − PIO data out command protocol(continued)

Page 227
T13/1153D revision 18

Device: When ready to transfer data block, set DRQ=1

Device: Clear BSY=0

Host: Read Status or Alternate Status register

No Host:
BSY=0 &
DRQ=1?

Yes

Host: Write Data register C

No Device;
DRQ block
transfer
complete?

Yes

Device: Set BSY=1 and DRQ=0 See 7.15.6.1

Yes Device:
Error?

No

Device:
No
All data for
Device:Set error status B
command
transferred?

Yes

Figure 13 − PIO data out command protocol(continued)

Page 228
 T13/1153D revision 18

Device: When ready to transfer

data block, set DRQ=1

Device: Clear BSY=0

NOTE − This
Host: Read Alternate prevents a
Device: No Status register and polling host from
nIEN=0 ? ignore results reading status
before it is valid.
Yes Host: Read
Status register NOTE −
Device: Assert INTRQ Status
register is
read to clear
Host: No pending
Host: Read Status register
BSY=0 & interupt.
DRQ=1 ?

Yes
Device; Negate INTRQ

Figure 13 − PIO data out command protocol(continued)

Page 229
T13/1153D revision 18

Device: Clear BSY=0

No
Device:
nIEN=0 ? NOTE − This
Host: Read prevents
Yes Alternate Status polling host
register and from reading
Device: Assert INTRQ ignore results status before it
is valid.

Host: Read Status register Host: Read of Status

register recommended

NOTE − Status
Device : Negate INTRQ
register is read to
clear pending
interupt.
End
NOTE − Device: Command is complete (see 7.15.6.1 and 7.15.6.4).
Host: a) Should perform its error routine if an error is reported.
b) May issue another command to device.
c) May select other device and issue it a command.

Figure 13 − PIO data out command protocol(concluded)

Page 230
 T13/1153D revision 18

9.9 Non-data command protocol

This class includes:

− CFA ERASE SECTORS

− CFA REQUEST EXTENDED ERROR CODE
− CHECK POWER MODE
− FLUSH CACHE
− GET MEDIA STATUS
− IDLE
− IDLE IMMEDIATE
− INITIALIZE DEVICE PARAMETERS
− MEDIA EJECT
− MEDIA LOCK
− MEDIA UNLOCK
− NOP
− READ NATIVE MAX ADDRESS
− READ VERIFY SECTOR(S)
− SECURITY ERASE PREPARE
− SECURITY FREEZE LOCK
− SEEK
− SET FEATURES
− SET MAX ADDRESS
− SET MULTIPLE MODE
− SLEEP
− SMART DISABLE OPERATION
− SMART ENABLE/DISABLE AUTOSAVE
− SMART ENABLE OPERATION
− SMART EXECUTE OFFLINE IMMEDIATE
− SMART RETURN STATUS
− STANDBY
− STANDBY IMMEDIATE

Execution of these commands involves no data transfer. Figure 14 describes the protocol of a no data
transfer command. This description does not include all possible error conditions.

See the NOP command description in 0 and the SLEEP command description in 8.40 for additional protocol
requirements.

Page 231
T13/1153D revision 18

Start

Host: Execute device selection

protocol described in 9.6

Host: Write any required command parameters to the

Features, Sector Count, Sector Number, Cylinder
High, Cylinder Low, and Device/Head registers

Host: Write command code to the Command register

(The host shall wait at least 400 ns before reading the
Status register to ensure the content is valid.)

Device: Set BSY=1 and execute command

No
Device:
Error ?

Yes

Device: Set error status

Device: Clear BSY=0

No
Device:
nIEN=0 ?

Yes NOTE − Status

register is read to
Device: Assert INTRQ
clear pending
interupt.

Host: Read Status register Host: Read of Status register

recommended

Device: Negate INTRQ

End
NOTE − Device: Command is complete (see 7.15.6.1 and 7.15.6.4).
Host: a) Should perform its error routine if an error is reported.
b) May issue another command to device.
c) May select other device and issue it a command.

Figure 14 − Non-data command protocol

Page 232
 T13/1153D revision 18

9.10 DMA command protocol

This class comprises:

− READ DMA
− WRITE DMA

Data transfers using DMA commands differ in two ways from PIO transfers:

1) data transfers are performed using the DMA channel;

2) A Single interrupt is issued at command completion.

Initiation of the DMA transfer commands is identical to the READ SECTOR(S) or WRITE SECTOR(S)
commands except that the host initializes the DMA channel prior to issuing the command.

The interrupt handler for DMA transfers is different in that no intermediate sector interrupts are issued on
multi-sector commands.

Figure 15 describes the protocol of a DMA command..

Start

Host: Execute device selection

protocol described in 9.6

Host: Write any required command parameters to the

Features, Sector Count, Sector Number, Cylinder
High, Cylinder Low, and Device/Head registers

Host: Write command code to the Command register

(The host shall wait at least 400 ns before reading
the Status register to ensure the content is valid.)

Device: Set BSY=1 and begin command execution

Device: Yes
B
Error ?

No

Figure 15 − DMA command protocol(continued)

Page 233
T13/1153D revision 18

Device: Set BSY=1, or BSY=0 and DRQ=1

Device: When ready to transfer data, assert DMARQ

Host: When ready to transfer data, assert DMACK-

NOTE − Transfer data as

described in Multiword DMA
timing or Ultra DMA protocol

Device: No
Transfer
done?

Yes

No
Device:
Error ?

Yes

B Device: Set error status

Device: Clear BSY=0 and DRQ=0

No
Device:
nIEN=0 ?

Yes NOTE − Status

register is read to
Device: Assert INTRQ
clear pending
interupt.

Host: Read Status register Host: Read of Status register

recommended

Device: Negate INTRQ

End
NOTE − Device: Command is complete (see 7.15.6.1 and 7.15.6.4).
Host: a) Should perform its error routine if an error is reported.
b) May issue another command to device.
c) May select other device and issue it a command.
Figure 15 − DMA command protocol(concluded)

Page 234
 T13/1153D revision 18

9.11 PACKET command protocol

This class comprises:

− PACKET
− SERVICE

The use of the PACKET command includes two different protocols. Figure 16 describes the use of the
PACKET command for non data transfer and PIO data transfer commands. Figure 17 describes DMA
transfer commands.

Start

Host: Execute device selection

protocol described in 9.6

Host: Write any required command parameters to the

Features, Sector Count, Sector Number, Cylinder
High, Cylinder Low, and Device/Head registers

Host: Write command code to the Command register

(The host shall wait at least 400 ns before reading
the Status register to ensure the content is valid.)

Device: Set BSY=1 and prepares to accept

command packet

Device: Yes
Error ? C

No

Device: When ready to accept command

packet, set C/D=1, clear I/O=0, clear REL=0

Device: Set DRQ=1

NOTE − Some devices prior to
ATA/ATAPI-4 set DRDY=1 at this point.
Device: Clear BSY=0

Figure 16 − PACKET non-data and PIO data command protocol(continued)

Page 235
T13/1153D revision 18

A
NOTE − Some devices prior to ATA/ATAPI-4
assert INTRQ if enabled at this point. See
IDENTIFY PACKET DEVICE, word 0, bits 5-6
to determine if an interrupt will occur.

Host: Read Status or Alternate Status register

No Host:
BSY=0 &
DRQ=1?

Yes

Host: Write Data register

No Host:
Command
packet transfer
complete ?

Yes

Device: Set BSY=1 and DRQ=0

Device: Yes
Error ? C

No

Device: No
Data transfer Device: Execute non
required? data transfer command

Yes
D
B

Figure 16 − PACKET non-data and PIO data command protocol(continued)

Page 236
 T13/1153D revision 18

Device:
Yes
Overlap supported,
enabled and F
OVL set ?

No
Device: When ready to transfer data block; set Tag; byte G
count; I/O=1 for data in, I/O=0 for data out; C/D=0, DRQ=1

Device: Clear BSY=0

Device: Yes
K Device: Assert INTRQ
nIEN=0 ?

No Host: Read Status

NOTE − This register (clear interrupt)
prevents polling host Host: Read Alternate
from reading status Status register and ignore
before it is valid. results
Device: Negate INTRQ

J Host: Read Status register

NOTE − Status
register is read to
clear pending
Host: No
interupt.
BSY=0 &
DRQ=1?

Yes

Host: Read or write Data register

Device:
No
DRQ block
transfer
complete ?

Yes

Figure 16 − PACKET non-data and PIO data command protocol(continued)

Page 237
T13/1153D revision 18

Device: Set BSY=1

Device: Clear DRQ=0

Device:
No No
All data for Device:
command B
Error?
transferred?

Yes Yes

Device: Yes Device: Set error

D C
Error? status

No

Device: Set I/O=1, C/D=1, DRDY=1, REL=0

Device: Clear BSY=0

No
Device:
nIEN=0 ?
NOTE − This
Host: Read Alternate prevents polling
Yes Status register and host from
ignore results reading status
Device: Assert INTRQ before it is valid.

Host: Read Status register Host: Read of Status register

recommended

Device: Negate INTRQ NOTE − Status

register is read to
clear pending
End interupt.

NOTE − Device: Command is complete (see 7.15.6.1 and 7.15.6.4).

Host: a) Should perform its error routine if an error is reported.
b) May issue another command to the device.
c) May select other device and issue it a command.
Figure 16 − PACKET non-data and PIO data command protocol(continued)

Page 238
 T13/1153D revision 18

Device:
Yes Bus release
interrupt
enabled ?

No

Device: No
Bus G
release ?

Yes

Device: Set REL, clear I/O=0,C/D=0

Device: Clear BSY

Device:
No
Bus release
interrupt
enabled ?

Yes

Device: Yes
Device: Assert INTRQ
nIEN=0 ?

NOTE − This Host: Read Status

No
prevents register
polling host Host: Read Alternate Status
from reading register and ignore results
status before
it is valid. Device: Negate INTRQ
Host: Read Status register

NOTE − Status
register is read to
clear pending
Host: No
interupt.
BSY=0 &
DRQ=0?

Yes

H
Figure 16 − PACKET non-data and PIO data command protocol
(continued)

Page 239
T13/1153D revision 18

H
NOTE − The device has performed a bus release at this
point.
The host may:
a) issue another command if the device
supports queuing.
b) select the other device and issue it
commands.
c) if overlapped commands are outstanding
to both devices, the host may poll INTRQ
by first selecting one device, then selecting
the other device.
See 6.6 and 6.7.

Device: When ready to transfer

data, set SERV=1

Host: No
Host: Write Device/Head register to
Device
select device (The host shall wait at
selected?
least 400ns before reading the Status
register to ensure the content is valid.)
Yes

Device: Yes
Device: Assert INTRQ
nIEN=0?

NOTE − This No
prevents
polling host Host: Read Alternate Status Host: Read Status register
from reading register and ignore results
status before it
is valid.
Host: Read Status register Device: Negate INTRQ

NOTE − Status
register is read to
clear pending
No Host:
interupt.
SERV=1 &
BSY=0?

Yes

Figure 16 − PACKET non-data and PIO data command protocol

(continued)

Page 240
 T13/1153D revision 18

Host: Write SERVICE command (A2h) to Command

register (The host shall wait at least 400 ns before
reading the Status register to ensure the content is valid.)

Device: Set BSY=1 and begin SERVICE execution

Device: Yes
Device: Set error status
Error ?

No C
Device: When ready to transfer data block; set Tag;
byte count; SERV=0; C/D=0; REL=0, I/O=1 for data NOTE − If another queued
in, I/O=0 for data out; DRQ=1 command is ready for service,
SERV shall remain equal to one.

Device: Clear BSY=0

Device:
Yes
Service
K
interrupt
enabled?

No

Figure 16 − PACKET non-data and PIO data command protocol

(concluded)

Page 241
T13/1153D revision 18

Start

Host: Execute device selection

protocol described in 9.6

Host: Write any required command parameters to the

Features, Sector Count, Sector Number, Cylinder
High, Cylinder Low, and Device/Head registers

Host: Write command code to the Command register

(The host shall wait at least 400 ns before reading
the Status register to ensure the content is valid.)

Device: Set BSY=1 and prepares to accept

command packet

Device: Yes
Error ? C

No

Device: When ready to accept command packet,

set C/D=1, clear I/O=0

Device: Set DRQ=1 NOTE − Some devices prior to

ATA/ATAPI-4 set DRDY=1 at this point.
Device: Clear BSY=0

Figure 17 − PACKET DMA command protocol

(continued)

Page 242
 T13/1153D revision 18

A
NOTE − Some devices prior to ATA/ATAPI-4
assert INTRQ if enabled at this point. See
IDENTIFY PACKET DEVICE, word 0, bits 5-6
to determine if an interrupt will occur.

Host: Read Status or Alternate Status register

No Host:
BSY=0 &
DRQ=1?

Yes

Host: Write Data register

No Host:
Command
packet transfer
complete ?

Yes

Device: Set BSY=1 and DRQ=0

Device: Yes
Error ? C

No

Device: No
Data transfer Device: Execute non
required? data transfer command

Yes
D
B

Figure 17 − PACKET DMA command protocol(continued)

Page 243
T13/1153D revision 18

Device: Yes
Overlap supported, F
enabled & OVL set ?

No
Device: When ready to transfer data block; I/O=1 for data G
in, I/O=0 for data out, C/D=0, REL=0, SERV=0, DMRD=1,
DRQ=1
NOTE − If another queued
command is ready for service,
SERV shall remain equal to
Device: Clear BSY=0 one.

Device: When ready to transfer data, assert DMARQ J

Host: When ready to transfer data, assert DMACK-

NOTE − Transfer data as

described in Multi Word DMA
timing or Ultra DMA protocol

Figure 17 − PACKET DMA command protocol(continued)

Page 244
 T13/1153D revision 18

Device:
No No
All data for Device:
command B
Error?
transferred?

Yes Yes

Device: Yes Device: Set error

D C
Error? status

No

Device: Set I/O=1, C/D=1, DRDY=1,

DRQ=0

Device: Clear BSY=0

No
Device:
nIEN=0 ?

Yes NOTE − Status

register is read to
Device: Assert INTRQ clear pending
interupt.

Host: Read Status register Host: Read of Status register

recommended

Device: Negate INTRQ

End
NOTE − Device: Command is complete (see 7.15.6.1 and 7.15.6.4).
Host: a) Should perform its error routine if an error is reported.
b) May issue another command to the device.
c) May select other device and issue it a command.
Figure 17 − PACKET DMA command protocol(continued)

Page 245
T13/1153D revision 18

Device:
Yes Bus release
interrupt
enabled ?

No

Device: No
Bus G
release ?

Yes

Device: Set REL=1, clear I/O=0,C/D=0

Device: Clear BSY=0

Device:
No
Bus release
interrupt
enabled ?

Yes

Device: Yes
Device: Assert INTRQ
nIEN=0 ?

No Host: Read Status

register
Host: Read Status register

NOTE − Status Device: Negate INTRQ

register is read to
clear pending
Host: No
interrupt.
BSY=0 &
DRQ=0?

Yes

Figure 17 − PACKET DMA command protocol(continued)

Page 246
 T13/1153D revision 18

H
NOTE − The device has performed a bus release at this
point.
The host may:
a) issue another command if the device
supports queuing.
b) select the other device and issue it
commands.
c) if overlapped commands are outstanding
to both devices, the host may poll INTRQ
by first selecting one device, then selecting
the other device.
See 6.6 and 6.7.

Device: When ready to transfer

data, set SERV=1

Host: No
Host: Write Device/Head register to
Device
select device (The host shall wait at
selected?
least 400ns before reading the Status
register to ensure the content is valid.)
Yes

Device: Yes
Device: Assert INTRQ
nIEN=0?
NOTE − Status
register is read to
clear pending No
interupt.
Host: Read Status register Host: Read Status register

No Host: Device: Negate INTRQ

SERV=1 &
BSY=0?

Yes

Figure 17 − PACKET DMA command protocol(continued)

Page 247
T13/1153D revision 18

Host: Write SERVICE command (A2h) to Command

register (The host shall wait at least 400 ns before
reading the Status register to ensure the content is valid.)

Device: Set BSY=1 and begin SERVICE execution

Device: Yes
Device: Set error status
Error ?

No C
Device: When ready to transfer data block; set Tag;
byte count; SERV=0; C/D=0; REL=0, I/O=1 for data NOTE − If another queued
in, I/O=0 for data out; DRQ=1 command is ready for service,
SERV shall remain equal to one.

Device: Clear BSY=0

Device: No
Service
J
interrupt
enabled?

Yes

Device: Yes
Device: Assert INTRQ
nIEN=0 ?
NOTE − Status
register is read to
clear pending interrupt No Host: Read Status register
Host: Read Status register

Device: Negate INTRQ

No
Host:
BSY=1 ?

Yes

Figure 17 − PACKET DMA command protocol(concluded)

Page 248
 T13/1153D revision 18

9.12 READ/WRITE DMA QUEUED command protocol

This class includes:

− READ DMA QUEUED

− SERVICE
− WRITE DMA QUEUED

Figure 18 describes the execution of a READ DMA QUEUED or WRITE DMA QUEUED command.

Start

Host: Execute device selection

protocol described in 9.6

Host: Write any required command parameters to the

Features, Sector Count, Sector Number, Cylinder
High, Cylinder Low, and Device/Head registers

Host: Write command code to the Command register

(The host shall wait at least 400 ns before reading
the Status register to ensure the content is valid.)

Device: Set BSY=1 and begin command execution

Device: Yes
D Error ? B

No

Device: No
Data ready ? C

Yes
Device: Set Tag, SERV=0, C/D=0, I/O NOTE − If another queued
appropriately, REL=0, DRQ=1 command is ready for
service, SERV shall remain
equal to one.
Device: Clear BSY=0

Figure 18 − READ/WRITE DMA QUEUED command protocol

(continued)

Page 249
T13/1153D revision 18

NOTE − When DMARQ has been asserted at least

A
one data word shall be transferred.

Device: When ready to transfer data, assert DMARQ

Host: When ready to transfer data, assert DMACK-

NOTE − Transfer data as

described in Multi Word DMA
timing or Ultra DMA protocol

Device: No
Transfer
done?

Yes

No
Device:
Error ?

Yes

B Device: Set error status

Device: Set Tag, SERV=0, I/O=1, C/D=1, REL=0, DRQ=0

NOTE − If another queued
Device Clear BSY=0 command is ready for
service, SERV shall remain
equal to one.

No
Device:
nIEN=0 ?

Yes

Device: Assert INTRQ NOTE − Status register

is read to clear pending
interrupt
Host: Read Status register Host: Read of Status register
recommended

Device: Negate INTRQ

End
NOTE − Device: Command is complete (see 7.15.6.1 and 7.15.6.4).
Host: a) Should perform its error routine if an error is reported.
b) May issue another command to device.
c) May select other device and issue it a comand.
Figure 18 − READ/WRITE DMA QUEUED command protocol
(continued)

Page 250
 T13/1153D revision 18

Device: Set REL=1, I/O=0, C/D=0

Device: Clear BSY=0

Device:
No
Bus release
interrupt
enabled ?

Yes

Device: Yes
Device: Assert INTRQ
nIEN=0 ?

No Host: Read Status

register
Host: Read Status register

NOTE − Status Device: Negate INTRQ

register is read to
clear pending
Host: No
interrupt.
BSY=0 &
DRQ=0?

Yes

NOTE − The device has performed a bus release.

The host may:
a) issue another command if the device
supports queuing.
b) select the other device and issue it
commands.
c) if overlapped commands are outstanding
to both devices, the host may poll INTRQ
by first selecting one device, then selecting
the other device.
See 6.6 and 6.7.

Figure 18 − READ/WRITE DMA QUEUED command protocol

(continued)

Page 251
T13/1153D revision 18

Device: When ready to transfer

data, set SERV=1

Host: No
Host: Write Device/Head register to
Device select device (The host shall wait at
selected? least 400 ns before reading the Status
register to ensure the content is valid.)
Yes

Device: Yes
Device: Assert INTRQ
nIEN=0?
NOTE − Status
register is read to
clear pending No Host: Read Status register
interrupt
Host: Read Status register

Device: Negate INTRQ

No
Host:
BSY=0?

Yes

Host: Write SERVICE command (A2h) to Command

register (The host shall wait at least 400 ns before
reading the Status register to ensure the content is valid.)

Device: Set BSY=1 and begin SERVICE execution

Figure 18 − READ/WRITE DMA QUEUED command protocol

(concluded)

Page 252
 T13/1153D revision 18

9.13 Ultra DMA data in commands

9.13.1 Initiating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see
10.2.4.1 and 10.2.4.2 for specific timing requirements):

a) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.
b) The device shall assert DMARQ to initiate an Ultra DMA burst. After assertion of DMARQ the device
shall not negate DMARQ until after the first negation of DSTROBE.
c) Steps (c), (d), and (e) may occur in any order or at the same time. The host shall assert STOP.
d) The host shall negate HDMARDY-.
e) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-, DA2, DA1,
and DA0 negated until after negating DMACK- at the end of the burst.
f) Steps (c), (d), and (e) shall have occurred at least tACK before the host asserts DMACK-. The host shall
keep DMACK- asserted until the end of an Ultra DMA burst.
g) The host shall release DD(15:0) within tAZ after asserting DMACK-.
h) The device may assert DSTROBE tZIORDY after the host has asserted DMACK-. Once the device has
driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK- at
the end of an Ultra DMA burst.
i) The host shall negate STOP and assert HDMARDY- within tENV after asserting DMACK-. After negating
STOP and asserting HDMARDY-, the host shall not change the state of either signal until after receiving
the first transition of DSTROBE from the device (i.e., after the first data word has been received).
j) The device shall drive DD(15:0) no sooner than tZAD after the host has asserted DMACK-, negated
STOP, and asserted HDMARDY-.
k) The device shall drive the first word of the data transfer onto DD(15:0). This step may occur when the
device first drives DD(15:0) in step (j).
l) To transfer the first word of data the device shall negate DSTROBE within tFS after the host has negated
STOP and asserted HDMARDY-. The device shall negate DSTROBE no sooner than tDVS after driving
the first word of data onto DD(15:0).

9.13.2 The data in transfer

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see
10.2.4.3 and 10.2.4.2):

a) The device shall drive a data word onto DD(15:0).

b) The device shall generate a DSTROBE edge to latch the new word no sooner than tDVS after changing
the state of DD(15:0). The device shall generate a DSTROBE edge no more frequently than tCYC for the
selected Ultra DMA mode. The device shall not generate two rising or two falling DSTROBE edges
more frequently than 2t cyc for the selected Ultra DMA mode.
c) The device shall not change the state of DD(15:0) until at least tDVH after generating a DSTROBE edge
to latch the data.
d) The device shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA burst is
paused, whichever occurs first.

9.13.3 Pausing an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see
10.2.4.4 and 10.2.4.2 for specific timing requirements).

9.13.3.1 Device pausing an Ultra DMA data in burst

a) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has
been transferred.
b) The device shall pause an Ultra DMA burst by not generating DSTROBE edges.

Page 253
T13/1153D revision 18

c) NOTE − The host shall not immediately assert STOP to initiate Ultra DMA burst termination when the
device stops generating STROBE edges. If the device does not negate DMARQ, in order to initiate
ULTRA DMA burst termination, the host shall negate HDMARDY- and wait t RP before asserting STOP.
d) The device shall resume an Ultra DMA burst by generating a DSTROBE edge.

9.13.3.2 Host pausing an Ultra DMA data in burst

a) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been
transferred.
b) The host shall pause an Ultra DMA burst by negating HDMARDY-.
c) The device shall stop generating DSTROBE edges within tRFS of the host negating HDMARDY-.
d) If the host negates HDMARDY- within tSR after the device has generated a DSTROBE edge, then the
host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY-
greater than tSR after the device has generated a DSTROBE edge, then the host shall be prepared to
receive zero, one or two additional data words. The additional data words are a result of cable round
trip delay and t RFS timing for the device.
e) The host shall resume an Ultra DMA burst by asserting HDMARDY-.

9.13.4 Terminating an Ultra DMA data in burst

9.13.4.1 Device terminating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see
10.2.4.5 and 10.2.4.2 for specific timing requirements):

a) The device shall initiate termination of an Ultra DMA burst by not generating DSTROBE edges.
b) The device shall negate DMARQ no sooner than tSS after generating the last DSTROBE edge. The
device shall not assert DMARQ again until after the Ultra DMA burst is terminated.
c) The device shall release DD(15:0) no later than t AZ after negating DMARQ.
d) The host shall assert STOP within tLI after the device has negated DMARQ. The host shall not negate
STOP again until after the Ultra DMA burst is terminated.
e) The host shall negate HDMARDY- within tLI after the device has negated DMARQ. The host shall
continue to negate HDMARDY- until the Ultra DMA burst is terminated. Steps (d) and (e) may occur at
the same time.
f) The host shall drive DD(15:0) no sooner than tZAH after the device has negated DMARQ. For this step,
the host may first drive DD(15:0) with the result of its CRC calculation (see 9.15);
g) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP.
No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE.
DSTROBE shall remain asserted until the Ultra DMA burst is terminated.
h) If the host has not placed the result of its CRC calculation on DD(15:0) since first driving DD(15:0)
during (f), the host shall place the result of its CRC calculation on DD(15:0) (see 9.15).
i) The host shall negate DMACK- no sooner than tMLI after the device has asserted DSTROBE and
negated DMARQ and the host has asserted STOP and negated HDMARDY-, and no sooner than tDVS
after the host places the result of its CRC calculation on DD(15:0).
j) The device shall latch the host’s CRC data from DD(15:0) on the negating edge of DMACK-.
k) The device shall compare the CRC data received from the host with the results of its own CRC
calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command,
at the end of the command the device shall report the first error that occurred (see 9.15).
l) The device shall release DSTROBE within t IORDYZ after the host negates DMACK-.
m) The host shall not negate STOP nor assert HDMARDY- until at least tACK after negating DMACK-.
n) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating
DMACK.

9.13.4.2 Host terminating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see
10.2.4.6 and 10.2.4.2 for specific timing requirements):

Page 254
 T13/1153D revision 18

a) The host shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst
has been transferred.
b) The host shall initiate Ultra DMA burst termination by negating HDMARDY-. The host shall continue to
negate HDMARDY- until the Ultra DMA burst is terminated.
c) The device shall stop generating DSTROBE edges within tRFS of the host negating HDMARDY-.
d) If the host negates HDMARDY- within tSR after the device has generated a DSTROBE edge, then the
host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY-
greater than tSR after the device has generated a DSTROBE edge, then the host shall be prepared to
receive zero, one or two additional data words. The additional data words are a result of cable round
trip delay and t RFS timing for the device.
e) The host shall assert STOP no sooner than tRP after negating HDMARDY-. The host shall not negate
STOP again until after the Ultra DMA burst is terminated.
f) The device shall negate DMARQ within tLI after the host has asserted STOP. The device shall not assert
DMARQ again until after the Ultra DMA burst is terminated.
g) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP.
No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE.
DSTROBE shall remain asserted until the Ultra DMA burst is terminated.
h) The device shall release DD(15:0) no later than t AZ after negating DMARQ.
i) The host shall drive DD(15:0) no sooner than tZAH after the device has negated DMARQ. For this step,
the host may first drive DD(15:0) with the result of its CRC calculation (see 9.15).
j) If the host has not placed the result of its CRC calculation on DD(15:0) since first driving DD(15:0)
during (9), the host shall place the result of its CRC calculation on DD(15:0) (see 9.15).
k) The host shall negate DMACK- no sooner than tMLI after the device has asserted DSTROBE and
negated DMARQ and the host has asserted STOP and negated HDMARDY-, and no sooner than tDVS
after the host places the result of its CRC calculation on DD(15:0).
l) The device shall latch the host’s CRC data from DD(15:0) on the negating edge of DMACK-.
m) The device shall compare the CRC data received from the host with the results of its own CRC
calculation. If a miscompare error occurs during one or more Ultra DMA burst for any one command, at
the end of the command, the device shall report the first error that occurred (see 9.15) .
n) The device shall release DSTROBE within t IORDYZ after the host negates DMACK-.
o) The host shall neither negate STOP nor assert HDMARDY- until at least tACK after the host has negated
DMACK-.
p) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating
DMACK.

9.14 Ultra DMA data out commands

9.14.1 Initiating an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see
10.2.4.7 and 10.2.4.2 for specific timing requirements):

a) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.
b) The device shall assert DMARQ to initiate an Ultra DMA burst.
c) Steps (c), (d), and (e) may occur in any order or at the same time. The host shall assert STOP.
d) The host shall assert HSTROBE.
e) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-, DA2, DA1,
and DA0 negated until after negating DMACK- at the end of the burst.
f) Steps (c), (d), and (e) shall have occurred at least tACK before the host asserts DMACK-. The host shall
keep DMACK- asserted until the end of an Ultra DMA burst.
g) The device may negate DDMARDY- tZIORDY after the host has asserted DMACK-. Once the device has
negated DDMARDY-, the device shall not release DDMARDY- until after the host has negated DMACK-
at the end of an Ultra DMA burst.
h) The host shall negate STOP within tENV after asserting DMACK-. The host shall not assert STOP until
after the first negation of HSTROBE.
i) The device shall assert DDMARDY- within tLI after the host has negated STOP. After asserting
DMARQ and DDMARDY- the device shall not negate either signal until after the first negation of
HSTROBE by the host.

Page 255
T13/1153D revision 18

j) The host shall drive the first word of the data transfer onto DD(15:0). This step may occur any time
during Ultra DMA burst initiation.
k) To transfer the first word of data: the host shall negate HSTROBE no sooner than tUI after the device
has asserted DDMARDY-. The host shall negate HSTROBE no sooner than tDVS after the driving the
first word of data onto DD(15:0).

9.14.2 The data out transfer

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see
10.2.4.8 and 10.2.4.2 for specific timing requirements):

a) The host shall drive a data word onto DD(15:0).

b) The host shall generate an HSTROBE edge to latch the new word no sooner than tDVS after changing the
state of DD(15:0). The host shall generate an HSTROBE edge no more frequently than tCYC for the
selected Ultra DMA mode. The host shall not generate two rising or falling HSTROBE edges more
frequently than 2t cyc for the selected Ultra DMA mode.
c) The host shall not change the state of DD(15:0) until at least tDVH after generating an HSTROBE edge to
latch the data.
d) The host shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA burst is
paused, whichever occurs first.

9.14.3 Pausing an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see
10.2.4.9 and 10.2.4.2 for specific timing requirements).

9.14.3.1 Host pausing an Ultra DMA data out burst

a) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been
transferred.
b) The host shall pause an Ultra DMA burst by not generating an HSTROBE edge.
NOTE − The device shall not immediately negate DMARQ to initiate Ultra DMA burst
termination when the host stops generating HSTROBE edges. If the host does not assert
STOP, in order to initiate Ultra DMA burst termination, the device shall negate DDMARDY- and
wait tRP before negating DMARQ.
c) The host shall resume an Ultra DMA burst by generating an HSTROBE edge.

9.14.3.2 Device pausing an Ultra DMA data out burst

a) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has
been transferred.
b) The device shall pause an Ultra DMA burst by negating DDMARDY-.
c) The host shall stop generating HSTROBE edges within tRFS of the device negating DDMARDY-.
d) If the device negates DDMARDY- within tSR after the host has generated an HSTROBE edge, then the
device shall be prepared to receive zero or one additional data words. If the device negates
DDMARDY- greater than tSR after the host has generated an HSTROBE edge, then the device shall be
prepared to receive zero, one or two additional data words. The additional data words are a result of
cable round trip delay and t RFS timing for the host.
e) The device shall resume an Ultra DMA burst by asserting DDMARDY-.

9.14.4 Terminating an Ultra DMA data out burst

9.14.4.1 Host terminating an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see
10.2.4.10 and 10.2.4.2 for specific timing requirements):

Page 256
 T13/1153D revision 18

a) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges.
b) The host shall assert STOP no sooner than tSS after it last generated an HSTROBE edge. The host
shall not negate STOP again until after the Ultra DMA burst is terminated.
c) The device shall negate DMARQ within tLI after the host asserts STOP. The device shall not assert
DMARQ again until after the Ultra DMA burst is terminated.
d) The device shall negate DDMARDY- within tLI after the host has negated STOP. The device shall not
assert DDMARDY- again until after the Ultra DMA burst termination is complete.
e) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated
DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition on
HSTROBE. HSTROBE shall remain asserted until the Ultra DMA burst is terminated.
f) The host shall place the result of its CRC calculation on DD(15:0) (see 9.15).
g) The host shall negate DMACK- no sooner than tMLI after the host has asserted HSTROBE and STOP
and the device has negated DMARQ and DDMARDY-, and no sooner than tDVS after placing the result of
its CRC calculation on DD(15:0).
h) The device shall latch the host’s CRC data from DD(15:0) on the negating edge of DMACK-.
i) The device shall compare the CRC data received from the host with the results of its own CRC
calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command,
at the end of the command, the device shall report the first error that occurred (see 9.15).
j) The device shall release DDMARDY- within t IORDYZ after the host has negated DMACK-.
k) The host shall neither negate STOP nor negate HSTROBE until at least t ACK after negating DMACK-.
l) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating
DMACK.

9.14.4.2 Device terminating an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see
10.2.4.11 and 10.2.4.2 for specific timing requirements):

a) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA
burst has been transferred.
b) The device shall initiate Ultra DMA burst termination by negating DDMARDY-.
c) The host shall stop generating an HSTROBE edges within tRFS of the device negating DDMARDY-.
d) If the device negates DDMARDY- within tSR after the host has generated an HSTROBE edge, then the
device shall be prepared to receive zero or one additional data words. If the device negates
DDMARDY- greater than tSR after the host has generated an HSTROBE edge, then the device shall be
prepared to receive zero, one or two additional data words. The additional data words are a result of
cable round trip delay and t RFS timing for the host.
e) The device shall negate DMARQ no sooner than tRP after negating DDMARDY-. The device shall not
assert DMARQ again until after the Ultra DMA burst is terminated.
f) The host shall assert STOP within tLI after the device has negated DMARQ. The host shall not negate
STOP again until after the Ultra DMA burst is terminated.
g) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated
DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition of
HSTROBE. HSTROBE shall remain asserted until the Ultra DMA burst is terminated.
h) The host shall place the result of its CRC calculation on DD(15:0) (see 9.15).
i) The host shall negate DMACK- no sooner than tMLI after the host has asserted HSTROBE and STOP
and the device has negated DMARQ and DDMARDY-, and no sooner than tDVS after placing the result of
its CRC calculation on DD(15:0).
j) The device shall latch the host’s CRC data from DD(15:0) on the negating edge of DMACK-.
k) The device shall compare the CRC data received from the host with the results of its own CRC
calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command,
at the end of the command, the device shall report the first error that occurred (see 9.15).
l) The device shall release DDMARDY- within t IORDYZ after the host has negated DMACK-.
m) The host shall neither negate STOP nor HSTROBE until at least t ACK after negating DMACK-.
n) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating
DMACK.

Page 257
T13/1153D revision 18

9.15 Ultra DMA CRC rules

The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra
DMA burst, and reporting any error that occurs at the end of a command.

1) Both the host and the device shall have a 16-bit CRC calculation function.
2) Both the host and the device shall calculate a CRC value for each Ultra DMA burst.
3) The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning
of an Ultra DMA burst before any data is transferred.
4) For each STROBE transition used for data transfer, both the host and the device shall calculate a new
CRC value by applying the CRC polynomial to the current value of their individual CRC functions and
the word being transferred. CRC is not calculated for the return of STROBE to the asserted state after
the Ultra DMA burst termination request has been acknowledged.
5) At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the
device on DD(15:0) with the negation of DMACK-.
6) The device shall then compare the CRC data from the host with the calculated value in its own CRC
calculation function. If the two values do not match, the device shall save the error and report it at the
end of the command. A subsequent Ultra DMA burst for the same command that does not have a CRC
error shall not clear an error saved from a previous Ultra DMA burst in the same command. If a
miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the
command, the device shall report the first error that occurred.
7) For READ DMA, WRITE DMA, READ DMA QUEUED, or WRITE DMA QUEUED commands: When a
CRC error is detected, it shall be reported by setting both ICRC and ABRT (bit 7 and bit 2 in the Error
register) to one. ICRC is defined as the “Interface CRC Error” bit. The host shall respond to this error by
re-issuing the command.
8) For a REQUEST SENSE packet command (see SPC T10/955D for definition of the REQUEST SENSE
command): When a CRC error is detected during transmission of sense data the device shall complete
the command and set CHK to one. The device shall report a Sense key of 0Bh (ABORTED
COMMAND). The device shall preserve the original sense data that was being returned when the CRC
error occurred. The device shall not report any additional sense data specific to the CRC error. The
host device driver may retry the REQUEST SENSE command or may consider this an unrecoverable
error and retry the command that caused the Check Condition.
9) For any packet command except a REQUEST SENSE command: If a CRC error is detected, the
device shall complete the command with CHK set to one. The device shall report a Sense key of 04h
(HARDWARE ERROR). The sense data supplied via a subsequent REQUEST SENSE command shall
report an ASC/ASCQ value of 08h/03h (LOGICAL UNIT COMMUNICATION CRC ERROR). Host
drivers should retry the command that resulted in a HARDWARE ERROR.

NOTE − If excessive CRC errors are encountered while operating in Ultra mode 2 or 1, the
host should select a slower Ultra mode. Caution: CRC errors are detected and reported only
while operating in an Ultra mode.

10) A host may send extra data words on the last Ultra DMA burst of a data out command. If a device
determines that all data has been transferred for a command, the device shall terminate the burst. A
device may have already received more data words than were required for the command. These extra
words are used by both the host and the device to calculate the CRC, but, on an Ultra DMA data out
burst, the extra words shall be discarded by the device.
11) The CRC generator polynomial is: G(X) = X16 + X12 + X5 + 1. Table 28 describes the equations for 16-
bit parallel generation of the resulting polynomial (based on a word boundary).

NOTE − Since no bit clock is available, the recommended approach for calculating CRC is
to use a word clock derived from the bus strobe. The combinational logic is then equivalent
to shifting sixteen bits serially through the generator polynomial where DD0 is shifted in first
and DD15 is shifted in last.

Page 258
 T13/1153D revision 18

DD(15:0) CRCIN (15:0:) CRCOUT (15:0)

Combinational Edge
Logic Triggered
f1-f16 Register
Device
Word
Clock

Figure 19 − Example Parallel CRC generator

Table 28 − Equations for parallel generation of a CRC polynomial

CRCIN0 = f16 CRCIN8 = f8 XOR f13
CRCIN1 = f15 CRCIN9 = f7 XOR f12
CRCIN2 = f14 CRCIN10 = f6 XOR f11
CRCIN3 = f13 CRCIN11 = f5 XOR f10
CRCIN4 = f12 CRCIN12 = f4 XOR f9 XOR f16
CRCIN5 = f11 XOR f16 CRCIN13 = f3 XOR f8 XOR f15
CRCIN6 = f10 XOR f15 CRCIN14 = f2 XOR f7 XOR f14
CRCIN7 = f9 XOR f14 CRCIN15 = f1 XOR f6 XOR f13
f1 = DD0 XOR CRCOUT15 f9 = DD8 XOR CRCOUT7 XOR f5
f2 = DD1 XOR CRCOUT14 f10 = DD9 XOR CRCOUT6 XOR f6
f3 = DD2 XOR CRCOUT13 f11 = DD10 XOR CRCOUT5 XOR f7
f4 = DD3 XOR CRCOUT12 f12 = DD11 XOR CRCOUT4 XOR f1 XOR f8
f5 = DD4 XOR CRCOUT11 XOR f1 f13 = DD12 XOR CRCOUT3 XOR f2 XOR f9
f6 = DD5 XOR CRCOUT10 XOR f2 f14 = DD13 XOR CRCOUT2 XOR f3 XOR f10
f7 = DD6 XOR CRCOUT9 XOR f3 f15 = DD14 XOR CRCOUT1 XOR f4 XOR f11
f8 = DD7 XOR CRCOUT8 XOR f4 f16 = DD15 XOR CRCOUT0 XOR f5 XOR f12

NOTES −
1 f = feedback
2 DD = Data to or from the bus
3 CRCOUT = 16-bit edge triggered result (current CRC)
4 CRCOUT(15:0) are sent on matching order bits of DD(15:0)
5 CRCIN = Output of combinatorial logic (next CRC)

Page 259
T13/1153D revision 18

9.16 Single device configurations

9.16.1 Device 0 only configurations

In a single device configuration where Device 0 is the only device and the host selects Device 1, Device 0
shall respond as follows:

1) A write to the Device Control register shall complete as if Device 0 was the selected device;
2) A write to a Command Block register, other than the Command register, shall complete as if
Device 0 was selected;
3) A write to the Command register shall be ignored, except for EXECUTE DEVICE DIAGNOSTIC;
4) A read of the Control Block or Command Block registers, other than the Status or Alternate
Status registers, shall complete as if Device 0 was selected;
5) A read of the Status or Alternate status register shall return the value 00h.

NOTE − Even though Device 1 is not present, the register content may appear valid for
Device 1. Further means may be necessary to determine the existence of Device 1, e.g.,
issuing a command.

9.16.2 Device 1 only configurations

Host support of Device 1 only configurations is host specific.

In a single device configuration where Device 1 is the only device and the host selects Device 0, Device 1
shall respond to accesses of the Command Block and Control Block registers in the same way it would if
Device 0 was present. This is because Device 1 cannot determine if Device 0 is, or is not, present.

Host implementation of read and write operations to the Command and Control Block registers of non-
existent Device 0 are host specific.

NOTE − The remainder of this section is a host implementation note. The host implementor
should be aware of the following when supporting Device 1 only configurations:

1) Following a hardware reset or software reset, Device 1 will not be selected. The following
steps may be used to reselect Device 1:
a) Write to the Device/Head register with DEV bit set to one;
b) Using one or more of the Command Block registers that may be both written and
read, such as the Sector Count or Sector Number, write a data pattern other than
00h or FFh to the register(s);
c) Read the register(s) written in step (b). If the data read is the same as the data
written, proceed to step (e);
d) Repeat steps (a) to (c) until the data matches in step (c) or until 31 s has past.
After 31 s it may probably be assumed that Device 1 is not functioning properly;
e) Read the Status register and Error registers. Check the Status and Error register
contents for any error conditions that Device 1 may have posted.
2) Following the execution of an EXECUTE DEVICE DIAGNOSTIC command, Device 1 will
not be selected. Also, no interrupt will be generated to signal command completion. After
writing the EXECUTE DEVICE DIAGNOSTIC command to the Command register,
execute steps (a) to (e) as described in (1) above;
3) At all other times, do not write zero into the DEV bit of the Device/Head register. All other
commands execute normally.

Page 260
 T13/1153D revision 18

10 Timing

10.1 Deskewing
The host shall provide cable deskewing for all signals originating from the device. The device shall provide
cable deskewing for all signals originating at the host.

All timing values and diagrams are shown and measured at the connector of the selected device.

10.2 Transfer timing

The minimum cycle time supported by the device in PIO mode 3, 4 and Multiword DMA mode 1, 2
respectively shall always be greater than or equal to the minimum cycle time defined by the associated
mode e.g., a device supporting PIO mode 4 timing shall not report a value less than 120 ns, the minimum
cycle time defined for PIO mode 4 timings.

See 3.2.6 for timing diagram conventions.

10.2.1 Register transfers

Figure 20 defines the relationships between the interface signals for register transfers. Peripherals reporting
support for PIO mode 3 or 4 shall power up in a PIO mode 0, 1, or 2.

For PIO modes 3 and above, the minimum value of t0 is specified by word 68 in the IDENTIFY DEVICE
parameter list. Table 29 defines the minimum value that shall be placed in word 68.

IORDY shall be supported when PIO mode 3 or 4 are the current mode of operation.

NOTE − Some devices implementing the PACKET Command feature set prior to this
standard power up in PIO mode 3 and enable IORDY as the default.

Page 261
T13/1153D revision 18

t 0

ADDR valid
(See note 1)
t 1 t2 t9

t 2i
DIOR-/DIOW-

WRITE
DD(7:0)
(See note 2)
t 3 t4

READ
DD(7:0)
(See note 2)
t 5 t6

t 6z

IORDY
(See note 3,3-1)
t A

IORDY
(See note 3,3-2) t C
t RD

IORDY
(See note 3,3-3)
t B tC

NOTES −
1 Device address consists of signals CS0-, CS1- and DA(2:0)
2 Data consists of DD(7:0).
3 The negation of IORDY by the device is used to extend the PIO cycle. The determination of whether the
cycle is to be extended is made by the host after t A from the assertion of DIOR- or DIOW-. The
assertion and negation of IORDY are described in the following three cases:
3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2 Device negates IORDY before t A, but causes IORDY to be asserted before t A. IORDY is released
prior to negation and may be asserted for no more than 5 ns before release: no wait generated.
3-3 Device negates IORDY before t A. IORDY is released prior to negation and may be asserted for no
more than 5 ns before release: wait generated. The cycle completes after IORDY is reasserted. For
cycles where a wait is generated and DIOR- is asserted, the device shall place read data on DD(7:0)
for t RD before asserting IORDY.
Figure 20 − Register transfer to/from device

Page 262
 T13/1153D revision 18

Table 29 − Register transfer to/from device

PIO timing parameters Mode Mode Mode Mode Mode Note
0 1 2 3 4
ns ns ns ns ns
t0 Cycle time (min) 600 383 240 180 120 1
t1 Address valid to DIOR-/DIOW- (min) 70 50 30 30 25
setup
t2 DIOR-/DIOW- pulse width 8-bit (min) 290 290 290 80 70 1
t2i DIOR-/DIOW- recovery time (min) - - - 70 25 1
t3 DIOW- data setup (min) 60 45 30 30 20
t4 DIOW- data hold (min) 30 20 15 10 10
t5 DIOR- data setup (min) 50 35 20 20 20
t6 DIOR- data hold (min) 5 5 5 5 5
t6Z DIOR- data tristate (max) 30 30 30 30 30 2
t9 DIOR-/DIOW- to address valid (min) 20 15 10 10 10
hold
tRD Read Data Valid to IORDY active (min) 0 0 0 0 0
(if IORDY initially low after t A)
tA IORDY Setup time 35 35 35 35 35 3
tB IORDY Pulse Width (max) 1250 1250 1250 1250 1250
tC IORDY assertion to release (max) 5 5 5 5 5
NOTES −
1 t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum
command recovery time or command inactive time. The actual cycle time equals the sum of the actual
command active time and the actual command inactive time. The three timing requirements of t0, t2, and t2i
shall be met. The minimum total cycle time requirements is greater than the sum of t2 and t2i. This means a
host implementation may lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value
reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host
implementation.
2 This parameter specifies the time from the negation edge of DIOR- to the time that the data bus is no
longer driven by the device (tri-state).
3 The delay from the activation of DIOR- or DIOW- until the state of IORDY is first sampled. If IORDY is
inactive then the host shall wait until IORDY is active before the PIO cycle is completed. If the device is not
driving IORDY negated at the tA after the activation of DIOR- or DIOW-, then t5 shall be met and tRD is not
applicable. If the device is driving IORDY negated at the time tA after the activation of DIOR- or DIOW-,
then tRD shall be met and t 5 is not applicable.

10.2.2 PIO data transfers

Figure 21 defines the relationships between the interface signals for PIO data transfers. Peripherals
reporting support for PIO mode 3 or 4 shall power up in a PIO mode 0, 1, or 2.

For PIO modes 3 and above, the minimum value of t0 is specified by word 68 in the IDENTIFY DEVICE
parameter list. Table 30 defines the minimum value that shall be placed in word 68.

IORDY shall be supported when PIO mode 3 or 4 are the current mode of operation.

NOTE − Some devices implementing the PACKET Command feature set prior to this
standard power up in PIO mode 3 and enable IORDY as the default.

Page 263
T13/1153D revision 18

t 0

ADDR valid
(See note 1)
t 1 t2 t9

t 2i
DIOR-/DIOW-

WRITE
DD(15:0)
(See note 2)
t 3 t4

READ
DD(15:0)
(See note 2)
t 5 t6

t 6z

IORDY
(See note 3,3-1)
t A

IORDY
(See note 3,3-2) t C
t RD

IORDY
(See note 3,3-3)
t B tC

NOTES −
1 Device address consists of signals CS0-, CS1- and DA(2:0)
2 Data consists of DD(15:0).
3 The negation of IORDY by the device is used to extend the PIO cycle. The determination of whether the
cycle is to be extended is made by the host after t A from the assertion of DIOR- or DIOW-. The
assertion and negation of IORDY are described in the following three cases:
3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2 Device negates IORDY before t A, but causes IORDY to be asserted before t A. IORDY is released
prior to negation and may be asserted for no more than 5 ns before release: no wait generated.
3-3 Device negates IORDY before t A. IORDY is released prior to negation and may be asserted for no
more than 5 ns before release: wait generated. The cycle completes after IORDY is reasserted. For
cycles where a wait is generated and DIOR- is asserted, the device shall place read data on DD(15:0)
for t RD before asserting IORDY.
Figure 21 − PIO data transfer to/from device

Page 264
 T13/1153D revision 18

Table 30 − PIO data transfer to/from device

PIO timing parameters Mode Mode Mode Mode Mode Note
0 1 2 3 4
ns ns ns ns ns
t0 Cycle time (min) 600 383 240 180 120 1
t1 Address valid to DIOR-/DIOW- (min) 70 50 30 30 25
setup
t2 DIOR-/DIOW- 16-bit (min) 165 125 100 80 70 1

t2i DIOR-/DIOW- recovery time (min) - - - 70 25 1

t3 DIOW- data setup (min) 60 45 30 30 20
t4 DIOW- data hold (min) 30 20 15 10 10
t5 DIOR- data setup (min) 50 35 20 20 20
t6 DIOR- data hold (min) 5 5 5 5 5
t6Z DIOR- data tristate (max) 30 30 30 30 30 2
t9 DIOR-/DIOW- to address valid (min) 20 15 10 10 10
hold
tRD Read Data Valid to IORDY active (min) 0 0 0 0 0
(if IORDY initially low after tA)
tA IORDY Setup time 35 35 35 35 35 3
tB IORDY Pulse Width (max) 1250 1250 1250 1250 1250
tC IORDY assertion to release (max) 5 5 5 5 5
NOTES −
1 t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum
command recovery time or command inactive time. The actual cycle time equals the sum of the actual
command active time and the actual command inactive time. The three timing requirements of t0, t2, and t2i
shall be met. The minimum total cycle time requirements is greater than the sum of t2 and t2i. This means a
host implementation may lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value
reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host
implementation.
2 This parameter specifies the time from the negation edge of DIOR- to the time that the data bus is no
longer driven by the device (tri-state).
3 The delay from the activation of DIOR- or DIOW- until the state of IORDY is first sampled. If IORDY is
inactive then the host shall wait until IORDY is active before the PIO cycle is completed. If the device is not
driving IORDY negated at the tA after the activation of DIOR- or DIOW-, then t5 shall be met and tRD is not
applicable. If the device is driving IORDY negated at the time tA after the activation of DIOR- or DIOW-,
then tRD shall be met and t 5 is not applicable.

Page 265
T13/1153D revision 18

10.2.3 Multiword DMA data transfer

Figure 22 defines the timings associated with Multiword DMA transfers.

For Multiword DMA modes 1 and above, the minimum value of t0 is specified by word 65 in the IDENTIFY
DEVICE parameter list. Table 31 defines the minimum value that shall be placed in word 65.

Devices shall power up with mode 0 as the default Multiword DMA mode.

CS0-/CS1-
tM tN

t0

DMARQ
(See note 1) tL

DMACK-
(See note 2) tI tD tK tJ

DIOR-/DIOW-

tE tZ
Read
DD(15:0)

tG tF
Write
DD(15:0)

tG tH

NOTE −
1 For Multi-Word DMA transfers, the Device may negate DMARQ within the tL specified time once
DMACK- is asserted and reassert it again at a later time to resume the DMA operation. Alternatively,
if the device is able to continue the transfer of data, the device may leave DMARQ asserted and wait
for the host to reassert DMACK-.
2 This signal may be negated by the Host to suspend the DMA transfer in process.
Figure 22 − Multiword DMA data transfer

Page 266
 T13/1153D revision 18

Table 31 − Multiword DMA data transfer

Multiword DMA timing Mode 0 Mode 1 Mode 2 Note
parameters ns ns ns
t0 Cycle time (min) 480 150 120 see note
tD DIOR-/DIOW- (min) 215 80 70 see note
tE DIOR- data access (max) 150 60 50
tF DIOR- data hold (min) 5 5 5
tG DIOR-/DIOW- data setup (min) 100 30 20
tH DIOW- data hold (min) 20 15 10
tI DMACK to DIOR-/DIOW- setup (min) 0 0 0
tJ DIOR-/DIOW- to DMACK hold (min) 20 5 5
tKR DIOR- negated pulse width (min) 50 50 25 see note
tKW DIOW- negated pulse width (min) 215 50 25 see note
tLR DIOR- to DMARQ delay (max) 120 40 35
tLW DIOW- to DMARQ delay (max) 40 40 35
tM CS(1:0) valid to DIOR-/DIOW- (min) 50 30 25
tN CS(1:0) hold (min) 15 10 10
tZ DMACK- to tristate (max) 20 25 25
NOTE − t0 is the minimum total cycle time, tD is the minimum command active time, and tK (tKR or tKW , as
appropriate) is the minimum command recovery time or command inactive time. The actual cycle time
equals the sum of the actual command active time and the actual command inactive time. The three timing
requirements of t0, tD, tK shall be met. The minimum total cycle time requirement, t0, is greater than the sum
of tD and tK. This means a host implementation may lengthen either or both tD or tK to ensure that t0 is equal
to the value reported in the devices IDENTIFY DEVICE data. A device implementation shall support any
legal host implementation.

Page 267
T13/1153D revision 18

10.2.4 Ultra DMA data transfer

Figures 23 through 32 define the timings associated with all phases of Ultra DMA bursts.

Table 32 contains the values for the timings for each of the Ultra DMA modes.

10.2.4.1 Initiating an Ultra DMA data in burst

The values for the timings for each of the Ultra DMA modes are contained in 10.2.4.2.

DMARQ
(device)
tUI
DMACK-
(host)
tFS
tACK tENV
tZAD
STOP
(host)

tFS
tACK tENV
HDMARDY-
(host)
tZAD

tZIORDY

DSTROBE
(device)

tAZ tDVS tDVH

DD(15:0)

tACK
DA0, DA1, DA2,
CS0-, CS1-

NOTES −
1 See 9.13.1 Initiating an Ultra DMA data in burst.
2 The definitions for the STOP, HDMARDY and DSTROBE signal lines are not in effect until
DMARQ and DMACK are asserted.
Figure 23 − Initiating an Ultra DMA data in burst

Page 268
 T13/1153D revision 18

10.2.4.2 Ultra DMA data burst timing requirements

Table 32 − Ultra DMA data burst timing requirements

NAME MODE 0 MODE 1 MODE 2 COMMENT
(in ns) (in ns) (in ns)
MIN MAX MIN MAX MIN MAX
t2CYC 240 160 120 Typical sustained average two cycle time
tCYC 114 75 55 Cycle time allowing for assymetry and clock
variations (from STROBE edge to STROBE edge)
t2CYC 235 156 117 Two cycle time allowing for clock variations (from
rising edge to next rising edge or from falling edge to
next falling edge of STROBE)
tDS 15 10 7 Data setup time (at recipient)
tDH 5 5 5 Data hold time (at recipient)
tDVS 70 48 34 Data valid setup time at sender (from data bus being
valid until STROBE edge)
tDVH 6 6 6 Data valid hold time at sender (from STROBE edge
until data may become invalid)
tFS 0 230 0 200 0 170 First STROBE time (for device to first negate
DSTROBE from STOP during a data in burst)
tLI 0 150 0 150 0 150 Limited interlock time (see note 1)
tMLI 20 20 20 Interlock time with minimum (see note 1)
tUI 0 0 0 Unlimited interlock time (see note 1)
tAZ 10 10 10 Maximum time allowed for output drivers to release
(from being asserted or negated)
tZAH 20 20 20 Minimum delay time required for output drivers to
assert or negate (from released state)
tZAD 0 0 0
tENV 20 70 20 70 20 70 Envelope time (from DMACK- to STOP and
HDMARDY- during data out burst initiation)
tSR 50 30 20 STROBE to DMARDY time ( if DMARDY- is negated
before this long after STROBE edge, the recipient
shall receive no more than one additional data word)
tRFS 75 60 50 Ready-to-final-STROBE time (no STROBE edges
shall be sent this long after negation of DMARDY-)
tRP 160 125 100 Ready-to-pause time (time that recipient shall wait to
initiate pause after negating DMARDY-)
tIORDYZ 20 20 20 Pull-up time before allowing IORDY to be released
tZIORDY 0 0 0 Minimum time device shall wait before driving
IORDY
tACK 20 20 20 Setup and hold times for DMACK- (before assertion
or negation)
tSS 50 50 50 Time from STROBE edge to negation of DMARQ or
assertion of STOP (when sender terminates a burst)
NOTES −
1 tUI , tMLI , and tLI indicate sender-to-recipient or recipient-to-sender interlocks, that is, one agent (either
sender or recipient) is waiting for the other agent to respond with a signal before proceeding. tUI is an
unlimited interlock that has no maximum time value. tMLI is a limited time-out that has a defined minimum.
tLI is a limited time-out, that has a defined maximum.
2 All timing parameters are measured at the connector of the device to which the parameter applies. For
example, the sender shall stop generating STROBE edges tRFS after the negation of DMARDY-. Both
STROBE and DMARDY- timing measurements are taken at the connector of the sender. Even though the
sender stops generating STROBE edges, additional STROBE edges may be received by the receiver due
to propagation delay (see 9.13.3.2).
3 All timing measurement switching points (low to high and high to low) are to be taken at 1.5V.

Page 269
T13/1153D revision 18

Page 270
 T13/1153D revision 18

10.2.4.3 Sustained Ultra DMA data in burst

The values for the timings for each of the Ultra DMA modes are contained in 10.2.4.2.

t2CYC
tCYC tCYC
t2CYC
DSTROBE
at device
tDVH tDVH tDVH
tDVS tDVS

DD(15:0)
at device

DSTROBE
at host

tDH tDS tDH tDS tDH

DD(15:0)
at host

NOTES −
1 See 9.13.2 The data in transfer.
2 DD(15:0) and DSTROBE signals are shown at both the host and the device to emphasize that
cable settling time as well as cable propagation delay shall not allow the data signals to be
considered stable at the host until some time after they are driven by the device.
Figure 24 − Sustained Ultra DMA data in burst

Page 271
T13/1153D revision 18

10.2.4.4 Host pausing an Ultra DMA data in burst

The values for the timings for each of the Ultra DMA modes are contained in 10.2.4.2.

DMARQ
(device)

DMACK-
(host)
tRP
STOP
(host)
tSR
HDMARDY-
(host)

tRFS
DSTROBE
(device)

DD(15:0)
(device)

Figure 25 − Host pausing an Ultra DMA data in burst

Page 272
 T13/1153D revision 18

10.2.4.5 Device terminating an Ultra DMA data in burst

The values for the timings for each of the Ultra DMA modes are contained in 10.2.4.2.

DMARQ
(device)

tMLI
DMACK-
(host)
tLI tLI tACK

STOP
(host)
tLI tACK
HDMARDY-
(host)
tSS tIORDYZ
DSTROBE
(device)
tZAH
tAZ tDVS tDVH

DD(15:0) CRC

tACK
DA0, DA1, DA2,
CS0-, CS1-

NOTES −
1 See 9.13.4.1 Device terminating an Ultra DMA data in burst.
2 The definitions for the STOP, HDMARDY and DSTROBE signal lines are no longer in effect
after DMARQ and DMACK are negated.
Figure 26 − Device terminating an Ultra DMA data in burst

Page 273
T13/1153D revision 18

10.2.4.6 Host terminating an Ultra DMA data in burst

The values for the timings for each of the Ultra DMA modes are contained in 10.2.4.2.

DMARQ
(device)
tLI tMLI

DMACK-
(host) tZAH

tRP tAZ tACK

STOP
(host)

tACK
HDMARDY-
(host)
tRFS tMLI
tLI tIORDYZ
DSTROBE
(device)

tDVS tDVH

DD(15:0) CRC

tACK
DA0, DA1, DA2,
CS0-, CS1-

NOTES −
1 See 9.13.4.2 Host pausing an Ultra DMA data in burst.
2 The definitions for the STOP, HDMARDY and DSTROBE signal lines are no longer in effect
after DMARQ and DMACK are negated.
Figure 27 − Host terminating an Ultra DMA data in burst

Page 274
 T13/1153D revision 18

10.2.4.7 Initiating an Ultra DMA data out burst

The values for the timings for each of the Ultra DMA modes are contained in 10.2.4.2.

DMARQ
(device)
tUI
DMACK-
(host)

tACK tENV
STOP
(host)

tZIORDY tLI tUI

DDMARDY-
(device)
tACK

HSTROBE
(host)
tDVS tDVH
DD(15:0)
(host)
tACK

DA0, DA1, DA2,

CS0-, CS1-

NOTES −
1 See 9.14.1 Initiating an Ultra DMA data out burst.
2 The definitions for the STOP, DDMARDY and HSTROBE signal lines are not in effect
until DMARQ and DMACK are asserted.
Figure 28 − Initiating an Ultra DMA data out burst

Page 275
T13/1153D revision 18

10.2.4.8 Sustained Ultra DMA data out burst

The values for the timings for each of the Ultra DMA modes are contained in 10.2.4.2.

t2CYC
tCYC tCYC
t2CYC
HSTROBE
at host

tDVH tDVH tDVH

tDVS tDVS

DD(15:0)
at host

HSTROBE
at device

tDH tDS tDH tDS tDH

DD(15:0)
at device

NOTES −
1 See 9.14.2 The data out transfer.
2 DD(15:0) and HSTROBE signals are shown at both the device and the host to emphasize that
cable settling time as well as cable propagation delay shall not allow the data signals to be
considered stable at the device until some time after they are driven by the host.
Figure 29 − Sustained Ultra DMA data out burst

Page 276
 T13/1153D revision 18

10.2.4.9 Device pausing an Ultra DMA data out burst

The values for the timings for each of the Ultra DMA modes are contained in 10.2.4.2.

tRP
DMARQ
(device)
DMACK-
(host)

STOP
(host)
tSR
DDMARDY-
(device)

tRFS
HSTROBE
(host)

DD(15:0)
(host)

NOTES −
1 See 9.14.3.2 Device pausing an Ultra DMA data out burst.
2 The device may negate DMARQ to request termination of the Ultra DMA burst no sooner
than t RP after DDMARDY- is negated.
3 If the t SR timing is not statisfied, the device may receive zero, one, or two more data
words from the host.
Figure 30 − Device pausing an Ultra DMA data out burst

Page 277
T13/1153D revision 18

10.2.4.10 Host terminating an Ultra DMA data out burst

The values for the timings for each of the Ultra DMA modes are contained in 10.2.4.2.

tLI
DMARQ
(device)
tMLI

DMACK-
(host)
tLI tACK
tSS

STOP
(host)

tLI tIORDYZ
DDMARDY-
(device)

tACK

HSTROBE
(host)
tDVS tDVH
DD(15:0)
CRC
(host)
tACK
DA0, DA1, DA2,
CS0-, CS1-

NOTES −
1 See 9.14.4.1 Host terminating an Ultra DMA data out burst.
2 The definitions for the STOP, DDMARDY and HSTROBE signal lines are no longer in
effect after DMARQ and DMACK are negated.
Figure 31 − Host terminating an Ultra DMA data out burst

Page 278
 T13/1153D revision 18

10.2.4.11 Device terminating an Ultra DMA data out burst

The values for the timings for each of the Ultra DMA modes are contained in 10.2.4.2.

DMARQ
(device)

DMACK-
(host)

tLI tMLI tACK

STOP
(host)

tRP tIORDYZ
DDMARDY-
(device)
tRFS
tLI tMLI tACK

HSTROBE
(host)
tDVS tDVH

DD(15:0)
CRC
(host)
tACK
DA0, DA1, DA2,
CS0-, CS1-

NOTES −
1 See 9.14.4.2 Device pausing an Ultra DMA data out burst.
2 The definitions for the STOP, DDMARDY and HSTROBE signal lines are no longer in
effect after DMARQ and DMACK are negated.

Figure 32 − Device terminating an Ultra DMA data out burst

Page 279
T13/1153D revision 18

Annex A
(normative)
Connectors
The device shall implement one of the connector options described in this annex.

A.1 40-pin connector

The I/O connector is a 40-pin connector as described by SFF8059. The connector is as shown in figure A.1
with pin assignments as shown in table A.1. The connector shall be keyed to prevent the possibility of
installing it upside down. A key is provided by the removal of pin 20. The corresponding pin on the cable
connector shall be plugged.

The pin locations are governed by the cable plug, not the receptacle. The way in which the receptacle is
mounted on the printed circuit board affects the pin positions, and pin 1 shall remain in the same relative
position. This means the pin numbers of the receptacle may not reflect the conductor number of the plug.
The header receptacle is not polarized, and all the signals are relative to pin 20, that is keyed.

By using the plug positions as primary, a straight cable connects devices. As shown in figure A.2, conductor
1 on pin 1 of the plug shall be in the same relative position no matter what the receptacle numbering looks
like. If receptacle numbering was followed, the cable would have to twist 180 degrees between a device
with top-mounted receptacles, and a device with bottom-mounted receptacles.

3 1
9 9 1

K
4 2 2
0 0
Not to scale
Figure A.1 − 40-pin connector

1
40 20 2
Circuit board Circuit board
1
40 20 2

Not to scale
Figure A.2 − 40-pin connector mounting

Page 280
 T13/1153D revision 18

Table A.1 − 40-pin connector interface signals

Signal name Connector Conductor Connector Signal name
contact contact
RESET- 1 1 2 2 Ground
DD7 3 3 4 4 DD8
DD6 5 5 6 6 DD9
DD5 7 7 8 8 DD10
DD4 9 9 10 10 DD11
DD3 11 11 12 12 DD12
DD2 13 13 14 14 DD13
DD1 15 15 16 16 DD14
DD0 17 17 18 18 DD15
Ground 19 19 20 20 (keypin)
DMARQ 21 21 22 22 Ground
DIOW-:STOP 23 23 24 24 Ground
DIOR-:HDMARDY- 25 25 26 26 Ground
:HSTROBE
IORDY:DDMARDY- 27 27 28 28 CSEL
:DSTROBE
DMACK- 29 29 30 30 Ground
INTRQ 31 31 32 32 reserved
DA1 33 33 34 34 PDIAG-
DA0 35 35 36 36 DA2
CS0- 37 37 38 38 CS1-
DASP- 39 39 40 40 Ground

A.1.1 Assembly using 40-pin connectors and an 80-conductor cable

The Small Form Factor committee has defined an assembly that uses 40-pin connectors and 80-conductor
ribbon cable in SFF8049. The I/O connectors are 40-pin connectors as shown in figure A.1. However, for
this assembly, an 80-conductor ribbon cable is used where all of the even numbered conductors are
connected to the ground pins in all of the connectors in the assembly in order to improve signal integrity.
Table A.2 shows the pin assignments for this assembly. The connectors shall be keyed to prevent the
possibility of installing them upside down. A key is provided by the removal of pin 20 from the device and
host connectors. The corresponding pin on the cable connectors shall be plugged.

The connector contact for CBLID- shall be connected to the ground pins in the host-side connector. The
conductor for PDIAG- shall not be connected to the connector contact (and, thus, not the ground pins in the
host-side connector) for CBLID- in the connector for the host.

CSEL shall be connected to the connectors at the ends of the cable. If a connector is present in the middle
of the cable, then CSEL shall not be connected to this connector.

The pin locations are governed by the cable plug, not the receptacle. The way in which the receptacle is
mounted on the printed circuit board affects the pin positions, and pin 1 shall remain in the same relative
position. This means the pin numbers of the receptacle may not reflect the conductor number of the plug.
The header receptacle is not polarized, and all the signals are relative to pin 20, that is keyed.

By using the plug positions as primary, a straight cable connects devices. As shown in figure A.2, conductor
1 on pin 1 of the plug shall be in the same relative position no matter what the receptacle numbering looks
like. If receptacle numbering was followed, the cable would have to twist 180 degrees between a device with
top-mounted receptacles, and a device with bottom-mounted receptacles.

Page 281
T13/1153D revision 18

Table A.2 − 40-pin connector interface signals using 80-conductor cable

Signal name Connecto Conductor Connector Signal name
r contact contact
RESET- 1 1 3 2 Ground
DD7 3 5 7 4 DD8
DD6 5 9 11 6 DD9
DD5 7 13 15 8 DD10
DD4 9 17 19 10 DD11
DD3 11 21 23 12 DD12
DD2 13 25 27 14 DD13
DD1 15 29 31 16 DD14
DD0 17 33 35 18 DD15
Ground 19 37 39 20 (keypin)
DMARQ 21 41 43 22 Ground
DIOW-:STOP 23 45 47 24 Ground
DIOR-:HDMARDY- 25 49 51 26 Ground
:HSTROBE
IORDY:DDMARDY- 27 53 55 28 CSEL (see note 2)
:DSTROBE
DMACK- 29 57 59 30 Ground
INTRQ 31 61 63 32 reserved
DA1 33 65 67 34 PDIAG-:CBLID-(see note
3)
DA0 35 69 71 36 DA2
CS0- 37 73 75 38 CS1-
DASP- 39 77 79 40 Ground
NOTES −
1 All even-numbered conductors are connected to ground inside each of the connectors.
2 In a cable assembly providing connectors for two devices and a host, conductor 55 shall not be
connected to connector contact 28 in the connector in the middle position. This configuration
results in Device 0 being at the opposite end of the cable from the host.
3 Connector contact 34 in the connector for the host shall be connected to the ground pins in the
host-side connector. Conductor 67 shall not be connected to connector contact 34 in the connector
for the host.

A.1.2 4-pin power connector

When the device uses the 40-pin connector, the device receives DC power through a 4-pin connector as
defined by SFF8012. The pin assignments are shown in table A.2.

Table A.2 − DC interface using 4-pin power connector

Power line designation Pin Number
+12 Volts 1
+12 Volt return 2
+5 Volt return 3
+5 Volts 4

4 3 2 1
+5 V DC +5 V return +12 V return +12 V DC

Not to scale
Figure A.3 − Device side connector pin numbering

Page 282
 T13/1153D revision 18

A.2 44-pin small form factor connector

This annex describes a connector alternative often used for 2 1/2 inch or smaller devices. This alternative
is defined by the SFF8212.

A.2.1 44-pin signal assignments

The signals assigned for 44-pin applications are described in table A.3. Although there are 50 pins in the
plug, a 44-pin mating receptacle may be used (the removal of pins E and F provides room for the wall of the
receptacle).

Some devices may utilize pins A, B, C, and D for option selection via physical jumpers. Such
implementations may require use of the 44-pin receptacle.

Pins A through D of the connector plug located on the device shall not be connected to the host, as they are
reserved for manufacturer's use. Pins E, F, and 20 are keys, and are removed (see figure A.4).

4 1
3 9 1 E C A
K
K K
4 2 2 F D B
4 0
Not to scale
Figure A.4 − 44-pin connector

A.2.2 Use of pins A-D for device selection

If a device uses pins A, B, C, and D for device selection, when no jumper is present the device should be
designated as Device 0. When a jumper is present between pins B and D, the device should to respond to
the CSEL signal to determine its device number.

Page 283
T13/1153D revision 18

Table A.3 − Signal assignments for 44-pin connector

Signal name Connector Conductor Connector Signal name
contact contact
Vendor specific (see note) A B Vendor specific (see note)
Vendor specific (see note) C D Vendor specific (see note)
(keypin) (see note) E F (keypin) (see note)
RESET- 1 1 2 2 Ground
DD7 3 3 4 4 DD8
DD6 5 5 6 6 DD9
DD5 7 7 8 8 DD10
DD4 9 9 10 10 DD11
DD3 11 11 12 12 DD12
DD2 13 13 14 14 DD13
DD1 15 15 16 16 DD14
DD0 17 17 18 18 DD15
Ground 19 19 20 20 (keypin)
DMARQ 21 21 22 22 Ground
DIOW-:STOP 23 23 24 24 Ground
DIOR-:HDMARDY- 25 25 26 26 Ground
:HSTROBE
IORDY:DDMARDY- 27 27 28 28 CSEL
:DSTROBE
DMACK- 29 29 30 30 Ground
INTRQ 31 31 32 32 reserved
DA1 33 33 34 34 PDIAG-
DA0 35 35 36 36 DA2
CS0- 37 37 38 38 CS1-
DASP- 39 39 40 40 Ground
+5 V (logic) 41 41 42 42 +5 V (Motor)
(see note) (see note)
Ground(return) 43 43 44 44 Reserved - no connection
(see note) (see note)
NOTE − Pins that are additional to those of the 40-pin cable.

Page 284
 T13/1153D revision 18

A.3 68-pin small form factor connector

This clause defines the pinouts used for the 68-pin alternative connector for the AT Attachment Interface.
This connector is defined in the PCMCIA PC Card Standard. This clause defines a pinout alternative that
allows a device to function as an AT Attachment Interface compliant device, while also allowing the device
to be compliant with PC Card ATA mode defined by PCMCIA. The signal protocol allows the device to
identify the host interface as being 68-pin as defined in this standard or PC Card ATA.

To simplify the implementation of dual-interface devices, the 68-pin AT Attachment Interface maintains
commonality with as many PC Card ATA signals as possible, while supporting full command and signal
compliance with this standard.

The 68-pin pinout shall not cause damage or loss of data if a PCMCIA card is accidentally plugged into a
host slot supporting this interface. The inversion of the RESET signal between this standard and PCMCIA
interfaces prevents loss of data if the device is unable to reconfigure itself to the appropriate host interface.

A.3.1 Signals

This specification relies upon the electrical and mechanical characteristics of PCMCIA and unless otherwise
noted, all signals and registers with the same names as PCMCIA signals and registers have the same
meaning as defined in PCMCIA.

The PC Card-ATA specification is used as a reference to identify the signal protocol used to identify the host
interface protocol.

A.3.2 Signal descriptions

Any signals not defined below shall be as described in this standard, PCMCIA, or the PC Card ATA
documents.

Table A.4 shows the signals and relationships such as direction, as well as providing the signal name of the
PCMCIA equivalent.

Page 285
T13/1153D revision 18

Table A.4 − Signal assignments for 68-pin connector

Pin Signal Hst Dir Dev PCMCIA Pin Signal Hst Dir Dev PCMCIA
1 Ground x → x Ground 35 Ground x → x Ground
2 DD3 x ↔ x D3 36 CD1- x ← x CD1-
3 DD4 x ↔ x D4 37 DD11 x ↔ x D11
4 DD5 x ↔ x D5 38 DD12 x ↔ x D12
5 DD6 x ↔ x D6 39 DD13 x ↔ x D13
6 DD7 x ↔ x D7 40 DD14 x ↔ x D14
7 CS0- x → x CE1- 41 DD15 x ↔ x D15
8 → i A10 42 CS1- x → x(1) CE2-
9 SELATA- x → x OE- 43 ← i VS1-
10 44 DIOR- x → x IORD-
11 CS1- x → x(1) A9 45 DIOW- x → x IOWR-
12 → i A8 46
13 47
14 48
15 → i WE- 49
16 INTRQ x ← x READY/ 50
IREQ-
17 Vcc x → x Vcc 51 Vcc x → x Vcc
18 52
19 53
20 54
21 55 M/S- x → x(2)
22 → i A7 56 CSEL x → x(2)
23 → i A6 57 ← i VS2-
24 → i A5 58 RESET- x → x RESET
25 → i A4 59 IORDY o ← x(3) WAIT-
26 → i A3 60 DMARQ o ← x(3) INPACK-
27 DA2 x → x A2 61 DMACK- o → o REG-
28 DA1 x → x A1 62 DASP- x ↔ x BVD2/
SPKR-
29 DA0 x → x A0 63 PDIAG- x ↔ x BVD1/
STSCHG
30 DD0 x ↔ x D0 64 DD8 x ↔ x D8
31 DD1 x ↔ x D1 65 DD9 x ↔ x D9
32 DD2 x ↔ x D2 66 DD10 x ↔ x D10
33 x ← x WP/ 67 CD2- x ← x CD2-
IOIS16
34 Ground x → x Ground 68 Ground x → x Ground
Key:
Dir = the direction of the signal between host and device.
x in the Hst column = this signal shall be supported by the Host.
x in the Dev column = this signal shall be supported by the device.
i in the Dev column = this signal shall be ignored by the device while in 68-pin mode as defined in this
standard.
o = this signal is Optional.
Nothing in Dev column = no connection should be made to that pin.

NOTES −
1 The device shall support only one CS1- signal pin.
2 The device shall support either M/S- or CSEL but not both.
3 The device shall hold this signal negated if it does not support the function.

Page 286
 T13/1153D revision 18

A.3.2.1 CD1- (Card Detect 1)

This signal shall be grounded by the device. CD1- and CD2- are used by the host to detect the presence of
the device.

A.3.2.2 CD2- (Card Detect 2)

This signal shall be grounded by the device. CD1- and CD2- are used by the host to detect the presence of
the device.

A.3.2.3 CS1- (Device chip select 1)

Hosts shall provide CS1- on both the pins identified in table A.4.

Devices shall recognize only one of the two pins as CS1-.

A.3.2.4 DMACK- (DMA acknowledge)

This signal is optional for hosts and devices.

If this signal is supported by the host or the device, the function of DMARQ shall also be supported.

A.3.2.5 DMARQ (DMA request)

This signal is optional for hosts.

If this signal is supported by the host or the device, the function of DMACK- shall also be supported.

A.3.2.6 IORDY (I/O channel ready)

This signal is optional for hosts.

A.3.2.7 M/S- (Master/slave)

This signal is the inverted form of CSEL. Hosts shall support both M/S- and CSEL though devices need only
support one or the other.

Hosts shall assert CSEL and M/S- prior to applying VCC to the connector.

A.3.2.8 SELATA- (Select 68-pin ATA)

This pin is used by the host to select which mode to use, PC Card-ATA mode or the 68-pin mode defined in
this standard. To select 68-pin ATA mode, the host shall assert SELATA- prior to applying power to the
connector, and shall hold SELATA- asserted.

The device shall not re-sample SELATA- as a result of either a hardware or software reset. The device shall
ignore all interface signals for 19 ms after the host supplies Vcc within the device's voltage tolerance. If
SELATA- is negated following this time, the device shall either configure itself for PC Card-ATA mode or not
respond to further inputs from the host.

A.3.3 Removability considerations

This specification supports the removability of devices that use the protocol. As removability is a new
consideration for devices, several issues need to be considered with regard to the insertion or removal of
devices.

Page 287
T13/1153D revision 18

A.3.3.1 Device recommendations

The following are recommendations to device implementors:

− CS0-, CS1-, RESET-, and SELATA- signals be negated on the device to prevent false selection
during hot insertion.

− Ignore all interface signals except SELATA- until 19 ms after the host supplies VCC within the
device's voltage tolerance. This time is necessary to de-bounce the device's power on reset
sequence. Once in the 68-pin mode as defined in this standard, if SELATA- is ever negated
following the 19 ms de-bounce delay time, the device disables itself until VCC is removed.

− The DOOR LOCK and DOOR UNLOCK commands and the MC and MCR bits in the Error
register are used to prevent unexpected removal of the device or media.

A.3.3.2 Host recommendations

The following are recommendations to host implementors:

− Connector pin sequencing to protect the device by making contact to ground before any other
signal in the system.

− SELATA- to be asserted at all times.

− All devices reset and reconfigured to the same base address each time a device at that address
is inserted or removed.

− The removal or insertion of a device at the same address to be detected so as to prevent the
corruption of a command.

− The DOOR LOCK and DOOR UNLOCK commands and the MC and MCR bits in the Error
register used to prevent unexpected removal of the device or media.

A.4 Unitized connectors

The Small Form Factor committee has defined two unitized connectors for use on ATA/ATAPI devices of
3.5” and larger form factor. Each of these connectors consists of a signal portion that complies with the 40-
pin signal definition of A.1 and a 4-pin power portion that complies with the definition in A.1.1. In addition,
each has a jumper connector portion.

Figure A.5 shows the unitized connector defined by SFF8057 and defines the usage of the jumper connector
pins.

Figure A.6 shows the unitized connector defined by SFF8058 and defines the usage of the jumper connector
pins.

Page 288
 T13/1153D revision 18

40-pin signal connector 4-pin power connector

Pin 1 Pin A

Pin 40 Pin H
Jumper connector

Jumpers: E-F - CSEL

No jumper - Slave
G-H - Master
G-H and E-F - Master w/Slave present
Use of pins A through D is vendor specific
Pin I is reserved Not to scale
Figure A.5 − SFF 8057 connector

40-pin signal connector 4-pin power connector

Pin 1 Pin A

Pin 40 Pin J
Jumper connector

Jumpers: A-B - CSEL

C-D - Slave
E-F - Master
Use of pins G through J is vendor specific
Not to scale
Figure A.6 − SFF 8058 connector

Page 289
T13/1153D revision 18

Annex B
(informative)
Identify device data for devices with more than 1024 logical cylinders

B.1 Definitions and background information

The original IBM PC BIOS (Basic Input/Output System) imposed several restrictions on the support of
devices, and these have been incorporated into many higher level software products. One such restriction
limits the capacity of a device. BIOS software cannot support a device with more than 1,024 cylinders, 16
heads, and 63 sectors per track without translating an input logical geometry to a different output logical
geometry. The maximum addressable capacity of a device that does not require BIOS translation is
1,032,192 sectors.

These rules allow BIOSes using bit shifting translation to access 15,481,935 (16,383*15*63) sectors, and
BIOSes using LBA assisted translation to access 16,450,560 (1024*255*63) sectors. Extended BIOS
functionality is defined in the ANSI Technical Report Enhanced BIOS Services for Disk Drives, which
describes new services provided by BIOS firmware to support ATA hard disks up to 16 mega-terra-sectors.

B.2 Cylinder, head, and sector addressing

BIOSs and other software that operate a device in CHS translation employ a combination of IDENTIFY
DEVICE data words 1, 3, 6, words 53-58, and words 60-61 to ascertain the appropriate translation to use
and determine the capacity of a device.

Maximum compatibility is facilitated if the following guidelines are used. These guidelines limit the values
placed into words 1, 3, 6, 53-58, and 60-61. Accessing beyond 15,481,935 sectors should be performed
using LBA.

B.2.1 Word 1

For devices with a capacity less than or equal to 1,032,192 sectors, if IDENTIFY DEVICE data word 1
(Default Cylinders) does not specify a value greater than 1,024, then no guideline is necessary.

If a device is greater than 1,032,192 sectors, but less than or equal to 16,514,064 sectors, the maximum
value that can be placed into this word is determined by the value in word 3 as shown in table B.1.

If a device is greater than 15,481,935 sectors and supports CHS, this word should contain 16,383 (3FFFh).

The INITIALIZE DEVICE PARAMETERS command does not change this value.

The value in this word is changed by the SET MAX ADDRESS command.

Page 290
 T13/1153D revision 18

Table B.1 − Word 1 value for devices between 1,032,192 and 16,514,064 sectors
Value in word 3 Maximum value in word 1
1 1h 65,535 FFFFh
2 2h 65,535 FFFFh
3 3h 65,535 FFFFh
4 4h 65,535 FFFFh
5 5h 32,767 7FFFh
6 6h 32,767 7FFFh
7 7h 32,767 7FFFh
8 8h 32,767 7FFFh
9 9h 16,383 3FFFh
10 Ah 16,383 3FFFh
11 Bh 16,383 3FFFh
12 Ch 16,383 3FFFh
13 Dh 16,383 3FFFh
14 Eh 16,383 3FFFh
15 Fh 16,383 3FFFh
16 10h 16,383 3FFFh

B.2.2 Word 3

IDENTIFY DEVICE data word 3 (Default Heads) does not specify a value greater than 16. If the device has
less than or equal to 8,257,536 sectors, then set word 3 to 16 heads. If the device has more than 16,514,064
sectors, then set word 3 to 15 heads. If this value is set to 16 when the device has more than 16,514,064
sectors, some systems will not boot some operating systems.

The INITIALIZE DEVICE PARAMETERS command does not change this value.

B.2.3 Word 6

If the device is above 1,032,192 sectors then the value should be 63. This value does not exceed 63 (3Fh).

The INITIALIZE DEVICE PARAMETERS command does not change this value.

B.2.4 Use of words 53 through 58

Devices with a capacity over 1,032,192 sectors implement words 53-58. Devices with a capacity less than or
equal to 1,032,192 sectors may also implement these words. These words define the address range for all
sectors accessible in CHS mode under 16,514,064. The product of word 54, word 55, and word 56 must not
exceed 16,514,064.

B.2.5 Words 60-61

IDENTIFY DEVICE data words 60-61 contain a 32-bit value that is equal to the total number of sectors that
can be accessed using LBA. If the device is less than or equal to 15,481,935 sectors, this value should be
the product of words 1, 3, and 6. Setting the total number of LBA sectors in this manner reduces the
probability of conflicting device capacities being calculated by different operating systems.

Page 291
T13/1153D revision 18

B.3 Orphan sectors

The sectors, if any, between the last sector addressable in CHS mode and the last sector addressable in
LBA mode are known as "orphan" sectors. A device may or may not allow access to these sectors in CHS
addressing mode.

The values in words 1, 3, and 6 are selected such that the number of orphan sectors is minimized.
Normally, the number of orphan sectors should not exceed ( [word55] x [word56] - 1 ). However, the host
system may create conditions where there are a larger number of orphans sectors by issuing the INITIALIZE
DEVICE PARAMETERS command with values other than the values in words 3 and 6. If the
recommendation in B.2.5 is followed, there will be no orphan sectors and problems associated with new
operating systems calculating a different device size from older operating systems will be minimized.

Page 292
 T13/1153D revision 18

Annex C
(informative)
Signal integrity

C.1 Introduction
The ATA bus (a.k.a. IDE bus) is a disk drive interface originally designed for the ISA Bus of the IBM
PC/AT. With the advent of faster devices the definition of the bus has been expanded to include new
operating modes. Each of the PIO modes, numbered zero through four, is faster than the one before it
(higher numbers translate to faster transfer rates). PIO modes 0, 1, and 2 correspond to transfer rates for
the interface as it was originally defined with maximum transfer rates of 3.3, 5.2, and 8.3 MB/s, respectively.
PIO mode 3 defines a maximum transfer rate of 11.1 MB/s, and PIO mode 4 defines a maximum rate of
16.7 MB/s. Additionally, Multiword DMA and Ultra DMA modes have been defined. Multiword DMA mode
0, 1, and 2 have maximum transfer rates of 4.2, 13.3, and 16.7 MB/s, respectively. Ultra DMA modes 0, 1,
and 2 have maximum transfer rates of 16.7, 25, and 33.3 MB/s, respectively.

With the increases in speed the weaknesses of the original cabling scheme has become apparent. System
manufacturers, chipset designers, and device manufacturers must all take measures to insure that signal
integrity is maintained on the bus. The areas of concern are:

a) ringing due to improper termination;

b) crosstalk between signals;
c) bus timing.

The intended audience for this annex is digital and analog engineers who design circuits interfacing to the
ATA bus. Familiarity with this standard and a basic understanding of circuit theory is assumed.

C.1.1 The problems

Early implementations of the bus used LS-TTL parts to drive an 18-inch cable. The slow edges of LS-TTL
and the short cable length worked well at the time. PIO modes 3 and 4 demand higher performance. In an
effort to cut cycle times, edge rates have inadvertently been increased, causing ringing on the cable and
increased crosstalk between adjacent signals.

When a host adapter was little more than a few buffers and some gates there was no issue with host adapter
timing. With the advent of local bus architectures and faster transfer rates, timing issues have become
more important. Propagation delay with worst-case loads must now be taken into account when designing
host adapters.

One of the frequently asked questions is, “Why are problems with ringing on the bus seen now when they
were not seen before?” The answer is in the edge speed of the logic. How the edge speed changed may be
found by looking at the history of the IBM PC.

When the IBM PC/AT was introduced in 1983, the 8 MHz 80286 processor quickly became the dominant
platform. The AT bus (now called the ISA bus) became standardized around an 8 MHz processor speed.
When the first disk drive was introduced a few years later, it was designed as a simple extension of the bus
leading to the name “AT Attachment” interface (see figure C.1). The idea was to remove the disk drive
controller electronics from the PC and place them on the drive instead. What remained on the PC was a
pair of bi-directional data buffers and an address decoder. This simple interface was most often
implemented with a pair of 74LS245 buffers and a programmable logic device such as a PAL. These TTL
devices had rise and fall times in the 5 to 6 ns range. Although this was fast enough to cause some ringing
on the bus, it was not so severe as to prevent millions of successful system implementations.

Page 293
T13/1153D revision 18

CPU Bus ISA Bus ATA Intf Device

8 Mhz Interface (simple)
8 Mhz

RAM Card
Slots

ROM

Figure C.1 − Original IBM PC/AT architecture

The architecture of modern PCs has changed from the original PC/AT. As the processor speed increased
it became necessary to separate the processor bus from the ISA bus (see figure C.2). To maintain
compatibility the ISA bus continues to run at an 8 MHz rate. Processors have increased beyond 200 MHz,
and their associated busses have increased from 8 MHz to 33 MHz and above.

Devices have also increased in speed. The increase in rotational speed and linear bit density has increased
the rate at that data comes off the heads, and the presence of cache on the device makes data available at
the access rates of RAM. This has created a data bottleneck at the ISA bus. The device is faster, the
processor is faster, but the data can’t be moved from one to the other any faster.

CPU Bus ISA Bus

200 Mhz Interface
8 Mhz
Card
Slots
RAM

ROM Local Bus Local Bus ATA Intf ATA Device

Interface 33 MHZ (complex) (fast)
Local
Bus
Card
Slots

Figure C.2 − Modern PC architecture

This bottleneck inspired the invention of new, faster interfaces to the processor. Local busses are designed
to run at the speed of the processor bus. Two local bus standards have emerged, the VESA Local Bus
(VLB) and the Peripheral Component Interconnect bus (PCI). These local busses have the potential for
faster data transfer from the device to the processor.

To allow devices to transfer data faster, the standard had to be updated to allow faster transfer modes.
These enhanced modes are still not as fast as a processor bus. To synchronize the data flow between 32-
bit 33 MHz processor busses and slower 16-bit devices, a VLSI chip is required. Most of these bridge chips

Page 294
 T13/1153D revision 18

were implemented with fast CMOS processes to achieve the required bus speeds. As a result the edge
rates on the bus were often 1 to 2 ns, and sometimes less. These fast edges have aggravated the ringing
on the bus to the point that system/device combinations fail to work.

In summary, the reason for signal integrity problems appearing now, when they were absent before, is the
advent of faster transfer rates on the bus coupled with a change of IC process at the interface. The
problems are not insurmountable, and the bus can be a robust, fast, and inexpensive interface.

C.1.2 The goals

The recommendations in this annex make the following assumptions. The word “device” is used generically
to describe hard disk drives and other peripheral devices on the bus.

− Backward compatibility must be maintained. Old devices must work with new host adapters, and old
host adapters must work with new devices.
− This standard must be followed as closely as possible. Without this, solutions implemented by different
manufacturers will tend to diverge, creating incompatible systems.
− Solutions must be simple and inexpensive. The market for these products is very cost sensitive.

C.2 Termination
When analyzing the bus, the standard 18-inch ribbon cable used to connect devices must be considered in
three different areas of frequency. At low frequencies it is a lumped capacitive load; higher in frequency it is
a lumped LCR circuit; and at high frequencies it is a transmission line with distributed parameters. At
standard transfer rates both the LCR circuit and distributed model apply.

The cable used in most systems is a PVC-coated 40-conductor ribbon cable with the conductor spacing at
0.05 inches on center. This cable is modeled as a transmission line with a typical characteristic impedance
of 110 ohms and propagation velocity of 60% c when connected in a ground-signal-ground configuration.
When there are fewer grounds the characteristic impedance is higher. For the data lines adjacent to ground
lines the characteristic impedance is about 160 ohms. The 110 ohm case applies to data strobes.

C.2.1 The problem

Many users experienced problems with early implementations of PIO mode 3 devices and hosts. Most
failures in the systems observed were attributed to signal integrity problems on the control lines that go from
the host to the device. The problem appears most frequently as ringing on the DIOR- (during read
commands) and DIOW- (during write commands) lines.

During a read cycle when DIOR- is asserted, it is possible for the ringing to create a short duration negation
pulse (see figure C.3). This pulse occurs early in the read cycle. Inside the interface portion of the data
path controller chip is a FIFO buffer that contains the data to be read. The extra pulse on the DIOR- line
advances the FIFO pointer by one. This results in losing one word of data. The host system read operation
therefore receives one word too few, and the remaining bytes are shifted. A typical data word (Wn)
sequence might look like . . .W7, W8, W9, W11, W12 . . . Notice that word 10 is missing from the returned
data. This also means that the host tries to read one more word from the device than the device has
remaining in its buffer. Depending on the implementation of the BIOS, this locks up the system or simply
returns a byte of random data at the end of the sector transfer.

Pulse slivers due to ringing on the DIOW- line cause a similar problem during write transfers. The pulse
sliver advances the FIFO pointer by one, writing an extra word of random data into the FIFO. Subsequent
data bytes are shifted by one word. A typical stored data word (Wn) sequence on the device might look like
. . . W7, W8, W9, XX, W10, W11 . . . In this example an extra word was inserted during the write cycle for
word 10. From the device's point of view, the host is trying to write 514 bytes rather than the expected 512
bytes. The device throws away the final word and may flag an error. A properly written BIOS detects this
error and indicates a problem to the user.

Page 295
T13/1153D revision 18

Actual
Waveform

Switching Threshold

Waveform
seen by
chip

Figure C.3 − Typical ringing on bus and its effect

These are only two examples of a systemic problem. Ringing on any control signal, and possibly on data
lines, may cause system failures or data loss. To address this problem it is necessary to examine the circuit
structure of the bus.

Figure C.4 shows the seven basic driver/receiver structures that appear in bus interfaces. The host circuitry
appears on the left side of the diagram and the device circuitry appears on the right. The first circuit in
figure C.4 shows the structure of the seven control lines that go from the host to the device. A SPICE
model of the circuit can be designed if some assumptions are made about the circuitry at the host and
device. Virtually all devices today use a CMOS VLSI chip as part of the bus interface. This high-
impedance input is modeled with clamp diodes to supply and ground and a typical input capacitance of 8 pf.
Since the ringing problem is worse with CMOS VLSI bridge chips at the source, the host is modeled as a
voltage source with 1 ns edges, a 12 ohm output impedance, and clamp diodes to supply and ground. The
ribbon cable is modeled as a 110 ohm transmission line. The resulting SPICE model appears in figure C.5.

Page 296
 T13/1153D revision 18

HOST DEVICE
CS0- DIOR-
CS1- DIOW-
DA0 DMACK-
DA1 DA2

DD(15:0)

DMARQ

5.6 K

INTRQ
V+

1K
IORDY

V+

10 K
DASP-
PDIAG-

V+

10 K

CSEL

Figure C.4 − The seven basic driver/receiver structures

+ V4
− 5V D1 D3
R7 D1N4148 D1N4148
12 + V3
− 5V
D2 C2 D4
V1 D1N4148
Tr = 1 ns D1N4148 8 pf
TD = 2.5 ns
Tf = 1 ns Z0 = 110
Host Cable Device

Figure C.5 − Schematic of SPICE simulation model

Page 297
T13/1153D revision 18

8.0 v

6.0 v

4.0 v
device end

host end

2.0 v

0v

-2.0 v
0 50 ns 100 ns 150 ns 200 ns
time

Figure C.6 − Simulation waveforms at host and device ends of cable

The simulation results in figure C.6 show the waveforms at both the host and device ends of the cable. The
signal at the device end has ringing of sufficient amplitude to cause false triggering of the device. This is
confirmed by transmission line theory that indicates that ringing will occur whenever the source impedance
is lower than the characteristic impedance of the cable, and the termination impedance is higher than the
cable impedance. The greater the mismatch, the greater the amplitude of the ringing. The oscilloscope
trace shown in figure C.7 confirms the results of the simulations.

In an effort to decrease propagation delay, some bridge chip manufacturers have increased the output drive
current of the host in order to slew the output signal faster with the capacitive load of the cable. This has
caused the edge rates and the output impedance to decrease, both of which increase the ringing at the
device end of the cable. The oscilloscope trace in figure C.7 using a generic driver and receiver illustrates
the problem of ringing that is a fundamental characteristic of the interface. This has not always been the
case.

Page 298
 T13/1153D revision 18

5V

0V

50 ns/div horizontal 1 V/div vertical

Figure C.7 − Oscilloscope trace at device end of DIOR- signal on a typical system

C.2.2 What are the options?

The proper solutions are to terminate the transmission line and limit the frequency range of the signals.
There are two termination possibilities: series or source, and parallel or load. Unfortunately, each of these
solutions has problems of its own, and, regardless of the method of termination, ringing occurs in two-device
configurations. The input impedance of devices is not infinite: they appear as a reactive load due as the
input capacitance forms transmission line discontinuities.

Source termination is suited to situations where the signal is received at the far end of the line, and not in-
between. But devices can be placed anywhere along a cable. The signals at the device in the middle of the
cable have an initial step in their edges due to the series termination. Another problem with source
termination is devices are not necessarily at one end of the cable.

Load termination has different problems. A 110 ohm termination at the device end causes excessive DC
loading. The SCSI interface standard avoids ringing by requiring terminations at each end of the physical
cable and having each device drive the cable with a current sink. However, SCSI configurations often have
too many, too few, or improperly located terminations. Changing this standard to a user-installed
termination scheme loses all backward compatibility and is therefore not considered to be a viable option.

One of the solutions used in the past to “fix” failing configurations has been to place a capacitor at the input
of the device. Since the ringing is the result of a resonant system, adding purely reactive elements
(capacitors and inductors) that simply change the frequency of oscillation is not recommended. These
elements may fix a given configuration of a device and cable, but they really just move the interfering
resonance peaks to a different frequency, solving the problem only for that particular configuration. Proper
solutions include resistive elements to dissipate the energy stored in the transmission line.

No single solution meets the dual criteria of solving the ringing problem and being backward compatible with
current systems. The suggested approach uses partial solutions in three different areas: partial termination
at the host, partial termination at the device, and edge rate control at both the host and the device.

C.2.3 Design goals

Before a solution can be designed the design goals must be explicitly stated. This leads to the question of
“How much ringing is acceptable?” To answer this question the design and specification of the bus must be
considered.

Page 299
T13/1153D revision 18

The bus was originally designed to use standard TTL signals. TTL was designed with built-in noise margin.
All drivers are required to have a “low” (zero) signal level of 0.5 V or less, and a “high” (one) signal level of
2.4 V or more. All receivers are specified to accept any signal below 0.8 V as a logical zero and any signal
above 2.0 V as a logical one. This results in a low-side noise margin of 0.3 V (0.8 - 0.5) and a high-side
margin of 0.4 V (2.4 - 2.0). Signals between 0.8 V and 2.0 V are in no man’s land, interpreted by the
receiver as either a zero or a one. TTL compatible inputs typically use a switching threshold of 1.3 to 1.4 V.

Bus designers have long known that the noise margins of TTL are insufficient for signals passed on cables.
To improve the noise margin inherent in TTL systems, hysteresis has been added to the receiver input.
Hysteresis changes the input switching threshold depending on the present state of the logic output of the
receiver. For example, if the receiver is currently in a zero state, it might require an input voltage of 1.7 V
before changing to a one. Once in a one state, the receiver might require the input voltage to drop below
0.9 V before changing back to a zero. Modern design practice dictates that all signals passing across a bus
be received with hysteresis.

It is desirable that, even with ringing, the input signal remain less than 0.5 V after a falling edge and remain
above 2.4 V after a rising edge. With CMOS drivers only the falling edge is of concern. This is due to the
input switching threshold of TTL (typically 1.4 V) being closer to ground than to the supply. It turns out that
designing to the 0.5 V requirement is too restrictive, so the looser requirement of 0.8 V is used here. This
relaxed requirement removes the noise margin inherent in TTL and depends on receiver hysteresis for
proper operation. As input hysteresis has been the norm in device design for many years now, this
limitation is not considered unreasonable.

Depending on system timing and other issues, a designer may elect to use a looser threshold of 0.9 V or a
tighter one of 0.7 V. For these cases circuit simulation of the bus and receiver is done to verify the design.
The resulting termination circuits have different values from those derived here.

C.2.4 Source termination

A series resistor at the source (host) acts as a termination to the transmission line. When the value of the
resistor matches the characteristic impedance of the cable (110 ohms) then the reflection returning from the
load is reduced to zero. Resistor values less than the characteristic impedance will partially terminate the
cable and reduce the reflection.

NOTE − This assumes that the output impedance of the driver is zero. In reality, an
optimum match occurs when the output impedance and the series resistor together equal
the cable impedance. This also assumes that the host is at the end of the cable. If it is in
the middle of the cable, then it sees two cables in parallel and the optimum impedance
match would be 55 ohms.

This standard requires that a source be able to sink 4 mA while maintaining a logical low output voltage of
0.5 V or less (see 4.3). For a TTL output the low output voltage is a combination of the saturation voltage
and resistance of the pulldown transistor. For a CMOS output the pulldown transistor has no saturation
voltage and is just a resistance. Adding a series resistor in the output of the driver causes the output logical
zero voltage to increase with greater resistance. For example, if the unterminated logical zero output of the
driver is 0.4 V, then a maximum series resistance of 25.0 ohms would be allowed ( (0.5-0.4)/4mA ). This
DC voltage drop requirement acts in opposition to the higher resistance values required for cable
termination.

If it is assumed that an unterminated CMOS output driver can drive a logical low to 0.3 V at the rated sink
current, then there is a 0.2 V to drop across the series resistor. This gives a maximum resistor value of 50
ohms. So the value of the series resistor depends on the CMOS output, the logical zero voltage, and the
sink current.

Another consideration in selecting the value of the series resistor is the initial voltage on an edge. Assume
a step function voltage source driving a transmission line through a series resistor. The initial amplitude of
the edge at the input of the line is a voltage divider of the series resistor and the characteristic impedance.

Page 300
 T13/1153D revision 18

A receiving device can be near the source and the edge must go through logic thresholds. The worst case
is a negative edge from 5 V and a control line of 110 ohms impedance. The attenuation of the voltage
divider must be small enough to allow the edge to cross from 5 V through 0.8 V. Assuming that the leading
edge will just reach 0 V at the source, An analysis shows the series resistor must be no larger than 21 ohms
to meet this ( (5.0)/(5.0-0.8)=(110+R)/110 ). The closest standard five-percent value is 22 ohms. If one
assumes that the leading edge will undershoot to 0.5V at the source, the resistor may be no larger than 33
ohms.

Is a 22 or 33 ohm resistor adequate for reducing the ringing? The simulation was repeated using the same
model as shown in figure C.5 with a 33 ohm series resistor added. The results of that simulation appear in
figure C.8. The ringing is significantly reduced from the previous simulation in figure C.6. Simulations were
also performed on the model using a 22 ohm source resistor and similar reduction in ringing was observed.

8.0 v

6.0 v

4.0 v device end

host end
2.0 v

0v

-2.0 v
0 50 ns 100 ns 150 ns 200 ns
time

Figure C.8 − Waveforms with 33 ohm series resistor at source

For data lines there are two factors that make the considerations for selecting the series resistor significantly
different. First, the characteristic impedance of a data line is higher since ground lines are farther away.
Second, data lines are not edge sensitive, data settling time is the issue. The value of the series resistor is
limited by the DC loading requirements, not the edge integrity. Adoption of this standard for DC loading
allows further increase of the series resistance since the DC loading is the limiting factor. The characteristic
impedance of lines adjacent to ground wires is the lowest of the data lines and is about 160 ohms; a higher
value of series resistance is necessary to dampen reflections.

C.2.5 Receiver termination

Device termination is more difficult than host termination. Viable solutions must work with one or two
devices located anywhere along the cable. The host may or may not have termination. These and other
considerations make device termination a multifaceted problem.

Page 301
T13/1153D revision 18

The first constraint is the maximum DC loading allowed. This standard requires that the host be capable of
providing 400 µA of current while in a logical one state. Assuming each device is allowed to take half of that
amount, the minimum DC resistance allowed is 25K ohms.

NOTE − This assumes a CMOS output with a high output voltage of 5.0 V : 5.0 V/200 µA =
25 KΩ

For a 110 ohm transmission line, 25K ohms is as good as infinity. This means that any practical termination
solution must not have significant DC loading.

One way of terminating the cable is with an “AC termination.” This is a simple RC network that provides
termination for high-frequency signals but does not load the line at DC (see figure C.9). This circuit acts as
both a cable termination and a filter for the ringing. The termination characteristics can be observed by
looking at the ringing signal at the host when the circuit is connected or removed. When the circuit is in
place, less energy is reflected back to the host, so the host waveform has less ringing. The lowpass filter
characteristics of the circuit help decrease the amount of ringing presented to the interface circuitry of the
device.

Although this may appear to be an unusual method of terminating the cable, it is not without precedent. The
IEEE P996 committee recognized the problems inherent in the design of the IBM PC/AT bus and
recommended a series RC termination for increased “data integrity and system reliability.” They suggested
that the termination circuit be added to each end of the backplane or motherboard. The recommended
values are 40 to 60 ohms for the resistor and 30 to 70 pf for the capacitor.

Deriving the optimum values for a bus AC termination circuit is difficult. The easiest way of determining the
values is to perform a number of trial-and-error SPICE simulations for different host and device
configurations. The recommended values are 82 ohms and 10 pf. Simulations show that capacitance
values between 8 pf and 20 pf work well. Since the input capacitance of many interface chips is between 8
and 10 pf, a discrete capacitor is often unnecessary. This reduces the cost of implementation on the device.
A conservative approach is to place pads so additional capacitance can be added if required.

Device manufacturers need to ensure that any partial termination circuits they implement present an
effective capacitance of 20 pf or less. What is an effective capacitance? From a practical point of view,
any circuit is valid provided it does not increase the propagation delay of a worst-case cable. This is
because systems manufacturers are counting on a certain cable delay in their design. The easiest way to
answer the question of acceptability is to run a SPICE simulation and measure the delay. The simulation
should be run twice: once with a simple 20 pf load, and again with the proposed termination circuit. If the
resulting delay of the proposed termination circuit is less than or equal to that obtained with a 20 pf load,
then it meets the criterion for acceptance. The recommended termination of 82 ohms and 10 pf passes the
test.

The major drawback of the RC termination circuit is that it adds delay to the signal. Since this standard
defines the timing at the input to the device (see clause 10), device manufacturers must ensure that their
interface chip still works properly with the additional delay. The delay can be calculated for rising edges (2.0
V threshold) and falling edges (0.8 V threshold) with a fairly straightforward SPICE simulation. For the 82
ohm and 10 pf termination the delay is less than 1.5 ns (0.7 ns for the rising edge, 1.2 ns for the falling
edge, derived from simulations ).

Will termination at both the host and the device “over-terminate” the transmission line? Figure C.10 shows
the simulation results for device termination with no host termination, and figure C.11 shows the same
simulation with a 33 ohm host termination added. It is clear that termination at both the host and the device
results in the best signal integrity.

Another option for controlling ringing at the device is the use of a clamping circuit. Biased diodes have been
shown to be excellent solutions, reducing the ringing to virtually zero. The advantage of clamp circuits is
that they do not require any components in series with the signal, and therefore do not add any delay. This
is particularly important for PIO mode 4 operation. The disadvantage of clamping circuits is that they take
considerably more space on the circuit board and cost much more than passive elements. Some

Page 302
 T13/1153D revision 18

implementations have used clamping circuits on sensitive edge-triggered lines (such as DIOR- and DIOW-)
and used passive terminations on less sensitive lines (such as data signals). Clamping circuits work well
both with and without host-end termination and are worthy of further investigation.

82 ohm

Figure C.9 − AC termination circuit at device end of cable

8.0 v

6.0 v

4.0 v device end

host end
2.0 v

0v

-2.0 v
0 50 ns 100 ns 150 ns 200 ns
time

Figure C.10 − Device waveform with 82 ohm device termination and no host termination

Page 303
T13/1153D revision 18

8.0 v

6.0 v

4.0 v
device end

host end
2.0 v

0v

-2.0 v
0 50 ns 100 ns 150 ns 200 ns
time

Figure C.11 − Device waveform with 82 ohm device and 33 ohm host terminations

C.2.6 Edge rate control

This standard requires that all sources have a rise time of not less than 5 ns (see 4.3). The original intent of
this requirement was to avoid transmission line problems on the bus. One of the common misconceptions is
that limiting the rise time of the source to 5 ns will fix the ringing problem.

A rule-of-thumb for analog designers is that when the propagation delay of the cable exceeds one-quarter
of the signal rise time, cable termination should be used.

NOTE − In reality this rule-of-thumb varies considerably. Various books use values of one-
half, one-third, one-fifth, and even one over the square root of two times pi.

In the case of the bus, the worst case propagation delay of the cable is approximately 4 ns so by this rule
rise times of less than 16 ns require termination. Many local bus to bridge chips available today have rise
times of 1 to 2 ns, in violation of the requirement of 5 ns.

NOTE − Assuming 18-inch cable, 60% c velocity factor; two drives, each device having a
maximum load of 25 pf.

This standard says that the rise time must be a minimum of 5 ns into a 40 pf load. The easiest way to
implement this from a chip designer’s point of view is to decrease the drive of the I/O cell until the timing
requirement is met. Unfortunately, very few systems in the real world ever approach 40 pf. Although the
cable and the devices have maximum capacitance specifications, these capacitance values are never seen
by the host. At DC and low frequencies the cable looks like a capacitor. But at high frequencies (or fast
edge rates) the cable appears as a transmission line. A properly terminated transmission line appears to be
a resistor with no capacitance or inductance. The capacitance of the drives is changed by the transmission
line and appears as anything but pure capacitance at the output of the host. As a result, real-world systems
rarely see more than 25 pf of capacitive loading at the host. The reduced capacitance causes the I/O cell to

Page 304
 T13/1153D revision 18

slew faster, creating rise times less than 5 ns. In actual system testing, it has been found that only a few
systems have rise times slower than 3 ns.

The best solution is to use special I/O cells that have slew rate feedback to keep the rise time at 5 ns
regardless of load. These are more difficult to design than conventional I/O cells and consume more die
area. This could be a problem for interface chip designs that are already pad ring limited. Another
approach is to use a conventional I/O cell that is designed to have 5 ns rise times into a 10 pf or 20 pf load.
The total delay of the cell is greater for heavier loads, but the maximum delay is determined with SPICE
modeling of a worst-case cable and load.

Rise time control is still an important tool for controlling ringing. Although it is not the total solution,
simulations show marked improvement between sources with 1 ns rise times and sources with 5 ns rise
times. Slower rise times give the added benefit of reduced crosstalk. Figure C.12 shows the simulation with
both host and device terminations with rise and fall times of ins. A reduction in ringing is clearly seen.

8.0 v

6.0 v

4.0 v
device end

host end
2.0 v

0v

-2.0 v
0 50 ns 100 ns 150 ns 200 ns
time

Figure C.12 − Device waveform with both device and host terminations and 5 ns rise/fall times

C.2.7 The solution: A combination

No one element (e.g., source termination, receiver termination, or rise time control) completely addresses
the problem of ringing on the bus. The recommended solution is a combination of all three. Each element
must be enough to exert some control over the ringing problem in order to maintain backward compatibility.
With the faster transfer rates of PIO mode 4, DMA mode 2, and Ultra DMA mode 2 it is even more
important to control undesired ringing on the bus. It is unlikely that any systems will function reliably without
improvements from cooperation throughout the industry.

The above discussion only addressed a particular group of signals driven by the host and received by the
device. There are other signals driven by the device and received by the host that are equally susceptible
to ringing. These signals need termination, but in the opposite manner. The device inserts 22 or 33 ohm
resistors in series with signals it drives and the host has an RC (or just R) receiving end termination.

Page 305
T13/1153D revision 18

The data lines are different in several ways. First, they must move data bidirectionally. Second, they are
not edge sensitive, ringing affects the settling time. Third, since there are no ground wires between data
lines in an ATA cable, the data lines are highly coupled. Fourth, the transmission line characteristic
impedances are higher than strobe lines since ground wires are farther away. These differences demand
other considerations than the previous treatment.

Since data lines are bidirectional, the terminations on drives and host should be the same. For settling time,
the ringing frequency and its rate of decay, or Q factor, are the concerns. The mutual coupling among data
lines affects the ringing frequency causing it to be lower. The higher characteristic impedance causes the
rate of decay of ringing to be slower since the Q factor is higher. Controlling the resistance in the data lines
helps by limiting the Q factor, peak currents, and decay rate of the ringing. Controlling the load capacitance
limits the frequency of the ringing.

Improper treatment of the data lines has several bad effects. Data settling time can increase to as long as
45 ns in severe cases. Excessive ringing on the data lines can induce spurious signals on adjacent control
lines (crosstalk to DIOW- or RESET-).

Good design dictates that some type of ringing control be used on data lines, but of a different type than on
control lines. A good practice is to insert 33 ohm series resistors on data lines at both the host and the
device. The maximum capacitance specification in this standard must be met. The trace lengths from the
load to the connector of the device or host board should be short. The driving end sees the same source
termination as before. The receiving end sees an RC network of 33 ohms combined with the input
capacitance of the interface chip. This is enough to substantially reduce the ringing and minimize settling
time.

The IORDY line is a unique case on the bus. Under PIO modes it is driven by an open collector outputs
from the device, a current source rather than a voltage source. The nature of this signal makes it relatively
insensitive to ringing that might occur. However, in Ultra DMA the IORDY line is used as a high speed data
strobe from the device to the host. Termination of IORDY is recommended.

The one remaining bus structure not discussed is the open collector output driven by the device (DASP-).
This signal is driven by a current source rather than a voltage source. Usually the transistor driving this
signal is relatively slow and does not cause an excessive amount of ringing. The nature of DASP- makes it
relatively insensitive to ringing that might occur.

Table C.1 summarizes the typical termination values:

Table C.1 − Typical termination

Signal Name Host Termination Device Termination
DIOR-, DIOW- 22 ohm series 82 ohm series
CS0-, CS1- 33 ohm series 82 ohm series
DA0, DA1, DA2 33 ohm series 82 ohm series
DMACK- 22 ohm series 82 ohm series
RESET- 33 ohm series 82 ohm series
DD0 through DD15 33 ohm series 33 ohm series
DMARQ 82 ohm series 22 ohm series
INTRQ 82 ohm series 22 ohm series
IORDY 82 ohm series 22 ohm series
DASP-, PDIAG- no change no change
CSEL no change no change
NOTE − For the 82 ohm series termination, an additional parallel capacitor may be needed
if the interface chip and circuit board layout have less than 8 pf of capacitance.

C.2.7.1 Example of device-end termination timing

Assume that 82 ohm series resistors are inserted on all receive signals and 22 or 33 ohm series resistors on
all transmit and bidirectional signals. Also assume that the input capacitance of the interface chip is 10 pf.

Page 306
 T13/1153D revision 18

There are three different RC configurations that occur (see figure C.13). All receive signals will see an 82
ohm and 10 pf network. The data lines will see a 33 ohm and 10 pf network when the device is receiving
data. Signals driven back to the host (including data lines during a read) will see 33 ohms and 50 pf. The
50 pf assumption is the worst-case condition of both the host and another device being located nearby
(negligible cable length), and both of them having the maximum allowed input capacitance.

Drive
82 ohm
Control Signal
(e.g.,DIOR-,CS0-) 10 pf

Drive
33 ohm
Data Line
(Write Cycle) 10 pf

Drive
33 ohm
Data Line
(Read Cycle)
50 pf

Figure C.13 − Signal models for device-end timing calculations

A simple SPICE simulation with a signal source and an RC load will show what the delays are through these
three networks. Because the switching thresholds are not symmetrical with respect to the supply (0.8 V and
2.0 V) the delay for rising edges is different than that for falling edges. Since the input edge rate is
unknown, both fast and slow edge inputs are simulated. The worst-case delay occurs with slow edges for
rise times and fast edges for fall times. This mixture of slow rise time and fast fall time does not occur in
real life, but since the edge speed is not known the worst case is planned for. The SPICE signal source is
programmed for a rise time of 6.25 ns (same as 5 ns for 10% to 90%) and a fall time of 0.1 ns. The net
result is six delay values. The results of the SPICE simulations are shown in table C.2.

Table C.2 − Typical device-end propagation delay times

Symbol Description Value
Tphlc Propagation delay, high to low, control line 1.0 ns
Tplhc Propagation delay, low to high, control line 0.9 ns
Tphldi Propagation delay, high to low, data in 0.5 ns
Tplhdi Propagation delay, low to high, data in 0.3 ns
Tphldo Propagation delay, high to low, data out 2.5 ns
Tplhdo Propagation delay, low to high, data out 1.1 ns

These delay values, combined with the interface chip timing specifications, will give the timing at the pins of
the device. The trick is to figure out how each one of the timing parameters is affected by the delays.

For example, consider the DIOW- Data Setup time (value t3). This is the amount of time that the data must
be stable before the rising edge of DIOW-. Assume that the interface chip has a value of 2.0 ns. It is
known that DIOW- is a control signal and the rising edge of control signals are delayed by 0.9 ns. This
means that the setup time at the chip is actually greater than expected, but the data is delayed, too. It is not
known what the data pattern is so it is assumed that the delay time is the maximum of Tphldi and Tplhdi.
The actual setup time is 2.0 + 0.9 - MAX(0.3, 0.5) = 2.4 ns. This is less than the requirement of 30 ns (for
PIO mode 3) and therefore within spec.

Page 307
T13/1153D revision 18

This careful thought process must be repeated for all 15 of the PIO timing parameters (and for DMA and
Ultra DMA also). The easiest way to do this is to make a spreadsheet and enter the six values for RC delay
and the interface chip timing parameters. Spreadsheet formulas can then compute the timing at the pins of
the device and highlight any that are not within specification. In this manner the difficult calculations need
only be derived once and it becomes easier to verify results.

C.2.7.2 Example of host-end termination timing calculation

The host-end timing calculations are similar to the device-end calculations described above with a few more
complicating factors added in. The four different signal configurations are shown in figure C.14. For this
design 82 ohm series resistors are used on control lines received by the host and 22 or 33 ohm resistors on
the data lines and control lines driven by the host. It is assumed that the host adapter chip input
capacitance plus stray capacitance is 15 pf.

82 ohm Control Signal In

Host
(e.g., INTRQ, DMARQ)
15 pF 25 pF 25 pF

22 ohm Control Signal Out

Host
(e.g., DIOR−, DIOW-)
25 pF 25 pF

33 ohm Data Line

Host
(Read Cycle)
15 pF 25 pF 25 pF

33 ohm Data Line

Host (Write Cycle)
25 pF 25 pF

Figure C.14 − Host-end signal configurations with terminations

For these values, the control signal out and the data out models are similar. The greatest uncertainty is the
delay through the cable for received signals. The total cable delay depends on the source impedance of the
device. This can be anything from zero to 82 ohms; the greater the impedance, the greater the delay. It is
assumed for this example that the device vendor has read this document and has decided to use 22 or 33
ohms resistors. If it is desired later to make a worst-case assumption of 82 ohms, then approximately 2 ns
are added to the numbers.

Using SPICE models similar to the one shown in figure C.15 the eight delay parameters required are
derived. A second device appears in the model as a lumped capacitance of 25 pf that causes the maximum
delay. The resulting values appear in table C.3. By examining the values in the table it should be clear why
the cable propagation delay is often referred to as being about 5 ns.

Page 308
 T13/1153D revision 18

R7 T2
22 Device 0

V1 C2
Tr = 0.1 ns 25 pf
TD = 1.5 ns
Tf = 0.1 ns Z0 = 110 T3 Device 1
Host Cable
C3
25 pf
TD = 1.0 ns
Z0 = 110

Cable

Figure C.15 − SPICE model for control signal out delay calculation

Table C.3 − Typical host-end propagation delay times

Symbol Description Value
Tphlci Propagation delay, high to low, control in 6.4 ns
Tplhci Propagation delay, low to high, control in 4.7 ns
Tphlco Propagation delay, high to low, control out 5.9 ns
Tplhco Propagation delay, low to high, control out 4.6 ns
Tphldi Propagation delay, high to low, data in 5.7 ns
Tplhdi Propagation delay, low to high, data in 4.3 ns
Tphldo Propagation delay, high to low, data out 5.9 ns
Tplhdo Propagation delay, low to high, data out 4.6 ns

The process of finding the timing values is the same as for the device-end example. The propagation delay
times are added to and subtracted from the host adapter chip timings to obtain the timings at the input to the
device, in this case calculating the timing at the device furthest from the host adapter. The resulting timing
values are compared against the values to determine what mode the device operates at.

C.2.8 Dual port cabling

One of the recent enhancements to the bus has been the use of primary and secondary ports, allowing the
user to attach up to four devices. The optimal way to implement dual ports is to have two completely
separate interfaces that have no circuitry in common. This guarantees isolation between the ports and
insures that no interference will occur.

The advent of local bus bridge chips has introduced new driving forces to the dual port cabling issue.
Implementing two independent ports on a single chip requires 66 I/O pins. Due to the cost of pins, some
designs have combined the data lines of the two ports into one set of pins. Sharing the data lines (or any
other lines) in this way without termination allows the two cables and devices attached to interact.
Simulations confirm that the ringing in such configurations is large and complex, particularly if the loads on
the two cables are not balanced. Even with termination the buffer output impedance is a consideration.

One alternative pin-saving solution would be to add a set of external buffers such as the 74ALS245. This
would require three new control lines but would save 16 data lines for a net improvement of 13 pins. This
also would require additional packages on the circuit board.

An economical solution is to add independent series resistors for each line (see figure C.16). Energy
reflected back from the first cable passes through a series termination resistor, the shunt output impedance
of the driver, a second series resistor and then into the second cable before getting to the host. This signal is
reflected from the end of the second cable (with loss), and must pass through the termination resistor again
before arriving at the host. The two series terminations and the shunt impedance of the buffer at the host

Page 309
T13/1153D revision 18

forms a T attenuator network isolating the two cables. The effectiveness of this network depends on the
values: the series resistors need to be large, the shunt needs to be small, and the traces need to be short.
The drivers must have high capacity to drive two cables, and additionally to attenuate ringing from one
cable to the other. This provides sufficient attenuation of reflected signals to make ringing not a problem if
all specifications are met, and all recommended terminations and trace lengths are implemented. When
some recommendations and specifications are not met, the situation is more uncertain.

In practice, configurations will have devices that do not follow these recommendations. Nevertheless, it is
reasonable to expect all manufacturers to conform to the ATA specification. Extensive simulation work has
been done assuming specification conformance, and configurations that have at least one conforming
device. The design of the host is a key factor in the performance of dual cable configurations.

Proving that any scheme works is a significant task. Simulations must be performed for all combinations of
one device vs. two devices, devices with terminations and devices without terminations, devices with little
load capacitance and maximum load capacitance, differing data patterns, etc. With two ports the number of
combinations is daunting. Simulations have not yet revealed a combination of devices that fails to operate
properly. Simulation results have been spot checked against actual systems.

Primary Port
Device 0 Device 1

33 ohm

Device 0 Device 1

Secondary Port

Figure C.16 − Preferred connection for shared lines in dual port systems

Not all of the signal lines in a shared dual port interface can be shared. If the chip select lines (CS0-, CS1-)
and the data strobe lines (DIOR-, DIOW-) are shared, then it is impossible to differentiate between the
primary and secondary ports. A write to a device on one port causes the same action to occur on the other
port, destroying the data on the other device. The data strobe lines are sensitive edge-triggered signals
while the chip select lines act more like level-sensitive address lines. It is recommended that designers
share the less sensitive chip select lines and not share the data strobe lines.

The purpose of the chip select lines is to select the active device. It makes sense to have independent chip
select lines for primary and secondary ports. This allows the DIOR- and DIOW- lines to be shared. The
ATA bus signals that can and cannot be shared are shown in table C.4.

Table C.4 makes some assumptions about how the dual porting is being implemented. If the data lines are
shared, there can not be simultaneous accesses to the primary and secondary ports. The IORDY line
cannot be shared since it is a strobe in Ultra DMA mode and because of transmission line considerations.
The INTRQ and DMARQ signals are driven by tristate buffers on the devices. Either Device 0 or Device 1
enables its tristate driver depending on the state of the DEV bit in the Device/Head Register. Therefore
INTRQ and DMARQ cannot be shared because either Device 0 or Device 1 will be driving these lines at all
times. The primary port devices do not know about the secondary port devices, so sharing these lines
would create a conflict. In theory, the DMACK- line could be shared since it is driven by the host. In
practice this is not recommended. It is likely that some devices respond unconditionally to the DMACK-
signal, whether they ever requested a DMA cycle or not. This could lead to a conflict on a DMA cycle
between a primary port device and a secondary port device during the data cycle. For these reasons the
INTRQ, DMARQ, and DMACK- lines cannot be shared.

Page 310
 T13/1153D revision 18

Table C.4 − Possible sharing of signals in dual port configurations

Signal name
DIOR-, DIOW- Not shareable
CS0-, CS1- Shareable
DA0, DA1, DA2 Shareable
DMACK- Not shareable
RESET- Shareable
DD0 – DD15 Shareable
DMARQ Not shareable
INTRQ Not shareable
IORDY Shareable
DASP-, PDIAG- Not shareable
CSEL Not shareable

The DASP- lines cannot be shared. Assume there are two devices on the primary port, and one device on
the secondary port. With the DASP- lines connected, the single device on the secondary port will incorrectly
“see” Device 1 on the primary port. This would be a problem for all manufacturers who follow the
specifications. Similar problems can occur with the PDIAG- lines; they cannot be shared.

Sharing lines between ports will lead to lower performance than fully independent ports. Newer operating
systems are multithreaded, so it is possible for accesses to be occurring independently and concurrently on
the primary and secondary ports. With shared signals lines concurrent access is not possible, hence the
impact on performance.

Note that the entries in table C.4 are not the last word on line sharing. There are specific conditions under
which some lines may be sharable. For example, if separate DIOR- and DIOW- lines were provided for
primary and secondary ports, then the CS0- and CS1- lines could be shared. Many combinations of shared
and non-shared lines are possible provided that the functionality of the signals is carefully considered.

C.3 Crosstalk
Crosstalk is switching on one signal line causing induced signals in an adjacent line. Crosstalk has not been
a significant issue in the past with slower edge rates; in newer systems the problem is often masked by
ringing. Once the cable is terminated and the ringing is under control, then the presence of crosstalk
becomes apparent.

C.3.1 Coupling mechanisms

There are three mechanisms by which a signal couples into an adjacent line. The first is mutual
capacitance, the second is mutual inductance, and the third is common impedance coupling. As a switching
signal wavefront propagates down the cable it couples energy into the adjacent line. Once this energy is in
the second transmission line, it propagates in both directions: forward toward the receiver and back toward
the source (see figure C.17).

First the forward coupling components are examined. The coupling capacitance between the two line
causes a current pulse in the secondary line proportional to the capacitance and the rate of change of
voltage on the primary side. A positive voltage step on the primary line causes a positive voltage spike on
the secondary line at both source and load.

The voltage induced in the second transmission line is proportional to the coupling coefficient, the
inductance, and the rate of change of current in the primary side. This induced potential appears
longitudinally and presents as a negative voltage at the load, and a positive voltage at the source.

An additional voltage appears in series with the load from the current carried in the ground or signal return
wire. This type of coupling is called common impedance since the voltage is coupled from an impedance
common to the two circuits. Here, the common impedance is that of the signal return or ground wire, and it

Page 311
T13/1153D revision 18

is primarily inductive. The voltage induced in the second line is proportional to the inductance, and the rate
of current from the first line.

Lm Cm Lm Cm Lm Cm

Figure C.17 − Crosstalk coupling mechanisms

These coupling mechanisms have some interesting characteristics. The polarity of the coupling at the load
is opposite for the mutual inductance and coupling capacitance. If the magnitudes of these effects are
comparable, then they will cancel, resulting in no forward crosstalk. Unfortunately, accurately computing
these values is difficult, and the easiest way to determine the actual amount of crosstalk is to measure it.
The other noteworthy characteristic is that the magnitude of the coupled signal is proportional to the rate of
change of the signal in the primary line. This is a major reason for controlling the slew rate on bus drivers.
Here it is seen that fast edge rates and ringing on the data lines can couple by crosstalk into adjacent control
lines, causing control sequence errors through mistriggering. The presence of crosstalk-induced voltage
spikes on the control signals reduces the noise margin, and can increase the long-term error rate.

The amplitude of the coupled signal is proportional to the total amount of coupling capacitance and mutual
inductance, and common impedance, and is therefore proportional to cable length. Once a line is
terminated properly, ringing is no longer a function of length. This leaves crosstalk as the major factor
limiting cable length.

Reducing crosstalk involves reducing the mutual inductance, mutual capacitance, and common impedance,
or decreasing the source signal amplitude. Controlling the inductance and capacitance can be done by
either keeping the length of the cable short or by increasing the distance between conductors. Placing a
ground conductor between critical signals increases the separation of the signals, adds a shielding effect
from the intervening ground, and reduces the common impedance. In this environment the only control that
can be exercised over the cable is to keep the length at 18 inches or less. The amplitude of the source
signal can be reduced somewhat and still maintain compatibility, and some elements of the source signal
can be controlled. Slew rate limitation reduces the high-frequency components of the source signal and
therefore reduces the coupling of these components into adjacent lines. Terminating the lines reduces
ringing that also decreases the amount of energy coupled at the ringing frequency.

C.4 Bus timing

Terminating the bus has its cost. Partial terminations at the host and the device increase propagation
delays throughout the system. This standard specifies that timing is referenced to the input pins of the
device (see clause 10). This means that most of the timing issues must be addressed by systems
manufacturers and bridge chip designers.

C.4.1 The issues

The most significant timing issue is the propagation delay of the cable. This needs to be added to the host-
side timing. The SPICE model in figure C.18 shows an unterminated host with very fast rise times driving a
cable with worst case loads. Two unterminated devices are assumed with the maximum allowed capacitive
loading of 20 pf.

NOTE − 25 pf was specified in ATA-2.

Page 312
 T13/1153D revision 18

The simulation results are shown in figure C.19. The period of the ringing is four times the propagation
delay of the cable. This simulation shows a cable propagation delay of 5.6 ns. This is twice the value
obtained by assuming an 18-inch cable with a propagation velocity of 60% c. The additional delay is due to
the presence of the capacitive loads on the cable. This result is important to system designers who take into
account worst-case cable delay when specifying the bridge chip timing.

T2
Device 0

V1 C2
TD = 1.5 ns 25 pf
Tr = 0.1 ns Z0 = 110
Tf = 0.1 ns T3 Device 1
Cable
Host C3
25 pf
TD = 1.5 ns
Z0 = 110

Cable

Figure C.18 − SPICE model of cable with worst case loads

12 V

8V

4V

0V

-4 V

-8 V

-12 V
40 ns 80 ns 120 ns 160 ns
time
Figure C.19 − Simulation of unterminated cable with worst case loads

From the host point of view, all of the timings are corrected by adding the propagation delay of the cable to
insure that the timing is correct at the input pins of the furthest device. Figure C.20 shows a typical
corrected result using the read cycle data setup time as an example. This standard specifies a setup time at
the device of 20 ns (PIO mode 3). The remaining setup time at the host is only 8.8 ns (20 - 2 x 5.6).

C.4.2 The influence of termination

If the host has a series partial termination resistor then the bridge chip includes additional timing margin to
account for the RC delay of that resistor. Simulations show that the incremental delay added by a series
termination resistor at the host is approximately 0.2 ns for a 33 ohm resistor and 1.7 ns for an 82 ohm
resistor.

Page 313
T13/1153D revision 18

NOTE − Assuming a two device load, 25 pf at each device, an 18-inch cable, and 25 pf at
host

The extra delay of higher resistor values is one of the reasons that 33 ohm series resistors at the host are
recommended.

DIOR- at host

5.6 ns 8.8 ns 5.6 ns

DIOR at device

20 ns

Data at device

5.6 ns

Data at host

Figure C.20 − Host data setup time during a read cycle

The series resistor at the host is located as close as possible to the connector. To see the importance of
this, SPICE simulations are done with the stray capacitance on the driver side of the series resistor and
again with the stray capacitance on the cable side. The ringing is reduced when the stray capacitance of the
host is on the driver side of the series resistor. A related issue is the distance from the host adapter chip (or
chipset) to the connector. Some motherboards have the chip located up to 10 inches away from the
connector. This effectively adds another 10 inches to the 18-inch ribbon cable, resulting in an equivalent
cable length of 28 inches.

NOTE − The traces on the circuit board are from 25 to 90 ohm impedance, so the electrical
length of the trace cannot simply be added to the 110 ohm ribbon cable. A SPICE
simulation can be used to find the actual delay.

This additional length is not necessarily a problem. If the system manufacturer takes the extra trace delay
into account in the application of the host adapter chip, and the total capacitance is kept below the host limit
of 25 pf, then in theory there is no difference. Real-world experience indicates that this calculation is rarely
done. The distance from the chip to the connector is not addressed in this standard. Keeping the connector
within 3 inches (by trace length) of the host adapter chip is recommended.

C.4.3 Calculating rise time

Chip designers often use a lumped capacitance model for simulating the delay of the output cell. For the
simulations this sometimes consists of adding the maximum capacitance allowed for the host and the
devices ((2 x 20) + (1 x 25) pf) to an estimated capacitance value for the cable (25 pf). Simulation is then
performed with 100 pf capacitance on the output. This does not give an accurate measurement of the
timing. A better approximation is to use an output capacitance for the motherboard, a host end termination
resistor, and a transmission line to the devices (see figure C.21).

To illustrate how these models are different, suppose that the propagation delay of the output cell simulation
is 2 ns too slow. The chip designer (using a 100 pf model) increases the drive current of the output
devices. With enough drive current into a purely capacitive load, the 2 ns is removed, bringing the output
cell timing back into spec.

Page 314
 T13/1153D revision 18

Increasing the drive of the output cell in the transmission line model, the length of the cable is not increased
and the speed of signal propagation in the cable is not increased. The 2 ns required time reduction is not
achieved by increasing the output drive current. The time must come from somewhere else in the internal
circuitry. Increasing the output drive current only increases the edge speed, making the ringing worse at the
device end (some time is gained with the faster edge speed, but not nearly as much as is predicted with a
simple capacitive load model). It is not possible to decrease the overhead by increasing the drive current.

Most ASIC designers find that simulations using the recommended model of figure C.21 show their output
cells to be faster than in models with a 100 pf load.

D6 R4
T1 500 K
D1N4148
+ V3
− 5V
C1 D3 R3
25 pf D1N4148 500 K
Buffer
TD = 2.5 ns
under
Z0 = 110
test

D5 R7
T2 D1N4148 500 K
+ V4
− 5V
C4 D4 R6
25 pf D1N4148 500 K
TD = 0.7 ns
Z0 = 110

Figure C.21 − Recommended model for I/O cell propagation delay

C.4.4 Measuring propagation delay

Propagation delay times at the host (and at the device) are measured to the standard of 0.8 V for high to low
transitions and 2.0 V for low to high transitions. Many IC manufacturers measure propagation delay at the
typical switch point for TTL of 1.4 V. This is not appropriate for the interface since virtually every chip
manufacturer (both host and device end) has included hysteresis for noise immunity. Since both the
hysteresis window and hysteresis offset of a given receiver move with process, voltage, and temperature,
the only guaranteed switch points are the TTL high and low values (0.8 V and 2.0 V).

C.5 Summary of guidelines

This summary is a collection of reminders for device, system, and chipset designers. They are separated
into three groups by relevancy. The guidelines below are not intended to be a strict mandate, but a tool to
help everyone build compatible, reliable, high-performance products.

Page 315
T13/1153D revision 18

C.5.1 Guidelines for device designers

− Terminate signals as shown in table C.1. Consider adding capacitors to ground on these lines if the
input capacitance is less than 8 pf, or use active clamping circuits. Place these resistors as close to the
connector as possible.
− Verify that the termination circuit used on received signals has less than 20 pf of equivalent
capacitance.
− Perform a timing analysis to verify that timings are met at the input to the device. Include the time delay
due to propagation and cable termination circuits.

C.5.2 Guidelines for system designers

− Do not use any value less than 1 K ohm for pull up resistors on open-collector signals such as IORDY
(as per this standard).
− The host adapter chip should be located as close as possible to the connector. Keep the trace length
between them less than 3 in.
− After circuit board fabrication, verify that the total input capacitance at the host is less than 25 pf.
− Terminate signals as shown in table C.1. Place these resistors as close to the connector as possible.
− Perform a system timing analysis to verify that timings are met at the input to the device.
− For dual port implementations, terminate signals as shown in figure C.16. These resistors should be
placed as close to the connector of that port as possible.
− For dual port implementations, the signal lines CS0- and CS1- may be shared, or the signals DIOR- and
DIOW- may be shared, but not both pairs.
− For dual port implementations, do not share DASP- or PDIAG- signal lines.
− For dual port implementations, perform a system timing analysis to verify that timings are met at the
input of the device. In particular watch the assertion widths of DIOR- and DIOW- to insure that they
meet the specification.
− Route cable away from chassis, power supplies, and high speed circuits.
− Use the shortest cable practical and never greater than 18 in.

C.5.3 Guidelines for chip designers

− Design I/O cells to have rise and fall times of 5 ns or more under both minimum and maximum load
conditions.
− Perform timing simulations using a transmission line load model, not a 100 pf capacitor model.
− Take worst-case cable delay into account when designing the interface. Ensure that timing can be met
at the device-end of the cable. Provide typical application data with timing for system manufacturers.

Page 316
 T13/1153D revision 18

Annex D
(informative)
Bibliography

AT Attachment Interface (ATA-1), ANSI X3.221-1994

AT Attachment Interface with Extensions (ATA-2), ANSI X3.279-1996
AT Attachment - 3, ANSI X3.298-1997
BIOS Enhanced Disk Drive Specification (EDD), T13/1226DT
ATA Packet Interface (ATAPI) for Streaming Tape, QIC-157 1
Suite of 2.5” Form Factor Specifications, SFF-8200, SFF-8201 2
Suite of 3.5” Form Factor Specifications, SFF-8300, SFF-8301, SFF-8302 2
ATA Packet Interface for CD-ROMs, SFF-8020i 2
ATAPI Removable Rewritable Media, SFF-8070 2
ATAPI CD-R/RW Devices, SFF-8080 2
Commands for DVD Devices, SFF-8090 2
CompactFlash Association Specification Revision 1.2 3

1) QIC documents are published by:

Quarter-Inch Cartridge Drive Standards, Inc.
311 East Carrillo Street
Santa Barbara, CA 93101
Tel: 805-963-3853
Fax: 805-962-1541

2) SFF documents are published by:

SFF
14426 Black Walnut Court, Saratoga, California 95070
FaxAccess: 408 741-1600

SFF documents may be obtained from:

Global Engineering
15 Inverness Way East
Englewood, CO 80112-5704
Tel: 303-792-2181 or 800-854-7179
Fax: 303-792-2192

3) The CFA specification is published by:

CompactFlash Association
P.O. Box 51537
Palo Alto, CA 94303
http://www.compactflash.org

Page 317
T13/1153D revision 18

Annex E
(informative)
Command set summary
The following four tables are provided to facilitate the understanding of the command set. Table E.1
provides information on which command codes are currently defined. Table E.2 provides a list of all of the
commands in order of command code. Table E.3 provides a summary of all commands with the protocol,
required use, command code, and registers used for each. Table E.4 shows the status and error bits used by
each command.

Table E.1 − Command matrix

x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
0x C R R C* R R R R C* R R R R R R R
1x O E* E* E* E* E* E* E* E* E* E* E* E* E* E* E*
2x C C O* O* R R R R R R R R R R R R
3x C C O* O* R R R R C* R R R O* R R R
4x C C R R R R R R R R R R R R R R
5x O* R R R R R R R R R R R R R R R
6x R R R R R R R R R R R R R R R R
7x C E* E* E* E* E* E* E* E* E* E* E* E* E* E* E*
8x V V V V V V V F* V V V V V V V V
9x C C C R E* E* E* E* E* E* V R R R R R
Ax C* C* C* R R R R R R R R R R R R R
Bx C R R R R R R R R R R R R R R R
Cx F* V V V C C C C* C C C C C* C* R R
Dx R R R R R R R R R R C* E* E* E* C* C*
Ex C C C C C C C C* C E* R R C* C* O* C
Fx V C C C C C C V C C* V V V V V V
Key:
C = a defined command, R = Reserved, undefined in current specifications, V = Vendor specific
commands
O = Obsolete, E=a retired command, F=If the device does not implement the CFA feature set, this
command code is Vendor specific, * indicates that the definition of this command has changed from ATA-
3, X3.298-1997.

Page 318
 T13/1153D revision 18

Table E.2 − Commands sorted by command value

Command name Command code
NOP 00h
CFA REQUEST EXTENDED ERROR CODE 03h
DEVICE RESET 08h
READ SECTOR(S) 20h-21h
WRITE SECTOR(S) 30h-31h
CFA WRITE SECTORS WITHOUT ERASE 38h
READ VERIFY SECTOR(S) 40h-41h
SEEK 70h
CFA TRANSLATE SECTOR 87h
EXECUTE DEVICE DIAGNOSTIC 90h
INITIALIZE DEVICE PARAMETERS 91h
DOWNLOAD MICROCODE 92h
PACKET A0h
IDENTIFY PACKET DEVICE A1h
SERVICE A2h
SMART B0h
CFA ERASE SECTORS C0h
READ MULTIPLE C4h
WRITE MULTIPLE C5h
SET MULTIPLE MODE C6h
READ DMA QUEUED C7h
READ DMA C8h-C9h
WRITE DMA CAh-CBh
WRITE DMA QUEUED CCh
CFA WRITE MULTIPLE WITHOUT ERASE CDh
GET MEDIA STATUS DAh
MEDIA LOCK DEh
MEDIA UNLOCK DFh
STANDBY IMMEDIATE E0h
IDLE IMMEDIATE E1h
STANDBY E2h
IDLE E3h
READ BUFFER E4h
CHECK POWER MODE E5h
SLEEP E6h
FLUSH CACHE E7h
WRITE BUFFER E8h
IDENTIFY DEVICE ECh
MEDIA EJECT EDh
SET FEATURES EFh
SECURITY SET PASSWORD F1h
SECURITY UNLOCK F2h
SECURITY ERASE PREPARE F3h
SECURITY ERASE UNIT F4h
SECURITY FREEZE LOCK F5h
SECURITY DISABLE PASSWORD F6h
READ NATIVE MAX ADDRESS F8h
SET MAX ADDRESS F9h

Page 319
T13/1153D revision 18

Table E.3 − Command codes and parameters

proto Command typ PKT Command Parameters used
fea code FR SC SN CY DH
ND CFA ERASE SECTORS O N C0h y y y y
ND CFA REQUEST EXTENDED ERROR O N 03h D
PI CFA TRANSLATE SECTOR O N 87h y y y
PO CFA WRITE MULTIPLE W/OUT O N CDh y y y y
ERASE
PO CFA WRITE SECTORS W/OUT O N 38h y y y y
ERASE
ND CHECK POWER MODE M M E5h y D
DR DEVICE RESET O M 08h D
PO DOWNLOAD MICROCODE O N 92h y y y y D
DD EXECUTE DEVICE DIAGNOSTIC M M 90h D*
ND FLUSH CACHE O O E7h y y y y
ND GET MEDIA STATUS O O DAh D
PI IDENTIFY DEVICE M N ECh D
PI IDENTIFY PACKET DEVICE N M A1h
ND IDLE M O E3h y D
ND IDLE IMMEDIATE M M E1h D
ND INITIALIZE DEVICE PARAMETERS M N 91h y y
ND MEDIA EJECT O O EDh D
ND MEDIA LOCK O O DEh D
ND MEDIA UNLOCK O O DFh D
ND NOP O M 00h D
P PACKET N M A0h y y y y D
PI READ BUFFER O N E4h D
DM READ DMA M N C8h C9h y y y y
DMO READ DMA QUEUED O N C7h y y y y y
PI READ MULTIPLE M N C4h y y y y
ND READ NATIVE MAX ADDRESS O N F8h D
PI READ SECTOR(S) M N 20h 21h y y y y
ND READ VERIFY SECTOR(S) M N 40h 41h y y y y
PO SECURITY DISABLE PASSWORD O O F6h D
ND SECURITY ERASE PREPARE O O F3h D
PO SECURITY ERASE UNIT O O F4h D
ND SECURITY FREEZE O O F5 D
PO SECURITY SET PASSWORD O O F1H D
PO SECURITY UNLOCK O O F2h D
ND SEEK M N 70h y y y
P SERVICE N O A2h y y y D
ND SET FEATURES M M EFh y D
ND SET MAX ADDRESS O N F9h y y y y
ND SET MULTIPLE MODE M N C6h y D
ND SLEEP M M E6h D
ND SMART DISABLE OPERATIONS O O B0h y y D
ND SMART ENABLE/DISABLE O O B0h y y y D
AUTOSAVE
ND SMART ENABLE OPERATIONS O O B0h y y D
ND SMART EXECUTE OFF_LINE O O B0h y y D
PI SMART READ DATA O O B0h y y D
ND SMART RETURN STATUS O O B0h y y D
ND STANDBY M O E2h y D
ND STANDBY IMMEDIATE M M E0h D
(continued)

Page 320
 T13/1153D revision 18

Table E.3 − Command codes and parameters(concluded)

proto Command typ PKT Command Parameters used
fea code FR SC SN CY DH
PO WRITE BUFFER O N E8h D
DM WRITE DMA M N CAh CBh y y y y
DMO WRITE DMA QUEUED O N CCh y y y y y
PO WRITE MULTIPLE M N C5h y y y y
PO WRITE SECTOR(S) M N 30h 31h y y y y
VS Vendor specific V V 9Ah,C0h-
C3h,8xh,
F0h,F7h,
FAh-FFh
- Reserved: all remaining codes R R
Key:
DM = DMA command ND = Non-data command PI = PIO data in command
PO = PIO data out command VS = Vendor specific command O = Optional P=PACKET command
DR = DEVICE RESET protocol DD = EXECUTE DEVICE DIAGNOSTIC protocol
DMO = Overlapped/queued DMA
typ=Command type PKT fea=Command type when PACKET Command feature set implemented
M = Mandatory R = Reserved N=Not to be used V = Vendor specific
implementation
CY = Cylinder registers SC = Sector Count register DH = Device/Head register
SN = Sector Number register FR = Features register (see command descriptions for use)
y = the register contains a valid parameter for this command. For the Device/Head register, y means both the device
and head parameters are used.
D = only the device parameter is valid and not the head parameter.
d = the device parameter is valid, the usage of the head parameter vendor specific.
D* = Addressed to device 0 but both devices execute it.

Page 321
T13/1153D revision 18

Table E.4 − I/O port functions and selection addresses except PACKET and SERVICE commands
Addresses Functions
CS0- CS1- DA2 DA1 DA0 Read (DIOR-) Write (DIOW-)
N N x x x Data bus high impedance Not used
Control block registers
N A N x x Data bus high impedance Not used
N A A N x Data bus high impedance Not used
N A A A N Alternate Status Device Control
N A A A A obsolete(see note) Not used
Command block registers
A N N N N Data Data
A N N N A Error Features
A N N A N Sector Count Sector Count
A N N A A Sector Number Sector Number
A N A N N Cylinder Low Cylinder Low
A N A N A Cylinder High Cylinder High
A N A A N Device/Head Device/Head
A N A A A Status Command
A A x x x Invalid address Invalid address
Key:
A = signal asserted, N = signal negated, x = don’t care
NOTE − This register is obsolete. It is recommended that a device not respond to a read of this
address.

Table E.5 − I/O port functions and selection addresses for PACKET and SERVICE commands
Addresses Functions
CS0- CS1- DA2 DA1 DA0 Read (DIOR-) Write (DIOW-)
N N x x x Data bus high impedance Not used
Control block registers
N A N x x Data bus high impedance Not used
N A A N x Data bus high impedance Not used
N A A A N Alternate Status Device Control
N A A A A obsolete(see note) Not used
Command block registers
A N N N N Data Data
A N N N A Error Features
A N N A N Interrupt reason
A N N A A
A N A N N Byte count low Byte count low
A N A N A Byte count high Byte count high
A N A A N Device select Device select
A N A A A Status Command
A A x x x Invalid address Invalid address
Key:
A = signal asserted, N = signal negated, x = don’t care
NOTE − This register is obsolete. A device should not respond to a read of this address.

Page 322
 T13/1153D revision 18

Annex F
(informative)
Command packet format example
Table F.1 is an example of the command packet for most PACKET commands.

Table F.1 − Command packet

Byte 7 6 5 4 3 2 1 0
0 Operation code
1 reserved reserved
2 (MSB)
3 Logical block address (if required)
4
5 (LSB)
6 reserved
7-8 (MSB) Transfer length (if required) or
Parameter list length (if required) or
Allocation length (if required) (LSB)
9 reserved
10 reserved
11 reserved

Page 323