Department of Electronics & Communication Engineering

Graphic Era (Deemed to be University), Dehradun, UK

LABORATORY MANUAL

Name of the Laboratory

PEC 151: Basic Electronics Lab

PREPARED BY

Dr. Anurag Vidyarthi

APPROVED BY

Dr. Md. Irfanul Hasan

Lab Manual: Basic Electronics Lab Page 1

 Department of Electronics & Communication Engineering
Graphic Era (Deemed to be University), Dehradun, UK

EXPERIMENT NO. 01
Aim: Study of Logic Gates

Objectives:

i. To verify truth table of basic logic gates (AND, OR, NOT)

ii. To verify truth table of universal gates (NAND, NOR)
iii. To verify truth table of Exclusive gates (XOR, XNOR)

Apparatus Required: IC 7408 (AND Gate), IC 7432 (OR Gate), IC 7404 (NOT Gate),IC 7400
(NAND Gate),IC 7402 (NOR Gate), IC 7486(XOR Gate),Bread Board, Power Supply,
Connecting Wires, LED.

Theory:

Logic Gates:A logic gate is an elementary building block of a digital circuit. Most logic gates
have two inputs and one output. At any given moment, every terminal is in one of the
two binaryconditions: LOW (0) or HIGH (1), represented by different voltage levels. In most
logic gates, the low state is approximately zero volts (0 V), while the high state is approximately
five volts positive (+5 V).

AND, OR and NOT are basic gates. XOR and XNOR are derived gates. NAND and NOR gate
are universal gatesas anylogic can be implemented using only NAND or only NOR.

a) AND Gate gives logic 1 as output only if all of its inputs are at logic 1.

Fig. 1.1. Symbol of AND gate

Lab Manual: Basic Electronics Lab Page 2

 Department of Electronics & Communication Engineering
Graphic Era (Deemed to be University), Dehradun, UK

Truth Table of AND Gate:

A B A•B
0 0 0
0 1 0
1 0 0
1 1 1

Fig. 1.2. Pin Diagram of AND gate

Fig. 1.3. AND gate with LED as load

b) OR Gategives logic 0 as output only if all of its inputs are at logic 0.

Fig. 1.4. Symbol of OR gate

Lab Manual: Basic Electronics Lab Page 3

 Department of Electronics & Communication Engineering
Graphic Era (Deemed to be University), Dehradun, UK

Truth Table of OR Gate:

A B A+B
0 0 0
0 1 1
1 0 1
1 1 1

Fig. 1.5. Pin Diagram of OR gate

Fig. 1.6. OR gate with LED as load

c) NOT Gate complements the input.

Fig. 1.7. Symbol of NOT gate

Lab Manual: Basic Electronics Lab Page 4

 Department of Electronics & Communication Engineering
Graphic Era (Deemed to be University), Dehradun, UK

Truth Table of NOT Gate:

A Y
0 1
1 0

Fig. 1.8. Pin Diagram of NOT gate

Fig. 1.9. NOT gate with LED as load

d) NAND Gate gives logic 0 as output only if all of its inputs are at logic 1.NAND gate is a
contraction of AND-NOT.

Fig. 1.10. Symbol of NAND gate

Lab Manual: Basic Electronics Lab Page 5

 Department of Electronics & Communication Engineering
Graphic Era (Deemed to be University), Dehradun, UK

Truth Tableof NAND Gate:

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

Fig. 1.11. Pin Diagram of NAND gate

Fig. 1.12. NAND gate with LED as load

e) NOR Gate gives logic 1 as output only if all of its inputs are at logic 0.NOR gate is a
contraction of OR-NOT.

Fig. 1.13. Symbol of NOR gate

Truth Tableof NOR Gate:

Lab Manual: Basic Electronics Lab Page 6

 Department of Electronics & Communication Engineering
Graphic Era (Deemed to be University), Dehradun, UK

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

Fig. 1.14. Pin Diagram of NOR gate

Fig. 1.15. NOR gate with LED as load

f) XOR Gate gives logic 1 output if the two inputs are dissimilar.

Fig. 1.16. Symbol of XORgate

Lab Manual: Basic Electronics Lab Page 7

 Department of Electronics & Communication Engineering
Graphic Era (Deemed to be University), Dehradun, UK

Truth Tableof XOR Gate:

A B Y
0 0 0
0 1 1
1 0 1
1 1 0

Fig. 1.17. Pin Diagram of XOR gate (7486N)

Fig. 1.18. XOR gate with LED as load

g) XNOR Gate gives high output (logic 1)only if both inputs are same. It is complement of
XOR gate. It can be implemented using IC 7486(XOR Gate) and IC 7404 (NOT Gate).

Fig. 1.19. Symbol of XNORgate

Lab Manual: Basic Electronics Lab Page 8

 Department of Electronics & Communication Engineering
Graphic Era (Deemed to be University), Dehradun, UK

Truth Tableof XNOR Gate:

A B C
0 0 1
0 1 0
1 0 0
1 1 1

Experimental Procedure:
1. Turn the power (Trainer Kit) off during circuit implementation.
2. Connect the +5V and ground (GND) leads of the power supply to the power and ground
bus strips on your breadboard.
3. Point all the chips in the same direction with pin 1 at the lower-left corner on
breadboard. (Pin 1 is often identified by a dot or a notch next to it on the chip package).
4. Select a connection and place a piece of hook-up wire between corresponding pins of
the chips on breadboard. It is better to make the short connections before the longer
ones. Mark each connection of schematic in steps, so as not to try to make the same
connection again at a larger stage.
5. If an error is made and not spotted before you turn the power on, turn the power off
immediately before reconstructing the circuit.
6. Verify the truth table of given circuit.

Result: The truth tables of all logic gates AND, OR, NOT, XOR, XNOR, NAND and NOR
gates have been verified.

Result Analysis & Discussion: This section should be written individually by each student.

Inferences & Conclusion: This section should be written individually by each student.

Learning Outcomes:

1. Depth knowledge of basic gates ICs.

Lab Manual: Basic Electronics Lab Page 9

 Department of Electronics & Communication Engineering
Graphic Era (Deemed to be University), Dehradun, UK

2. Learning the pin description of ICs.

Applications:

1. NOT gates are used in oscillators to generate clock signals.

2. AND gate is used in the measurement of frequency of a pulsed waveform.

3. EX-OR gates are used in parity generation, checking units and comparators.

Precautions:

1. Turn the power off before making any connection.

2. Make connections carefully.

Lab Manual: Basic Electronics Lab Page 10