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Blok Diagram

1. The document describes the power planes and power states of a computer system. 2. It explains that assertion of SLP_S3# and SLP_S4# shuts off power to non-critical components when the system transitions to different sleep states (S3, S4, S5). 3. The diagram shows the power sources, regulators, and signals that control power to different components like the CPU, PCH, and VRMs during normal operation and sleep/shutdown states.

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Muhammad Maimana
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153 views1 page

Blok Diagram

1. The document describes the power planes and power states of a computer system. 2. It explains that assertion of SLP_S3# and SLP_S4# shuts off power to non-critical components when the system transitions to different sleep states (S3, S4, S5). 3. The diagram shows the power sources, regulators, and signals that control power to different components like the CPU, PCH, and VRMs during normal operation and sleep/shutdown states.

Uploaded by

Muhammad Maimana
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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SLP_S3#(SUSB#): 4 39
S3 Sleep Power plane control Assertion of SLP_S3# shuts off power to non-critical components NBSWON#
when system transitions to S3, S4, or S5 states. 5 +5VPCU +5V_S5
SLP_S4#(SUSC#): MOS
S5_ON PQ33
S4 Sleep Power plane control - Assertion of SLP_S4# shuts power off to non-critical components 6
when system transitions to S4 or S5 state. (S5D)
2 +3VPCU +3V_S5
1 MOS
AC Adapter +3VPCU PQ12
Always System power
BATT Charger VIN
D Regulator 7 D

PU2 +5VPCU
Battery EC_RSMRST#
PU2 RSMRST#
10 8
3
DNBSWON#
SUSON(SUSD) PWRBTN#

13 SUSC# 9
SLP_S4#
MAINON(MAIND)
EC SUSB#
14 SLP_S3#
MAIND +3VPCU/+5VPCU +3V
MOS +5V 22
23 PCH
ECPWROK
TPT_PWROK
PWRGD
MAIND +1.5VSUS
+1.5V
MOS
100ms
C
MAINON C

+RC VIN 15
+1.05V
VR

HWPG_1.05V VRM_PWRGOOD

16
CPU_PG PLTRST#

VIN +VCC_CORE
17
Regulator VCCGFX
PU8
HWPG_SYS
+3.3V_PRIME_ON IMVP_PWRGD/ HWPG_VCCGFX 18
(From EC)
19a 21
+3V 19b HWPG CK505 24 25
+3V_PRIME
MOS EN
PQ9 H_PWRGD PLTRST_N
B B
20 HWPG_1.8V D
+3VSUS
MOS MAINON_ON_G NMOS
+1.8V HWPG_1.5V G
PU7 S
D
GND
NMOS MAINON_ON_G 12
G For Power Down Sequence PWRGD RESET_L
S For Power Down Sequence
DDR3_VCCA_PWROK
GND
MAINON +0.75V_DDR_VTT
VIN
CPU
SUSON Regulator +SMDDR_VREF
+1.5VSUS
PU5 DDR3_DRAM_PWROK
11
+3VPCU
SUSD MOS +3VSUS
PQ22
A A

Quanta Computer Inc.


PROJECT : ZE7
Size Document Number Rev
power sequence block diagram 1B

Date: Wednesday, November 02, 2011 Sheet 39 of 40


5 4 3 2 1

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