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Week 3 Assignment

The document contains 10 multiple choice questions about Verilog HDL concepts such as netlist representations, always blocks, and commenting syntax. It asks the reader to identify true/false statements and select the best answer from given options regarding Verilog terminology, semantics, and applications like synthesis and FPGA implementation.

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Ashish Sura
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
228 views

Week 3 Assignment

The document contains 10 multiple choice questions about Verilog HDL concepts such as netlist representations, always blocks, and commenting syntax. It asks the reader to identify true/false statements and select the best answer from given options regarding Verilog terminology, semantics, and applications like synthesis and FPGA implementation.

Uploaded by

Ashish Sura
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Week‐3 

Assignment Questions and Answers 

1. Netlist is a ______ representation of a circuit.
a. graphic
b. text‐based
c. handwritten
d. pictorial

2. RTL stands for _____________.
a. resistor‐transfer logic
b. register‐transistor logic
c. register‐transfer logic
d. none of these

3. Verilog HDL originated at
a. AT&T Bell laboratories
b. Defense Advanced Research Projects Agency(DARPA)
c. Gateway Design Automation
d. Institute of Electrical and Electronics Engineers(IEEE)

4. State whether the following statements are true or false:
a. Verilog is case sensitive.
i. True
ii. False

b. “beginmodule” and “endmodule” are reserved words in Verilog.
i. True
ii. False

c. The semantics of an “&” operator depends on the number of operands.
i. True
ii. False

d. An “if” statement must always be inside of an “always” block.
i. True
ii. False
e. Verilog may be written at the Behavioral, Structural, Gate, Switch, and Transistor levels.
i. True
ii. False

f. The use of a tick timescale (‘timescale) enables code to be synthesized with the
specified delays. 
i. True
ii. False

g. Use of Blocking Assignments is preferable to Non-Blocking Assignments


because race conditions are less likely to occur. 
i. True
ii. False

h. Verilog permits module ports to be unconnected.


i. True
ii. False

5. Which of the following is(are) equivalent to logic level 1?
a. 1
b. 1’b1
c. 1 ‘b1
d. a and b
e. a, b and c

6. Which of the following is true about parameters?


a. The default size of a parameter in most synthesizers is the size of an integer, 32 bits.
b. Parameters enable Verilog code to be compatible with VHDL.
c. Parameters cannot accept a default value.
d. All of the above.
e. None of the above

7. Which of following tool/tools can be used to synthesize and implement a digital circuit
on a Nexys 4 DDR board?
a. Quartus Prime
b. Xilinx ISE
c. Vivado
d. a and c
e. b and c
8. Which of the following is true about the always block?
a. There can be exactly one always block in a design.
b. There can be exactly one always block in a module.
c. Execution of an always block occurs exactly once per simulation run.
d. An always block may be used to generate a periodic signal.

9. For describing circuits like flip flops _____________ statement is used
a. Always
b. Entity
c. Component
d. Process

10. Consider the following choices below. To comment Verilog Code, one may use:

I. A “Double-slash” // for a single-line comment.


II. Multiple “Double-slashes” (one per line) for a multiple-line comment.
III. A “Block-comment” /* */ for a single-line comment.
IV. A “Block-comment” /* */ for a multiple-line comment.

a. I and II
b. I and IV
c. II and III
d. I, II, and IV
e. I, II, III and IV

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