COMPUTER ORGANIZATION &

ARCHITECTURE LAB
Paper code – ETCS-254

Faculty Name: Sachin Garg

Student name: Anupam Gupta

Roll No. :35114803119
Branch: IT (1stShift)
Group: 4I9

Maharaja Agrasen Institute of Technology

PSP Area, Sector-22, Rohini, Delhi-110085
 COMPUTER ORGANIZATION & ARCHITECTURE LAB
Paper code – ETCS-254
PRACTICAL DETAILS
EXP Date Signature
NO.
LIST OF
EXPERIMENTS
1 To study about 8085 pins.

2 To study instructions of 8085.

3 To study how to install 8085 GNU

simulator.
 EXPERIMENT 1

Aim: To study about 8085 pins

THEORY: The following image depicts the pin diagram of 8085

Microprocessor −

The pins of a 8085 microprocessor can be classified into seven

groups:
Address bus: A15-A8, it carries the most significant 8-bits of memory/IO
address.
Data bus: AD7-AD0, it carries the least significant 8-bit address and data
bus.
Control and status signals: These signals are used to identify the nature
of operation. There are 3 control signal and 3 status signals.
Three control signals are RD, WR & ALE.
 RD − This signal indicates that the selected IO or memory device is
to be read and is ready for accepting data available on the data bus.
 WR − This signal indicates that the data on the data bus is to be
written into a selected memory or IO location.
 ALE − It is a positive going pulse generated when a new operation is
started by the microprocessor. When the pulse goes high, it
indicates address. When the pulse goes down it indicates data.
Three status signals are IO/M, S0 & S1.
IO/M: This signal is used to differentiate between IO and Memory
operations, i.e. when it is high indicates IO operation and when it is low
then it indicates memory operation.
S1 & S0: These signals are used to identify the type of current operation.
Power supply: There are 2 power supply signals − VCC & VSS. VCC
indicates +5v power supply and VSS indicates ground signal.
Clock signals: There are 3 clock signals, i.e. X1, X2, CLK OUT.
X1, X2: A crystal (RC, LC N/W) is connected at these two pins and is used
to set frequency of the internal clock generator. This frequency is internally
divided by 2.
CLK OUT: This signal is used as the system clock for devices connected
with the microprocessor.
Interrupts & externally initiated signals: Interrupts are the signals
generated by external devices to request the microprocessor to perform a
task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5,
and INTR.
INTA: It is an interrupt acknowledgment signal.
RESET IN: This signal is used to reset the microprocessor by setting the
program counter to zero.
RESET OUT: This signal is used to reset all the connected devices when
the microprocessor is reset.
READY: This signal indicates that the device is ready to send or receive
data. If READY is low, then the CPU has to wait for READY to go high.
HOLD: This signal indicates that another master is requesting the use of
the address and data buses.
HLDA (HOLD Acknowledge): It indicates that the CPU has received the
HOLD request and it will relinquish the bus in the next clock cycle. HLDA
is set to low after the HOLD signal is removed.
Serial I/O signals: There are 2 serial signals, i.e. SID and SOD and these
signals are used for serial communication.
 SOD (Serial output data line): The output SOD is set/reset as
specified by the SIM instruction.
 SID (Serial input data line): The data on this line is loaded into
accumulator whenever a RIM instruction is executed.
 EXPERIMENT 2

Aim: To study instructions of 8085 microprocessor

Instructio Explanation States Flags Addre- Machine Example

n Set ssing Cycles

MOV r1, r2 Move the 4 none Register 1 MOV A,

[r1] ← content of B
[r2] the one
register to
another

MOV r, M Move the 7 none Register 2 MOV B,

[r]←[[H- content of Indirect M
L]] memory to
register

MVI r, Move 7 None Immedia 3 MVI M,

data immediate te 08
[r] ←data data to Register
register

STAX rp Store 7 None Register 2 STAX D

[[rp]] accumulator Indirect
←[A] indirect

XCHG Change the 4 None Register 1

[H-L] contents of
↔[D-E] H-L with D-
E pair
 THEORY: Classification of Instruction Set

Data Transfer Instruction-: -: Instructions which are used to transfer the

data from a register to another register from memory to register or register to
memory come under this group.

Arithmetic Instructions-: The instructions of this group perform arithmetic

operations such as addition, subtraction, increment or decrement of the
content of a register or a memory.

Instructi Explanati Stat Fla Addre- Machi Examp

on Set on es gs ssing ne le
Cycles

ADD r Add 4 All Register 1 ADD

[A] register K
←[A]+ to
[r] accumula
tor

ADD M Add 7 All Register 2 ADD

[A] ← memory indirect K
[A] + to
[[H-L]] accumula
tor

ACC r Add 4 All Register 1 ACC

[A] ← register K
[A] + with
[r] + carry to
[CS] accumula
tor
 ADI Add 7 All Immedi 2 ADI
data immediat ate 55K
[A] ← e data to
[A] + accumula
data tor

DAD rp Add 10 CS Register 3 DAD

[H-L] register K
←[H-L] paid to
+ [rp] H-L pair

SUB r Subtract 4 All Register 1 SUB

[A] register K
←[A]- from
[r] accumula
tor

SUB M Subtract 7 AL Register 2 SUB

[A] ← memory L indirect K
[A] - from
[[H-L]] accumula
tor

SUI Subtract 7 All Immedi 2 SUI

data immediat ate 55K
[A] e data
←[A]- from
data accumula
tor

Logical Instructions The instructions in this group perform logical

operation such as AND, OR, compare, rotate, etc.

Instruction Explanation States Flags Addressing Machine

Set Cycles
 ANA r AND register 4 Al Register 1
[A] with l
←[A]∧[r] accumulator

ANA M AND memory 4 Al Register 2

[A] with l indirect
←[A]∧[[H accumulator
-]]

ANI data AND immediate 7 Al Immediate 2

[A] ← [A] data with l
∧ [data] accumulator

ORA r OR-register 4 Al Register 1

[A] with l
←[A]∨[r] accumulator

ORA M OR-memory 7 Al Register 2

[A] with l indirect
←[A]∨[[H accumulator
-L]]

Branching Instructions -: This group contains the instructions for

conditional and unconditional jump, subroutine call and return, and restart.

Unconditional Jump

Instruction Explanation Stat Flag Addres Machi

Set es s sing ne
 Cycles

JMP Unconditional jump: jump 10 No Imme 3

addr(label to the instruction specified ne diate
) by the address
[PC] ←
Label

Conditional Jump

Instruction Explanation States Machine

Set Cycles

Jump addr Conditional jump: jump to the 10, if true 3, if true and
(label) instruction specified by the and 2, if not true
[PC] ← address if the specified 7, if not
Label condition is fulfilled true

EXPERIMENT 3

Aim: To study how to install 8085 GNU simulator.

THEORY:
STEP 1:
Visit the Website through the provided Link :- https://gnusim8085.github.io/

STEP 2:
Then click on All Downloads Option.

Step 3: Then download the exe file.

Step 4: Check on I accept the terms of the license Agreement.

Step 5: Click next , next..

Step 6: Then it will get installed and the screen will open like this:-

Now, it is installed, successfully.