Scribd
Upload
24 views5 pages

Elec 263 Computer Architecture and Organization

Uploaded by

anand_sesham
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
24 views5 pages

Elec 263 Computer Architecture and Organization

Uploaded by

anand_sesham
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

1

ELEC 263 COMPUTER


ARCHITECTURE AND
ORGANIZATION
Dr. Mohamed Al-Meer
485-2899
[email protected], [email protected]

CHAPTER 5:
BASIC COMPUTER ORGANIZATION AND DESIGN
5-1 Instruction Codes
5-2 Computer Registers
5-3 Computer Instructions
5-4 Timing & Control
5-5 Instruction Cycle
5-6 Memory Reference Instructions
5-7 Input-Output & Interrupts
5-8 Complete Computer Description
5-9 Design of Basic Computer
5-10 Design of Accumulator Logic

5-3 Computer Instructions

The Basic Computer has 3 instruction code formats as shown in next figure. Each format
has 16 bits.

 The op-code of the instruction contains 3 bits and the meaning of the remaining
13 bits depends on the operation code encountered.
 Memory reference instruction uses 12 bits to specify the operand address and
one bit for indirect address.
 The register reference instruction are recognized by op-code 111 with 0 in left
most bit (Bit 15) of the instruction. The 12 bits are used in to specify the
operation done with AC register.
 Input-Output instruction is recognized by op-code 111 and with 1 in bit 15. The
remaining 12 bits are used to specify type of Input-Output instruction type.
2

 Only 3 bits of the instruction are used for the operation code, op-code, and since
register reference instructions and IO instructions use the other unneeded 12
bits, so the total number of instruction coded in this computer is 25.

A computer should have a set of instructions so that the user can construct machine
language programs to evaluate any function that is known to be computable. Instruction
Types will be:

 Functional Instructions includes


o Arithmetic, logic, and shift instructions
o ADD, CMA, INC, CIR, CIL, AND, CLA

 Transfer Instructions
o Data transfers between the main memory and the processor registers
o LDA, STA

 Control Instructions
o Program sequencing and control
o BUN, BSA, ISZ

 Input-Output Instructions
o Input and output
o INP, OUT
3

5-4 Timing & Control

The timing for all registers is controlled by a master clock. The clock pulses generated
do not change the state of a register unless it is enabled by a control signal.

Control unit (CU) of a processor translates from machine instructions to the control
signals for the micro-operations that implement them. The control signals are generated
in the control unit and provides control inputs to

All register
Multiplexers
Common bus
And micro-operation indicators

Control units are implemented in one of two ways:

 Hardwired Control
o CU is made up of sequential and combinational circuits to generate the
control signals
4
 Micro-programmed Control
o A control memory on the processor contains micro-programs that
activate the necessary control signals

 We will consider a hardwired implementation of the control unit for the Basic
Computer

The next figure shows a block diagram of control unit of the basic computer

It consists of 2 decoders, a sequence counter, and a number control logic gates.

 The instruction register holds the instruction fetched from memory. It is divided
into 3 parts: I bit, op-code, and 12 bits.
o Op-codes is divided by 3 by 8 decoder into 8 different outputs; D0 to D7
o Bit 15 is transferred to I flip flop
o Bit 0 to Bit 11 (B0 to B11) are applied to control logic gates.

 The 4-bit sequence counter is connected to 4 by 16 decoder giving control inputs


T0 to T15.
o Used to synchronize action with those 16 different time intervals.
o Sequence counter can be incremented and cleared synchronously.
o Most of the time it is incremented to generate sequence of timing signals
o Once in a while it is cleared by specific condition causing next timing
5
sequence to go back to T0.

Example on Timing Control:

 Consider a case where SC is incremented to provide timing sequence T0, T1, T2,
T3, and T4, then T0 again. At time T4 Sc is cleared based on a condition D3 is
true. Expressed in symbolic RTL form:

D3T4: SC  0

The next figure shows its timing diagram. When D3T4 is true then at first
positive clock transition SC is cleared.

If SC is not cleared then it will continue its counting from T5 to T15 then it rolls
over to T0 again.

 For a memory read operation, it must be clear that between 2 rising edge of the
clock, the data should be read and applied to the bus, so that at next rising edge
the data can be saved in destination register.

 The next symbolic RTL

T0: AR  PC

That specifies transfer of data from PC to AR register in one clock pulse T0. The
content PC is put on the bus (S2S1S0=010) and LD of AR register is enabled
during T0 cycle only.

You might also like