MCQ WITH ANSWERS

DIGITAL ELECTRONICS [PC-EE-402]

SEMESTER-4TH [EE]
GROUP-A

Answer 50 MCQ type questions [each carrying one marks]

1. What is the next octal counting sequence 524, 525,526,527

A) 528 B) 529 * C) 530 D) 531

2. An example of reflected code is

A) BCD B) ASCII *C) GRAY D) Hamming code

3. One bit even parity detector code fails to detect

*A) any even number of error B) any odd number of error C) both (a) & (b) D)
none of these

4. What is the logical expression of D6 output of an active low decoder in terms of A,B and C?
A) AB ̅ B) ̅ C) ̅+ +C * D) both (b) and (c)

5. The minimum number of NAND gates required to design one X-OR gate is
A) 3 *B) 4 C) 5 D) 6

6. 8 X 1 MUX has
A) one select line B) two select line *C) three select line D) none of these

7. Gray code of (1011)2 is

A) 1000 B) 1100 *C) 1110 D) 1111

8. A bubbled AND gate is equivalent to a

A) OR-gate B) NAND gate *C) NOR gate D) X-OR gate

9. The code used for correcting errors in data transmission is

A) Gray code B) Excess-3 Code C) BCD *D) Hamming code

10. A carry look ahead adder is frequently used for addition because it
*A) is faster B) is more accurate C) used fewer gates D) less cost

11. The number of full adder required to add two m bit number
*A) m B) 3 C) m+1 D) 2
12. 1000 is a 2’s complement number. Its sign and magnitude
A) Positive, 0 B) negative, 7 * C) negative, 8 D) negative, 0

13. The maxterms corresponding to decimal 14 is

A. A B C *B) + + + D C) A + B + C + D) ̅ ̅D

14. The maximum positive number that can be represented in 1’s complement representation is
*A)2n-1 -1 B) 1-2n-1 C) –(2n-1 -1) D) 2n-1

15. Dual form of A(B+C) is

*A) A+BC B) AB+AC C) AB+C D) A+B

16. Decimal 43 in Hexadecimal and BCD number system is respectively

A) B2,01000011 *B) 2B, 0100 0011 C) 2B, 0011 0100 D)B2, 0100 0100

17. Boolean expression for the output of XNOR (equivalence) logic gate with inputs A and B is
A) A.B’+A’B *B) A’.B’+A.B C) (A’+B).(A+B’) D)
(A’+B’).(A+B)

18. The logical expression Y = A + AB is equivalent to

A) y = AB B) Y = AB C) y =A + B *D) Y = A + B

19. The output of a logic gate is ‘1’when all its inputs are at logic ‘0’. The gate is either
A) a NAND or an EX-OR gate *B) a NOR or an EX-NOR gate
C) an OR or an EX-NOR gate D) an AND or an EX-OR gate

20. Without any additional circuitry, an 8 :1 MUX can be used to obtain

A) some but not all Boolean functions of 3 variables
B) all functions of 3 variables but none of 4 variables
*C) all functions of 3 variables and some but not all of 4 variables
D) all functions of 4 variables

21. The JK FF has toggle state when-

A. J=1, K=0 B. J=0,K=1 C. J=0,K=0 *D. J=1,K=1
22. Asynchronous counter are known as-
A. decade counter B. mod counter C. parallel counter *D. ripple
counter

23. A D/A converter has a …………..input and …………output

*A. digital, analog B. analog, analog C. digital, digital D. analog,
digital

24. A ring counter is the same as

A. * shift register B. parallel counter C. up-down counter
D. none of the above
25. The maximum number of states that a counter with ‘n’ number of flip-flops has:
 A. 1/2 B. n *C. 2n D. 2n

26. A 4 stage ripple counters count up to

A. 12 *B. 15 C. 11 D. 4

27. Dual-Slop is a type of __________

*A. ADC B. DAC C. Memory device D. Register

28. 4 T flip-flop can generate

A. 0 – 16 binary states *B. 0 – 15 binary states
C. 0 – 11 binary states D. none of these.
29. To design an MOD-N Johnson Counter the number of F/F required are
A. N B. N-1 C. 1/(2N+1) *D. N/2

30. How many F/F are required to design MOD-1024 counter?

A. 1024 *B. 10 C. 102 D. 24
31. Which of the followings are correct?
1.A F/F is used to store 1-bit of information
2.Race around condition occurs in JK F/F when both the inputs are 1
3.master-slave F/F is used to store 2 bits of information
4.A transparent latch consists of a D F/F
A. 1, 2, 3 B. 1, 3, 4 * C. 1, 2, 4 D. 2, 3, 4

32. F/F that makes output equals to input after clock (act as a buffer) is
A. J-K F/F *B. D F/F C. T F/F D. none of these

33. By placing an inverter between both input of an S-R flip-flop, it becomes

A. J-K flip-flop *B. D flip-flop C. T flip-flop D. Master slave
flip-flop

34. The fastest logic family is

A. TTL *B. ECL C. TRL D. DRL

35. The power consumption is least for the …………logic gate family
A. ECL B. TTL *C. CMOS D. DCTL
36. The invalid state of a S-R NAND latch occurs when
A. S=1, R=0 B. S=0, R=1 C. S=0, R=0 *D.
S=1,R=1
37. A latch is a
*A. 1-bit memory cell B. 2-bit memory cell
C. 3-bit memory cell D. 10-bit memory cell
38. The number of comparators required in an 8-bit flash-type A/D converter is
A. 256 *B. 255 C. 64 D. 8
39. Which family has the better noise margin?
A. ECL B. DTL *C. MOS D. TTL

40. The number of flip-flops required for a MOD-10 ring counter is

A.4 B. 10 *C. 5 D. none of these.
41. The time required for a pulse to change from 10% to 90% of its maximum value is defined as
A. * rise time B. decay time C. propagation time D. operating speed
42. The information in ROM is stored
(A) By the user any number of times.
*(B) By the manufacturer during fabrication of the device.
(C) By the user using ultraviolet light.
(D) By the user once and only once.
43. Data can be changed from special code to temporal code by using
(A) *Shift registers (B) counters (C) Combinational circuits (D) A/D converters.
44. The speed of conversion is maximum in
(A) Successive-approximation A/D converter.
*(B) Parallel-comparative A/D converter.
(C) Counter ramp A/D converter.
(D) Dual-slope A/D converter.
45. Which of the memory is volatile memory
(A) ROM *(B) RAM (C) PROM (D) EEPROM

46. Which of the following is non-saturating?

A) TTL B) CMOS *C) ECL D) Both 1 and 2

47. A decade counter skips ………..

A)binary states 1000 to 1111 B) binary states 0000 to 0011 *C) binary states 1010 to 1111
D) binary states 1111 to higher

48. BCD input 1000 is fed to a 7 segment display through a BCD to 7 segment decoder/driver.
The segments which will lit up are ………….
A) a, b, d B) a, b, c *C) all D) a, b, g, c, d

49. The basic storage element in a digital system is ………….

A) *Flipflop B) Counter C) multiplexer D) encoder

50. The difference between a PLA and a PAL is:

A) *The PLA has a programmable OR plane and a programmable AND plane, while the
PAL only has a programmable AND plane.
B) The PAL has a programmable OR plane and a programmable AND plane, while the PLA
only has a programmable AND plane.
C) The PAL has more possible product terms than the PLA.
D) PALs and PLAs are the same thing.
 GROUP-B

Answer 50 MCQ type questions [each carrying two marks]

1. For the circuit shown below the output F is given by

A)F=1 *B) F=0 C) F = X D) F = X

2. The minimum number of NAND gates required to implement the Boolean function A + A B +
A B C is equal to
A) Zero B) 4 * C) 1 D) 7

3. The 2’s complement representation of -17 and +18 are respectively

A) 101110, 110010
B) *101111, 010010
C) 111110, 101101
D) 110001, 001101

4. The Boolean expression A + BC is equivalent to

A) AC + BC + AC
B) BC + AC+ BC + ACB
C) *ABC + A + A C + AB + B
D) ABC + ABC + ABC + ABC

5. The Boolean expression in POS form for the truth table shown is

A B C Y
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

A) (A+B+C) (A+B+C) (A+B+C) (A+B+C)

*B) (A+B+ ) (A+ +C) ( +B+ ) ( + +C)
 C) ABC + ABC + ABC+ A B C
D) ̅ BC + ABC + ABC + ABC

6. In the sum of products function Y(A, B, C)= ∑(2,3,4,5) , the prime implicates are

*A) +A
B) A B C + A B C
C) B C + B C
D) A B C + A B C

7. Let P = 25 and Q = 25, subtract Q from P using both 1’s complement and 2’s complement
methods, then the results obtained after 1’s complement and 2’s complement arithmetic are
respectively
A) -0, -0
B) 0, 0
*C) -0, +0
D) +0, -0

8. The output of the circuit shown in figure is equal to

A) 0 * B) 1 C) A B + A D) A B + A B

9. What are the minimum number of 2-to-1 multiplexers required to generate a 2-input AND gate and
a 2-input Ex-OR gate?

A) 1 and 2 B) 1 and 3 *C) 1 and 1 D) 2 and

2

10. Let F2 =1, represent the output of a 2-bit magnitude comparator circuit when input B ≥ A. How
many possible combinations for which F2 =1 is true

A) 6 B) 7 *C) 10 D) 8

11. A function of Boolean variables, X, Y and Z is expressed in terms of the min-terms as

F(X, Y, Z) = ∑(1, 2, 5, 6, 7).
Which one of the product of sums given below is equal to the function F(X, Y, Z)?
 A) (X + Y +Z)·( X + Y +Z)·(X + Y +Z)
B) *(X + Y + Z)· (X + + )· ( + Y + Z)
C) (X + Y +Z)·( X + Y +Z)·(X + Y+Z) ·(X + Y +Z)·(X + Y +Z)
D) (X + Y +Z)· (X + Y + Z)· (X + Y +Z) (X + Y+Z)·( X +Y +Z)

12. Simplified form the Boolean function F(A,B,C,D)= ∑(0,1,2,8,10,11,14,15)+∑d(3,13)

using K-MAP in SOP form is
A) * + AC +
B) AB + BD + A C
C) ( ̅ + B) ( + )( B + )
D) ̅ B + AC + B + ABD

13. The following circuit diagram represent by which of the following SOP expression

A) Y= Σ( 0,1,4,5,7)
*B) Y= Σ( 0,2,4,5)
C) Y= Σ( 0,1,5,7)
D) Y= Σ( 0,3, 5,7)

14. The Boolean expression

(X +Y) (X+ Y) + ((X Y ) + X ) simplifies to

A) *X
B) Y
C) XY
D) X+Y

15. The logic realized by the circuit shown in figure is

 *A) A ⊕ B B) A ⊙ B C) A.B D) A + b

16. An 8-to-1 multiplexer is used to implement a logical function Y as shown in the figure. The output

*A) A.B. + .C.D

B) ABC + ABC
C) ̅ BCD + ABC
D) A.BC + A.C.D
17. Two 4-bit binary numbers (1011 and 1111) are applied to a 4-bit parallel adder. The carry
input is 1. What are the values for the sum and carry output?
A) Sum= 1011, carry= 0
B) Sum= 1010, carry= 1
*C) Sum= 1011, carry= 1
D) Sum= 11011, carry= 1

18. A 16-bit ripple carry adder is realized using 16 identical full adders (FA). The carry-propagation
delay of each FA is 12 ns and the sum-propagation delay of each FA is 15 ns. The worst case delay
(in ns) of this 16-bit adder will be ________________.

A) 175 ns B) 185 ns *C) 195 ns D) 205 ns

19. To design a 5:32 Decoder how many 2:4 and 3:8 decoder ICs are required?
A) One 2:4 and five 3:8
 B) Eight 2:4 and four 3:8
C) *One 2:4 and four 3:8
D) Four 2:4 and four 3:8

20. During 4-bit BCD addition which of the following numbers generate invalid result
I. 4+5 II. 5+6 III. 8+9 IV. 5+2
A) III only *B) II and III C) II only D) All of the
above
21. A 10 MHz signal is applied to a MOD-5 counter followed by a MOD-8 counter then the
o/p frequency will be-
A. 10 KHz B. 2.5 KHz C. 5 KHz *D. 250 KHz

22. The resolution of 8 bit A/D converter is

A. 0.62٪ B. 0.38٪ *C. 0.39٪ D.
1.25٪
23. If tp is he pulse width, t is the propagation delay and T is the period of the pulse train,
then which one of the following condition can avoid the race around conditions?
A. tp = t = T B. 2tp >t > T *C. tp <t < T D. 2tp
<t < T
24. The total conversion time need for Successive Approximation type N-bit ADC is
A. (N-1) clock time period B. (2N X 1) clock time period
C. (2N-1) clock time period *D. none of these
25. For a n-bit parallel-in-parallel-out shift register we need ________ clock pulse(s) to
transfer all the input bits to output
A. * 1 B. n C. 2n+1 D. n+1
26. A 4-bit synchronous counter uses flip-flops with propagation delay time of 25ns each. The
maximum possible time required for change of state will be
*A. 25ns B. 50ns C. 75ns D. 100ns

27. If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in
cascade is
(A) 1000 Hz (B) 500 Hz (C) 333 Hz *(D) 12.5 Hz
28. Which of the following memories stores the most number of bits
(A) *a 5M×8 memory. (B) a 1M × 16 memory. (C) a 5M× 4memory. (D) a 1M×12
memory..
29. How many address bits are required to represent a 32 K memory
(A) 10 bits. (B) 12 bits. (C) 14 bits. *(D) 16 bits.
30. An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds.
The pulse width of the strobe is 50ns. The frequency of the input signal which can be used
for proper operation of the counter is approximately
(A) *1 MHz. (B) 500 MHz. (C) 2 MHz. (D) 4 MHz.
31. The output of a JK flip flop with asynchronous preset and clear inputs is ‘1’. The output
can be changed to ‘0’ with one of the following conditions.
(A) By applying J = 0, K = 0 and using a clock.
(B) By applying J = 1, K = 0 and using the clock.
(C) By applying J = 1, K = 1 and using the clock.
 *(D) By applying J = 0, K = 1 and using the clock.

32. A weighted resistor digital to analog converter using N bits requires a total of
(A) *N precision resistors. (B) 2N precision resistors. (C) N + 1 precision resistors.
(D) N – 1 precision resistors.
33. Shifting a register content to left by one bit position is equivalent to
(A) division by two. (B) addition by two. *(C) multiplication by two. (D)
subtraction by two.
34. How many flip-flops are required to construct mod 30 counter
(A) *5 (B) 6 (C) 4 (D) 8

35. CMOS circuits are extensively used for ON-chip computers mainly because of their
extremely
A) *low power dissipation. (B) high noise immunity. (C) large packing density. (D)
low cost.
36. Which of following can not be accessed randomly
(A) DRAM. (B) SRAM. (C) ROM. *(D) Magnetic tape.
37. What is the analog output voltage of 6-bit DAC (R-2R ladder network) with Vref as 5V
when the digital input is 011100.
A) *2.1875 V (B) 28V. (C) 2.75V. (D) 3.1875V
38. What is the conversion time of a Successive Approximation A/D converter which uses a 2
MHz clock and a 5-bit binary ladder containing 8V reference.
A) 5 μ sec * B) 2.5 μ sec C) 10 μ sec D) 4 μ sec
39. A 6-bit R-2R ladder D/A converter has a reference voltage of 6.5V. It meets standard
linearity. What is the percentage resolution?
A) 3.2 % B) 1.11 % *C) 1.59 % D) 2.59 %
40. An 8-bit successive approximation ADC has a resolution of 20mV. What will be its digital
output for an analog input of 2.17V?
A) 0110011.1 B)1111111.1 C)1111000.1 *D) 1101100.1
41. Find how many bits of ADC are required to get an resolution of 0.5 mV if the maximum
full scale voltage is 10 V.
A) 20 B) 18 C) 10 *D) 16
42. The logic 0 level of a CMOS logic device is approximately
(A) 1.2 volts (B) 0.4 volts (C) 5 volts *(D) 0 volts

43. An 8 bit DAC has a full scale output of 2 mA and full scale error of ± 0.5%. If input is
10000000 the range of outputs is ………….

*A) 994 to 1014 μA B) 990 to 1020 μA C) 800 to 1200 μA D) none of the above

44. The access time of a word in 4 MB main memory is 100 ms. The access time of a word in
a 32 kb data cache memory is 10 ns. The average data cache bit ratio is 0.95. The
efficiency of memory access time is ………
A) 9.5 ns *B) 14.5 ns C) 20 ns D) 95 ns

45. A JK flip flop has tpd= 12 ns. The largest modulus of a ripple counter using these flip flops
and operating at 10 MHz is ……..
 A) 16 B) 64 C) 128 *D)
D) 256

46. The counter in the given figure

re is ………….

A) Mod 3 *B) Mod 6 C) Mod 8 D) Mod 7

47. A memory system of size 16 k bytes is to be designed using memory chips which have 12
address lines and 4 data lines each. The number of such chips required to design the
memory system is ……….

A) 2 B) 4 *C) 8 D) 18

48. A counter type A/D converter contains a 4 bit binary ladder and a counter driven by a 2
MHz clock. Then conversion time is ………..
A) *8 μ sec B) 10 μ sec C) 2 μ sec D) 5 μ sec

49. The circuit in the given figure is a ………… gate.

A) positive logic OR gate *B)

B) negative logic OR gate C) negative logic AND gate D)
positive logic AND gate

50. The access time of a word in 4 MB main memory is 100 ms. The access time of a word in
a 32 kb data cache memory is 10 ns. The average data cache bit ratio is 0.95. The
efficiency
ncy of memory access time is ………
A) 9.5 ns *B) 14.5 ns C) 20 ns D) 95 ns