Name : Umar ali

Roll# : 522

Class# : 5th semester

Submitted to : Sir Farhatullah

Week : 07
Subject : Microprocessor and
Assembly language
Instruction Set of 8085:
The various techniques to specify data for instructions are:
• 8-bit or 16-bit data may be directly given in the instruction itself.

• The address of the memory location, I/O port or I/O device, where data

resides, may be given in the instruction itself.

• In some instructions, only one register is specified. The content of the

specified register is one of the operands.

• Some instructions specify two registers. The contents of the registers are the

required data.

• In some instructions, data is implied. The most instructions of this type

operate on the content of the accumulator.

Due to different ways of specifying data for instructions, the machine codes
of all instructions are not of the same length. It may 1-byte, 2-byte or 3-
byte instruction.

Addressing Modes:
Each instruction requires some data on which it has to operate. There
are different techniques to specify data for instructions. These
techniques are called addressing modes. Intel 8085 uses the
following addressing modes:
• Direct Addressing

In this addressing mode, the address of the operand (data) is given in the
instruction itself.
Example
STA 2400H: It stores the content of the accumulator in the memory
location 2400H.
32, 00, 24: The above instruction in the code form.
In this instruction, 2400H is the memory address where data is to be stored.
It is given in the instruction itself. The 2nd and 3rd bytes of the instruction
specify the address of the memory location. Here, it is understood that the
source of the data is accumulator.
• Register Addressing

In register addressing mode, the operand is in one of the general purpose

registers. The opcode specifies the address of the register(s) in addition to
the operation to be performed.
Example:
MOV A, B: Move the content of B register to register A.
78: The instruction in the code form.
In the above example, MOV A, B is 78H. Besides the operation to be
performed the opcode also specifies source and destination registers.
The opcode 78H can be written in binary form as 01111000. The first two
bits, i.e. 0 1 are for MOV operation, the next three bits 1 1 1 are the binary
code for register A, and the last three bits 000 are the binary code for
register B.
• Register Indirect Addressing

In Register Indirect mode of addressing, the address of the operand is

specified by a register pair.
Example
• LXI H, 2500 H - Load H-L pair with 2500H.

• MOV A, M - Move the content of the memory location, whose address is in

H-L pair (i.e. 2500 H) to the accumulator.

• HLT - Halt.

In the above program the instruction MOV A, M is an example of register

indirect addressing. For this instruction, the operand is in the memory. The
address of the memory is not directly given in the instruction. The address of
the memory resides in H-L pair and this has already been specified by an
earlier instruction in the program, i.e. LXI H, 2500 H.
• Immediate Addressing

In this addressing mode, the operand is specified within the instruction itself.
Example
LXI H, 2500 is an example of immediate addressing. 2500 is 16-bit data
which is given in the instruction itself. It is to be loaded into H-L pair.
• Implicit Addressing

There are certain instructions which operate on the content of the

accumulator. Such instructions do not require the address of the operand.
Example
CMA, RAL, RAR, etc.

Status Flags:
There is a set of five flip-flops which indicate status (condition) arising after
the execution of arithmetic and logic instructions. These are:
• Carry Flag (CS)

• Parity Flag (P)

• Auxiliary Carry Flags (AC)

• Zero Flags (Z)

• Sign Flags (S)

Symbols and Abbreviations

The symbol and abbreviations which have been used while explaining Intel
8085 instructions are as follows:
Symbol/Abbreviations Meaning
Addr 16-bit address of the

memory location.

Data 8-bit data

data 16 16-bit data

r, r1, r2 One of the registers A, B,

C, D, E, H or L

A, B, C, D, H, L 8-bit register
A Accumulator

H-L Register pair H-L

B-C Register pair B-C

D-E Register pair D-E

PSW Program Status Word

M Memory whose address is

in H-L pair

H Appearing at the end of

the group of digits

specifies hexadecimal,

e.g. 2500H

Rp One of the register pairs.

Rh The high order register of

a register pair

Rl The low order register of

a register pair

PC 16 bit program counter,

PCH is high order 8 bits

and PCL low order 8 bits

of register PC.

CS Carry Status

[] The contents of the

register identified within

bracket

[ [] ] The content of the

memory location whose

address is in the register

pair identified within

 brackets

^ AND operation

∨ OR operation

⊕ or ∀ Exclusive OR

← Move data in the

direction of arrow

⇔ Exchange contents

Intel 8085 Instructions:

An instruction of a computer is a command given to the computer to
perform a specified operation on given data. In microprocessor,
the instruction set is the collection of the instructions that the
microprocessor is designed to execute.
The programmer writes a program in assembly language using these
instructions. These instructions have been classified into the following
groups:
Data Transfer Group
Instructions which are used to transfer the data from a register to another
register from memory to register or register to memory come under this
group.
Instructio Explanation State Flags Addre-ssing Machin Exampl
n Set s e Cycles e
MOV r1, Move the 4 non Register 1 MOV

r2   content of e A, B

[r1] ← the one

[r2] register to

another

MOV r, Move the 7 non Register 2 MOV

M  content of e Indirect B, M

[r]←[[H memory to
-L]] register

MOV M, Move the 7 non Register 2 MOV

r content of e Indirect M, C

[[H- register to

L]]←[r] memory

MVI r, Move 7 Non Immediat 3 MVI

data immediate e e Register M, 08

[r] data to

←data register

LXI rp, Load 10 Non Immediat 3 LXI H,

data 16 Register e e 2500

[rp] pair H

←data immediate

16 bits,

[rh] ←8

MSBs,

[rl] ←8

LSBs of

data

LDA Load 13 Non Direct 4 LDA

addr Accumulato e 2400

[A] r direct H

←[addr]

STA Store 13 Non Direct 4 STA

Addr accumulato e 2000

[addr] r direct H

←[A]
 LHLD Load H-L 16 Non Direct 5 LHLD

addr pair direct e 2500

[L] H

←[addr]

, [H] ←

[addr +

1]

SHLD Store H-L 16 Non Direct 5 SHLD

addr pair direct e 2500

[addr] H

←[L],

[addr

+1] ←

[H]

LDAX rp Load 7 Non Register 2 LDAX

[A] accumulato e Indirect B

←[[rp]] r indirect

STAX rp Store 7 Non Register 2 STAX

[[rp]] accumulato e Indirect D

←[A] r indirect

XCHG Change the 4 Non Register 1

[H-L] contents of e

↔[D-E] H-L with D-

E pair

Arithmetic Group
The instructions of this group perform arithmetic operations such as
addition, subtraction, increment or decrement of the content of a register or
a memory.
Instructio Explanation State Flags Addre-ssing Machin Exampl
n Set s e Cycles e
ADD r Add 4 All Register 1 ADD

[A] register to K

←[A]+ accumulat

[r] or

ADD M Add 7 All Register 2 ADD

[A] ← memory to indirect K

[A] + accumulat

[[H-L]] or

ACC r Add 4 All Register 1 ACC

[A] ← register K

[A] + with carry

[r] + to

[CS] accumulat

or

ADC M Add 7 All Register 2 ADC

[A] ← memory indirect K

[A] + with carry

[[H-L]] to

[CS] accumulat

or

ADI Add 7 All Immediat 2 ADI

data immediate e 55K

[A] ← data to

[A] + accumulat

data or
ACI Add with 7 All Immediat 2 ACI

data carry e 55K

[A] ← immediate

[A] + data to

data + accumulat

[CS] or

DAD rp Add 10 CS Register 3 DAD

[H-L] register K

←[H-L] paid to H-L

+ [rp] pair

SUB r Subtract 4 All Register 1 SUB

[A] register K

←[A]- from

[r] accumulat

or

SUB M Subtract 7 ALL Register 2 SUB

[A] ← memory indirect K

[A] - from

[[H-L]] accumulat

or

SBB r Subtract 7 All Register 2 SBB

[A] memory indirect K

←[A]- from

[H-L]] - accumulat

[CS] or with

borrow

SUI Subtract 7 All Immediat 2 SUI

data immediate e 55K

[A] data from

←[A]- accumulat

data or

SBI Subtract 7 All Immediat 2 XCHG

data immediate e

[A] data from

←[A]- accumulat

data- or with

[CS] borrow

INR r Increment 4 All Register 1 INR K

[r] ←[r] register excep

+1 content t

carry

flag

INR M Increment 10 All Register 3 INR K

[[H-L]] memory excep indirect

←[[H- content t

L]]+1 carry

flag

DCR r Decrement 4 All Register 1 DCR

[r] ←[r] register excep K

-1 content t

carry

flag

DCR M Decrement 10 All Register 3 DCR

[[H-L]] memory excep indirect K

 ← [[H- content t

L]]-1 carry

flag

INX rp Increment 6 None Register 1 INX K

[rp] memory

←[rp] content

+1

DCX rp Decrement 6 None Register 1 DCX

[rp] register K

←[rp]-1 pair

DAA Decimal 4 1 DAA

adjust

accumulat

or

Logical Group
The instructions in this group perform logical operation such as AND, OR,
compare, rotate, etc.
Instruction Explanation States Flags Addressing Machine
Set Cycles
ANA r AND 4 All Register 1

[A] register with

←[A]∧[r] accumulator

ANA M AND 4 All Register 2

[A] memory indirect

←[A]∧[[H- with

]] accumulator

ANI data AND 7 All Immediat 2

[A] ← [A] immediate

∧ [data] data with e

accumulator

ORA r OR-register 4 All Register 1

[A] with

←[A]∨[r] accumulator

ORA M OR-memory 7 All Register 2

[A] with indirect

←[A]∨[[H- accumulator

L]]

ORI data OR 7 All Immediat 2

[A] ← [A] -immediate e

∨ [data] data with

accumulator

XRA r [A] XOR 4 All Register 1

← [A]∀[r] register with

accumulator

XRA M [A] XOR 7 All Register 2

← [A] ∀ memory indirect

[[H-L]] with

accumulator

XRI data XOR 7 All Immediat 2

[A] ←[A] immediate e

∀ [data] data with

accumulator

CMA [A] Complement 4 None Implicit 1

←[A] the

accumulator
CMC Complement 4 CS 1

[CS] the carry

←[CS] status

STC Set carry 4 CS 1

[CS] ← 1 status

CMP r Compare 4 All Register 1

[A]-[r] register with

accumulator

CMP M Compare 7 All Register 2

[A] - [[H- memory indirect

L]] with

accumulator

CPI data Compare 7 All Immediat 2

[A] - data immediate e

data with

accumulator

RLC Rotate 4 Cs Implicit 1

[An+1] accumulator

←[An], left

[A0]

←[A7],

[CS]

←[A7]

RRC Rotate CS Implicit 1

[A7] accumulator

←[A0], right

[CS]
 ←[A0],

[An]

←[An+1]

RAL Rotate CS Implicit 1

[An+1] accumulator

←[An], left through

[CS] carry

←[A7],

[A0]

←[CS]

RAR Rotate CS Implicit 1

[An] accumulator

←[An+1], right

[CS] through

←[A0], carry

[A7]

←[CS]

Branch Control Group

This group contains the instructions for conditional and unconditional jump,
subroutine call and return, and restart.
Unconditional Jump
Instruction Explanation States Flags Addressing Machine
Set Cycles
JMP Unconditional 10 None Immediate 3

addr(label jump: jump

) to the

[PC] ← instruction

specified by
 Label the address

Conditional Jump
Instruction Explanation States Machine
Set Cycles
Jump addr Conditional 10, 3, if

(label) jump: jump if true

[PC] ← to the true and

Label instruction and 2, if not

specified by 7, if true

the address not

if the true

specified

condition is

fulfilled

Instructio Explanatio Status States Flags Addressing Machin

n Set n e Cycles
JZ addr Jump, if Jump 7/1 Non Immediat 2/3

(label) the result if 0 e e

[PC] ← is zero Z=1

address

(label)

JNZ Jump if Jump 7/1 Non Immediat 2/3

addr the result if 0 e e

(label) is not Z=0

[PC] ← zero

address

(label)

JC addr Jump if Jump 7/1 Non Immediat 2/3

(label) there is a if CS 0 e e

[PC] ← carry =1

address

(label)

JNC Jump if Jump 7/1 Non Immediat 2/3

addr there is if CS 0 e e

(label) no carry =0

[PC] ←

address

(label)

JP addr Jump if Jump 7/1 Non Immediat 2/3

(label) result is if 0 e e

[PC] ← plus S=0

address

(label)

JM addr Jump if Jump 7/1 Non Immediat 2/3

(label) result is if 0 e e

[PC] ← minus S=1

address

(label)

JPE addr Jump if The 7/1 Non Immediat 2/3

(label) even parity 0 e e

[PC] ← parity statu

address s P

(label) =1

JPO addr Jump if The 7/1 Non Immediat 2/3

(label) odd parity 0 e e

 [PC] ← parity statu

address s P

(label) =0

Unconditional CALL
Instruction Explanation States Flags Addressing Machine
Set Cycles
CALL addr Unconditional 18 None Immediate 5

(label) CALL: Call /register

[SP]-1] ← the

[PCH] , subroutine

[[SP-2] ← identified by

[PCL], the address

[SP] ←

[SP]-2,

[PC] ←

addr(label

Conditional CALL
Instruction Explanation States Machine
Set Cycles
CALL addr Unconditional 18, 5, if

(label) CALL: Call the if true

[SP]-1] ← subroutine true and

[PCH] , identified by and 2, if

[[SP-2] ← the address if 9, if not

[PCL], the specified not true

[PC] ← condition is true

 addr fulfilled

(label),

[SP] ←

[SP]-2

Instruction Explanation Status States Flags Addressing Machin

Set e Cycles
CC Call CS 9/1 Non Immediat 2/5

addr(label subroutin =1 8 e e

) e if carry /register

status

CS=1

CNC addr Call CS 9/1 Non Immediat 2/5

(label) subroutin =0 8 e e

e if carry /register

status

CS=0

CZ addr Call Zero 9/1 Non Immediat 2/5

(label) Subroutin status 8 e e

e if the Z=1 /register

result is

zero

CNZ addr Call Zero 9/1 Non Immediat 2/5

(label) Subroutin status 8 e e

e if the Z=0 /register

result is

not zero

CP addr Call Sign 9/1 Non Immediat 2/5

 (label) Subroutin status 8 e e

e if the S=0 /register

result is

plus

CM addr Call Sign 9/1 Non Immediat 2/5

(label) Subroutin status 8 e e

e if the S= 1 /register

result is

minus

CPE Call Parity 9/1 Non Immediat 2/5

addr(label subroutin Statu 8 e e

) e if even s P=1 /register

parity

CPO Call Parity 9/1 Non Immediat 2/5

addr(label subroutin Statu 8 e e

) e if odd s P= /register

parity 0

Unconditional Return
Instruction Explanation States Flags Addressin Machine
Set g Cycles
RET Unconditional 10 None Indirect 3

[PCL] ← RET: Return

[[SP]], from

[PCH] ← subroutine

[[SP] +

1], [SP]

← [SP]
 +2

Conditional Return
Instruction Explanation States Machine
Set Cycles
RET Conditional 12, if 3, if true

[PCL] ← RET: Return true and 1, if

[[SP]],  from and not true

[PCH] ← subroutine 6, if

[[SP] + not

1], true

[SP] ←

[SP] + 2

Instruction Explanation Status States Flags Addressing Machine

Set Cycles
RC Return CS =1 6/1 None Register 1/3

from 2 indirect

subroutine

if carry

status is

zero.

RNC Return CS = 6/1 None Register 1/3

from 0 2 indirect

subroutine

if carry

status is

not zero.

RZ Return Zero 6/1 None Register 1/3

from status
 subroutine Z=1 2 indirect

if result is

zero.

RNZ Return Zero 6/1 None Register 1/3

from status 2 indirect

subroutine Z= 0

if result is

not zero.

RP Return Sign 6/1 None Register 1/3

from Status 2 indirect

subroutine S= 0

if result is

not plus.

RM Return Sign 6/1 None Register 1/3

from Status 2 indirect

subroutine S= 0

if result is

not

minus.

RPE Return Parity 6/1 None Register 1/3

from Status 2 indirect

subroutine P= 1

if even

parity.

RPO Return Parity 6/1 None Register 1/3

from Status 2 indirect

subroutine P= 1
 if odd

parity.

Restart
Instruction Explanation States Flags Addressin Machine
Set g Cycles
RST Restart is 12 None Register 3

[[SP]-1] a one word Indirect

← CALL

[PCH], instruction.

[[SP]-2]

[PCL], 

[SP] ←

[SP] -

2, 

[PC] ←

8 times

The restart instructions and locations are as follows:

Instruction Opcode Restart Locations
RST 0 C7 0000

RST 1 CF 0008

RST 2 D7 0010

RST 3 DF 0018

RST 4 E7 0020

RST 5 EF 0028

RST 6 F7 0030

RST 7 FF 0038
PCHL
Instruction Set Explanation States Flags Addressin Machine
g Cycles
PCHL Jump 6 None Register 1

[PC] ← [H- address

L],  specified

[PCH] by H-L

←[H], [PCL] pair

←[L]

Stack, I/O and Machine Control Group

This group contains the instructions for input/output ports, stack and
machine control.
Instruction Explanation State Flags Addressing Machin
Set s e
Cycles
IN port - Input to 10 Non Direct 3

address accumulat e

[A] ← or from

[Port] I/O port

OUT Output 10 Non Direct 3

port- from e

address accumulat

[Port] ← or to I/O

[A] port

PUSH rp Push the 12 Non Register(source)/regis 3

[[SP] - content of e ter

1] ← register Indirect(destination)
[rh], pair to

[[SP] - stack

2] ←

[rh],

[SP] ←

[SP] - 2

PUSH Push 12 Non Register(source)/regis 3

PSW processor e ter

[SP]-1] word Indirect(destination)

← [A], 

[[SP] -2]

← PSW, 

[SP] ←

[SP] - 2

POP rp Pop the 10 Non Register(source)/regis 3

[rl] ← [ [ content of e ter

SP ] ], register Indirect(destination)

[rh] ← pair,

[[SP] which was

+1],  saved,

[SP] ← from the

[SP] + 2 stack

HLT Halt 5 Non 1

XTHL Exchange 16 Non Register indirect 5

[L] ↔ top stack e

[[SP]],  with H-L

[H] ↔

[[SP] +

1]

SPHL Moves the 6 Non Register 1

[H-L] → contents e

[SP] of H-L pair

to stack

pointer

EI Enable 4 Non 1

Interrupts e

SIM Set 4 Non 1

Interrupts e

Masks

RIM Read 4 Non 1

Interrupts e

Masks

NOP No 4 Non 1

Operation e